Method for manufacturing image display device and image display device

Abstract

The manufacturing method of the image display device of the embodiment includes the following steps: forming a graphene layer on a first substrate; forming a semiconductor layer including a light-emitting layer on the graphene layer; processing the semiconductor layer to form a light-emitting element having a bottom surface on the graphene layer and including a light-emitting surface as a surface opposite to the bottom surface; forming a first insulating film covering the first substrate, the graphene layer, and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the first insulating film and the circuit element; removing a portion of the first insulating film and a portion of the second insulating film to expose the light-emitting surface; forming a through hole penetrating through the first insulating film and the second insulating film; and forming a wiring layer on the second insulating film.

Description

Technical Field

[0001] The embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Technology

[0002] There is a desire to achieve thin image display devices with high brightness, wide viewing angles, high contrast, and low power consumption. To meet this market demand, the development of display devices utilizing self-emissive elements is underway.

[0003] As self-emissive elements, display devices utilizing micro-LEDs, which are tiny light-emitting elements, are anticipated. A method for manufacturing such a display device using micro-LEDs has been described, which involves sequentially transferring separately formed micro-LEDs onto a driving circuit. However, with the increasing demand for high image quality such as Full HD, 4K, and 8K, the number of micro-LEDs increases. Therefore, when multiple micro-LEDs are formed separately and sequentially transferred onto a substrate containing the driving circuit, the transfer process requires a significant amount of time. Furthermore, there is a risk of poor connection between the micro-LEDs and the driving circuit, leading to a decrease in yield.

[0004] A known technique involves growing a semiconductor layer containing a light-emitting layer on a Si substrate, forming electrodes on the semiconductor layer, and then attaching it to a circuit substrate on which a driving circuit is formed (see, for example, Patent Document 1).

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2002-141492 Summary of the Invention

[0008] The problem that the invention will solve

[0009] One embodiment of the present invention provides a method for manufacturing an image display device and an image display device that shortens the transfer process of the light-emitting element and improves the yield rate.

[0010] Methods for solving problems

[0011] A method for manufacturing an image display device according to an embodiment of the present invention includes the following steps: forming a graphene-containing layer on a first substrate; forming a semiconductor layer containing a light-emitting layer on the graphene-containing layer; processing the semiconductor layer to form a light-emitting element, the light-emitting element having a bottom surface on the graphene-containing layer and including a light-emitting surface as the side opposite to the bottom surface; forming a first insulating film covering the first substrate, the graphene-containing layer, and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the first insulating film and the circuit element; removing a portion of the first insulating film and a portion of the second insulating film to expose the surface containing the light-emitting surface; forming a through-hole penetrating the first insulating film and the second insulating film; and forming a wiring layer on the second insulating film. The light-emitting element includes a connection portion formed on the graphene-containing layer. The through-hole is provided between the wiring layer and the connection portion, electrically connecting the wiring layer and the connection portion.

[0012] An image display device according to an embodiment of the present invention includes: a substrate having a first surface; a graphene-containing layer disposed on the first surface; a light-emitting element disposed on the graphene-containing layer, having a bottom surface on the graphene-containing layer and including a light-emitting surface that is the opposite side of the bottom surface; a first insulating film covering the side surface of the light-emitting element, the first surface, and the graphene-containing layer; a circuit element disposed on the first insulating film; a second insulating film covering the first insulating film and the circuit element; a through-hole penetrating the first insulating film and the second insulating film; and a wiring layer disposed on the second insulating film. The light-emitting element includes a first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light-emitting layer, wherein the first semiconductor layer, the light-emitting layer, and the second semiconductor layer are sequentially stacked from the bottom surface toward the light-emitting surface. The through-hole is disposed between a connection portion formed from the first semiconductor layer to the graphene-containing layer and the wiring layer, electrically connecting the first semiconductor layer and the wiring layer.

[0013] An image display device according to one embodiment of the present invention includes: a substrate having a first surface; a second portion disposed on the first surface and having light reflectivity; a graphene-containing layer disposed on the second portion; a semiconductor layer disposed on the graphene-containing layer, having a bottom surface on the graphene-containing layer, and including a plurality of light-emitting surfaces on a surface opposite to the bottom surface; a first insulating film covering the first surface, the graphene-containing layer, and the side surface of the semiconductor layer; a plurality of transistors disposed on the first insulating film; a second insulating film covering the first insulating film and the plurality of transistors; a plurality of vias penetrating the first insulating film and the second insulating film; and a wiring layer disposed on the second insulating film, including wiring electrically connected to the plurality of transistors, the plurality of light-emitting surfaces, and the plurality of vias. In a top view, the outer periphery of the semiconductor layer is disposed within the outer periphery of the second portion. The semiconductor layer includes a first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light-emitting layer. The first semiconductor layer, the light-emitting layer, and the second semiconductor layer are sequentially stacked from the bottom surface toward the light-emitting surface. The plurality of vias are disposed between the connection portion formed from the first semiconductor layer to the graphene-containing layer and the wiring layer, electrically connecting the first semiconductor layer and the wiring layer.

[0014] Invention Effects

[0015] According to one embodiment of the present invention, a method for manufacturing an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield rate.

[0016] According to one embodiment of the present invention, an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield rate. Attached Figure Description

[0017] Figure 1 This is a schematic cross-sectional view illustrating a portion of the image display device according to the first embodiment.

[0018] Figure 2 This is a cross-sectional view schematically showing a portion of a modified example of the image display device according to the first embodiment.

[0019] Figure 3 This is a schematic block diagram illustrating the image display device according to the first embodiment.

[0020] Figure 4 This is a schematic top view illustrating a portion of the image display device according to the first embodiment.

[0021] Figure 5A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0022] Figure 5B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0023] Figure 6A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0024] Figure 6B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0025] Figure 7A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0026] Figure 7B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0027] Figure 8A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a variation of the first embodiment.

[0028] Figure 8B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a variation of the first embodiment.

[0029] Figure 9 This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0030] Figure 10A This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0031] Figure 10B This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0032] Figure 10C This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0033] Figure 10D This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to the first embodiment.

[0034] Figure 11 This is a schematic perspective view illustrating the image display device of the first embodiment.

[0035] Figure 12 This is a schematic cross-sectional view illustrating a portion of the image display device according to the second embodiment.

[0036] Figure 13 This is a schematic block diagram illustrating the image display device according to the second embodiment.

[0037] Figure 14A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0038] Figure 14B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0039] Figure 14C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0040] Figure 15A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0041] Figure 15B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0042] Figure 16A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0043] Figure 16B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0044] Figure 17A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0045] Figure 17B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0046] Figure 18 This is a schematic cross-sectional view illustrating a portion of the image display device according to the third embodiment.

[0047] Figure 19A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0048] Figure 19B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0049] Figure 20A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0050] Figure 20B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0051] Figure 21 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fourth embodiment.

[0052] Figure 22A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0053] Figure 22B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0054] Figure 23 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fifth embodiment.

[0055] Figure 24A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0056] Figure 24B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0057] Figure 24C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0058] Figure 25A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0059] Figure 25B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0060] Figure 26A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0061] Figure 26B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0062] Figure 27 This is a schematic cross-sectional view of a portion of an image display device illustrating a variation of the fifth embodiment.

[0063] Figure 28A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment.

[0064] Figure 28B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment.

[0065] Figure 28C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment.

[0066] Figure 29A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment.

[0067] Figure 29B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment.

[0068] Figure 30 This is a chart illustrating the characteristics of pixel LED elements.

[0069] Figure 31 This is a block diagram illustrating an image display device according to the sixth embodiment.

[0070] Figure 32 This is a block diagram illustrating a modified example of the sixth embodiment of an image display device. Detailed Implementation

[0071] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0072] Furthermore, the accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., do not necessarily have to be the same as in reality. In addition, even when showing the same parts, there are cases where the dimensions and ratios of each other are shown differently depending on the accompanying drawings.

[0073] In addition, in this application specification and various figures, the same reference numerals are used for elements that are the same as those described with respect to the figures that have appeared, and detailed descriptions are omitted where appropriate.

[0074] (First Implementation)

[0075] Figure 1 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0076] Figure 1 The diagram schematically illustrates the configuration of the sub-pixels 20 of the image display device according to this embodiment. Pixels constituting an image displayed on the image display device are composed of a plurality of sub-pixels 20.

[0077] The following explanations sometimes use a three-dimensional coordinate system of XYZ. Subpixels 20 are arranged in a two-dimensional plane. This two-dimensional plane with subpixels 20 is designated as the XY plane. Subpixels 20 are arranged along the X-axis and Y-axis. Figure 1 Indicates what will be said later Figure 4The view along line AA' is presented as a cross-sectional view connecting multiple planes perpendicular to the XY plane on a single plane. The same applies to other drawings. Figure 1 Therefore, in cross-sectional views on multiple planes perpendicular to the XY plane, the X and Y axes are not shown; instead, the Z-axis, perpendicular to the XY plane, is shown. That is, in these views, the plane perpendicular to the Z-axis is designated as the XY plane. Furthermore, for convenience, the positive direction of the Z-axis is sometimes designated as "up" or "above," and the negative direction as "down" or "below," but the direction along the Z-axis is not necessarily the direction in which gravity applies. Additionally, the length along the Z-axis is sometimes referred to as height.

[0078] Sub-pixel 20 has a light-emitting surface 153S that is approximately parallel to the XY plane. The light-emitting surface 153S is a surface that mainly radiates light in the positive direction of the Z-axis, which is orthogonal to the XY plane.

[0079] like Figure 1 As shown, the sub-pixel 20 of the image display device includes a substrate 102, a graphene layer 140, a light-emitting element 150, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 161k, and a wiring layer 110.

[0080] In this embodiment, the substrate 102 on which the light-emitting element 150 is formed is a light-transmitting substrate, such as a glass substrate. The substrate 102 has a first surface 102a, on which the light-emitting element 150 is formed. The light-emitting element 150 is driven by a TFT disposed with a first interlayer insulating film 156 in between. The process of forming circuit elements including TFTs on a large glass substrate is established for manufacturing liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing complete sets of equipment.

[0081] Subpixel 20 also includes a color filter 180. The color filter (wavelength conversion component) 180 is disposed on the surface resin layer 170 through a transparent thin film adhesive layer 188. The surface resin layer 170 is disposed on the second interlayer insulating film 108 and the wiring layer 110.

[0082] The following is a detailed explanation of the composition of subpixel 20.

[0083] A graphene layer 140 is disposed on the first surface 102a. The graphene layer 140 includes a graphene sheet 140a. The graphene sheet (containing the graphene layer) 140a is disposed on each light-emitting element 150, and the light-emitting element 150 is disposed on the graphene sheet 140a. The graphene sheet 140a has an outer perimeter that is substantially consistent with the outer perimeter of the light-emitting element 150 when viewed from above in the XY plane. The graphene layer 140 and the graphene sheet 140a are monolayers of graphene, for example, a layered structure consisting of several to about 10 layers.

[0084] In this example, the light-emitting element 150 is disposed on the graphene sheet 140a via a buffer layer 145. The buffer layer 145 has an outer perimeter that substantially coincides with the outer perimeter of the light-emitting element 150 when viewed from above in the XY plane. In this example, the buffer layer 145 is formed of an insulating material, such as AlN. The buffer layer 145 is primarily used to facilitate the growth of the semiconductor layer used to form the light-emitting element 150.

[0085] The light-emitting element 150 includes a light-emitting surface 153S and a bottom surface 151B. The light-emitting surface 153S is the surface opposite to the bottom surface 151B of the light-emitting element 150. The light-emitting element 150 is a prism-shaped or cylindrical element having a bottom surface 151B on a first surface 102a. In this example, the bottom surface 151B of the light-emitting element 150 is the surface in contact with the buffer layer 145.

[0086] The light-emitting element 150 includes an n-type semiconductor layer (first semiconductor layer) 151, a light-emitting layer 152, and a p-type semiconductor layer (second semiconductor layer) 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked sequentially from the bottom surface 151B toward the light-emitting surface 153S. Therefore, in this example, the n-type semiconductor layer 151 is disposed in contact with the buffer layer 145.

[0087] The n-type semiconductor layer 151 includes a connection portion 151a. For example, the connection portion 151a, together with the buffer layer 145 and the graphene sheet 140a, protrudes from the n-type semiconductor layer 151 in one direction on the first surface 102a. The protruding direction is not limited to one direction; it can be two or more directions, or it can protrude along the entire circumference of the n-type semiconductor layer 151. The height of the connection portion 151a is the same as or lower than the height of the n-type semiconductor layer 151, and the light-emitting element 150 is formed in a stepped shape. The connection portion 151a is n-type and electrically connected to the n-type semiconductor layer 151. The connection portion 151a is connected to one end of a via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

[0088] When the light-emitting element 150 is prismatic, its shape when viewed from above in the XY plane is, for example, approximately square or rectangular. When the light-emitting element 150's shape when viewed from above in the XY plane is a polygon containing a square, the corners may be rounded. When the light-emitting element 150's shape when viewed from above in the XY plane is cylindrical, its shape is not limited to a circle; for example, it could be elliptical. By appropriately selecting the shape and arrangement of the light-emitting element when viewed from above in the XY plane, the flexibility of the layout is increased.

[0089] The light-emitting element 150 preferably uses, for example, an element containing In.X Al Y Ga 1－X－Y Gallium nitride (GaN) compound semiconductors with light-emitting layers such as N (0≤X, 0≤Y, X+Y<1). Hereinafter, the aforementioned gallium nitride compound semiconductors are sometimes simply referred to as gallium nitride (GaN). In one embodiment of the present invention, the light-emitting element 150 is a so-called light-emitting diode (LED). The wavelength of the light emitted by the light-emitting element 150 is, for example, approximately 467 nm ± 30 nm. The wavelength of the light emitted by the light-emitting element 150 can also be approximately 410 nm ± 30 nm, which is blue-violet light. The wavelength of the light emitted by the light-emitting element 150 is not limited to the above values ​​and can be any suitable wavelength.

[0090] The area of ​​the light-emitting layer 152 when viewed from above the XY plane is set according to the emission color of the red, green, and blue sub-pixels. Hereinafter, the area when viewed from above the XY plane will sometimes be referred to simply as the area. The area of ​​the light-emitting layer 152 is appropriately set according to factors such as visibility and the conversion efficiency of the color conversion unit 182 of the color filter 180. That is, the area of ​​the light-emitting layer 152 of each emission color sub-pixel 20 is sometimes the same, and sometimes it is different according to the emission color. In addition, the area of ​​the light-emitting layer 152 is the area of ​​the region surrounded by the outer periphery of the light-emitting layer 152 projected onto the XY plane.

[0091] A first interlayer insulating film (first insulating film) 156 covers the first surface 102a, the graphene layer 140, the buffer layer 145, and the light-emitting element 150. In this example, the first interlayer insulating film 156 covers the side surface of the graphene sheet 140a, the side surface of the buffer layer 145, and the side surface of the light-emitting element 150. The first interlayer insulating film 156 insulates the light-emitting elements 150 from each other. The first interlayer insulating film 156 insulates the light-emitting elements 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming a circuit 101 containing circuit elements such as the transistor 103. By covering the light-emitting element 150, the first interlayer insulating film 156 protects the light-emitting element 150 from the effects of thermal stress and other factors during the formation of the transistor 103, etc.

[0092] The first interlayer insulating film 156 is formed of organic or inorganic insulating material. The insulating material used for the first interlayer insulating film 156 is preferably white resin. White resin reflects the reflected light from the transverse emitted light of the light-emitting element 150, the interface of the color filter 180, etc., so making the first interlayer insulating film 156 white resin helps to substantially improve the luminous efficiency of the light-emitting element 150.

[0093] White resin is formed by dispersing scattering fine particles exhibiting Mie scattering effect in transparent resins such as silicone resins (SOG, Spin On Glass) and phenolic varnish-type phenolic resins. The scattering fine particles are colorless or white and have a diameter approximately 1 / 10 to several times the wavelength of the light emitted by the light-emitting element 150. Preferably, the scattering fine particles have a diameter approximately 1 / 2 the wavelength of the light. Examples of such scattering fine particles include TiO2, Al2O3, and ZnO.

[0094] White resin can also be formed by flexibly utilizing multiple tiny pores dispersed within transparent resin. When whitening the first interlayer insulating film 156, a SiO2 film formed by, for example, ALD (Atomic-Layer-Deposition) or CVD can be used instead of SOG.

[0095] The first interlayer insulating film 156 can also be made of black resin. By making the first interlayer insulating film 156 black resin, light scattering within the sub-pixel 20 can be suppressed, and stray light can be suppressed more effectively. Image display devices that suppress stray light can display clearer images.

[0096] A TFT lower layer film 106 is formed on the first interlayer insulating film 156. The TFT lower layer film 106 is provided for purposes such as ensuring flatness during the formation of the transistor 103 and protecting the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is, for example, an insulating film such as SiO2.

[0097] Transistor 103 is formed on the lower TFT film 106. Besides transistor 103, other transistors, capacitors, and other circuit elements are formed on the lower TFT film 106, and circuit 101 is constructed using wiring and other methods. For example, as described later... Figure 3 In this configuration, transistor 103 corresponds to driving transistor 26. In addition, in... Figure 3 In the circuit, transistor 24, capacitor 28, etc. are selected as circuit elements. Circuit 101 includes TFT channel 104, insulating layer 105, second interlayer insulating film 108, vias 111s and 111d, and wiring layer 110.

[0098] In this example, transistor 103 is a p-channel thin-film transistor (TFT). Transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed using a low-temperature polycrystalline silicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallineizing and activating a region of amorphous Si formed on the lower TFT film 106. For example, laser-based laser annealing is used for the polycrystallineization and activation of the amorphous Si region. TFTs formed by the LTPS process have sufficiently high mobility.

[0099] The TFT channel 104 includes regions 104s, 104i, and 104d. Regions 104s, 104i, and 104d are all disposed on the lower TFT film 106. Region 104i is disposed between regions 104s and 104d. Regions 104s and 104d are doped with impurities such as boron (B) through ion implantation to form p-type semiconductor regions, and are ohmically connected to vias 111s and 111d.

[0100] Gate 107 is disposed on TFT channel 104 via insulating layer 105. Insulating layer 105 is provided to insulate TFT channel 104 from gate 107 and from other adjacent circuit elements. If a potential lower than that of region 104s is applied to gate 107, the current flowing through regions 104s and 104d can be controlled by forming a channel in region 104i.

[0101] The insulating layer 105 is, for example, SiO2. The insulating layer 105 may also be a multilayer insulating layer containing SiO2, Si3N4, etc., depending on the area it covers.

[0102] The gate 107 can be formed from polycrystalline Si, or from high-melting-point metals such as W and Mo. The polycrystalline Si film of the gate 107 is generally formed by CVD or the like.

[0103] A second interlayer insulating film (second insulating film) 108 is disposed on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed, for example, of the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of an inorganic film such as white resin or SiO2. The second interlayer insulating film 108 also functions as a planarization film for forming the wiring layer 110.

[0104] The first interlayer insulating film 156, the lower TFT film 106, the insulating layer 105, and the second interlayer insulating film 108 are configured as described above, and therefore are not located on the upper part of the light-emitting surface 153S. That is, the opening 15 is formed by removing a portion of each of the first interlayer insulating film 156, the lower TFT film 106, the insulating layer 105, and the second interlayer insulating film 108. The light-emitting surface 153S is exposed through the opening 158. As will be described later, the opening 158 is filled with the surface resin layer 170.

[0105] Through-holes 111s and 111d are provided to penetrate the second interlayer insulating film 108 and the insulating layer 105. A wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes multiple wirings with different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110k.

[0106] A portion of wiring 110s is positioned above region 104s. Other portions of wiring 110s are connected, for example, to [the area described later]. Figure 3 The power line 3 is shown. A portion of wiring 110d is located above region 104d. Another portion of wiring (second wiring) 110d is connected to the surface containing the light-emitting surface 153S. A portion of wiring 110k is located above the connecting portion 151a. Other portions of wiring 110k are connected, for example, to the surface described later. Figure 3 Grounding wire 4 is shown.

[0107] exist Figure 1 In subsequent cross-sectional views of wiring layers, unless otherwise specified, the reference numerals for the wiring layers will be displayed at the lateral position of a wiring layer contained in the wiring layer for which reference numerals should be attached.

[0108] Through-hole 111s is disposed between wiring 110s and area 104s, electrically connecting wiring 110s and area 104s. Through-hole 111d is disposed between wiring 110d and area 104d, electrically connecting wiring 110d and area 104d.

[0109] Wiring 110s is connected to region 104s via via 111s. Region 104s is the source region of transistor 103. Therefore, the source region of transistor 103 is electrically connected to power line 3 via via 111s and wiring 110s.

[0110] Wiring 110d is connected to region 104d via via 111d. Region 104d is the drain region of transistor 103. Therefore, the drain region of transistor 103 is electrically connected to p-type semiconductor layer 153 via via 111d and wiring 110d.

[0111] A via 161k is provided that penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 161k is located between the wiring (first wiring) 110k and the connection portion 151a, electrically connecting the wiring 110k and the connection portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to the ground line 4 via the connection portion 151a, the via 161k, and the wiring 110k.

[0112] The wiring layer 110 and vias 111s, 111d, and 161k are formed, for example, of Al, Cu, or alloys thereof, or of a laminated film of Al and Ti. For example, in an Al and Ti laminated film, Al is laminated on a Ti film, and Ti is laminated on Al.

[0113] A surface resin layer 170 covers the second interlayer insulating film 108 and the wiring layer 110. The surface resin layer 170 also fills the opening 158. The surface resin layer 170 covers the light-emitting surface 153S. The surface resin layer 170 filling the opening 158 covers a portion of the sidewalls of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The surface resin layer 170 is a transparent resin, providing protection for the second interlayer insulating film 108 and the wiring layer 110 and serving to bond the planarized surface of the color filter 180.

[0114] The color filter 180 includes a light-blocking section 181 and a color conversion section 182. The color conversion section 182 is positioned directly above the light-emitting surface 153S of the light-emitting element 150, according to the shape of the light-emitting surface 153S. In the color filter 180, the portion other than the color conversion section 182 is designated as the light-blocking section 181. The light-blocking section 181 is a so-called black matrix, which can reduce color bleeding caused by color mixing and other factors from the adjacent color conversion section 182, thereby enabling the display of a clear image.

[0115] The color conversion unit 182 is set to one layer or two layers or more. Figure 1 The diagram shows a case where the color conversion unit 182 has two layers. Whether the color conversion unit 182 has one or two layers is determined by the color, i.e., the wavelength, of the light emitted by the sub-pixel 20. When the emitted color of the sub-pixel 20 is red, it is preferable that the color conversion unit 182 consists of two layers: a color conversion layer 183 and a filter layer 184 that allows red light to pass through. When the emitted color of the sub-pixel 20 is green, it is preferable that the color conversion unit 182 consists of two layers: a color conversion layer 183 and a filter layer 184 that allows green light to pass through. When the emitted color of the sub-pixel 20 is blue, it is preferable to have only one layer.

[0116] When the color conversion unit 182 has two layers, the first layer is the color conversion layer 183, and the second layer is the filter layer 184. The first color conversion layer 183 is located closer to the light-emitting element 150. The filter layer 184 is stacked on top of the color conversion layer 183.

[0117] The color conversion layer 183 converts the wavelength of light emitted by the light-emitting element 150 to a desired wavelength. When emitting red sub-pixels 20, light with a wavelength of 467nm ± 30nm (the wavelength of the light-emitting element 150) is converted, for example, to light with a wavelength of approximately 630nm ± 20nm. When emitting green sub-pixels 20, light with a wavelength of 467nm ± 30nm (the wavelength of the light-emitting element 150) is converted, for example, to light with a wavelength of approximately 532nm ± 20nm.

[0118] The filter layer 184 blocks the wavelength components of blue light that remain after the color conversion layer 183 has not been converted.

[0119] When the light emitted by sub-pixel 20 is blue, it can be output as is, either via color conversion layer 183 or without color conversion layer 183. When the wavelength of the light emitted by light-emitting element 150 is approximately 467nm ± 30nm, the light can also be output without color conversion layer 183. When the wavelength of the light emitted by light-emitting element 150 is set to 410nm ± 30nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to approximately 467nm ± 30nm.

[0120] Even in the case of the blue sub-pixel 20, the sub-pixel 20 can have a filter layer 184. By providing a filter layer 184 that allows blue light to pass through in the blue sub-pixel 20, minute external light reflections other than the blue light generated on the surface of the light-emitting element 150 can be suppressed.

[0121] Figure 2 This is a cross-sectional view schematically showing a portion of a modified example of the image display device of this embodiment.

[0122] exist Figure 2 To avoid unnecessary complexity, the surface resin layer 170, the transparent film adhesive layer 188, and the color filter 180 are omitted from the display. The structures above the surface resin layer 170 are provided on the second interlayer insulating film 108, the wiring layer 110, and the opening 158.

[0123] In this modified example, the connection method between the sub-pixel 20a light-emitting element 150a and the wiring 110d1 differs from the connection method between the light-emitting element 150 and the wiring 110d1 in the first embodiment described above. In this modified example, the presence of a light-transmitting electrode 159s throughout the wiring 110s differs from the first embodiment. Otherwise, this modified example is the same as the first embodiment, with the same reference numerals used for the same constituent elements and detailed descriptions appropriately omitted.

[0124] like Figure 2 As shown, sub-pixel 20a includes a light-emitting element 150a, wiring 110d1, and a light-transmitting electrode 159d. A portion of wiring 110d1 is disposed above region 104d and via 111d. A portion of wiring 110d1 is connected to region 104d via via 111d. Another portion of wiring 110d1 does not extend to the light-emitting surface 153S and is not directly connected to the light-emitting surface 153S.

[0125] A light-transmitting electrode 159d is disposed throughout the wiring 110d1. A light-transmitting electrode 159d is disposed throughout the light-emitting surface 153S. The light-transmitting electrode 159d is also disposed between the wiring 110d1 and the light-emitting surface 153S, electrically connecting the wiring 110d1 and the light-emitting surface 153S.

[0126] Transparent electrodes 159s are provided throughout the wiring 110s. Both transparent electrodes 159d and 159s are formed of a transparent conductive film. ITO films, ZnO films, etc., are preferably used as transparent conductive films. In this example, transparent electrodes are not provided on the wiring 110k, but they can also be specifically provided on the wiring 110k.

[0127] The light-emitting surface 153S is preferably roughened. When the light-emitting surface 153S is roughened, the light extraction efficiency of the light-emitting element 150 can be improved.

[0128] By providing a transparent electrode 159d on the light-emitting surface 153S, the connection area between the transparent electrode 159d and the p-type semiconductor layer 153 can be increased, and the area of ​​the light-emitting surface 153S can also be increased, thus improving the luminous efficiency. When the light-emitting surface 153S is a rough surface, increasing the connection area between the light-emitting surface 153S and the transparent electrode 159d reduces the contact resistance, further improving the luminous efficiency.

[0129] In this embodiment, one of the sub-pixels 20 and 20a described above may be included. In other embodiments described later, it may also be one of direct electrical connection based on metal wiring or electrical connection based on a light-transmitting electrode.

[0130] Figure 3 This is a schematic block diagram illustrating the image display device of this embodiment.

[0131] like Figure 3 As shown, the image display device 1 of this embodiment includes a display area 2. Subpixels 20 are arranged in the display area 2. The subpixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X-axis and m subpixels are arranged along the Y-axis.

[0132] Pixel 10 contains multiple sub-pixels 20 that emit light of different colors. Sub-pixel 20R emits red light. Sub-pixel 20G emits green light. Sub-pixel 20B emits blue light. The three sub-pixels 20R, 20G, and 20B emit light at the desired brightness, thus determining the emission color and brightness of a pixel 10.

[0133] A pixel 10 contains three subpixels: 20R, 20G, and 20B. For example, subpixels 20R, 20G, and 20B... Figure 3 As shown, they are arranged in a straight line along the X-axis. Each pixel 10 can also arrange subpixels of the same color into the same column, or, as in this example, arrange subpixels of different colors in each column.

[0134] The image display device 1 also includes a power line 3 and a ground line 4. The power line 3 and the ground line 4 are arranged in a grid pattern along the sub-pixels 20. The power line 3 and the ground line 4 are electrically connected to each sub-pixel 20, supplying power to each sub-pixel 20 from a DC power supply connected between the power terminal 3a and the GND terminal 4a. The power terminal 3a and the GND terminal 4a are respectively located at the ends of the power line 3 and the ground line 4, and are connected to a DC power supply circuit located outside the display area 2. The power terminal 3a is supplied with a positive voltage with reference to the GND terminal 4a.

[0135] The image display device 1 also includes scan lines 6 and signal lines 8. The scan lines 6 are routed in a direction parallel to the X-axis. That is, the scan lines 6 are routed along the row direction of the sub-pixels 20. The signal lines 8 are routed in a direction parallel to the Y-axis. That is, the signal lines 8 are routed along the column direction of the sub-pixels 20.

[0136] The image display device 1 also includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are disposed along the outer edge of the display area 2. The row selection circuit 5 is disposed along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via scan lines 6 and supplies selection signals to each sub-pixel 20.

[0137] The signal voltage output circuit 7 is arranged along the X-axis direction of the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 of each row via signal lines 8, and supplies signal voltage to each sub-pixel 20.

[0138] Subpixel 20 includes a light-emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. Figure 3 And the following Figure 4 In the text, sometimes the select transistor 24 is shown as T1, the drive transistor 26 is shown as T2, and the capacitor 28 is shown as Cm.

[0139] The light-emitting element 22 and the driving transistor 26 are connected in series. In this embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the select transistor 24 are the drain electrode and the source electrode, respectively. The anode electrode of the light-emitting element 22 is connected to a p-type semiconductor layer. The cathode electrode of the light-emitting element is connected to an n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 and... Figure 1 The transistor 103 corresponds to the light-emitting element 22 and Figure 1 The light-emitting element 150 corresponds to this. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness corresponding to the current flowing through it.

[0140] Select transistor 24 is connected via its main electrode between the gate electrode of drive transistor 26 and signal line 8. The gate electrode of select transistor 24 is connected to scan line 6. A capacitor 28 is connected between the gate electrode of drive transistor 26 and power line 3.

[0141] The row selection circuit 5 selects one row from the arrangement of m rows of sub-pixels 20 and supplies a selection signal to the scan line 6. The signal voltage output circuit 7 supplies a signal voltage with the required analog voltage value to each sub-pixel 20 of the selected row. The signal voltage is applied between the gate and source of the driving transistor 26 of the selected row's sub-pixel 20. The signal voltage is held by the capacitor 28. The driving transistor 26 causes a current corresponding to the signal voltage to flow through the light-emitting element 22. The light-emitting element 22 emits light with a brightness corresponding to the flowing current.

[0142] The row selection circuit 5 sequentially switches the selected row to supply a selection signal. That is, the row selection circuit 5 scans the rows arranged with sub-pixels 20. A current corresponding to the signal voltage flows through the light-emitting element 22 of the sequentially scanned sub-pixels 20 to emit light. Each pixel 10 emits light with a color and brightness determined by the light emitted by the sub-pixels 20 of each of the RGB colors, and displays an image in the display area 2.

[0143] Figure 4 This is a schematic top view illustrating a portion of the image display device of this embodiment.

[0144] In this embodiment, as in Figure 1 As described above, the light-emitting element 150 and the driving transistor 103 are stacked along the Z-axis direction, separated by a first interlayer insulating film 156. The light-emitting element 150 is... Figure 3 The middle corresponds to the light-emitting element 22. The driving transistor 103 is in Figure 3 The one corresponding to the driving transistor 26 is also referred to as T2.

[0145] like Figure 4 As shown, the cathode electrode of the light-emitting element 150 is provided by a connection portion 151a. The connection portion 151a is located below the transistor 103 and the wiring layer 110. The connection portion 151a is electrically connected to the wiring 110k via a through-hole 161k. More specifically, one end of the through-hole 161k is connected to the connection portion 151a. The other end of the through-hole 161k is connected to the wiring 110k via a contact hole 161k1.

[0146] The anode electrode of the light-emitting element 150 is made of Figure 1 A p-type semiconductor layer 153 is provided. A wiring 110d extends through an opening 158 to a surface containing a light-emitting surface 153S. The p-type semiconductor layer 153 is connected to one end of the wiring 110d via the surface containing the light-emitting surface 153S. The surface containing the light-emitting surface 153S is a surface that is coplanar with the light-emitting surface 153S. One end of the wiring 110d is connected to the surface containing the light-emitting surface 153S, and the remaining surface is the light-emitting surface 153S.

[0147] The other end of wiring 110d is connected to the drain electrode of transistor 103 via via 111d. The drain electrode of transistor 103 is Figure 1 The region 104d is shown. The source electrode of transistor 103 is connected to wiring 110s via via 111s. The source electrode of transistor 103 is Figure 1 The area 104s is shown. In this example, the wiring layer 110 includes power lines 3, and the wiring 110s is connected to the power lines 3.

[0148] In this example, grounding wire 4 is located on a layer higher than wiring layer 110. Figure 1 Although the diagram is omitted, an interlayer insulating film is also provided on the wiring layer 110. The grounding wire 4 is located on the top interlayer insulating film and is insulated from the power line 3.

[0149] Thus, the light-emitting element 150 can be electrically connected to the wiring layer 110 located above the light-emitting element 150 by using the through hole 161k. In addition, the light-emitting element 150 can be electrically connected to the wiring layer 110 located above the light-emitting element 150 by providing an opening 158 that exposes the light-emitting surface 153S.

[0150] The manufacturing method of the image display device 1 of this embodiment will be described.

[0151] Figures 5A to 7B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0152] like Figure 5A As shown, in the manufacturing method of the image display device 1 of this embodiment, a substrate (first substrate) 102 is prepared. The substrate 102 is a light-transmitting substrate, such as a generally rectangular glass substrate of about 1500mm × 1800mm. A graphene layer 1140 is formed on the first surface 102a. The graphene layer 1140 is a layer containing graphene, preferably formed by stacking several to about 10 single-layer graphene layers. The graphene layer 1140, cut to an appropriate size and shape, is disposed at a predetermined position on the first surface 102a and adsorbed onto the substrate 102 by the flatness of the first surface 102a. The graphene layer 1140 may also be bonded to the first surface 102a, for example, by an adhesive or the like.

[0153] like Figure 5B As shown, throughout Figure 5A A buffer layer 1145 is formed on the graphene layer 1140 shown. The buffer layer 1145 is formed, for example, by a physical vapor deposition method such as sputtering. By providing the buffer layer 1145, the crystal growth of GaN can be promoted. There are no restrictions on the type of material used for the buffer layer 1145 as long as it is a material that promotes the crystal growth of GaN; it can be an insulating material or a conductive material such as a metal. For example, a metal layer containing single crystals such as Hf or Cu can also be used as the buffer layer. Alternatively, as in other embodiments described later, the formation of the buffer layer can be omitted, and the semiconductor layer can be grown directly on the graphene layer.

[0154] A semiconductor layer 1150 is formed over a buffer layer 1145. The semiconductor layer 1150 is formed from one side of the buffer layer 1145 towards the positive Z-axis in the following order: an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153. The semiconductor layer 1150 may contain, for example, GaN, and more specifically, In. X Al Y Ga 1－X－YN (0≤X, 0≤Y, X+Y<1), etc. In the early stages of growth of the semiconductor layer 1150, crystal defects caused by lattice mismatch are easily generated. Crystals with GaN as the main component generally exhibit n-type semiconductor characteristics. Therefore, by growing from the n-type semiconductor layer 1151 onto the buffer layer 1145, the yield can be improved.

[0155] In the process of forming the semiconductor layer 1150, physical vapor deposition methods such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), and sputtering are used, with cryogenic sputtering being the preferred method. In cryogenic sputtering, the temperature can be further reduced by using light or plasma assistance during film formation, which is therefore preferred. In MOCVD-based epitaxial growth, temperatures exceeding 1000°C are not uncommon. In contrast, it is known that in cryogenic sputtering, GaN crystals including a light-emitting layer can be epitaxially grown on the graphene layer 1140 at temperatures as low as approximately 400°C to 700°C (see Non-Patent Literature 1, 2, etc.). This cryogenic sputtering method is suitable for forming the semiconductor layer 1150 on a circuit substrate with TFTs or the like, formed in an LTPS process.

[0156] A GaN semiconductor layer 1150 is grown on a graphene layer 1140 and a buffer layer 1145 using appropriate film-forming techniques. A single-crystallized semiconductor layer 1150, including a light-emitting layer 1152, is formed on the buffer layer 1145. Since the graphene layer 1140 is cut to an appropriate size and shape and disposed on the first surface 102a, the buffer layer 1145 does not grow in areas where the graphene layer 1140 is absent, but grows throughout the graphene layer 1140. Similarly, the semiconductor layer 1150 does not grow in areas where the buffer layer 1145 is absent, but grows throughout the buffer layer 1145. Although not shown, during the growth of the buffer layer 1145 and the semiconductor layer 1150, sometimes an amorphous deposit containing Al, Ga, or other materials serving as seed crystals is deposited in areas where the graphene layer 1140 is absent.

[0157] like Figure 6A As shown, Figure 5BThe semiconductor layer 1150 shown is etched into a desired shape to form a light-emitting element 150. In the formation process of the light-emitting element 150, a connecting portion 151a is formed, and then other portions are formed by further etching. Thus, a light-emitting element 150 having a connecting portion 151a protruding in one direction from the first surface 102a of the n-type semiconductor layer 151 can be formed. The light-emitting element 150 is formed, for example, using a dry etching process, preferably using anisotropic plasma etching (RIE). If deposits are formed at locations where the graphene layer 1140 is not present, the deposits are removed during the etching process of forming the light-emitting element 150.

[0158] Figure 5B The graphene layer 1140 shown is formed into a graphene sheet 140a with an outer peripheral shape that is approximately the same as the outer peripheral shape of the connecting part 151a by over-etching during the forming process of the connecting part 151a. Figure 5B The buffer layer 1145 shown is also formed by over-etching during the forming process of the connecting part 151a, so that the outer peripheral shape is approximately the same as the outer peripheral shape of the connecting part 151a.

[0159] like Figure 6B As shown, a first interlayer insulating film (first insulating film) 156 is formed by covering the first surface 102a, the graphene layer 140, the buffer layer 145, and the light-emitting element 150. The TFT lower layer film 106 is formed on the first interlayer insulating film 156, for example, by CVD or the like.

[0160] A TFT channel 104 is formed at a predetermined location on the lower TFT film 106. For example, in the LTPS process, the transistor 103 is formed as follows: First, an amorphous Si film is formed into the shape of the TFT channel 104. The amorphous Si film is formed, for example, by CVD. The formed amorphous Si film is polycrystalline by film laser annealing to form the TFT channel 104.

[0161] Subsequently, impurities such as boron (B) are introduced into regions 104s and 104d using techniques such as ion implantation to the source and drain electrodes of the TFT channel 104, thereby forming regions that are p-type semiconductors.

[0162] An insulating layer 105 is formed over the TFT lower layer film 106 and the TFT channel 104. The insulating layer 105 is formed, for example, by CVD. The gate 107 is formed on the TFT channel 104, with the insulating layer 105 in between. In the formation of the gate 107, an appropriate formation method is used depending on the material of the gate 107. For example, if the gate 107 is polycrystalline Si, it is formed by polycrystallineizing amorphous Si through laser annealing, similar to the TFT channel 104. Alternatively, the gate 107 can also be formed by etching a high-melting-point metal film such as W or Mo formed by sputtering.

[0163] A second interlayer insulating film (second insulating film) 108 is formed on the insulating layer 105 and the gate 107. In forming the second interlayer insulating film 108, an appropriate fabrication method is applied depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is formed of SiO2, techniques such as ALD and CVD are used.

[0164] The flatness of the second interlayer insulating film 108 can be sufficient to form the wiring layer 110 on the second interlayer insulating film 108, or it may not necessarily require a planarization process. By not performing a planarization process on the second interlayer insulating film 108, the number of processes can be reduced. For example, if there are areas around the light-emitting element 150 where the thickness of the second interlayer insulating film 108 is thinner, the depth of the via 162k (described later) becomes shallower, thus ensuring a sufficient opening diameter for the via. Therefore, it is easier to ensure electrical connections based on vias, and the decrease in yield caused by poor electrical characteristics can be suppressed.

[0165] Figure 7A As shown, via 162k is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 to reach the connection portion 151a. Opening 158 is formed to reach the light-emitting surface 153S by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156. Via 112d is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 to reach region 104d. Via 112s is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 to reach region 104s. The vias and openings are formed, for example, using a resonant interconnect (RIE).

[0166] like Figure 7B As shown, by sending Figure 7A The via 162k shown is filled with conductive material to form via 161k. Vias 111d and 111s are also formed by filling the via with conductive material. Figure 7AThe vias 112d and 112s shown are formed by filling them with conductive material. Then, a wiring layer 110 containing wirings 110k, 110d, and 110s is formed on the second interlayer insulating film 108. Wirings 110k, 110d, and 110s are connected to vias 161k, 111d, and 111s, respectively. The wiring layer 110 can also be formed simultaneously with the vias 161k, 111d, and 111s.

[0167] Figure 8A as well as Figure 8B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a variation of this embodiment.

[0168] Figure 8A as well as Figure 8B It shows the method for forming Figure 2 The process of sub-pixel 20a shown. In this case, the process up to forming the second interlayer insulating film 108 and forming vias 162k, 112d, and 112s is the same as the process described above. Hereinafter, it is assumed that in Figure 7A After the process, execute Figure 8A as well as Figure 8B The process will be explained in detail below.

[0169] like Figure 8A As shown, through holes 161k, 111d, and 111s pass through... Figure 7A The vias 162k, 112d, and 112s shown are formed by filling them with conductive material. Then, a wiring layer 110 containing wirings 110k, 110d1, and 110s is formed. Here, a portion of wiring 110d1 is connected to via 111d. On the other hand, another portion of wiring 110d1 is not directly connected to the light-emitting surface 153S, but is located away from the opening 158. Similar to the first embodiment, vias 161k, 111d, 111s, and wiring layer 110 can also be formed simultaneously.

[0170] like Figure 8B As shown, a light-transmitting electrode 159d is formed on the wiring 110d1 and the light-emitting surface 153S. As in this example, the light-emitting surface 153S is preferably roughened by wet etching or the like before forming the light-transmitting electrode 159d. Alternatively, the roughening process can be performed after forming the opening 158. The light-transmitting electrode 159d is also formed between the wiring 110d1 and the light-emitting surface 153S, electrically connecting the wiring 110d1 and the light-emitting surface 153S. A light-transmitting electrode 159s is formed on the wiring 110s. Light-transmitting electrodes 159d and 159s are formed simultaneously. When a light-transmitting electrode is formed on the wiring 110k, light-transmitting electrodes 159d and 159s are formed simultaneously.

[0171] Then, the upper structure, such as the color filter, is formed to form the sub-pixel 20a of the modified example of the image display device of the first embodiment.

[0172] For example Figure 3 The circuit is a driving circuit that drives the light-emitting element 150 by selecting transistor 24, driving transistor 26, and capacitor 28. This driving circuit is formed within the sub-pixels 20 and 20a. A portion of the circuitry outside the driving circuitry is formed outside the sub-pixels 20 and 20a, for example, at the periphery of the display area 2. Figure 3 The row selection circuit 5 shown is formed simultaneously with the driving transistor, selection transistor, etc., and is formed at the periphery of the display area 2. That is, the row selection circuit 5 can be assembled simultaneously through the above-described manufacturing process.

[0173] The signal voltage output circuit 7 is intended to be assembled into a semiconductor device manufactured through a highly integrated manufacturing process capable of micro-machining. The signal voltage output circuit 7 is mounted on another substrate along with the CPU and other circuit elements, for example, before or after the color filter is assembled, and is interconnected with the sub-pixels 20, 20a, for example, via connectors located at the periphery of the display area.

[0174] In the image display device 1 of this embodiment, each light-emitting element 150 can form an image in the display area 2 by emitting light upward from the light-emitting surface 153S. However, if light is scattered downward from the light-emitting surface 153S, the luminous efficiency is substantially reduced because the substrate 102 is transparent. Therefore, for example, a light-reflecting film or a light-reflecting plate can be provided on the surface opposite to the first surface 102a of the substrate 102, so that light scattered in the direction of the substrate 102 can be reflected in the direction of the light-emitting surface 153S. Such a light-reflecting film or the like can be provided on the substrate 102 or inside the housing, frame, or other components that fix the image display device 1.

[0175] Figure 9 This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0176] exist Figure 9 In the diagram above the arrow, the structure includes the color filter 180, and the structure below the arrow includes the light-emitting element 150 and the like formed through the above-described process. Figure 9 The arrows indicate the process of attaching the color filter to the structure containing the light-emitting element 150, etc.

[0177] exist Figure 9 To avoid clutter, components other than those on the substrate 102 shown in the illustration are omitted. The omitted components are... Figure 1The circuit 101 shown includes a TFT channel 104, a wiring layer 110, etc., and a via 161k. Additionally, in Figure 9 The image shows a portion of the color conversion components, such as the color filter 180. (In conjunction with...) Figures 9-10D In the relevant description, the structure including substrate 102, light-emitting element 150, first interlayer insulating film 156, TFT lower layer film 106, insulating layer 105, second interlayer insulating film 108, surface resin layer 170, and the display components are referred to as structure 1192.

[0178] like Figure 9 As shown, the color filter (wavelength conversion component) 180 is bonded to the structure 1192 with one side attached. The other side of the color filter 180 is bonded to the glass substrate 186. A transparent film adhesive layer 188 is provided on one side of the color filter 180, and the transparent film adhesive layer 188 is bonded to the exposed surface of the surface resin layer 170 of the structure 1192.

[0179] In this example, the color filter 180 has color conversion units arranged in the positive direction of the X-axis in the order of red, green, and blue. For red, a red color conversion layer 183R is provided in the first layer; for green, a green color conversion layer 183G is provided in the first layer; and both are provided with filter layers 184 in the second layer. For blue, a single color conversion layer 183B or a filter layer 184 can be provided. A light-blocking part 181 is provided between each color conversion unit, but the frequency characteristics of the filter layer 184 can of course be changed according to each color of the color conversion unit.

[0180] The positions of the color conversion layers 183R, 183G, and 183B are aligned with the position of the light-emitting element 150, and the color filter 180 is adhered to the structure 1192.

[0181] Figures 10A to 10D This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to this embodiment.

[0182] Figures 10A to 10D The image shows a method for forming color filters using inkjet printing.

[0183] like Figure 10A As shown, a structure 1192 with light-emitting elements such as light-emitting elements 150 is prepared to be formed on a substrate 102.

[0184] like Figure 10B As shown, a light-shielding portion 181 is formed on the structure 1192. The light-shielding portion 181 is formed, for example, using screen printing, photolithography, or other techniques.

[0185] like Figure 10CAs shown, a phosphor corresponding to the emitted color is ejected from the inkjet nozzle to form a color conversion layer 183. The phosphor colors the areas where the light-shielding portion 181 is not formed. The phosphor uses a fluorescent coating material, such as a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material. Using perovskite phosphor materials or quantum dot phosphor materials allows for the realization of various emitted colors and provides high monochromaticity, thus improving color reproducibility; therefore, this is preferred. After drawing using the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0186] As already explained, for blue emitting subpixels, the color conversion layer 183 is not formed if a color conversion section is not formed. Furthermore, for blue emitting subpixels, when forming a blue color conversion layer, if the color conversion section can be a single layer, it is preferable that the thickness of the blue phosphor coating is the same as the thickness of the light-shielding section 181.

[0187] like Figure 10D As shown, the paint for the filter layer 184 is ejected from the inkjet nozzle. The paint is applied overlappingly to the phosphor coating. The combined thickness of the phosphor and the paint coating is the same as the thickness of the light-shielding portion 181.

[0188] Whether it's a thin-film color filter or an inkjet color filter, to improve color conversion efficiency, it's desirable for the color conversion layer 183 to be as thick as possible. On the other hand, if the color conversion layer 183 is too thick, the emitted light after color conversion approximates a Lambert, while the blue light that hasn't undergone color conversion is restricted in its emission angle by the light-shielding portion 181. This results in a viewing angle dependence problem in the displayed color of the image. To ensure that the light distribution of the subpixels where the color conversion layer 183 is located is consistent with the light distribution of the blue light that hasn't undergone color conversion, it's desirable that the thickness of the color conversion layer 183 is approximately half the opening size of the light-shielding portion 181.

[0189] For example, in the case of a high-resolution image display device with a resolution of around 250 ppi (pitch per inch), the spacing between subpixels 20 is approximately 30 μm, therefore the thickness of the color conversion layer 183 is expected to be around 15 μm. Here, when the color conversion material is composed of spherical phosphor particles, it is preferable to stack them in the densest possible configuration to suppress light leakage from the light-emitting element 150. Therefore, at least three layers of particles are required. Consequently, the particle diameter of the phosphor material constituting the color conversion layer 183 is preferably, for example, around 5 μm or less, and more preferably around 3 μm or less.

[0190] Figure 11 This is a schematic perspective view illustrating the image display device of this embodiment.

[0191] like Figure 11 As shown, the image display device of this embodiment has a light-emitting circuit section 172 having a plurality of sub-pixels 20 on the substrate 102. A color filter 180 is provided on the light-emitting circuit section 172. Regarding other embodiments and variations described later, it also has the same characteristics as... Figure 11 The configuration shown is the same.

[0192] The effects of the image display device 1 in this embodiment will be explained.

[0193] In the manufacturing method of the image display device 1 of this embodiment, a light-emitting element 150 is formed by etching a semiconductor layer 1150 crystallized and grown on a substrate 102. Then, the light-emitting element 150 is covered with a first interlayer insulating film 156, and a circuit 101 including circuit elements such as a transistor 103 driving the light-emitting element 150 is fabricated on the first interlayer insulating film 156. Therefore, compared to the case where the monolithically formed light-emitting elements are individually transferred to the substrate 102, the manufacturing process can be significantly shortened.

[0194] In the manufacturing method of the image display device 1 of this embodiment, the graphene layer 1140 formed on the substrate 102 can serve as a seed crystal for the crystallization growth of the buffer layer 1145 and the semiconductor layer 1150. When the first surface 102a of the substrate 102 is sufficiently flat, the graphene layer 1140 can be easily adsorbed and fixed on the first surface 102a. Therefore, the manufacturing process can be simplified, and the manufacturing process can be carried out without contaminating the production site, achieving substantially high production performance.

[0195] For example, in a 4K image quality display device, the number of subpixels exceeds 24 million, and in an 8K image quality display device, the number exceeds 99 million. Forming such a large number of light-emitting elements and mounting them on a circuit board requires a significant amount of time. Therefore, it is difficult to realize a micro-LED-based image display device at a realistic cost. Furthermore, if a large number of light-emitting elements are mounted separately, poor connections during installation can lead to a lower yield rate and further increases in cost.

[0196] In contrast, in the manufacturing method of the image display device 1 of this embodiment, the light-emitting element 150 is formed after the semiconductor layer 1150 is deposited on the graphene layer 1140 formed on the substrate 102. Therefore, the transfer process of the light-emitting element 150 can be reduced. Thus, in the manufacturing method of the image display device 1 of this embodiment, the transfer process time can be shortened and the number of processes can be reduced compared to the conventional manufacturing method.

[0197] A semiconductor layer 1150 with a uniform crystalline structure is grown on a buffer layer 1145 formed on a graphene layer 1140. Therefore, by appropriately patterning the graphene layer 1140, the light-emitting element 150 can be self-aligned. Thus, there is no need to align the light-emitting element on the substrate 102, and the miniaturization of the light-emitting element 150 is also easy, making it suitable for high-resolution displays.

[0198] After the light-emitting element is directly formed on the substrate 102 by etching or the like, the light-emitting element 150 and the circuit elements formed on the upper layer of the light-emitting element 150 are electrically connected through through holes. Therefore, a uniform connection structure can be achieved, and the decrease in yield can be suppressed.

[0199] In this embodiment, for example, an interlayer insulating film can be used to cover the glass substrate formed as described above, and a driving circuit including TFTs and scanning circuits can be formed on the planarized surface using a process such as LTPS. Therefore, it has the advantage of being able to utilize existing flat panel display manufacturing processes and complete sets of equipment.

[0200] In this embodiment, the light-emitting element 150, formed on a layer lower than transistor 103, can be electrically connected to power lines, ground lines, driving transistors, etc., formed on the upper layer by forming through-holes that penetrate the first interlayer insulating film 156, the lower TFT film 106, the insulating layer 105, and the second interlayer insulating film 108. By using this technically established multilayer wiring technology, a uniform connection structure can be easily achieved, and the yield rate can be improved. Therefore, the decrease in yield rate caused by poor connection of the light-emitting element, etc., can be suppressed.

[0201] (Second Implementation)

[0202] Figure 12 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0203] This embodiment differs from the other embodiments described above in that the light-reflecting layer 120, including the light reflector 120a, is disposed on the first surface 102a, and the light-emitting element 150 is disposed on the light reflector 120a via the insulating layer 114. This embodiment also differs from the other embodiments described above in that the n-type semiconductor layer 251 provides the light-emitting surface 251S. Furthermore, this embodiment differs from the other embodiments in that it has a configuration that uses an n-type transistor 203 to drive the light-emitting element 250. The same reference numerals are used for components that are the same as in other embodiments, and detailed descriptions are omitted where appropriate.

[0204] like Figure 12As shown, the sub-pixel 220 of the image display device in this embodiment includes a substrate 102, a light-reflecting layer 120, a graphene layer 140, a light-emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 261a, and a wiring layer 110.

[0205] A light-reflecting layer 120 is disposed on the first surface 102a. The light-reflecting layer 120 includes a light-reflecting plate 120a. The light-reflecting plate (first part) 120a is disposed on the first surface 102a and is a film-like, layer-like, or plate-like component with a square or arbitrary polygonal, elliptical, circular, or other shapes when viewed from above on the XY plane.

[0206] The light-reflecting layer 120 includes a plurality of light-reflecting plates 120a, which in this example are arranged for each light-emitting element 250. In this example, the plurality of light-reflecting plates 120a are separate, but they can also be connected to each other.

[0207] The outer periphery of the light reflector 120a is configured such that, when viewed from above on the XY plane, it includes the outer periphery of the light-emitting element 250 when the projection light-emitting element 250 is included. That is, when viewed from above on the XY plane, the outer periphery of the light-emitting element 250 is disposed within the outer periphery of the light reflector 120a. The light reflector 120a can be provided with one light-emitting element 250 or with one light-emitting element 250 among multiple light-emitting elements 250. Multiple light reflectors 120a may not be separated individually, but may be connected in a grid-like arrangement. The light reflecting layer 120 may also have a single light reflector 120a. A single light reflector 120a is provided, for example, in the following description... Figure 13 The entire surface of display area 2 shown.

[0208] The light reflector 120a is made of a material that has light reflectivity. For example, the light reflector 120a is formed of a metallic material such as Ag or an alloy containing Ag. It is not limited to materials with light reflectivity such as Ag; any suitable material can be used.

[0209] An insulating layer 114 is provided over the first surface 102a, the light-reflecting layer 120, and the light-reflecting plate 120a. The insulating layer 114 is formed of an oxide film such as SiO2. The insulating layer 114 is provided to insulate the light-reflecting plate 120a from the light-emitting element 250. In addition, the insulating layer 114 provides a planarized surface for forming the graphene sheet 140a.

[0210] A graphene layer 140, comprising a graphene sheet 140a, is disposed on an insulating layer 114. A light reflector 120a is disposed between the first surface 102a and the graphene layer 140. A light-emitting element 250 is disposed on the light reflector 120a via the graphene sheet 140a and the insulating layer 114. The light-emitting element 250 is positioned directly above the light reflector 120a.

[0211] Because of this light reflector 120a, light scattered downwards from the light-emitting element 250 is reflected upwards by the light reflector 120a. Therefore, the luminous efficiency of the light-emitting element 250 is substantially improved.

[0212] The light-emitting element 250 includes a light-emitting surface 251S. The light-emitting element 250 is a prism-shaped or cylindrical element having a bottom surface 253B on a first surface 102a. The light-emitting surface 251S is the surface opposite to the bottom surface 253B. The bottom surface 253B is the surface that is in contact with the graphene sheet 140a.

[0213] The light-emitting element 250 includes a p-type semiconductor layer (first semiconductor layer) 253, a light-emitting layer 252, and an n-type semiconductor layer (second semiconductor layer) 251. The p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 are stacked sequentially from the bottom surface 253B toward the light-emitting surface 251S. In this embodiment, the light-emitting surface 251S is provided by the n-type semiconductor layer 251. The n-type semiconductor layer 251 can have a lower resistance value than the p-type semiconductor layer 253, and therefore its thickness can be increased. Therefore, roughening of the light-emitting surface 251S becomes easier.

[0214] The light-emitting element 250 includes a connecting portion 253a. The connecting portion 253a is disposed on the insulating layer 114, protruding in one direction from the p-type semiconductor layer 253. Similar to other embodiments described above, the connecting portion 253a can protrude in multiple directions or extend throughout the outer periphery of the p-type semiconductor layer 253. The height of the connecting portion 253a is the same as or lower than the p-type semiconductor layer 253, and the light-emitting element 250 is formed in a stepped shape. The connecting portion 253a is p-type and electrically connected to the p-type semiconductor layer 253. The connecting portion 253a is connected to one end of a through-hole 261a, electrically connecting the p-type semiconductor layer 253 to the through-hole 261a.

[0215] The light-emitting element 250 has the same shape in the XY plane as the light-emitting element 150 in the other embodiments described above. An appropriate shape is selected based on the layout of the circuit elements, etc. The shape of the light reflector 120a in the XY plane can be any shape as described above; an appropriate shape is selected based on the layout of the circuit elements, etc.

[0216] The light-emitting element 250 is the same light-emitting diode as the light-emitting element 150 in the other embodiments described above. That is, the wavelength of the light emitted by the light-emitting element 250 is, for example, blue light emitting at approximately 467nm ± 30nm, or blue-violet light emitting at approximately 410nm ± 30nm. The wavelength of the light emitted by the light-emitting element 250 is not limited to the above values ​​and can be any appropriate wavelength.

[0217] Transistor 203 is disposed on the lower TFT film 106. Transistor 203 is an n-channel TFT. Transistor 203 includes a TFT channel 204 and a gate 107. Preferably, transistor 203 is formed by an LTPS process or the same as in other embodiments described above. In this embodiment, circuit 101 includes a TFT channel 204, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a wiring layer 110.

[0218] The TFT channel 204 includes regions 204s, 204i, and 204d. Regions 204s, 204i, and 204d are disposed on the lower TFT film 106. Regions 204s and 204d are doped with impurities such as phosphorus (P) through ion implantation to form p-type semiconductor regions. Region 204s is ohmically connected to via 111s. Region 204d is ohmically connected to via 111d.

[0219] The gate 107 is disposed on the TFT channel 204 through an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

[0220] In transistor 203, if a voltage higher than that in region 204s is applied to gate 107, a channel is formed in region 204i. The current flowing through regions 204s and 204d is controlled by the voltage applied to gate 107 in region 204s. TFT channel 204 and gate 107 are formed of the same material and fabrication method as in the other embodiments described above.

[0221] Routing layer 110 includes routing layers 110s, 110d1, and 210a. Routing layers 110s and 110d1 are... Figure 2 The situation is the same as in the variation of the first embodiment described above. A portion of the wiring 210a is provided above the connecting portion 253a. Other portions of the wiring 210a extend, for example, to the portion described later. Figure 13 The power cord 3 shown is connected to the power cord 3.

[0222] Through-holes 111s and 111d are provided through the second interlayer insulating film 108. Through-hole 111s is located between wiring 110s and region 204s. Through-hole 111s electrically connects wiring 110s and region 204s. Through-hole 111d is located between wiring 110d1 and region 204d. Through-hole 111d electrically connects wiring 110d1 and region 204d. Through-holes 111s and 111d are formed from the same material and using the same manufacturing method as in the other embodiments described above.

[0223] The through-hole 261a is provided to pass through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The through-hole 261a is provided between the wiring 210a and the connecting part 253a, and electrically connects the wiring 210a and the connecting part 253a.

[0224] Wiring 110s, for example, electrical connections as described later. Figure 13 The grounding wire 4 is shown. Wiring 110d1 is electrically connected to the n-type semiconductor layer 251 via the light-transmitting electrode 159d.

[0225] In this embodiment, the light-transmitting electrode 159d is provided throughout the light-emitting surface 251S of the roughened n-type semiconductor layer 251. The light-transmitting electrode 159d is also provided throughout the wiring 110d1. The light-transmitting electrode 159d is also provided between the light-emitting surface 251S and the wiring 110d, electrically connecting the n-type semiconductor layer 251 and the wiring 110d.

[0226] As with the other embodiments described above, it is also possible to... Figure 1 As shown in the example, the extended wiring 110d is directly connected to the n-type semiconductor layer 251.

[0227] Figure 13 This is a schematic block diagram illustrating the image display device of this embodiment.

[0228] like Figure 13 As shown, the image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in other embodiments described above, for example, the sub-pixels 220 are arranged in a grid pattern on the XY plane.

[0229] Pixel 10, like the other embodiments described above, includes multiple sub-pixels 220 that emit light of different colors. Sub-pixel 220R emits red light. Sub-pixel 220G emits green light. Sub-pixel 220B emits blue light. The three sub-pixels 220R, 220G, and 220B emit light at a desired brightness, thereby determining the emission color and brightness of pixel 10.

[0230] A pixel 10 contains three subpixels 220R, 220G, and 220B, which are arranged in a straight line along the X-axis, as shown in this example. Each pixel 10 can arrange subpixels of the same color in the same column, or it can arrange subpixels of different colors in each column, as shown in this example.

[0231] Subpixel 220 includes a light-emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. Figure 13In the text, sometimes the select transistor 224 is shown as T1, the drive transistor 226 is shown as T2, and the capacitor 228 is shown as Cm.

[0232] In this embodiment, the light-emitting element 222 is disposed on the power line 3 side, and the driving transistor 226, which is connected in series with the light-emitting element 222, is disposed on the ground line 4 side. That is, the driving transistor 226 is connected to a side with a lower potential than the light-emitting element 222. The driving transistor 226 is an n-channel transistor.

[0233] A select transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. A capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

[0234] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity to the signal line 208 in order to drive the driving transistor 226, which is an n-channel transistor. This is different from the other embodiments described above.

[0235] In this embodiment, since the driving transistor 226 is n-channel, the polarity of the signal voltage differs from that in the other embodiments described above. Specifically, the row selection circuit 205 supplies a selection signal to the scan line 206 to sequentially select one row from the arrangement of m rows of sub-pixels 220. The signal voltage output circuit 207 supplies a signal voltage with the desired analog voltage value to each sub-pixel 220 of the selected row. The driving transistor 226 of the selected row's sub-pixel 220 causes a current corresponding to the signal voltage to flow through the light-emitting element 222. The light-emitting element 222 emits light with a brightness corresponding to the current flowing through it.

[0236] The manufacturing method of the image display device according to this embodiment will be described.

[0237] Figures 14A to 17B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0238] like Figure 14A As shown, a light-reflecting layer 120 is formed on the first surface 102a. The light-reflecting layer 120 can be formed by sputtering or the like, or by applying Ag paste or the like into the shape of a light-reflecting plate 120a and then firing it. The light-reflecting plate (first part) 120a of the light-reflecting layer 120 is provided at the position where the light-emitting element 250 is formed.

[0239] like Figure 14BAs shown, the insulating layer 114 is formed over the first surface 102a and the light-reflecting layer 120. The insulating layer 114 is formed by CVD or the like. In order to adsorb and adhere the graphene layer 1140, the exposed surface of the insulating layer 114 is preferably planarized using CMP (Chemical Mechanical Polishing) or the like.

[0240] like Figure 14C As shown, a graphene layer 1140 is formed on the insulating layer 114. Preferably, the graphene layer 1140 is then cut to a size sufficiently large compared to the area of ​​the light-emitting element 250 formed on the graphene layer 1140, and adsorbed and adhered to the insulating layer 114.

[0241] like Figure 15A As shown, a semiconductor layer 1150 is formed over the graphene layer 1140. The semiconductor layer 1150 consists of a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151, sequentially formed from the graphene layer 1140 in the positive Z-axis direction. In this embodiment, the semiconductor layer 1150 is formed starting from the p-type semiconductor layer 1153, unlike in the other embodiments described above, but it can be formed using the same techniques as in the other embodiments. That is, physical vapor deposition (PVD) is used, preferably cryogenic sputtering. Alternatively, physical vapor deposition methods such as evaporation, ion beam deposition, and MBE can also be used to form the semiconductor layer 1150.

[0242] In addition, a deposit containing the growth type of material is deposited in the area where the graphene layer 1140 is not present, which is the same as in the other embodiments described above.

[0243] like Figure 15B As shown, the light-emitting element 250 transmits light through... Figure 15A The semiconductor layer 1150 shown is formed into a desired shape through dry etching and other processes. In the formation process of the light-emitting element 250, the connecting portion 253a is formed, and then other portions are formed through further etching. Figure 15A The graphene layer 1140 shown was over-etched during the formation of the connection portion 253a. Therefore, the outer periphery of the graphene sheet 140a is shaped to be approximately consistent with the outer periphery of the light-emitting element 250.

[0244] he Figure 16A As shown, the first interlayer insulating film 156 is formed by covering the graphene layer 140, the insulating layer 114, and the light-emitting element 250.

[0245] like Figure 16BAs shown, a TFT lower layer 106 is formed on the first interlayer insulating film 156 by CVD or the like. A TFT channel 204 is formed on the planarized TFT lower layer 106. An insulating layer 105 is formed covering the TFT lower layer 106 and the TFT channel 204. A gate 107 is formed on the TFT channel 204 via the insulating layer 105. A second interlayer insulating film 108 covers the insulating layer 105 and the gate 107.

[0246] like Figure 17A As shown, via 162a is formed to penetrate the second interlayer insulating film 108, insulating layer 105, TFT lower layer film 106, and first interlayer insulating film 156 to reach the surface of connection portion 253a. Opening 158 is formed to reach the light-emitting surface 251S by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156. After forming opening 158, the light-emitting surface 251S may also be roughened. Via 112d is formed to penetrate the second interlayer insulating film 108 and insulating layer 105 to reach region 204d. Via 112s is formed to penetrate the second interlayer insulating film 108 and insulating layer 105 to reach region 204s. Via and opening are formed, for example, using a resonant interconnect (RIE).

[0247] like Figure 17B As shown, through hole 261a allows for the connection of... Figure 17A The through-hole 162a shown is formed by filling it with conductive material. Through-holes 111d and 111s are also formed by... Figure 17A The vias 112d and 112s shown are formed by filling them with conductive material. Then, a wiring layer 110 containing wirings 210a, 110d1, and 110s is formed. Wirings 210a, 110d1, and 110s are connected to vias 261a, 111d, and 111s, respectively. The wiring layer 110 can also be formed simultaneously with the vias 261a, 111d1, and 111s.

[0248] A transparent conductive film, including transparent electrodes 159d and 159s, is formed by covering a second interlayer insulating film 108, a light-emitting surface 251S, and a wiring layer 110. Transparent electrodes 159d are formed throughout the wiring 110d1 and the light-emitting surface 251S, and are also formed between the wiring 110d1 and the light-emitting surface 251S to electrically connect them. Transparent electrodes 159s are formed throughout the wiring 110s. Although not shown in this embodiment, transparent electrodes may also be formed on the wiring 210a.

[0249] Then, by setting a color filter (wavelength conversion component) 180, etc., the sub-pixels 220 of the image display device 201 of this embodiment are formed.

[0250] The effects of the image display device in this embodiment will be explained.

[0251] In the image display device of this embodiment, similar to the other embodiments described above, in addition to shortening the transfer process time for forming the light-emitting element 250 and reducing the number of processes, the light-emitting surface 251S can be sufficiently roughened by making the n-type semiconductor layer 251 the light-emitting surface 251S. Therefore, the luminous efficiency is improved, and the increase in losses caused by contact resistance can be suppressed.

[0252] (Third Implementation)

[0253] Figure 18 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0254] In this embodiment, the light-emitting element 250, which uses an n-type semiconductor layer 251 as its light-emitting surface 251S, is driven by a p-type transistor 103, unlike the other embodiments described above. The same reference numerals are used for components that are identical to those in the other embodiments described above, and detailed descriptions are omitted where appropriate.

[0255] like Figure 18 As shown, the sub-pixel 320 of the image display device in this embodiment includes a substrate 102, a light-reflecting layer 120, a graphene layer 140, a light-emitting element 250, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 361a, and a wiring layer 110. The transistor 103 is a p-channel TFT. The light-emitting element 250 provides a light-emitting surface 251S based on an n-type semiconductor layer 251.

[0256] The light-emitting element 250 is disposed on the light-reflecting plate 120a, separated from the graphene sheet 140a and the insulating layer 114. The light-reflecting plate 120a is configured in the same way as in the other embodiments described above. The light-reflecting plate 120a is disposed directly below the light-emitting element 250. The outer periphery of the light-reflecting plate 120a is configured such that, when viewed from above in the XY plane, it includes the outer periphery of the light-emitting element 250 when projecting onto it. The light-reflecting plate 120a reflects scattered light downwards from the light-emitting element 250 toward the light-emitting surface 251S, substantially improving the luminous efficiency.

[0257] The light-emitting element 250 is a prism-shaped or cylindrical element having a bottom surface 253B on the first surface 102a. The light-emitting surface 251S is the surface opposite to the bottom surface 253B. The bottom surface 253B is the surface that is in contact with the graphene sheet 140a.

[0258] The light-emitting element 250 includes a p-type semiconductor layer (first semiconductor layer) 253, a light-emitting layer 252, and an n-type semiconductor layer (second semiconductor layer) 251. The p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 are stacked sequentially from the bottom surface 253B toward the light-emitting surface 251S. The p-type semiconductor layer 253 includes a connecting portion 253a. The connecting portion 253a is provided such that it protrudes from the p-type semiconductor layer 253 in one direction on the insulating layer 114. The connecting portion 253a is connected to one end of a through-hole 361a, electrically connecting the p-type semiconductor layer 253 to the through-hole 361a.

[0259] The configuration of transistor 103 is the same as in the first embodiment. Detailed description of the configuration of transistor 103 is omitted.

[0260] Wiring layer 110 is formed on the second interlayer insulating film 108. Wiring layer 110 includes wirings 310k, 310a, 110d1, and 110s. Wirings 310a and 310k are disposed above and close to the light-emitting element 250. Wiring 310a is disposed above the connecting portion 253a. Wiring 310k is disposed at a position that does not intersect with wiring 310a.

[0261] The through-hole 361a is provided through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The through-hole 361a is provided between the wiring (third wiring) 310a and the connecting part 253a. The through-hole 361a electrically connects the wiring 310a and the connecting part 253a.

[0262] The through holes 111d and 111s are provided in the same manner as in the other embodiments described above.

[0263] A light-transmitting electrode 359k is disposed throughout the wiring 310k. The light-transmitting electrode 359k is also disposed throughout the light-emitting surface 251S. The light-transmitting electrode 359k is also disposed between the wiring 310k and the light-emitting surface 251S, electrically connecting the wiring 310k and the light-emitting surface 251S. The wiring 310k and the light-transmitting electrode 359k are connected, for example, to... Figure 3 The grounding wire 4 is shown. Therefore, the n-type semiconductor layer 251 is electrically connected to the grounding wire 4 via the light-emitting surface 251S, the light-transmitting electrode 359k, and the wiring (fourth wiring) 310k.

[0264] A light-transmitting electrode 359d is provided throughout the wiring 310a. A light-transmitting electrode 359d is also provided throughout the wiring 110d1. A light-transmitting electrode 359k is also provided between the wiring 310a and the wiring 110d1, electrically connecting the wiring 310a and the wiring 110d1. Therefore, the p-type semiconductor layer 253 is electrically connected to region 104d via the connection portion 253a, the via 361a, the wiring 310a, the light-transmitting electrode 359d, the wiring 110d1, and the via 111d.

[0265] A light-transmitting electrode 159s is disposed along the wiring 110s. The wiring 110s and the light-transmitting electrode 159s are, for example, connected to... Figure 3 The power line 3 is shown. Therefore, region 104s of transistor 103 is electrically connected to power line 3 via via 111s, wiring 110s, and transparent electrode 159s.

[0266] The through holes 361a, 111d, 111s and the wiring 310k, 310a, 110d1, 110s are formed from the same materials and manufacturing methods as in the other embodiments and their variations described above.

[0267] Similar to the other embodiments described above, a color filter 180 is also provided.

[0268] The manufacturing method of the image display device according to this embodiment will be described.

[0269] Figures 19A to 20B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0270] On a substrate 102 on which a light-reflecting layer 120 and an insulating layer 114 are formed, a graphene layer 1140 is formed, and a semiconductor layer 1150 is formed on the graphene layer 1140. Up to this point, the same process as in the second embodiment can be used. Hereinafter, [the process described in the second embodiment] will be further explained. Figure 15A Execute in subsequent processes Figures 19A to 20B The process details will be explained.

[0271] like Figure 19A As shown, Figure 15A The semiconductor layer 1150 shown is processed into a desired shape to form a light-emitting element 250. After the connection portion 253a is formed, other portions are formed on the light-emitting element 250. Figure 15A The graphene layer 1140 shown was over-etched during the formation of the connection portion 253a, and the graphene sheet 140a was shaped to have an outer periphery that substantially coincides with the outer periphery of the light-emitting element 250. In this example, the connection portion 253a and the graphene sheet 140a are formed to protrude in one direction on the insulating layer 114 when viewed from the light-emitting surface 251S.

[0272] like Figure 19B As shown, a first interlayer insulating film 156 is formed to cover the insulating layer 114, the graphene sheet 140a, and the light-emitting element 250. Similar to the first embodiment, a TFT lower layer film 106 is formed, a TFT channel 104 is formed, an insulating layer 105 is formed, and a gate 107 is formed. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

[0273] like Figure 20A As shown, the through-hole 362a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 to reach the connection portion 253a. The opening 158 and the through holes 112d and 112s are formed in the same way as in the other embodiments described above.

[0274] like Figure 20B As shown, Figure 20A The vias 362a, 112d, and 112s shown are filled with conductive material to form vias 361a, 111d, and 111s. A wiring layer 110, including wirings 310k, 310a, 110d1, and 110s, is formed on the second interlayer insulating film 108. Wirings 310a, 110d1, and 110s are respectively connected to vias 361a, 111d, and 111s. A light-transmitting conductive film is formed on the wiring layer 110, forming light-transmitting electrodes 359k, 359d, and 159s. Light-transmitting electrode 359k is formed throughout wiring 310k and the light-emitting surface 251S, and also between wiring 310k and the light-emitting surface 251S. Light-transmitting electrode 359d is formed throughout wiring 310a and wiring 110d1, and also between wiring 310a and wiring 110d1. The light-transmitting electrode is formed by spreading the wiring over the wires for 159s.

[0275] According to the image display device of this embodiment, a circuit configuration can be formed in which the n-type semiconductor layer 251 is the light-emitting surface 251S and the light-emitting element 250 is driven by the p-channel transistor 103. Therefore, the freedom in circuit configuration and circuit layout is increased, and the design period of the image display device can be shortened.

[0276] (Fourth Implementation)

[0277] Figure 21 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0278] The image display device of this embodiment replaces the glass substrate with a flexible substrate 402. Light-emitting elements and circuit elements such as transistors are formed on the first surface 402a of the substrate 402. Other aspects are the same as in the other embodiments described above, and the same reference numerals are used to refer to the same constituent elements, and detailed descriptions are omitted where appropriate.

[0279] like Figure 21 As shown, the image display device of this embodiment includes a sub-pixel 420. The sub-pixel 420 includes a substrate 402. The substrate 402 includes a first surface 402a. When the substrate 402 is made of a resin such as polyimide resin, a layer 113 containing a silicon compound such as SiO2 is formed on the first surface 402a. The silicon compound layer 113 is disposed between the substrate 402 and the graphene layer 140. A light-reflecting layer 120 and a light-reflecting plate 120a are formed on the silicon compound layer 113. The silicon compound layer 113 is provided to improve the adhesion between the resin-formed substrate 402 and the light-reflecting layer 120 formed of a metal material.

[0280] An insulating layer 114 is formed over the silicon compound layer 113 and the light-reflecting layer 120. The insulating layer 114 is planarized by CMP or the like.

[0281] The light-emitting element 250 is disposed on the light reflector 120a via the graphene sheet 140a and the insulating layer 114. In this example, the structure and constituent elements above the insulating layer 114 are the same as in the second embodiment described above, and detailed description is omitted.

[0282] The substrate 402 is flexible. The substrate 402 is formed, for example, from polyimide resin. The first interlayer insulating film 156, the second interlayer insulating film 108, and the wiring layer 110 are preferably formed from materials with a certain degree of flexibility, corresponding to the flexibility of the substrate 402. Furthermore, the wiring layer 110, having the longest wiring length, is at the highest risk of damage during bending. When the image display device is bent, the inner surface is subjected to compressive stress and shrinks, while the outer surface is subjected to elongation stress and stretches. A neutral surface exists inside the image display device where the stresses of both sides cancel each other out, and no stretching or contraction due to bending stress occurs on this neutral surface. Therefore, by placing the wiring layer 110 on the neutral surface, the risk of damage to the wiring layer 110 can be avoided. If necessary, multiple protective films can also be provided on the surface and back of the image display device to reduce bending stress. Furthermore, it is preferable to adjust the thickness, film quality, and material of these protective films so that the neutral surface overlaps with the wiring layer 110.

[0283] In this example, the structure and constituent elements above the insulating layer 114 are the same as in the second embodiment, but other embodiments or variations are also possible.

[0284] The manufacturing method of the image display device according to this embodiment will be described.

[0285] Figure 22A as well as Figure 22B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0286] like Figure 22A As shown, in this embodiment, a substrate 1002 is prepared that differs from the other embodiments described above. The substrate (first substrate) 1002 includes two substrates 102 and 402. The substrate 102 is a light-transmitting substrate, such as a glass substrate. The substrate (second substrate) 402 is disposed on the first surface 102a of the substrate 102. For example, the substrate 402 is formed by coating a polyimide material onto the first surface 102a of the substrate 102 and then firing it. Alternatively, SiN can be formed on the substrate 102 before forming the substrate 402. x Inorganic films are used. In this case, substrate 402 is formed by coating an inorganic film with a polyimide material and then firing it. A layer 113 containing a silicon compound is formed over a first surface 402a of substrate 402. The first surface 402a of substrate 402 is the side opposite to the surface on which substrate 102 is provided.

[0287] For example, this substrate 1002 is used in applications such as Figures 14A to 17B , Figures 9-10D The above-mentioned processes are used to form the upper structure of sub-pixel 420.

[0288] like Figure 22B As shown, substrate 102 is removed from a structure having an upper structure including color filters (not shown). The removal of substrate 102 is performed, for example, by laser stripping.

[0289] The substrate 102 can be removed at any appropriate time, not limited to the time mentioned above. In cases where the substrate 402 is made of organic resin and a high-temperature process follows the removal of the substrate 102, there is a concern that the substrate 402 may shrink due to the heat from this process. Therefore, it is preferable that the substrate 102 be removed in a process following such a high-temperature process. For example, it is preferable that the substrate 102 be removed after the process of forming the wiring layer 110 is completed. By removing the substrate 102 at an appropriate time, defects such as cracks and defects during the manufacturing process can sometimes be reduced.

[0290] The effects of the image display device in this embodiment will be explained.

[0291] In addition to shortening the transfer process time for forming the light-emitting element 150 and reducing the number of processes, as in the other embodiments described above, the image display device of this embodiment also has the following effects. That is, since the substrate 402 is flexible, it can be bent as an image display device, and can be adhered to curved surfaces and used in wearable terminals without any sense of disharmony.

[0292] (Fifth Implementation)

[0293] Figure 23 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0294] In this embodiment, by forming multiple light-emitting surfaces 551S1 and 551S2 on a single semiconductor layer 550 containing a light-emitting layer, an image display device with higher luminous efficiency is achieved. In the following description, the same reference numerals are used to denote the same components as in other embodiments described above, and detailed descriptions are omitted where appropriate.

[0295] like Figure 23 As shown, the image display device of this embodiment includes a subpixel group 520. The subpixel group 520 includes a substrate 102, a light-reflecting layer 120, a graphene layer 140, a semiconductor layer 550, a first interlayer insulating film 156, a plurality of transistors 103-1 and 103-2, a second interlayer insulating film 108, a plurality of vias 561a1 and 561a2, and a wiring layer 110. In this embodiment and its variations, the reference numerals for the light-reflecting layer 120 are shown side-by-side with the reference numerals for the light-reflecting plate 530. The reference numerals for the graphene layer 140 are also shown side-by-side with the reference numerals for the graphene sheet 540.

[0296] A semiconductor layer 550 is disposed on the first surface 102a of the substrate 102. In this example, a light-reflecting layer 120 is disposed between the substrate 102 and the semiconductor layer 550. The light-reflecting layer 120 is disposed on the first surface 102a. The light-reflecting layer 120 includes a light-reflecting plate 530. An insulating layer 114 covers the first surface 102a, the light-reflecting layer 120, and the light-reflecting plate 530. The insulating layer 114 is planarized.

[0297] In this embodiment, by turning on the p-channel transistors 103-1 and 103-2, holes are injected from one side of the semiconductor layer 550 via the wiring layer 110 and vias 561a1 and 561a2. By turning on the p-channel transistors 103-1 and 103-2, electrons are injected from the other side of the semiconductor layer 550 via the wiring layer 110. The semiconductor layer 550 is injected with holes and electrons, and the light-emitting layer 552 emits light through the combination of holes and electrons. A driving circuit for driving the light-emitting layer 552 is, for example, suitable for… Figure 3The circuit configuration shown is also possible. Alternatively, using other embodiments described above, the n-type and p-type semiconductor layers can be replaced vertically to drive the semiconductor layers using an n-channel transistor. In this case, the driving circuit is suitable for… Figure 13 The circuit configuration.

[0298] The composition of subpixel group 520 is explained in detail.

[0299] The graphene layer 140 includes a graphene sheet 540. The graphene sheet 540 is disposed on the insulating layer 114. The graphene sheet 540 has an outer periphery that is substantially consistent with the outer periphery of the semiconductor layer 550. The semiconductor layer 550 is disposed on the light reflector 530 via the insulating layer 114 and the graphene sheet 540. The outer periphery of the light reflector 530 (second portion) is configured such that, when viewed from above in the XY plane, the semiconductor layer 550 is included when it is projected onto the light reflector 530.

[0300] Semiconductor layer 550 includes multiple light-emitting surfaces 551S1 and 551S2. Semiconductor layer 550 is a prism-shaped or cylindrical laminate having a bottom surface 553B on a first surface 102a. The light-emitting surfaces 551S1 and 551S2 are surfaces opposite to the bottom surface 553B of semiconductor layer 550. In this example, the bottom surface 553B is the surface in contact with the graphene sheet 540. The light-emitting surfaces 551S1 and 551S2 are preferably surfaces in generally parallel planes. These generally parallel planes can be the same plane or different planes. The light-emitting surfaces 551S1 and 551S2 are disposed separately.

[0301] Semiconductor layer 550 includes a p-type semiconductor layer 553, a light-emitting layer 552, and an n-type semiconductor layer 551. The p-type semiconductor layer 553, the light-emitting layer 552, and the n-type semiconductor layer 551 are stacked sequentially from the bottom surface 553B toward the light-emitting surfaces 551S1 and 551S2.

[0302] The p-type semiconductor layer 553 includes connecting portions 553a1 and 553a2. Connecting portion 553a1 protrudes from the p-type semiconductor layer 553 in one direction on the insulating layer 114. Connecting portion 553a2 protrudes from the p-type semiconductor layer 553 in a different direction on the insulating layer 114 than connecting portion 553a1. Connecting portions 553a1 and 553a2 are not limited to protruding in one direction; they may protrude in multiple directions. A portion of the protruding part extending throughout the outer periphery of the semiconductor layer 550 may also be used as connecting portions 553a1 and 553a2. The height of connecting portions 553a1 and 553a2 is lower than the height of the semiconductor layer 550, the same as the height of the p-type semiconductor layer 553, or, as in this example, lower than the height of the p-type semiconductor layer 553, and the semiconductor layer 550 is formed in a stepped shape.

[0303] The connector 553a1 is p-type, and a through-hole 561a1 connected to one end of the connector 553a1 is electrically connected to the p-type semiconductor layer 553. The connector 553a2 is p-type, and a through-hole 561a2 connected to one end of the connector 553a2 is electrically connected to the p-type semiconductor layer 553.

[0304] The n-type semiconductor layer 551 has two light-emitting surfaces 551S1 and 551S2 on its upper surface. The two light-emitting surfaces 551S1 and 551S2 are arranged separately from each other. That is, a sub-pixel group 520 substantially contains two sub-pixels. In this embodiment, as in the other embodiments described above, the display area is formed by arranging the sub-pixel groups 520, which substantially contain two sub-pixels, in a grid pattern.

[0305] The protruding directions of the connecting portions 553a1 and 553a2 are determined, for example, according to the arrangement of the light-emitting surfaces 551S1 and 551S2. The connecting portion 553a1 is, for example, positioned such that its distance from the light-emitting surface 551S1 is sufficiently shorter than its distance from the light-emitting surface 551S2. That is, the connecting portion 553a1 is located sufficiently close to the light-emitting surface 551S1 than the light-emitting surface 551S2. The connecting portion 553a2 is, for example, positioned such that its distance from the light-emitting surface 551S2 is sufficiently shorter than its distance from the light-emitting surface 551S1. That is, the connecting portion 553a2 is located sufficiently close to the light-emitting surface 551S2 than the light-emitting surface 551S1.

[0306] The first interlayer insulating film (first insulating film) 156 covers the side surfaces of the p-type semiconductor layer 553, the side surfaces of the light-emitting layer 552, and the side surfaces of the n-type semiconductor layer 551. The first interlayer insulating film 156 also covers a portion of the upper surface of the n-type semiconductor layer 551. The light-emitting surfaces 551S1 and 551S2 in the n-type semiconductor layer 551 are not covered by the first interlayer insulating film 156. The first interlayer insulating film 156 is the same as in the other embodiments described above, and is preferably made of white resin.

[0307] A TFT lower layer film 106 is formed on the first interlayer insulating film 156. The TFT lower layer film 106 is not disposed on the light-emitting surfaces 551S1 and 551S2. The TFT lower layer film 106 is planarized, and TFT channels 104-1, 104-2, etc. are formed on the TFT lower layer film 106.

[0308] An insulating layer 105 covers the lower TFT film 106 and TFT channels 104-1 and 104-2. A gate 107-1 is disposed on the TFT channel 104-1 via the insulating layer 105. A gate 107-2 is disposed on the TFT channel 104-2 via the insulating layer 105. A transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. A transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

[0309] The second interlayer insulating film (second insulating film) 108 covers the insulating layer 105, gate 107-1, and gate 107-2.

[0310] TFT channels 104-1 and 104-2 contain p-type doped regions, and transistors 103-1 and 103-2 are p-channel TFTs. Transistor 103-1 is located closer to the light-emitting surface 551S1 than the light-emitting surface 551S2. Transistor 103-2 is located closer to the light-emitting surface 551S2 than the light-emitting surface 551S1.

[0311] An opening 558-1 is provided above the light-emitting surface 551S1. An opening 558-2 is provided above the light-emitting surface 551S2. The second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 are not provided in the openings 558-1 and 558-2, and the light-emitting surfaces 551S1 and 551S2 are exposed through the openings 558-1 and 558-2.

[0312] Transparent electrodes 559k are provided on the light-emitting surfaces 551S1 and 551S2. Electrons are injected through the transparent electrodes 559k and the light-emitting surfaces 551S1 and 551S2. The light-emitting surfaces 551S1 and 551S2 are covered by the transparent electrodes 559k, and the openings 558-1 and 558-2 are filled with the surface resin layer 170.

[0313] When viewed from above in the XY plane, the luminescent surfaces 551S1 and 551S2 are squares, rectangles, other polygons, circles, etc. The uppermost shapes of the openings 558-1 and 558-2 can also be squares, rectangles, other polygons, circles, etc. To reduce light loss due to reflection from the walls of the openings 558-1 and 558-2, it is preferable that the openings 558-1 and 558-2 are formed in a conical shape, for example, by widening upwards in area as shown in this example. When viewed from above in the XY plane, the shapes of the luminescent surfaces 551S1 and 551S2 may or may not be similar to the shapes of the uppermost parts of the openings 558-1 and 558-2.

[0314] The wiring layer 110 is disposed on the second interlayer insulating film 108. The wiring layer 110 includes wirings 510s1, 510d1, 510k, 510d2, and 510s2.

[0315] Wiring 510k is disposed between light-emitting surface 551S1 and light-emitting surface 551S2. A light-transmitting electrode 559k is disposed along the wiring 510k. The wiring 510k and the light-transmitting electrode 559k are connected, for example, to... Figure 3 Grounding wire 4.

[0316] Vias 111d1, 111s1, 111d2, and 111s2 are provided to penetrate the second interlayer insulating film 108 and the insulating layer 105. Via 111d1 is located between the p-type doped region of transistor 103-1 and wiring 510d1. Via 111s1 is located between the p-type doped region of transistor 103-1 and wiring 510s1. Via 111d2 is located between the p-type doped region of transistor 103-2 and wiring 510d2. Via 111s2 is located between the p-type doped region of transistor 103-2 and wiring 510s2.

[0317] Wiring 510d1 is disposed above the connection portion 553a1. Wiring 510d1 is connected to the p-type region corresponding to the drain electrode of transistor 103-1 via via 111d1. Wiring 510s1 is connected to the p-type region corresponding to the source electrode of transistor 103-1 via via 111s1. Wiring 510d2 is disposed above the connection portion 553a2. Wiring 510d2 is connected to the region corresponding to the drain electrode of transistor 103-2 via via 111d2. Wiring 510s2 is connected to the region corresponding to the source electrode of transistor 103-2 via via 111s2.

[0318] The through-hole 561a1 is provided to pass through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The through-hole 561a1 is provided between the connecting part 553a1 and the wiring 510d1, and electrically connects the connecting part 553a1 and the wiring 110d1.

[0319] The through-hole 561a2 is provided to pass through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The through-hole 561a2 is provided between the connecting part 553a2 and the wiring 510d2, and electrically connects the connecting part 553a2 and the wiring 510d2.

[0320] Transistors 103-1 and 103-2 are driving transistors for adjacent sub-pixels and are driven sequentially. Holes supplied from one of the two transistors 103-1 and 103-2 are injected into the light-emitting layer 552, and electrons supplied from wiring 510k are injected into the light-emitting layer 552, causing the light-emitting layer 552 to emit light.

[0321] In this embodiment, the drift current flowing in the direction parallel to the XY plane is suppressed by the resistance of the n-type semiconductor layer 551 and the p-type semiconductor layer 553. Therefore, electrons injected from the light-emitting surfaces 551S1 and 551S2, and holes injected from the vias 561a1 and 561a2, both travel along the stacking direction of the semiconductor layers 550. The outer sides of the light-emitting surfaces 551S1 and 551S2 hardly serve as light sources, so transistors 103-1 and 103-2 can be used to make the multiple light-emitting surfaces 551S1 and 551S2 provided on a semiconductor layer 550 emit light respectively.

[0322] As mentioned above, the area outside of the light-emitting surfaces 551S1 and 551S2 will not become a light source, so the light reflector 530 can also be set for each light-emitting surface 551S1 and 551S2.

[0323] The manufacturing method of the image display device according to this embodiment will be described.

[0324] Figures 24A to 26B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0325] In this embodiment, the process up to the formation of the light-reflecting layer 120 and the insulating layer 114 can be the same as in the other embodiments described above. Hereinafter, the process of performing the equivalent... Figure 14B The process is executed after the process. Figure 24A The process flow will be described. Furthermore, in this embodiment, the light-reflecting layer 120 includes a light-reflecting plate 530, the shape of which differs from that in the other embodiments described above.

[0326] like Figure 24A As shown, a graphene layer 1140 is disposed on an insulating layer 114. The graphene layer 1140 has a sufficient area, and the outer periphery of the graphene layer 1140 is, for example, configured to include the outer periphery of the light reflector 530.

[0327] like Figure 24B As shown, semiconductor layer 1150 is formed on graphene layer 1140. Semiconductor layer 1150 consists of p-type semiconductor layer 1153, light-emitting layer 1152 and n-type semiconductor layer 1151 sequentially formed from graphene layer 1140 toward the positive Z-axis.

[0328] like Figure 24C As shown, Figure 24BThe semiconductor layer 1150 shown is shaped into a desired shape by etching or the like, forming a semiconductor layer 550 including connection portions 553a1 and 553a2. The desired shape is, for example, a square, rectangle, or other polygonal or circular shape when viewed from above in the XY plane. In this example, connection portion 553a1 is formed in the negative direction of the X-axis, and connection portion 553a2 is formed in the positive direction of the X-axis. Figure 24B The graphene layer 1140 shown is over-etched during the formation of the semiconductor layer 1150 to form an outer perimeter that is substantially consistent with the outer perimeter of the semiconductor layer 1150.

[0329] like Figure 25A As shown, a first interlayer insulating film 156 is formed covering an insulating layer 114, a graphene layer 140, and a semiconductor layer 550.

[0330] like Figure 25B As shown, a TFT lower layer 106 is formed on the first interlayer insulating film 156, and TFT channels 104-1 and 104-2 are formed on the TFT lower layer 106. An insulating layer 105 is formed throughout the TFT lower layer 106 and the TFT channels 104-1 and 104-2. A gate 107-1 is formed on the TFT channel 104-1 via the insulating layer 105. A gate 107-2 is formed on the TFT channel 104-2 via the insulating layer 105. A second interlayer insulating film 108 is formed throughout the insulating layer 105 and the gates 107-1 and 107-2. The formation methods and materials of the TFT channels 104-1 and 104-2, the insulating layer 105, and the gates 107-1 and 107-2 can be the same as in the other embodiments described above.

[0331] like Figure 26AAs shown, vias 112d1 and 112s1 are formed, penetrating the second interlayer insulating film 108 and the insulating layer 105 to reach the TFT channel 104-1. Through-holes 112d2 and 112s2 are formed, penetrating the second interlayer insulating film 108 and the insulating layer 105 to reach the TFT channel 104-2. Through-hole 562a1 is formed, penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 to reach the connection portion 553a1. Through-hole 562a2 is formed, penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 to reach the connection portion 553a2. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156 are removed to form an opening 558-1 reaching the light-emitting surface 551S1. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156 are removed to form an opening 558-2 reaching the light-emitting surface 551S2.

[0332] like Figure 26B As shown, vias 112d1, 112s1, 112d2, 112s2, 562a1, and 562a2 are filled with conductive material to form vias 111d1, 111s1, 111d2, 111s2, 561a1, and 561a2. A wiring layer 110 is formed, and wirings 510d1, 510s1, 510d2, 510s2, and 510k are formed.

[0333] The light-emitting surfaces 551S1 and 551S2 are roughened. Then, a transparent conductive film is formed by covering the wiring layer 110 to create transparent electrodes 559d1, 559s1, 559d2, 559s2, and 559k. The transparent electrode 559k is formed by covering the light-emitting surfaces 551S1 and 551S2, electrically connecting the light-emitting surfaces 551S1 and 551S2 to the wiring 510k.

[0334] Then, the upper structure, such as the color filter, is formed.

[0335] Thus, a sub-pixel group 520 is formed, which includes a semiconductor layer 550 having two light-emitting surfaces 551S1 and 551S2.

[0336] In this embodiment, two light-emitting surfaces 551S1 and 551S2 are provided on a semiconductor layer 550, but the number of light-emitting surfaces is not limited to two; three or more light-emitting surfaces can also be provided on a semiconductor layer 550. As an example, one or two columns of sub-pixels can also be implemented using a single semiconductor layer 550. Thus, as described later, the recombination current that does not contribute to the light emission of each light-emitting surface can be reduced, and the effect of realizing finer light-emitting elements can be enhanced.

[0337] (Modified Example)

[0338] Figure 27 This is a schematic cross-sectional view of a portion of an image display device illustrating a variation of this embodiment.

[0339] In this modified example, the presence of two n-type semiconductor layers 5551a1 and 5551a2 on the light-emitting layer 552 differs from the fifth embodiment described above. Otherwise, it is the same as the fifth embodiment, with identical reference numerals used for the same constituent elements and detailed descriptions omitted where appropriate.

[0340] like Figure 27 As shown, the image display device of this modified example includes a subpixel group 520a. The subpixel group 520a includes a semiconductor layer 550a. The semiconductor layer 550a includes a p-type semiconductor layer 553, a light-emitting layer 552, and n-type semiconductor layers 5551a1 and 5551a2. The p-type semiconductor layer 553 and the light-emitting layer 552 are sequentially stacked from the graphene layer 140. The n-type semiconductor layers 5551a1 and 5551a2 are both stacked on the light-emitting layer 552.

[0341] The n-type semiconductor layers 5551a1 and 5551a2 are formed in an island shape on the light-emitting layer 552, and in this example, they are arranged separately along the X-axis direction. A first interlayer insulating film 156 is provided between the n-type semiconductor layers 5551a1 and 5551a2, and the n-type semiconductor layers 5551a1 and 5551a2 are separated by the first interlayer insulating film 156.

[0342] The n-type semiconductor layers 5551a1 and 5551a2 have roughly the same shape when viewed from above in the XY plane. Their shape is roughly square or rectangular, but can also be other polygonal, circular, etc.

[0343] The n-type semiconductor layer 5551a1 has a light-emitting surface 5551S1. The n-type semiconductor layer 5551a2 has a light-emitting surface 5551S2. The light-emitting surface 5551S1 is exposed through an opening 558-1 formed by removing a portion of each of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The exposed light-emitting surface 5551S1 is the surface of the n-type semiconductor layer 5551a1. The light-emitting surface 5551S2 is exposed through an opening 558-2 formed by removing a portion of each of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The exposed light-emitting surface 5551S2 is the surface of the n-type semiconductor layer 5551a2.

[0344] The shapes of the light-emitting surfaces 5551S1 and 5551S2 when viewed from above in the XY plane are the same as those of the light-emitting surfaces in the fifth embodiment, having approximately the same shape, such as a roughly square shape. The shapes of the light-emitting surfaces 5551S1 and 5551S2 are not limited to the square shape of this embodiment; they can also be polygons such as circles, ellipses, or hexagons. The shapes of the light-emitting surfaces 5551S1 and 5551S2 can be similar to the shapes of the openings 558-1 and 558-2, or they can be different shapes.

[0345] Transparent electrodes 559k are respectively disposed on the light-emitting surfaces 5551S1 and 5551S2. Transparent electrodes 559k are also disposed on the wiring 510k. Transparent electrodes 559k are located between the wiring 510k and the light-emitting surface 5551S1, and also between the wiring 510k and the light-emitting surface 5551S2. Transparent electrodes 559k electrically connect the wiring 510k and the light-emitting surfaces 5551S1 and 5551S2.

[0346] The manufacturing method of this modified example will be described.

[0347] Figures 28A to 29B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this modified example.

[0348] In this modified example, up to the process of forming the semiconductor layer 1150 on the graphene layer 1140, the application is the same as in the fifth embodiment described above. Figure 24A as well as Figure 24B The same process as described in [the previous section]. The following section describes the process in [the previous section]. Figure 24B The above-mentioned processes will be applied later. Figure 28A The process details will be explained.

[0349] like Figure 28A As shown, in this modified example, Figure 24BThe semiconductor layer 1150 shown is etched to form a p-type semiconductor layer 553, which includes a light-emitting layer 552 and connecting portions 553a1 and 553a2. Further etching is performed to form two n-type semiconductor layers 5551a1 and 5551a2.

[0350] When forming n-type semiconductor layers 5551a1 and 5551a2, deeper etching can be performed. For example, the etching used to form n-type semiconductor layers 5551a1 and 5551a2 can exceed the depth reaching the light-emitting layer 552 and the p-type semiconductor layer 553. Thus, when forming n-type semiconductor layers through deeper etching, it is preferable to... Figure 27 Etching is performed on the outer periphery of the light-emitting surfaces 5551S1 and 5551S2, which is at least 1 μm larger than the outer periphery. By moving the etched location away from the outer periphery of the light-emitting surfaces 5551S1 and 5551S2, recombination current can be suppressed.

[0351] like Figure 28B As shown, a first interlayer insulating film 156 is formed by covering an insulating layer 114, a graphene layer 140, and a semiconductor layer 550a.

[0352] like Figure 28C As shown, a TFT lower layer 106 is formed on the first interlayer insulating film 156, and TFT channels 104-1 and 104-2 are formed on the TFT lower layer 106. Furthermore, an insulating layer 105 is formed on the TFT channels 104-1 and 104-2, and gates 107-1 and 107-2 are formed on the insulating layer 105. A second interlayer insulating film 108 is formed covering the insulating layer 105 and the gates 107-1 and 107-2.

[0353] like Figure 29A As shown, through-holes 112d1, 112s1, 112d2, 112s2, 562a1, and 562a2 are formed in the same manner as in the fifth embodiment. Opening 558-1 is formed to reach the light-emitting surface 5551S1 by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156. Opening 558-2 is formed to reach the light-emitting surface 5551S2 by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower layer film 106, and a portion of the first interlayer insulating film 156.

[0354] like Figure 29B As shown, similar to the fifth embodiment, a wiring layer 110 is formed, and a light-transmitting conductive film is formed.

[0355] Thus, a sub-pixel group 520a with two light-emitting surfaces 5551S1 and 5551S2 is formed.

[0356] In this modified example, similar to the fifth embodiment, the number of light-emitting surfaces is not limited to two; three or more light-emitting surfaces may be disposed on a semiconductor layer 550a.

[0357] The effects of the image display device in this embodiment will be explained.

[0358] Figure 30 This is a chart illustrating the characteristics of pixel LED elements.

[0359] Figure 30 The vertical axis represents the luminous efficiency [%) of the pixel LED element. The horizontal axis represents the current density flowing through the pixel LED element in relative terms.

[0360] like Figure 30 As shown, in regions where the relative value of current density is less than 1.0, the luminous efficiency of the pixel LED element is approximately constant or monotonically increasing. In regions where the relative value of current density is greater than 1.0, the luminous efficiency monotonically decreases. That is, there exists an appropriate current density for the pixel LED element that maximizes its luminous efficiency.

[0361] By suppressing the current density to a level sufficient to obtain adequate brightness from the light-emitting element, a highly efficient image display device can be expected. However, through... Figure 30 The study shows that at low current densities, the luminous efficiency decreases as the current density decreases.

[0362] As described in the first to fourth embodiments, the light-emitting element is formed by separating the entire semiconductor layer 1150 containing the light-emitting layer using etching or the like. At this time, the interface between the light-emitting layer and the n-type semiconductor layer is exposed at the end of the light-emitting element. Similarly, the interface between the light-emitting layer and the p-type semiconductor layer is exposed at the end.

[0363] In the presence of such an end, electrons and holes recombine at the end. However, this recombination does not contribute to light emission. The recombination at the end occurs almost independently of the current flowing through the light-emitting element. It is believed that the recombination is generated based on the length of the junction surface that contributes to light emission at the end.

[0364] When two cube-shaped light-emitting elements of the same size emit light, since the four sides of each light-emitting element become ends, the two light-emitting elements have a total of 8 ends, and it is possible for them to be recombined at the 8 ends.

[0365] In contrast, in this embodiment, semiconductor layers 550 and 550a have square sides and four ends on the two light-emitting surfaces. However, the region between openings 558-1 and 558-2 has less electron and hole injection and contributes almost nothing to light emission; therefore, it can be considered that the six ends contribute to light emission. Thus, in this embodiment, by substantially reducing the number of ends of the semiconductor layers, recombination that does not contribute to light emission is reduced. By reducing recombination that does not contribute to light emission, the driving current of each light-emitting surface is reduced.

[0366] In cases where the distance between sub-pixels is shortened for purposes such as high precision, or where the current density is relatively high, the distance between the light-emitting surface 551S1 and the light-emitting surface 551S2 is shortened in the sub-pixel group 520 of the fifth embodiment. In this case, as in the fifth embodiment, if the n-type semiconductor layer is shared, there is a concern that some of the electrons injected into the driven light-emitting surface may be diverted, resulting in micro-emission from the undriven light-emitting surface. In the modified sub-pixel group 520a, the n-type semiconductor layer is separated into two, with each n-type semiconductor layer having a light-emitting surface, thus reducing the possibility of micro-emission from the undriven side of the light-emitting surface.

[0367] In this embodiment, the semiconductor layer including the light-emitting layer is stacked sequentially from one side of the first interlayer insulating film 156, consisting of a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer. This is preferred from the viewpoint of roughening the exposed surface of the n-type semiconductor layer to improve luminous efficiency. Similar to other embodiments, the stacking order of the p-type semiconductor layer and the n-type semiconductor layer may be replaced by stacking the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer, as described above.

[0368] In the image display apparatus of the above embodiments, specific examples have been described for each sub-pixel and sub-pixel group. Each specific example is just one example, and other configuration examples can be obtained by appropriately combining the configuration and process sequence of these embodiments. For example, in the case of the first embodiment, instead of using the p-type semiconductor layer as the light-emitting surface, it can be used as an n-type semiconductor layer; or in the cases of the second to fourth embodiments, instead of using the n-type semiconductor layer as the light-emitting surface, it can be used as a p-type semiconductor layer as the light-emitting surface.

[0369] (Sixth Implementation Method)

[0370] The aforementioned image display device, as an image display module with an appropriate number of pixels, can be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0371] Figure 31 This is a block diagram illustrating the image display device of this embodiment.

[0372] Figure 31 The diagram shows the main components of a computer monitor.

[0373] like Figure 31 As shown, the image display device 601 includes an image display module 602. The image display module 602 is, for example, an image display device configured as described in the first embodiment. The image display module 602 includes: a display area 2, on which a plurality of sub-pixels, including sub-pixels 20, are arranged; a row selection circuit 5; and a signal voltage output circuit 7.

[0374] The image display device 601 also includes a controller 670. The controller 670 takes in control signals separated and generated by an interface circuit (not shown) as input, and controls the driving of each sub-pixel and the driving sequence for the row selection circuit 5 and the signal voltage output circuit 7.

[0375] (Modified Example)

[0376] The aforementioned image display device, as an image display module with an appropriate number of pixels, can be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0377] Figure 32 This is a block diagram illustrating a modified example of this embodiment of an image display device.

[0378] Figure 32 The diagram shows the structure of a high-resolution thin-film television.

[0379] like Figure 32 As shown, the image display device 701 includes an image display module 702. The image display module 702 is, for example, the image display device 1 configured as described in the first embodiment. The image display device 701 includes a controller 770 and a frame memory 780. The controller 770 controls the driving sequence of each sub-pixel of the display area 2 based on control signals supplied by the bus 740. The frame memory 780 stores one frame of display data for processing such as smooth dynamic image reproduction.

[0380] The image display device 701 includes an I / O circuit 710. The I / O circuit 710 is in Figure 32 The term is simply "I / O". I / O circuit 710 provides interface circuitry for connecting to external terminals, devices, etc. I / O circuit 710 includes, for example, a USB interface for connecting external hard disk devices, an audio interface, etc.

[0381] The image display device 701 includes a receiving unit 720 and a signal processing unit 730. An antenna 722 is connected to the receiving unit 720, which separates and generates necessary signals from the radio waves received by the antenna 722. The signal processing unit 730 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and separates and generates image data, sound data, etc., from the signals separated and generated by the receiving unit 720.

[0382] By configuring the receiving unit 720 and the signal processing unit 730 as high-frequency communication modules such as mobile phone transceivers, WiFi receivers, and GPS receivers, they can also be configured as other image display devices. For example, an image display device with an image display module of appropriate screen size and resolution can be a portable information terminal such as a smartphone or a car navigation system.

[0383] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, and may also be a variation or other embodiment. Furthermore, the image display module in this embodiment and its variations, such as... Figure 11 As shown, it is composed of multiple sub-pixels.

[0384] According to the embodiments described above, a method for manufacturing an image display device and an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield rate.

[0385] While several embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims. Furthermore, the foregoing embodiments can be combined with each other for implementation.

[0386] Explanation of reference numerals in the attached figures

[0387] 1. Image display device (201, 601, 701); 2. Display area; 3. Power line; 4. Ground line; 5. Row selection circuit (205); 6. Scan line (206); 7. Signal voltage output circuit (207); 8. Signal line (208); 10. Pixel; 20, 20a, 220, 320, 420 sub-pixels; 22, 222 light-emitting elements; 24, 224 selection transistors; 26, 226 driving transistors; 28, 228 capacitors; 101 Circuit; 102, 402 Substrate; 102a, 402a First surface; 103, 103-1, 103-2, 203 Transistors; 104, 104-1, 104-2, 204 TFT channel; 105 Insulating layer; 107, 107-1, 107-2 Gate; 10 8. Second interlayer insulating film, 110 wiring layer, 110d, 110k, 310a, 310k wiring, 120 light-reflecting layer, 120a, 530 light-reflecting plates, 140 graphene layer, 140a, 540 graphene sheets, 150, 250 light-emitting elements, 151B, 253B, 553B bottom surface, 153S, 251S, 551S1, 551S2, 5551S1, 5551S2 light-emitting surfaces, 156. First interlayer insulating film, 159d, 159s, 359d, 359k, 559k light-transmitting electrodes, 161k, 261a, 361a, 561a1, 561a2 through holes, 180 color filter, 520, 520a sub-pixel groups, 1140 graphene layer, 1150 semiconductor layer

Claims

1. A method for manufacturing an image display device, characterized in that, It has the following processes: A layer containing graphene is formed on a first substrate; A semiconductor layer containing a light-emitting layer is formed on the graphene-containing layer; The semiconductor layer is processed to form a light-emitting element, which has a bottom surface on the graphene-containing layer and includes a light-emitting surface that is the opposite side of the bottom surface; A first insulating film is formed to cover the first substrate, the graphene-containing layer, and the light-emitting element; Circuit elements are formed on the first insulating film; A second insulating film is formed to cover the first insulating film and the circuit elements; Remove a portion of the first insulating film and a portion of the second insulating film to expose the surface containing the light-emitting surface; Forming a through-hole penetrating the first insulating film and the second insulating film; and A wiring layer is formed on the second insulating film. The light-emitting element includes a connection formed on the graphene-containing layer. The through hole is located between the wiring layer and the connection portion, electrically connecting the wiring layer and the connection portion.

2. The method for manufacturing the image display device according to claim 1, characterized in that, In the process of forming the semiconductor layer, the semiconductor layer is formed by sputtering.

3. The method for manufacturing an image display device according to claim 1, characterized in that, Before forming the graphene-containing layer, the process further includes forming a first portion with light reflectivity on the first substrate. When viewed from above, the outer periphery of the light-emitting element is positioned within the outer periphery of the first portion.

4. The method for manufacturing an image display device according to claim 1, characterized in that, The first substrate includes a light-transmitting substrate.

5. The method for manufacturing an image display device according to claim 4, characterized in that, The first substrate further includes a flexible second substrate disposed on the light-transmitting substrate. The method for manufacturing the image display device further includes a step of removing the light-transmitting substrate after forming the wiring layer.

6. The method for manufacturing an image display device according to claim 5, characterized in that, Before forming the graphene-containing layer, the process further includes forming a silicon compound-containing layer on the second substrate.

7. The method for manufacturing an image display device according to claim 1, characterized in that, It also includes a process of forming a light-transmitting electrode on the light-emitting surface.

8. The method for manufacturing an image display device according to claim 1, characterized in that, The semiconductor layer comprises a gallium nitride-based compound semiconductor.

9. The method for manufacturing an image display device according to claim 1, characterized in that, It also includes a process of forming a wavelength conversion component on the light-emitting element.

10. An image display device, characterized in that, have: A substrate having a first surface; A layer containing graphene is disposed on the first surface; A light-emitting element is disposed on the graphene-containing layer, having a bottom surface on the graphene-containing layer, and including a light-emitting surface that is the opposite side of the bottom surface. A first insulating film covers the side surface of the light-emitting element, the first surface, and the graphene-containing layer; Circuit elements are disposed on the first insulating film; A second insulating film covers the first insulating film and the circuit elements; A through-hole is provided, which penetrates the first insulating film and the second insulating film; and A wiring layer, which is disposed on the second insulating film, The light-emitting element includes a first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light-emitting layer, wherein the first semiconductor layer, the light-emitting layer, and the second semiconductor layer are sequentially stacked from the bottom surface toward the light-emitting surface. The via is disposed between the connection portion formed from the first semiconductor layer to the graphene-containing layer and the wiring layer, electrically connecting the first semiconductor layer and the wiring layer. The upper part of the light-emitting surface has an opening where the first insulating film, the circuit element, and the second insulating film are not provided. A light-transmitting electrode is provided on the light-emitting surface. The wiring layer is electrically connected to the light-emitting surface via the light-transmitting electrode.

11. The image display device according to claim 10, characterized in that, It also includes a first portion that is light-reflective and disposed between the first surface and the graphene-containing layer. When viewed from above, the outer periphery of the light-emitting element is positioned within the outer periphery of the first portion.

12. The image display device according to claim 10, characterized in that, The substrate includes a light-transmitting substrate.

13. The image display device according to claim 10, characterized in that, The substrate includes a flexible substrate.

14. The image display device according to claim 13, characterized in that, A layer containing a silicon compound is also provided between the flexible substrate and the graphene-containing layer.

15. The image display device according to claim 10, characterized in that, The wiring layer includes a first wiring connected to the through-hole and a second wiring connected to the surface containing the light-emitting surface. The second semiconductor layer is electrically connected to the circuit element via a surface including the light-emitting surface and a second wiring.

16. The image display device according to claim 10, characterized in that, The wiring layer includes a third wiring connected to the through-hole and a fourth wiring connected to the surface containing the light-emitting surface. The first semiconductor layer is electrically connected to the circuit element via the connection portion, the via, and the third wiring.

17. The image display device according to claim 10, characterized in that, The first semiconductor layer is p-type, and the second semiconductor layer is n-type.

18. The image display device according to claim 10, characterized in that, The light-emitting element comprises a gallium nitride-based compound semiconductor.

19. The image display device according to claim 10, characterized in that, The light-emitting element also includes a wavelength conversion component.

20. An image display device, characterized in that, have: A substrate having a first surface; The second part, which is disposed on the first surface, has light reflectivity; A graphene-containing layer is disposed on the second portion; A semiconductor layer is disposed on the graphene-containing layer, having a bottom surface on the graphene-containing layer, and having a plurality of light-emitting surfaces on the surface opposite to the bottom surface. A first insulating film covers the first surface, the graphene-containing layer, and the side surface of the semiconductor layer; Multiple transistors are disposed on the first insulating film; A second insulating film covers the first insulating film and the plurality of transistors; Multiple through holes are provided, which penetrate the first insulating film and the second insulating film; as well as A wiring layer, disposed on the second insulating film, includes wiring electrically connected to the plurality of transistors, the plurality of light-emitting surfaces, and the plurality of through holes. When viewed from above, the outer periphery of the semiconductor layer is disposed within the outer periphery of the second portion. The semiconductor layer includes a first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light-emitting layer. The first semiconductor layer, the light-emitting layer, and the second semiconductor layer are sequentially stacked from the bottom surface toward the light-emitting surface. The plurality of vias are disposed between the connection portion formed from the first semiconductor layer to the graphene-containing layer and the wiring layer, electrically connecting the first semiconductor layer and the wiring layer. The upper part of the light-emitting surface has an opening where the first insulating film, the plurality of transistors, and the second insulating film are not provided. A light-transmitting electrode is provided on the light-emitting surface. The wiring layer is electrically connected to the light-emitting surface via the light-transmitting electrode.

21. The image display device according to claim 20, characterized in that, The second semiconductor layer is separated using the first insulating film.

Images