A one-time fuse trimming circuit based on SPI communication protocol

Abstract

The application discloses a one-time fuse trimming circuit based on an SPI communication protocol and belongs to the field of electronic circuits, comprising an SPI communication module and a fuse burning and writing digital logic circuit; the SPI communication module comprises a normal mode and a fuse mode; the normal mode comprises data bits, control bits and redundant bits; the fuse mode comprises a fuse address bit, a fuse control bit, a fuse mode bit, a fuse flag bit and a fuse enable bit; the fuse burning and writing digital logic circuit comprises a FIFO unit, an interlocking unit, a rising edge trigger unit and a fuse burning and writing execution unit. The application reuses the general SPI communication protocol, can temporarily reuse the SPI channel to burn and write the fuse according to a special method, can burn and break the end flag fuse after burning and writing the fuse, permanently closes the burning and writing path, is safe and reliable, will not appear misoperation, and saves a large amount of interface resources.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a one-time fuse adjustment circuit based on the SPI communication protocol. Background Technology

[0002] In many custom circuits, there are often situations where it is necessary to program fuses. In this case, a specific fuse programming configuration interface is usually used. After the fuse programming is completed, the interface is no longer used, which will cause a great waste of resources. Summary of the Invention

[0003] The purpose of this invention is to provide a disposable fuse adjustment circuit based on the SPI communication protocol to solve the problems in the background art.

[0004] To solve the above-mentioned technical problems, the present invention provides a one-time fuse adjustment circuit based on the SPI communication protocol, including an SPI communication module and a fuse programming digital logic circuit;

[0005] The SPI communication module includes two modes: normal mode and fuse mode; the normal mode includes data bits, control bits, and redundancy bits; the fuse mode includes fuse address bits, fuse control bits, fuse mode bits, fuse flag bits, and fuse enable bits.

[0006] The fuse programming digital logic circuit includes a FIFO unit, an interlock unit, a rising edge trigger unit, and a fuse programming execution unit.

[0007] In one implementation, the SPI communication module defaults to normal mode with 0 redundant bits, and the normal mode and the fuse mode are switched through a special mechanism.

[0008] The special mechanism is as follows: First, configure the SPI protocol, setting control bits R0 and R1, data bit D0, and redundancy bit NU0 to 0. At this time, configure the fuse writing information at the corresponding fuse address. Second, configure the SPI protocol, setting control bits R0 and R1, data bit D0, and redundancy bit NU0 to 1, data bit D3 to 1, and other bits to 0. After two SPI configurations, the fuse mode can be opened.

[0009] In one embodiment, the fuse mode is configured with a decoder circuit, which has a programming end operation. Through a special mechanism, the programming end flag fuse can be programmed. After the fuse is burned out, the fuse programming mode is permanently exited and cannot be re-entered.

[0010] The second special mechanism is as follows: configure the first SPI protocol with fuse control bits R0 and R1 set to 0, fuse mode bits ST0 set to 1 and ST1 set to 0, and fuse flag bit FLA set to 1; configure the second SPI protocol with fuse control bits R0 and R1 set to 1, fuse mode bits ST0 and ST1 set to 1, and fuse flag bit FLA set to 0; these two SPI configurations can permanently disable the fuse programming mode.

[0011] In one embodiment, the decoder circuit includes digital decoding functionality and rising edge triggering functionality;

[0012] During normal fuse programming, the digital decoding function in the decoder circuit programs different fuses according to the input fuse programming code. When the fuse programming is finished, the rising edge triggering function in the decoder circuit triggers a step signal based on the logic transition of the input signals of the fuse control bits R0, R1, fuse mode bits ST0, ST1 and fuse flag bit FLA, thus burning the end flag fuse and permanently exiting the fuse mode.

[0013] In one implementation, when all input signals meet the level transition requirements, the rising edge triggering unit outputs a step signal.

[0014] In one embodiment, the FIFO unit has two parts: a normal mode FIFO and a fuse programming FIFO, which are connected by a gating logic associated with the SPI communication protocol. When the active high output of the rising edge triggering unit, the active low output of CSB, and the active high output of data bit D3 occur simultaneously, the gating logic gate is opened, and the normal mode FIFO signal is fanned out into the fuse programming FIFO by the SCLK clock signal.

[0015] In one implementation, the interlocking unit consists of a programming end flag fuse and a fuse programming module hard enable. Once the end flag fuse is burned out, the fuse programming module hard enable is turned off, and the fuse mode is permanently exited.

[0016] In one embodiment, the fuse programming execution unit is controlled by a fuse programming signal. Once a low-level signal appears, the fuse resistance is extremely small, and a large current will flow through it, instantly burning out the fuse. Once the fuse is burned out, it cannot be recovered.

[0017] In the one-time fuse adjustment circuit based on the SPI communication protocol provided by this invention, the general SPI communication protocol is reused. The SPI channel can be temporarily reused to program the fuse according to a special method. After programming the fuse, the end flag fuse can be burned to permanently close the programming path. It is safe and reliable, and will not cause misoperation, saving a lot of interface resources. In addition, it has reversible programming start logic and irreversible programming stop logic, which can meet the needs of custom circuit parameter solidification one-time programming and avoid unnecessary losses caused by user misoperation. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a one-time fuse adjustment circuit structure based on the SPI communication protocol provided by the present invention.

[0019] Figure 2 This is a flowchart illustrating a disposable fuse adjustment circuit based on the SPI communication protocol provided by the present invention. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a one-time fuse adjustment circuit based on the SPI communication protocol proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0021] This invention provides a disposable fuse adjustment circuit based on the SPI communication protocol, the structure of which is as follows: Figure 1 As shown, the system includes an SPI communication module and a fuse programming digital logic circuit. The SPI communication module has two modes: normal mode and fuse mode. In normal mode, it includes data bits, control bits, and redundancy bits; in fuse mode, it includes fuse address bits, fuse control bits, fuse mode bits, fuse flag bits, and fuse enable bits. The fuse programming digital logic circuit includes a FIFO unit, an interlock unit, a rising edge trigger unit, and a fuse programming execution unit.

[0022] The working process of the disposable fuse adjustment circuit based on the SPI communication protocol of the present invention is as follows: Figure 2 As shown, the SPI communication module defaults to normal mode, with the redundancy bit typically set to 0. Normal mode and fuse mode can be switched via a special mechanism. Specifically, the special mechanism involves configuring the SPI protocol for the first time, setting control bits R0 and R1, data bit D0, and redundancy bit NU0 to 0. At this point, fuse programming information can be configured at the corresponding fuse address. For the second SPI protocol configuration, control bits R0 and R1, data bit D0, and redundancy bit NU0 are set to 1, data bit D3 is 1, and all other bits are 0. These two SPI configurations enable fuse mode.

[0023] Please continue reading. Figure 1 In fuse mode, a decoder circuit is configured, enabling a programming completion operation. A special mechanism allows programming the completion flag fuse; once burned, the fuse programming mode is permanently exited and cannot be re-entered. This special mechanism involves configuring the SPI protocol twice: first, fuse control bits R0 and R1 are set to 0, fuse mode bits ST0 and ST1 are set to 1 and ST1 to 0, and fuse flag FLA is set to 1; second, the SPI protocol is configured twice, with fuse control bits R0 and R1 set to 1, fuse mode bits ST0 and ST1 set to 1, and fuse flag FLA set to 0. These two SPI configurations permanently disable fuse mode.

[0024] When all input signals meet the level transition requirements, the output of the rising edge triggering unit will trigger a step signal. The decoder circuit in fuse mode includes digital decoding and rising edge triggering functions; during normal fuse programming, the digital decoding function in the decoder circuit will program different fuses according to the input fuse programming code; when the fuse programming ends, the rising edge triggering function in the decoder circuit will trigger a step signal according to the logic transition of the input signals of the fuse control bits R0, R1, fuse mode bits ST0, ST1, and fuse flag bit FLA, burning the end flag fuse, thereby permanently exiting fuse mode.

[0025] The FIFO unit consists of two parts: a normal mode FIFO and a fuse programming FIFO, which are connected by a gating logic associated with the SPI communication protocol. When the active high output of the rising edge trigger unit, the active low output of the SPI protocol chip select signal CSB, and the active high output of data bit D3 occur simultaneously, the gating logic gate opens, and the SCLK clock signal fans out the normal mode FIFO signal into the fuse programming FIFO.

[0026] Figure 1 In this configuration, the interlocking unit consists of a programming end flag fuse and a fuse programming module hardware enable. Once the end flag fuse is burned out, the fuse programming module hardware enable is turned off, and the fuse mode is permanently exited. The fuse programming execution unit is controlled by the fuse programming signal. Once a low-level signal appears, the fuse resistance is extremely small, and a large current will flow through it, instantly burning out the fuse. Once the fuse is burned out, it cannot be recovered.

[0027] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A disposable fuse adjustment circuit based on the SPI communication protocol, characterized in that, Includes SPI communication module and fuse programming digital logic circuit; The SPI communication module includes two modes: normal mode and fuse mode; the normal mode includes data bits, control bits, and redundancy bits; the fuse mode includes fuse address bits, fuse control bits, fuse mode bits, fuse flag bits, and fuse enable bits. The fuse programming digital logic circuit includes a FIFO unit, an interlock unit, a rising edge trigger unit, and a fuse programming execution unit; The SPI communication module defaults to normal mode with 0 redundant bits. The normal mode and the fuse mode are switched through a special mechanism. The special mechanism mentioned above specifically involves configuring the SPI protocol for the first time, setting control bits R0 and R1, data bit D0, and redundancy bit NU0 to 0, and configuring fuse programming information at the corresponding fuse address. Then, configuring the SPI protocol for the second time, setting control bits R0 and R1, data bit D0, and redundancy bit NU0 to 1, data bit D3 to 1, and all other bits to 0. These two SPI configurations enable fuse mode. The fuse mode is equipped with a decoder circuit and has a programming end operation. Through special mechanism two, it can program the programming end flag fuse. After the fuse is burned out, it permanently exits the fuse programming mode and cannot be entered again. The second special mechanism is specifically configured as follows: the first SPI protocol is configured with fuse control bits R0 and R1 set to 0, fuse mode bits ST0 set to 1 and ST1 set to 0, and fuse flag bit FLA set to 1. Configure the second SPI protocol, with fuse control bits R0 and R1 set to 1, fuse mode bits ST0 and ST1 set to 1, and fuse flag bit FLA set to 0; after two SPI configurations, the fuse programming mode can be permanently disabled.

2. The disposable fuse adjustment circuit based on the SPI communication protocol as described in claim 1, characterized in that, The decoder circuit includes digital decoding functionality and rising edge triggering functionality; During normal fuse programming, the digital decoding function in the decoder circuit programs different fuses according to the input fuse programming code. When the fuse programming is finished, the rising edge triggering function in the decoder circuit triggers a step signal based on the logic transition of the input signals of the fuse control bits R0, R1, fuse mode bits ST0, ST1 and fuse flag bit FLA, thus burning the end flag fuse and permanently exiting the fuse mode.

3. The disposable fuse adjustment circuit based on the SPI communication protocol as described in claim 2, characterized in that, When all input signals meet the level transition requirements, the rising edge triggering unit will output a step signal.

4. The disposable fuse adjustment circuit based on the SPI communication protocol as described in claim 3, characterized in that, The FIFO unit consists of two parts: a normal mode FIFO and a fuse programming FIFO, which are connected by a gating logic associated with the SPI communication protocol. When the active high output of the rising edge triggering unit, the active low output of CSB, and the active high output of data bit D3 occur simultaneously, the gating logic gate is opened, and the normal mode FIFO signal is fanned out into the fuse programming FIFO by the SCLK clock signal.

5. The disposable fuse adjustment circuit based on the SPI communication protocol as described in claim 4, characterized in that, The interlock unit consists of a programming end flag fuse and a fuse programming module hardware enable. Once the end flag fuse is burned out, the fuse programming module hardware enable is turned off, and the fuse mode is permanently exited.

6. The disposable fuse adjustment circuit based on the SPI communication protocol as described in claim 5, characterized in that, The fuse programming execution unit is controlled by the fuse programming signal. Once a low-level signal appears, the fuse resistance is extremely small, and current will flow through it, instantly burning out the fuse. Once the fuse is burned out, it cannot be recovered.

Images