A bus interface type network card chip control system

Abstract

This invention relates to a bus-interface network interface card (NIC) chip control system, belonging to the field of integrated circuit applications. The invention includes an FPGA as the main controller and a controlled NIC chip. The FPGA includes a soft processor core, an APB bus module, and an interface module. The soft processor core acts as the CPU, and the APB bus module is connected to and controlled by the soft processor core via an AXI bus. The interface module ensures that the APB bus module can perform read and write operations on the NIC chip registers under the timing constraints of the NIC chip. This invention overcomes the constraint of peripheral timing limitations on the APB clock frequency, decouples the two, and improves the CPU's clock frequency and efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit applications, and specifically relates to a bus interface type network card chip control system. Background Technology

[0002] A network interface card (NIC) chip, also known as a network interface controller (NIC) chip, is a type of application-specific integrated circuit (ASIC) that integrates a TCP / IP protocol stack, TCP offload engine, Ethernet MAC, and PHY. It is widely used in home network devices, security equipment, embedded servers, and other applications. A bus-interface NIC chip communicates with the main CPU using address and data buses. Figure 1 As can be seen from the data, the ADDR[9:0] and DATA[15:0] of the network card chip are 10-bit wide address bus pins and 16-bit wide data bus pins, respectively. / CS, / WR, and / RD represent the chip select pin, write enable pin, and read enable pin, respectively, which are active low. Figure 2 and Figure 3 These are the read and write timing diagrams for the network interface card (NIC) chip, respectively. Tables 1 and 2 show the read and write timing constraints for the NIC chip, respectively.

[0003] MicroBlaze is a soft processor core provided by VIVADO that can run on FPGAs. It can be combined with other IPs (such as the APB bus bridge) to build functional circuits. Based on this, peripheral devices can be controlled by programming in C in VITIS.

[0004] The AMBA standard is a communication standard proposed by ARM specifically for high-performance embedded processors. It can be divided into AHB, ASB, and APB according to speed, from highest to lowest. The APB bus can reduce power consumption and the complexity of peripheral device interfaces, making it suitable for peripherals with low bandwidth requirements and no need for pipelined bus interfaces. The APB3 protocol based on the AMBA3 standard mainly includes the following signals:

[0005] (1) PCLK: APB bus clock signal, sampled on the rising edge.

[0006] (2) PRESETn: APB bus reset signal, active low.

[0007] (3) PADDR: APB bus address, 32-bit width.

[0008] (4) PSEL: APB slave chip select signal, active high.

[0009] (5) PENABLE: APB enable signal, active high.

[0010] (6) PWRITE: APB read / write control signal. A high level performs a write operation, and a low level performs a read operation.

[0011] (7).PWDATA: APB write data bus signal, 32-bit width.

[0012] (8)READY: Ready signal, active high.

[0013] (9)PRDATA: APB read data bus signal, 32-bit width.

[0014] In traditional designs, because the IP integrator in VIVADO only provides synchronous APB bridges, the APB clock frequency is always the same as the MicroBlaze processor's clock frequency. However, the timing of read / write operations on the peripheral network card chip limits the speed of the APB. For example, as shown in Table 1, a complete write operation requires at least 93ns. To complete the write operation within two clock cycles when PENABLE is high, the APB clock frequency is designed to be 10MHz (with a period of 100ns, sufficient for a complete network card write operation). This reduces the MicroBlaze processor's speed to 10MHz, severely limiting its performance. Summary of the Invention

[0015] The purpose of this invention is to provide a bus interface network card chip control system that overcomes the constraints imposed by peripheral timing limitations on the APB clock frequency (i.e., MicroBlaze clock frequency) in traditional designs, decouples the two, and thereby improves the CPU's clock frequency and efficiency.

[0016] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0017] A bus interface network interface card (NIC) chip control system includes an FPGA as the master controller and a controlled NIC chip. The FPGA includes a soft processor core, an APB bus module, and an interface module. The soft processor core acts as a CPU, and the APB bus module is connected to and controlled by the soft processor core via an AXI bus. The interface module is used to ensure that the APB bus module can perform read and write operations on the NIC chip registers under the timing constraints of the NIC chip.

[0018] Furthermore, the FPGA uses 4-byte alignment, and the soft processor core is MicroBlaze; the APB bus module's protocol version is APB3 based on the AMBA3 standard, wherein:

[0019] The PCLK frequency is the same as the MicroBlaze's main frequency;

[0020] In the 32-bit bus address PADDR of APB, only the lower 12 bits are used, of which PADDR[1:0] are reserved bits for four-byte alignment. In addition, data using PADDR[11:2] is passed to the address bus ADDR[9:0] of the network card chip.

[0021] APB’s 32-bit write data bus signal PWDATA only uses its lower 16 bits to transmit data to the network card chip’s data bus DATA[15:0];

[0022] APB's 32-bit read data bus signal PRDATA uses only its lower 16 bits to read data from the network card chip's DATA[15:0].

[0023] Furthermore, when the FPGA CPU initiates a write operation, the PSEL and PWRITE of the APB bus module are set to high level, and the physical address of the output register on PADDR is displayed. After one PCLK cycle, PENABLE jumps to high level, and when PREADY is high level, the data PWDATA[15:0] is transmitted to DATA[15:0] of the network card chip. The data in DATA[15:0] will be written into the register with address ADDR[9:0] within the sampling time of the network card chip.

[0024] When the FPGA CPU initiates a read operation, the PSEL of the APB bus module is set to high level, PWRITE is set to low level, and the physical address of the output register on PADDR is displayed. In order to sample the correct value from the slower DATA[15:0] and transmit it to PRDATA[15:0] of the APB bus module, a read method with a wait is used. That is, when PSEL is set to high level for one PCLK cycle, and PENABLE jumps to high level, the PREADY signal is first pulled low. The PREADY signal is only pulled high after the data on DATA[15:0] of the network card chip is ready, and the data of DATA[15:0] is assigned to PRDATA[15:0]. At this time, the read operation is completed.

[0025] Furthermore, after each write or read operation, the CPU delays for a period of time to wait for the network card chip to complete its operation before executing the next operation.

[0026] Furthermore, the interface module uses one-hot codes to define 7 states, and the state transition process is as follows:

[0027] S0: Idle state; In this state, when PSEL is high, it indicates that the APB bus module has a read or write request, and the state transitions to S1.

[0028] S1: Start state; In this state, if PWRITE is high, it indicates that the APB bus module is making a write request, and the / CS and / WR pins are pulled low; otherwise, it indicates that the APB bus module is making a read request, and the / CS and / RD pins are pulled low.

[0029] S2: Establish time-waiting state; in this state, if / WR is low, wait for T1 time and then jump to S3; if / RD is low, wait for T2 time and then jump to S3.

[0030] S3: Data sampling state; In this state, if / WR is low, the fetch signal is set high, and the CPU assigns PWDATA[15:0] to DATA[15:0] and jumps to S4; If / RD is low, data is read from DATA[15:0] to PRDATA[15:0] and jumps to S4.

[0031] S4: Chip select time wait state; in this state, if / WR is low, wait for T3 time and then jump to S5; if / RD is low, wait for T4 time and then jump to S5.

[0032] S5: Completed state; In this state, pull / WR, / RD, and / CS all high, then jump to S6;

[0033] S6: Chip select interval wait state; in this state, after waiting for T5 time, jump to S0.

[0034] Compared with the prior art, the present invention has the following advantages:

[0035] (1) The present invention controls the network card chip through FPGA, which can overcome the constraints of peripheral timing on the APB clock frequency, decouple the two, and thus improve the CPU clock frequency and efficiency.

[0036] (2) By designing a finite state machine, the limitations imposed on the APB by the read and write timing of the network card chip are decoupled from the CPU clock frequency, thereby improving the CPU speed.

[0037] (3) By inserting wait functions into the underlying register operation API, the complexity of cross-clock domain data processing is reduced. This approach is simple, clear, and easy to extend to similar bus interface chip control schemes. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the overall structure of a bus interface network card chip control system.

[0039] Figure 2 This is a timing diagram of the network card chip read operation.

[0040] Figure 3 This is a timing diagram of the network card chip write operation.

[0041] Figure 4 This is a schematic diagram of the FPGA module structure.

[0042] Figure 5 This is the state transition diagram of the interface module. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to embodiments, but the implementation of the present invention is not limited thereto.

[0044] A bus interface network interface card (NIC) chip control system includes an FPGA as the master controller and a controlled NIC chip. The FPGA includes a soft processor core, an APB bus module, and an interface module. The soft processor core acts as a CPU, and the APB bus module is connected to and controlled by the soft processor core via an AXI bus. The interface module is used to ensure that the APB bus module can perform read and write operations on the NIC chip registers under the timing constraints of the NIC chip.

[0045] like Figure 4 As shown, the MicroBlaze soft processor core is used as the CPU inside the FPGA. The APB bridge is connected to and controlled by the MicroBlaze via the AXI bus. A C program is written in VITIS to access the network card registers by reading and writing the APB peripheral addresses, making peripheral access as simple as accessing memory cells. The signal connection relationship between the FPGA and the network card chip is as follows: Figure 1 As shown.

[0046] When the FPGA loads the bitstream file, MicroBlaze is the CPU, and APB is mapped to a fixed address. The operation on the APB peripheral (network card chip) specified register is the operation on this fixed address plus the specified offset.

[0047] The detailed process of APB signal operation is as follows:

[0048] When the CPU initiates a write operation, PSEL and PWRITE of APB are set to high level, and the physical address of the output register on PADDR is set. Since the system uses 4-byte alignment, the address PADDR[11:2] needs to be assigned to ADDR[9:0]. The value to be assigned to the above physical address is on PWDATA[15:0]. After one PCLK cycle, PENABLE jumps to high level. When PREADY is high level, the data PWDATA[15:0] is transmitted to DATA[15:0] of the network card chip. The data in DATA[15:0] will be written into the register at address ADDR[9:0] within the sampling time of the network card chip.

[0049] When the CPU initiates a read operation, PSEL of APB is set to high and PWRITE is set to low. The physical address of the output register on PADDR is the same as in the read operation, requiring the address PADDR[11:2] to be assigned to ADDR[9:0] of the network card chip. In order to sample the correct value from the slower DATA[15:0] and transmit it to PRDATA[15:0] of APB, a read method with a wait is used. That is, when PSEL is set to high for one PCLK cycle, and PENABLE jumps to high, the PREADY signal is first pulled low. Only after the data on DATA[15:0] of the network card chip is ready is the PREADY signal pulled high, and the data in DATA[15:0] is assigned to PRDATA[15:0], at which point the read operation is completed.

[0050] according to Figure 2 The timing diagram of the network card chip read operation shown in Figure 1 and the timing constraints of the read operation shown in Table 1 divide the read operation of the network card chip into the following stages:

[0051] Step 1. Prepare ADDR by pulling / CS and / RD low;

[0052] Step 2. After T2 (50ns), the data setup is complete;

[0053] Step 3. After T4 (20ns), the read strobe and chip select times reach 70ns;

[0054] Step 4. After T5 (30ns), the chip select time interval reaches 30ns, as detailed in Table 3.

[0055] Table 1

[0056]

[0057] Table 3

[0058]

[0059]

[0060] according to Figure 3 The timing diagram for the write operation of the network interface card (NIC) chip shown in Figure 2 and the timing constraints for the write operation shown in Table 2 divide the write operation process of the NIC chip into the following stages:

[0061] Step 1. Prepare ADDR by pulling / CS and / WD low;

[0062] Step 2. After T1 (10ns), the data setup is complete;

[0063] Step 3. After T3 (40ns), make the write gating and chip select times reach 50ns;

[0064] Step 4. After T5 (30ns), the chip select time interval reaches 30ns, as detailed in Table 4.

[0065] Table 2

[0066]

[0067] Table 4

[0068]

[0069] Furthermore, based on the control method of the network card chip using a finite state machine and an insertion wait function, the process of controlling the network card chip is segmented in chronological order according to the timing constraints in Tables 1 and 2. Based on the above segmentation, a state machine containing 7 states (S0 to S6) is designed. In each state, the APB signal and the network card signals / CS, / RD, / WR, ADDR[9:0], and DATA[15:0] are controlled to realize read or write operations.

[0070] To accommodate read and write operations within the state machine and to refine the signal operations corresponding to each state, three states are inserted into the four read or write steps mentioned above. A one-hot code is used to define the seven states of the state machine. The operation descriptions for each state are as follows, and the state transition diagram is shown below. Figure 5 As shown:

[0071] S0: Idle state. When PSEL is set to 1, it indicates that APB has a read or write request, and the state transitions to S0.

[0072] S1: Start state. If PWRITE is high, it means APB is a write request, so pull the / CS and / WR pins low; otherwise, it means APB is a read request, so pull the / CS and / RD pins low.

[0073] S2: Establish a time-waiting state. If / WR is low, wait for T1 time and then jump to S3; if / RD is low, wait for T2 time and then jump to S3.

[0074] S3: Data sampling state. If / WR is low, set the fetch signal high (in the external combinational logic, when fetch is high, PWDATA[15:0] is assigned to DATA[15:0]), and jump to S4; if / RD is low, read data from DATA[15:0] to PRDATA[15:0], and jump to S4.

[0075] S4: Chip select time wait state. If / WR is low, wait for T3 time and then jump to S5; if / RD is low, wait for T4 time and then jump to S5.

[0076] S5: Completed state, raises / WR, / RD, and / CS all high, then jumps to S6.

[0077] S6: Chip select interval wait state. After waiting for T5 time, jump to S0.

[0078] While the aforementioned state machine ensures that the APB can perform read and write operations on its registers within the timing constraints of the network interface card chip, it cannot handle excessively fast CPU requests. A common approach is to add a FIFO module to process CPU requests in a queue; however, this increases design complexity. To reduce design complexity, this embodiment inserts a wait function into the register operation API of the C program, as shown below:

[0079] void nop(){volatile int delay=N; while(delay--);}

[0080] The value of N is set according to actual needs, thereby ensuring that the time between two adjacent APB operations is long enough; the state machine will not be destroyed by sudden APB operation requests, and the APB operation requests will not be lost.

[0081] In summary, this invention achieves network card chip control via FPGA, overcoming the constraints imposed by peripheral timing limitations on the APB clock frequency, decoupling the two, and thereby improving CPU clock frequency and efficiency. Furthermore, to address the issue that the APB operation speed is much higher than the signal transmission speed on the network card pins, this invention inserts a wait function `nop()` into the underlying operation register API, thus preventing state machine anomalies caused by excessively short time intervals between adjacent APB read / write operations.

[0082] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention fall within the protection scope of the present invention.

Claims

1. A bus interface type network card chip control system, characterized in that, It includes an FPGA as the main controller and a network interface card (NIC) chip as the controlled device. The FPGA includes a soft processor core, an APB bus module, and an interface module. The soft processor core acts as the CPU, and the APB bus module is connected to and controlled by the soft processor core via an AXI bus. The interface module is used to ensure that the APB bus module can perform read and write operations on the NIC chip registers under the timing constraints of the NIC chip. After each write or read operation, the CPU delays for a period of time to wait for the network card chip to complete the operation before executing the next operation. The interface module uses one-hot codes to define 7 states, and the state transition process is as follows: S0: Idle state; In this state, when the APB slave chip select signal PSEL is high, it indicates that the APB bus module has a read or write request, and the state transitions to S1. S1: Start state; In this state, if the APB read / write control signal PWRITE is high, it indicates that the APB bus module is making a write request, and the chip select pin / CS and the write enable pin / WR are pulled low; otherwise, it indicates that the APB bus module is making a read request, and the / CS and the read enable pin / RD are pulled low. S2: Establish time-waiting state; in this state, if / WR is low, wait for T1 time and then jump to S3; if / RD is low, wait for T2 time and then jump to S3. S3: Data sampling state; In this state, if / WR is low, the fetch signal is set to high. At this time, the CPU assigns the APB write data bus signal PWDATA[15:0] to the network card chip's data bus DATA[15:0] and jumps to S4; If / RD is low, data is read from DATA[15:0] to the APB read data bus signal PRDATA[15:0] and jumps to S4. S4: Chip select time wait state; in this state, if / WR is low, wait for T3 time and then jump to S5; if / RD is low, wait for T4 time and then jump to S5. S5: Completed state; In this state, pull / WR, / RD, and / CS all high, then jump to S6; S6: Chip select interval wait state; in this state, after waiting for T5 time, jump to S0.

2. The bus interface type network card chip control system according to claim 1, characterized in that, The FPGA uses 4-byte alignment, and the soft processor core is MicroBlaze; the APB bus module's protocol version is APB3 based on the AMBA3 standard, where: The frequency of the APB bus clock signal PCLK is the same as the main frequency of the MicroBlaze. In the 32-bit bus address PADDR of APB, only the lower 12 bits are used, of which PADDR[1:0] are reserved bits for four-byte alignment. In addition, data using PADDR[11:2] is passed to the address bus ADDR[9:0] of the network card chip. APB’s 32-bit write data bus signal PWDATA only uses its lower 16 bits to transmit data to the network card chip’s data bus DATA[15:0]; APB's 32-bit read data bus signal PRDATA uses only its lower 16 bits to read data from the network card chip's DATA[15:0].

3. The bus interface type network card chip control system according to claim 1, characterized in that, When the FPGA CPU initiates a write operation, the APB slave chip select signal PSEL and the APB read / write control signal PWRITE of the APB bus module are set to high level, and the physical address of the output register is displayed on the 32-bit bus address PADDR of the APB. After one cycle of the APB bus clock signal PCLK, the APB enable signal PENABLE jumps to high level. When the ready signal PREADY is high level, the data PWDATA[15:0] is transmitted to the DATA[15:0] of the network card chip. The data in DATA[15:0] will be written into the register with address ADDR[9:0] within the sampling time of the network card chip. When the FPGA CPU initiates a read operation, the PSEL of the APB bus module is set to high level, PWRITE is set to low level, and the physical address of the output register on PADDR is displayed. A read mode with a wait condition is used, that is, when PSEL is set to high level for one PCLK cycle, and PENABLE jumps to high level, the PREADY signal is first pulled low. The PREADY signal is only pulled high after the data on DATA[15:0] of the network card chip is ready, and the data on DATA[15:0] is assigned to PRDATA[15:0]. At this time, the read operation is completed.

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