Integrated circuit, main circuit, electronic device, and heat control method

Abstract

The present application provides an integrated circuit (IC) configurable to perform adaptive thermal upper limit control in a per-function block manner, an associated main circuit, an associated electronic device, and an associated thermal control method. The IC includes a plurality of hardware circuits arranged to perform operations of a first function block and at least one thermal control circuit. At least one temperature sensor is integrated with the first function block to detect a temperature of the first function block and generate at least one temperature detection result of the first function block. The thermal control circuit performs thermal control of the first function block by monitoring the temperature detection result and attempting to prevent the temperature detection result from exceeding a first temperature upper limit configurable with respect to a per-function block thermal operating capability of the first function block to prevent the first function block from overheating and causing operational anomalies.

Description

TECHNICAL FIELD

[0001] The present application relates to circuit design, and more particularly, to an integrated circuit (IC) configurable to perform adaptive thermal ceiling control in a per-functional-block manner, an associated master circuit, an associated electronic device, and a related thermal control method. BACKGROUND

[0002] According to the related art, a control circuit in an electronic device is implemented by way of IC manufacturing. For example, a design company designs a circuit (e.g., a control circuit) according to some design rules, and a production process can be performed in one or more highly specialized semiconductor manufacturing plants, which can be referred to as foundries or fabs. Further, a system running on the control circuit is designed to operate according to a maximum thermal equilibrium point (e.g., a throttling point) for better performance while preventing the system from entering an overheated state that causes the system to restart or operate abnormally. However, some problems can occur. The maximum thermal equilibrium point (e.g., a throttling point) is usually a fixed throttling point based on pre-silicon worst case analysis, and the pre-silicon worst case analysis pessimistically limits system performance, where the fixed throttling point is determined in advance before the IC mass production stage according to the pre-silicon worst case analysis. Therefore, a novel method and related architecture are needed to further enhance system performance without introducing side effects or in a way that is less likely to introduce side effects. SUMMARY

[0003] The following summary is illustrative only and is not intended to be limiting in any way. In other words, the following summary is provided to introduce some concepts, highlights, benefits and advantages of the novel and non-obvious technology described herein. Selected implementations are described in further detail in the detailed description. As such, the following summary is not intended to be used to identify key or essential features of the claimed subject matter nor is it intended for use in determining the scope of the claimed subject matter.

[0004] An object of the present application is to provide an IC configurable to perform adaptive thermal ceiling control in a per-functional-block manner, an associated master circuit, an associated electronic device, and a related thermal control method, which can further enhance system performance.

[0005] In a first aspect, the present invention provides an integrated circuit (IC) configurable to perform adaptive thermal upper limit control on a per-functional-block basis. The IC includes: a plurality of hardware circuits for performing operations of a first functional block, wherein at least one temperature sensor is integrated with the first functional block (i.e., at least one temperature sensor is associated with the first functional block) for detecting the temperature of the first functional block and generating at least one temperature detection result for the first functional block; and...

[0006] At least one thermal control circuit is configured to thermally control the first functional block by monitoring at least one temperature detection result of the first functional block and attempting to prevent the at least one temperature detection result of the first functional block from exceeding a first temperature limit of the first functional block of the IC, so as to prevent the first functional block from overheating and causing abnormal operation, wherein the first temperature limit is configured according to at least one per-functional-block thermal operation capability of the first functional block.

[0007] In some embodiments, the IC includes a plurality of functional blocks, the first functional block being one of the plurality of functional blocks, wherein a plurality of temperature sensors detect temperature and generate a plurality of temperature detection results of the plurality of functional blocks respectively; and the at least one thermal control circuit is configured to perform thermal control on the plurality of functional blocks respectively by monitoring the plurality of temperature detection results of the plurality of functional blocks and by attempting to prevent each of the plurality of temperature detection results of the plurality of functional blocks from exceeding a corresponding first temperature upper limit of a plurality of first temperature upper limits of the plurality of functional blocks, so as to prevent the plurality of functional blocks from overheating and causing abnormal functional operation.

[0008] In some embodiments, the at least one per-function-block thermal operation capability includes the power-thermal efficiency of the corresponding function block within the IC.

[0009] In some embodiments, the at least one per-function-block thermal operation capability includes the maximum voltage budget of the corresponding function block within the IC.

[0010] In some embodiments, the at least one per-function-block thermal operating capability includes the maximum power budget of the corresponding function block within the IC.

[0011] In some embodiments, the at least one per-function-block thermal operation capability includes the thermal control efficiency of the corresponding function block within the IC.

[0012] In some embodiments, the at least one per-function-block thermal operating capability includes operating power efficiency related to the temperature level of the corresponding function block within the IC.

[0013] In some embodiments, the at least one per-function-block hot-operation capability includes a reliability budget for the corresponding function block within the IC.

[0014] In some embodiments, the first temperature upper limit is configured as an adaptive thermal upper limit point within a predetermined temperature region according to the at least one function- by-function thermal operation capability, wherein a maximum of the predetermined temperature region is less than a second temperature upper limit of the first function block of the IC; the second temperature upper limit is determined according to a first function-by-function thermal sensor related characteristic such that a temperature region between the second temperature upper limit and a third temperature upper limit of the first function block of the IC corresponds to the first function-by-function thermal sensor related characteristic, wherein the third temperature upper limit is greater than the second temperature upper limit, and the third temperature upper limit represents a temperature upper limit without considering the first function-by-function thermal sensor related characteristic.

[0015] In some embodiments, the first function-by-function thermal sensor related characteristic represents a function-by-function thermal sensor detection tolerance related to a location of at least one temperature sensor integrated to a corresponding function block.

[0016] In some embodiments, the first function-by-function thermal sensor related characteristic represents a function-by-function thermal sensor accuracy related to at least one temperature detection accuracy of at least one temperature sensor integrated to a corresponding function block.

[0017] In some embodiments, the third temperature upper limit is determined according to a second function-by-function thermal sensor related characteristic such that a temperature region between the third temperature upper limit and a fourth temperature upper limit corresponds to the second function-by-function thermal sensor related characteristic, wherein the fourth temperature upper limit is greater than the third temperature upper limit, and the fourth temperature upper limit represents a temperature upper limit without considering the first function-by-function thermal sensor related characteristic and the second function-by-function thermal sensor related characteristic.

[0018] In some embodiments, the first function-by-function thermal sensor related characteristic represents a function-by-function thermal sensor detection tolerance related to a location of at least one temperature sensor integrated to a corresponding function block; the second function-by-function thermal sensor related characteristic represents a function-by-function thermal sensor accuracy related to at least one temperature detection accuracy of at least one temperature sensor integrated to a corresponding function block.

[0019] In some embodiments, the first function-by-function thermal sensor related characteristic represents a function-by-function thermal sensor accuracy related to at least one temperature detection accuracy of at least one temperature sensor integrated to a corresponding function block; the second function-by-function thermal sensor related characteristic represents a function-by-function thermal sensor detection tolerance related to a location of at least one temperature sensor integrated to a corresponding function block.

[0020] In some embodiments, the fourth temperature upper limit is a strict upper limit defined by manufacturing conditions provided by a manufacturer of the IC.

[0021] In some embodiments, the IC comprises a plurality of functional blocks, and the first functional block is a functional block among the plurality of functional blocks, one of the first per-functional-block thermal sensor related characteristic and the second per-functional-block thermal sensor related characteristic represents a per-functional-block thermal sensor accuracy; wherein the per-functional-block thermal sensor accuracy is related to at least one temperature detection accuracy of the at least one temperature sensor integrated to the first functional block, or the per-functional-block thermal sensor accuracy is related to respective temperature detection accuracies of at least a portion of a plurality of temperature sensors associated with the plurality of functional blocks.

[0022] In some embodiments, the per-functional-block thermal sensor accuracy is an average of the at least one temperature detection accuracy.

[0023] In some embodiments, the per-functional-block thermal sensor accuracy is a statistical value of the at least one temperature detection accuracy.

[0024] In some embodiments, the per-functional-block thermal sensor accuracy is a worst temperature detection accuracy among the at least one temperature detection accuracy.

[0025] In some embodiments, the at least one per-functional-block thermal operation capability of the first functional block within the IC is determined by performing a functional block or chip grouping procedure on the IC.

[0026] In some embodiments, the at least one thermal control circuit is implemented in a manner of at least one of hardware, software running on the first functional block, or a mixture of hardware and software.

[0027] In a second aspect, the present application provides a host circuit comprising an IC as described above, wherein the first temperature upper limit is a first chip-level temperature upper limit; and the host circuit further comprises: at least one other IC for performing at least one other operation for the IC; and a plurality of substrate-level temperature sensors for performing temperature detection within the host circuit to generate respective temperature detection results of the IC and the at least one other IC; wherein the at least one thermal control circuit is configured to perform thermal control on the IC and the at least one other IC by monitoring the respective temperature detection results of the IC and the at least one other IC and attempting to prevent the respective temperature detection results of the IC and the at least one other IC from exceeding at least one first substrate-level temperature upper limit of the host circuit, to prevent the IC and the at least one other IC from overheating and causing abnormal operation, wherein the at least one first substrate-level temperature upper limit is configured according to at least one per-substrate-level component thermal operation capability of the host circuit.

[0028] In a third aspect, the present application provides an electronic device comprising a main circuit as described above, wherein the main circuit is a main component of the electronic device, and the electronic device further comprises: at least one secondary component arranged to operate under the control of the main circuit; and a plurality of device-level temperature sensors for performing temperature detection within the electronic device to respectively generate corresponding temperature detection results of the main circuit and the at least one secondary component; wherein the at least one thermal control circuit is configured to thermally control the main circuit and the at least one secondary component by monitoring the corresponding temperature detection results of the main circuit and the at least one secondary component and in a manner that attempts to prevent the corresponding temperature detection results of the main circuit and the at least one secondary component from exceeding at least one first device-level temperature upper limit of the electronic device, to prevent the main circuit and the at least one secondary component from overheating and causing operational abnormalities, wherein the at least one first device-level temperature upper limit is configured according to at least one per-device-level component thermal operating capability of the electronic device.

[0029] In a fourth aspect, the present application provides a thermal control method applicable to at least one functional block of an integrated circuit (IC), the at least one functional block being configurable to perform adaptive thermal upper limit control in a per-functional block manner, the thermal control method comprising: detecting temperature using at least one temperature sensor integrated with a first functional block of the at least one functional block of the IC and generating at least one temperature detection result of the first functional block; and thermally controlling the first functional block by monitoring the at least one temperature detection result of the first functional block and in a manner that attempts to prevent the at least one temperature detection result from exceeding a first temperature upper limit of the first functional block of the IC, to prevent the first functional block from overheating and causing operational abnormalities, wherein the first temperature upper limit is configured according to at least one per-functional block thermal operating capability of the first functional block.

[0030] In some embodiments, the step of detecting temperature using at least one temperature sensor integrated with a first functional block of the at least one functional block of the IC and generating at least one temperature detection result of the first functional block and the step of thermally controlling the first functional block by monitoring the at least one temperature detection result of the first functional block and in a manner that attempts to prevent the at least one temperature detection result from exceeding a first temperature upper limit of the first functional block of the IC, to prevent the first functional block from overheating and causing operational abnormalities, are performed in a user phase of the IC, wherein the at least one per-functional block thermal operating capability is determined by performing a functional block or chip grouping procedure on the IC.

[0031] In some embodiments, the thermal control method is further applicable to a host circuit including the IC, the first temperature upper limit is a first chip-level temperature upper limit, and the thermal control method further includes: performing temperature detection within the host circuit using a plurality of substrate-level temperature sensors to generate respective temperature detection results of the IC and at least one other IC within the host circuit; and thermally controlling the IC and the at least one other IC by monitoring the respective temperature detection results of the IC and the at least one other IC and in a manner that attempts to prevent the respective temperature detection results of the IC and the at least one other IC from exceeding at least one first substrate-level temperature upper limit of the host circuit to prevent the IC and the at least one other IC from overheating to cause operational abnormality, wherein the at least one first substrate-level temperature upper limit is configured according to at least one per-substrate-level component thermal operating capability of the host circuit.

[0032] In some embodiments, the thermal control method is further applicable to an electronic device including the host circuit, wherein the host circuit is a primary component of the electronic device, and the thermal control method further includes: performing temperature detection within the electronic device using a plurality of device-level temperature sensors to generate respective temperature detection results of the host circuit and at least one secondary component within the electronic device; and thermally controlling the host circuit and the at least one secondary component by monitoring the respective temperature detection results of the host circuit and the at least one secondary component and in a manner that attempts to prevent the respective temperature detection results of the host circuit and the at least one secondary component from exceeding at least one first device-level temperature upper limit of the electronic device to prevent the host circuit and the at least one secondary component from overheating to cause operational abnormality, wherein the at least one first device-level temperature upper limit is configured according to at least one per-device-level component thermal operating capability of the electronic device.

[0033] The summary of the application is provided by way of example, and is not intended to limit the application. Other embodiments and advantages are described in the following detailed description. The application is defined by the claims. These and other objects of the application will be more fully understood and appreciated by reading the following detailed description, taken together with the accompanying drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0034] The application will be more fully understood and appreciated by reading the following detailed description, taken together with the accompanying drawings, in which:

[0035] Figure 1A is a schematic diagram of an integrated circuit (IC) according to an embodiment of the application.

[0036] Figure 1B is a schematic diagram illustrating some implementation details of the IC shown in FIG. 1 according to an embodiment of the application.

[0037] Figure 2 is a schematic diagram illustrating a system on chip (SoC) thermal control scheme applicable to a thermal control method according to an embodiment of the present application.

[0038] Figure 3 is a schematic diagram illustrating an adaptive thermal cap point control scheme (may also be described as an "adaptive thermal cap control scheme") of a thermal control method according to an embodiment of the present application.

[0039] Figure 4 is a schematic diagram illustrating an adaptive thermal cap control scheme for each functional block of a thermal control method according to an embodiment of the present application.

[0040] Figure 5 is a schematic diagram illustrating some implementation details of at least one multi- software architecture segment (part) adaptive cap policy controlling different levels (e.g., pre-throttle level decisions) that can be used in a thermal control method according to an embodiment of the present application.

[0041] Figure 6 is a schematic diagram illustrating some implementation details of at least one multi- hardware architecture level adaptive cap policy that can be used in a thermal control method according to an embodiment of the present application.

[0042] Figure 7 is a schematic diagram illustrating some implementation details of the aforementioned at least one multi- hardware architecture level adaptive cap policy that can be used in a thermal control method according to another embodiment of the present application.

[0043] Figure 8 is a schematic diagram illustrating a thermal operating capability assessment control scheme of a thermal control method according to a first embodiment of the present application.

[0044] Figure 9 is a schematic diagram illustrating a thermal operating capability assessment control scheme of a thermal control method according to a second embodiment of the present application.

[0045] Figure 10 is a schematic diagram illustrating a thermal operating capability assessment control scheme of a thermal control method according to a third embodiment of the present application.

[0046] Figure 11 is a schematic diagram illustrating a thermal operating capability assessment control scheme of a thermal control method according to a fourth embodiment of the present application.

[0047] Figure 12 is a schematic diagram illustrating a thermal operating capability assessment control scheme of a thermal control method according to a fifth embodiment of the present application.

[0048] Figure 13 is a schematic diagram illustrating a thermal operating capability assessment control scheme of a thermal control method according to a sixth embodiment of the present application.

[0049] Figure 14 A flow chart of a heat control method is shown according to an embodiment of the present application.

[0050] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the application. However, it will be apparent to one skilled in the art that one or more embodiments of the present application can be practiced without these specific details. In other instances, well-known methods have not been described in detail in order to avoid unnecessarily obscuring the embodiments of the present application. DETAILED DESCRIPTION

[0051] The following description is provided for the purposes of illustrating the general principles of the application, and is not meant to limit the present application in its broader aspects. The present application is described with reference to the attached drawings, wherein like reference numerals refer to like elements throughout the several views. The drawings described are intended to be illustrative, and not restrictive, of the present application. Certain terminology can also be used in the following description for the purpose of reference only, and thus is not intended to limit the present application. For example, the terms "one", "said" and "the" are open-ended, which means that they are intended to cover the singular as well as the plural, unless the context clearly indicates otherwise. Similarly, the term "another" is used interchangeably with the term "second". The terms "comprising", "comprise", "including", "include", "contain", "contain" or "has" are used generically that is, the terms are intended to encompass both the clean inclusion, and instances in which one or more additional elements are also present. The term "coupled" is used to express an indirect or direct electrical connection between two elements. Thus, if an element is described as being coupled to another element, it means that the element can be directly electrically connected to the other element, or indirectly electrically connected to the other element through other elements or connections.

[0052] Throughout the drawings, like reference numerals will be understood to refer to like parts, components and structures.

[0053] The terms "substantially" or "approximately" as used herein, mean within an acceptable range of the technical person skilled in the art, who can solve the technical problem to be solved, and substantially achieve the technical effect to be achieved. For example, "substantially equal" means that within an acceptable range, the skilled person can accept a certain error from "exactly equal" without affecting the correctness of the result.

[0054] It can be appreciated that in the description of the present application, the symbol {} is used to represent a set / collectively refer to a plurality. In addition, the description of "temperature sensor integrated with a functional block" or "temperature sensor integrated with a functional block" and the like described in the embodiments of the present application shall include a temperature sensor integrated in a functional block or integrated beside / adjacent to a functional block, and is not limited to only a temperature sensor integrated in a functional block, that is, it is used to represent that "the temperature sensor is associated with the functional block to detect the temperature of the functional block and generate a corresponding temperature detection result".

[0055] Figure 1A is a schematic diagram of an integrated circuit (IC) 100 according to an embodiment of the present application. The IC 100 can include a plurality of functional blocks, for example, N functional blocks, where the symbol "N" can represent a positive integer greater than 1 (including the case of equal to 1). More particularly, the plurality of functional blocks (e.g., N functional blocks) can include functional blocks 110_1, 110_2,..., and 110_N. Examples of the plurality of functional blocks can include, but are not limited to, a microprocessor, such as a central processing unit (CPU), a graphic processing unit (GPU), an accelerated processing unit (APU), and a modulator-demodulator (Modem). In addition to the functional blocks 110_1, 110_2,..., and 110_N, the IC 100 can also include at least one thermal control circuit (e.g., one or more thermal control circuits), which can be collectively referred to as a thermal control circuit 120. For better understanding, the IC 100 can represent a control circuit in an electronic device, and more particularly, can represent a processing circuit including at least one processor / microprocessor, etc., but the present application is not limited thereto.

[0056] IC 100 includes one or more temperature sensors integrated with any of the functional blocks 110_1, 110_2,... and 110_N, and more particularly, can include a plurality of temperature sensors respectively integrated with the functional blocks 110_1, 110_2,... and 110_N (e.g., integrated next to or into the functional blocks), such that any of the plurality of temperature sensors is within or next to a sub-area of a layout area of one of the functional blocks 110_1, 110_2,... and 110_N, respectively. It can be appreciated that in embodiments of the present application, at least one temperature sensor integrated into a functional block (also described as "at least one temperature sensor integrated with a functional block") can be within (i.e., in) and / or next to a layout area of the corresponding functional block; or in other words, each functional block is associated with at least one temperature sensor for detecting a temperature of the associated functional block and generating at least one temperature detection result. For ease of illustration and understanding, Figure 2 Six temperature sensors integrated into the functional block 110_1, two temperature sensors integrated into the functional block 110_2, two temperature sensors integrated into the functional block 110_3, and four temperature sensors integrated into the functional block 110_4 are shown in FIG. 1, but the present application is not limited thereto. For better understanding, any of the functional blocks 110_n (e.g., the symbol "n" can represent an integer falling within the interval [1, N]) of the functional blocks 110_1, 110_2,... and 110_N can include a plurality of hardware circuits 111_n, e.g., original internal hardware circuits of the any of the functional blocks 110_n before any of the plurality of temperature sensors is integrated with the any of the functional blocks 110_n. Any of the functional blocks 110_n can also include at least one temperature sensor (e.g., a plurality of temperature sensors), which can be collectively referred to as one or more temperature sensors 112_n. As shown in FIG. 1, Figure 1AAs shown, functional block 110_1 includes hardware circuit(s) 111_1 and temperature sensor(s) 112_1, functional block 110_2 includes hardware circuit(s) 111_2 and temperature sensor(s) 112_2, and so on, e.g., functional block 110_N includes hardware circuit(s) 111_N and temperature sensor(s) 112_N. For example, functional block 110_1 can represent a CPU. In this case, hardware circuit 111_1 of functional block 110_1 can include a CPU that is located within a main sub-region of a layout region of functional block 110_1, e.g., original internal hardware circuitry of functional block 110_1 prior to integration of one or more temperature sensors 112_1 with functional block 110_1, where any of the one or more temperature sensors 112_1 can be located within or outside of the main sub-region of the layout region of functional block 110_1, and, more particularly, can be located next to the main sub-region of the layout region of functional block 110_1 and / or within at least one remaining sub-region (e.g., one or more remaining sub-regions) of the layout region of functional block 110_1. For another example, functional block 110_2 can represent a GPU. In this case, hardware circuit 111_2 of functional block 110_2 can include a GPU that is located within a main sub-region of a layout region of functional block 110_2, e.g., original internal hardware circuitry of functional block 110_2 prior to integration of one or more temperature sensors 112_2 with functional block 110_2, where any of the one or more temperature sensors 112_2 can be located within or outside of the main sub-region of the layout region of functional block 110_2, and, more particularly, can be located next to the main sub-region of the layout region of functional block 110_2 and / or within at least one remaining sub-region (e.g., one or more remaining sub-regions) of the layout region of functional block 110_2.

[0057] IC 100 can be configured to perform adaptive thermal ceiling control in a per- functional-block manner, or in other words, individualized thermal ceiling control for each IC in a single functional block manner. Hardware circuit 111_n can be arranged to perform operations of functional block 111_n, and temperature sensor(s) 112_n can be arranged to perform temperature sensing related to functional block 110_n to generate at least one temperature sensing result (e.g., one or more temperature sensing results) of functional block 110_n. Furthermore, thermal control circuit 120 can be configured to perform thermal control for a plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N), and more particularly, to perform thermal control for functional block 110_n by monitoring the at least one temperature sensing result of functional block 110_n and trying to prevent the at least one temperature sensing result of functional block 110_n from exceeding a first temperature upper-limit UL1 of functional block 110_n to prevent functional block 110_n from overheating and causing operational abnormality. It can be appreciated that in embodiments of the present application, for a case where a single IC includes a plurality of functional blocks, a first temperature upper-limit based on a thermal operating capability of a corresponding functional block can be set for a portion or all of the plurality of functional blocks (may also be described as “at least a portion of the functional blocks”, and in embodiments of the present application, for the convenience of understanding and description, all of the functional blocks are exemplarily described, but the present application is not limited thereto), and the first temperature upper-limit of each functional block in the at least a portion of the functional blocks is configured / determined based on the thermal operating capability of the functional block itself.For example, the N functional blocks 110_1, 110_2, …, and 110_N can have N first temperature upper limits {UL1}, but the present application is not limited thereto, for example, the N functional blocks 110_1, 110_2, …, and 110_N can have M (e.g., M < N) first temperature upper limits {UL1}, for example, it can be that only the most concerned temperature or the most core M functional blocks among the N modules are respectively set based on the first temperature upper limit of the corresponding functional block, but the embodiments of the present application do not limit this, as long as any one functional block or multiple functional blocks (e.g., part or all functional blocks) in the IC are implemented in the unit of functional blocks and based on the first temperature upper limit of the corresponding functional block determined by the thermal operating capability of the corresponding functional block, and similarly, as described in the following embodiments, the main circuit can be executed in the manner of each substrate-level component, and the electronic device can be executed in the manner of each device-level component, and similarly, the adaptive thermal upper limit control executed in the manner of each functional block, and similar embodiments of the main circuit and the electronic device will not be repeated. In a preferred embodiment, the IC has N functional blocks, and the N functional blocks have N first temperature upper limits {UL1}, wherein each of the functional blocks 110_1, 110_2, …, and 110_N has a corresponding first temperature upper limit UL1. For ease of description and understanding, the multiple first temperature upper limits corresponding to the multiple functional blocks can be represented as a set {UL1}, for example, UL1_1 in {UL1} is the first temperature upper limit corresponding to the functional block 110_1, UL1_2 in {UL1} is the first temperature upper limit corresponding to the functional block 110_2, …, and UL1_N in {UL1} is the first temperature upper limit corresponding to the functional block 110_N, wherein the first temperature upper limit UL1 (e.g., UL1_1, UL1_2, …, UL1_N) is determined in the unit of functional blocks in the IC and based on the thermal operating capability of each functional block, that is, the present application provides an individual differentiated temperature upper limit control scheme. That is, UL1_n (wherein n is any integer in 1 to N) can be used to represent the first temperature upper limit corresponding to the functional block 110_n, which is determined according to the thermal operating capability of the functional block 110_n. In the embodiments of the present application, the first temperature upper limit UL1 of any of the aforementioned functional blocks 110_n in the functional blocks 110_1, 110_2, …, and 110_N in the IC 100 is configurable with respect to at least one item of the thermal operating capability of the functional block 110_n (e.g., one or more items of the thermal operating capability of the functional block), and more particularly, the multiple first temperature upper limits {UL1} are respectively configurable with respect to the aforementioned at least one item of the thermal operating capability of the functional block (e.g., one or more items of the thermal operating capability of the functional block), for example, the thermal operating capability of the functional block 110_1, 110_2, …, and 110_N in the IC 100.For better understanding, the plurality of first temperature upper limits {UL1} represent a plurality of thermal ceiling target values of the functional blocks 110_1, 110_2, …, and 110_N, respectively, to prevent the functional blocks 110_1, 110_2, …, and 110_N from overheating, and the at least one first temperature upper limit UL1 can represent a thermal ceiling target value of the functional blocks 110_1, 110_2, …, and 110_N to prevent the functional blocks 110_1, 110_2, …, and 110_N from overheating. For example, during a time interval between a start time point of a boot-up of the IC 100 and an end time point of a shutdown of the IC 100, the thermal control circuit 120 can be arranged to perform thermal control (e.g., control respective power consumptions of the functional blocks 110_1, 110_2, …, and 110_N) of the functional blocks 110_1, 110_2, …, and 110_N by monitoring the temperature detection results of each functional block (e.g., at least one temperature detection result of the functional block 110_n) and by attempting to prevent the temperature detection results of each functional block from exceeding the functional block-specific first temperature upper limit UL1 (e.g., the first temperature upper limit UL1_n corresponding to the functional block 110_n among the plurality of first temperature upper limits {UL1}) to prevent the functional blocks 110_1, 110_2, …, and 110_N from overheating to cause operational abnormality. The at least one per-functional-block thermal operation capability can include, but is not limited to, a power-to-thermal efficiency of the functional block 110_n, a maximum voltage budget of the functional block 110_n, a maximum power budget of the functional block 110_n, a thermal control efficiency of the functional block 110_n, an operation power efficiency related to a temperature level of the functional block 110_n, and a reliability budget of the functional block 110_n. It can be understood that, in embodiments of the present application, the thermal operation capability refers to a temperature-related operation capability or limitation. For example, the “per-functional-block thermal operation capability” refers to a thermal operation capability of a corresponding functional block obtained in units of functional blocks within an IC, for example. Figure 2The illustrated IC includes four functional blocks, such that a respective thermal operating capability can be determined for each functional block, i.e., the thermal operating capability corresponding to each functional block can be referred to as a “per-functional-block thermal operating capability,” where each per-functional-block thermal operating capability is associated with a respective functional block. Similarly, within the main circuit 200 (e.g., a circuit including multiple ICs on the same substrate), the main circuit 200 includes multiple substrate-level components (i.e., multiple ICs, such as IC 100, IC 220, IC 230, IC 240), such that obtaining a thermal operating capability for a respective substrate-level component on a substrate-level component basis can be referred to as a “per-substrate-level-component thermal operating capability,” i.e., the thermal operating capability corresponding to each substrate-level component can be referred to as a “per-substrate-level-component thermal operating capability,” where each per-substrate-level-component thermal operating capability is associated with a respective substrate-level component. Similarly, within the electronic device 300, the electronic device 300 includes multiple device-level components (such as Figure 5 the illustrated 200, 320, 330, 340, 350, 360), such that obtaining a thermal operating capability for a respective device-level component on a device-level component basis can be referred to as a “per-device-level-component thermal operating capability,” i.e., the thermal operating capability corresponding to each device-level component can be referred to as a “per-device-level-component thermal operating capability,” where each per-device-level-component thermal operating capability is associated with a respective device-level component. Embodiments of the present disclosure describe examples of per-functional-block thermal operating capabilities (such as Figures 8 to 13 For example, the per-functional-block thermal operating capabilities for the functional blocks within an IC can be obtained by testing / verifying the IC (e.g., by performing a binning flow on the IC to obtain the respective thermal operating capabilities), although the present disclosure is not limited thereto. Furthermore, one of ordinary skill in the art can obtain per-substrate-level-component thermal operating capabilities, per-device-level-component thermal operating capabilities (e.g., by testing / verifying the ICs within the main circuit, by testing / verifying the device-level components within the electronic device, etc.) based on similar ideas, although similar descriptions of embodiments of the present disclosure are not repeated.

[0058] According to some embodiments, the at least one per-functional-block thermal operating capability can include a combination of one or any of a power-thermal efficiency of the functional block 110_n, a maximum voltage budget of the functional block 110_n, a maximum power budget of the functional block 110_n, a thermal control efficiency of the functional block 110_n, an operational power efficiency related to a temperature level of the functional block 110_n, and a reliability budget of the functional block 110_n.

[0059] Figure 1Bis a schematic diagram illustrating some implementation details of the IC shown in FIG. 1 according to an embodiment of the present application. For better understanding, the aforementioned at least one thermal control circuit (e.g., the thermal control circuit 120) can include a plurality of thermal control circuits, e.g., the thermal control circuits 120_1, 120_2, …, and 120_N respectively corresponding to the functional blocks 110_1, 110_2, …, and 110_N, but the present application is not limited thereto. Moreover, within a time interval between a starting time point at which the IC 100 is started and an ending time point at which the IC 100 is shut down, the thermal control circuits 120_1, 120_2, …, and 120_N can be arranged to respectively thermally control (e.g., control power consumption of) the functional blocks 110_1, 110_2, …, and 110_N by monitoring respective temperature detection results of the functional blocks 110_1, 110_2, …, and 110_N and by trying to prevent the respective temperature detection results of the functional blocks 110_1, 110_2, …, and 110_N from exceeding first upper limits UL1_1, UL1_2, …, and UL1_N of the plurality of first upper limits {UL1} respectively corresponding to the functional blocks 110_1, 110_2, …, and 110_N, respectively, to prevent the functional blocks 110_1, 110_2, …, and 110_N from overheating and causing operational abnormality. For brevity, similar descriptions of this embodiment are not repeated here. For example, the functional block 110_1 is thermally controlled (e.g., power consumption of the functional block 110_1 is controlled) by monitoring a temperature detection result of the functional block 110_1 and by trying to prevent the temperature detection result of the functional block 110_1 from exceeding the first upper limit UL1_1 corresponding to the functional block 110_1, to prevent the functional block 110_1 from overheating and causing operational abnormality; the functional block 110_2 is thermally controlled (e.g., power consumption of the functional block 110_2 is controlled) by monitoring a temperature detection result of the functional block 110_2 and by trying to prevent the temperature detection result of the functional block 110_2 from exceeding the first upper limit UL1_2 corresponding to the functional block 110_2, to prevent the functional block 110_2 from overheating and causing operational abnormality; the functional block 110_3 is thermally controlled (e.g., power consumption of the functional block 110_3 is controlled) by monitoring a temperature detection result of the functional block 110_3 and by trying to prevent the temperature detection result of the functional block 110_3 from exceeding the first upper limit UL1_3 corresponding to the functional block 110_3, to prevent the functional block 110_3 from overheating and causing operational abnormality; and the functional block 110_4 is thermally controlled (e.g., power consumption of the functional block 110_4 is controlled) by monitoring a temperature detection result of the functional block 110_4 and by trying to prevent the temperature detection result of the functional block 110_4 from exceeding the first upper limit UL1_4 corresponding to the functional block 110_4, to prevent the functional block 110_4 from overheating and causing operational abnormality.In this embodiment of the invention, the first temperature limit for each functional block is determined based on the thermal operating capability of the corresponding functional block (i.e., "functional block-by-functional-block thermal operating capability"). Therefore, for different ICs or different functional blocks within the same IC, the first temperature limit for each functional block is configurable based on the functional block's (i.e., its own functional block) functional block's functional block-by-functional-block thermal operating capability. For example, the multiple first temperature limits obtained for different functional blocks within the same IC may be different; similarly, the multiple first temperature limits obtained for different functional blocks with the same function within different ICs may also be different. Thus, the present invention's thermal control within an IC at the level of a single functional block (also described as "each functional block") can further improve system performance. For example, it allows one or more functional blocks to operate differently in high-performance regions, rather than uniformly fixed in the worst-performance region.

[0060] Figure 2 This is an illustration of an embodiment of the invention applicable to ICs (such as...) Figure 1A The diagram illustrates a system-on-chip (SoC) thermal control scheme for the IC 100 shown, for example, at least one of its functional blocks 110_1, 110_2, ..., and 110_N. For example, the number N of functional blocks 110_1, 110_2, ..., and 110_N can be greater than or equal to 1. For better understanding, Figure 2 The embodiments are illustrated using functional blocks 110_1, 110_2, 110_3, and 110_4, but the invention is not limited thereto. In this case, functional blocks 110_1, 110_2, 110_3, and 110_4 may represent a CPU, GPU, APU, and Modem (labeled "MD" in the figures for simplicity), and the hardware circuits 111_1, 111_2, etc. of functional blocks 110_1 and 110_2 may include a CPU, GPU, etc. (e.g., the original internal hardware circuits of functional blocks 110_1 and 110_2, etc., before the temperature sensors 112_1, 112_2, etc. are integrated with functional blocks 110_1 and 110_2, etc.), which are located in the main sub-regions of the layout area of ​​functional blocks 110_1 and 110_2, etc., respectively, wherein the temperature sensors 112_1, 112_2, etc. (e.g., Figure 1B The TS shown in the figure can be located within or outside the main sub-regions of the layout areas of functional blocks 110_1, 110_2, etc. More specifically, they can be located next to the main sub-regions of the layout areas of functional blocks 110_1, 110_2, etc. and / or within the remaining sub-regions of the layout areas of functional blocks 110_1, 110_2, etc.

[0061] For better understanding, the plurality of temperature sensors can include a plurality of groups of temperature sensors (labeled as "T" for brevity) integrated with (e.g., integrated next to / in the functional blocks) the functional blocks 110_1, 110_2, etc. respectively, e.g., a first group of temperature sensors {TS(1), TS(2), TS(3), TS(4), TS(5), TS(6)} integrated into the functional block 110_1, a second group of temperature sensors {TS(7), TS(8)} integrated into the functional block 110_2, a third group of temperature sensors {TS(9), TS(10)} integrated into the functional block 110_3, a fourth group of temperature sensors {TS(15), TS(16), TS(17), TS(18)} integrated into the functional block 110_4, and at least one other group of temperature sensors {TS(11), TS(12), TS(13), TS(14)} integrated with (e.g., next to or in the functional blocks) at least one other functional block, but the present application is not limited thereto, e.g., in some embodiments, the temperature sensors associated with the functional blocks can be located next to the respective functional blocks, not necessarily inside the respective functional blocks, thus, in the present application, the temperature sensors are integrated with the functional blocks means that the temperature sensors are associated with (e.g., located inside or outside (e.g., next to) the functional blocks) the functional blocks so that the temperatures detected by the temperature sensors can better reflect the temperatures of the associated functional blocks, i.e., detect the temperatures of the associated functional blocks and generate temperature detection results. In embodiments of the present application, each functional block is associated with at least one temperature sensor, wherein the at least one temperature sensor associated with the respective functional block detects the temperature of the functional block associated therewith. In addition, the at least one thermal control circuit (e.g., the thermal control circuit 120) described above can be implemented by hardware and / or software, e.g., pure hardware, or at least one hybrid module (e.g., one or more hybrid modules) of hardware and software, and can be implemented as a single thermal control circuit (labeled as "TCC" for brevity) for collecting the temperature detection results of all the functional blocks 110_1, 110_2, etc. and controlling the functional blocks 110_1, 110_2, etc. in a centralized temperature detection and thermal control architecture, or can be implemented as a plurality of thermal control circuits, e.g., the thermal control circuits 120_1, 120_2, etc. corresponding to the functional blocks 110_1, 110_2, etc. respectively, for collecting the temperature detection results of the thermal control circuits 120_1, 120_2, etc. and controlling the functional blocks 110_1, 110_2, etc. in a distributed temperature detection and thermal control architecture. For brevity, similar descriptions of the embodiments are not repeated here.

[0062] According to some embodiments, the thermal control circuit 120 corresponding to the functional block 110_n is integrated with (e.g., located next to or in) the functional block 110_n, although the application is not limited thereto. Moreover, one or more temperature sensors 112_n integrated with (e.g., located next to or in) the functional block 110_n can be integrated with (e.g., located next to or in) the thermal control circuit 120 corresponding to the functional block 110_n. For brevity, similar descriptions of these embodiments are not repeated in detail here.

[0063] According to some embodiments, the thermal control circuit 120 can be integrated with (e.g., located next to or in) a certain one of the functional blocks 110_1, 110_2,..., and 110_N, such as the functional block 110_1 (e.g., a CPU). For brevity, similar descriptions of these embodiments are not repeated in detail here.

[0064] According to some embodiments, before the aforementioned at least one first temperature upper limit UL1 (e.g., one or more first temperature upper limits {UL1}) is determined, it is generally required to determine in advance some other temperature upper limits, such as at least one second temperature upper limit UL2 (e.g., one or more second temperature upper limits {UL2}), at least one third temperature upper limit UL3 (e.g., one or more third temperature upper limits {UL3}), and a fourth temperature upper limit UL4, but the present application is not limited thereto. For example, before the aforementioned at least one first temperature upper limit UL1 of the aforementioned at least one functional block (e.g., one or more functional blocks, such as some or all of the functional blocks 110_1, 110_2, …, and 110_N) is determined, it is generally required to determine in advance some other temperature upper limits of the aforementioned at least one functional block, such as the aforementioned at least one second temperature upper limit UL2 of the aforementioned at least one functional block, the aforementioned at least one third temperature upper limit UL3 of the aforementioned at least one functional block, and the aforementioned fourth temperature upper limit UL4. Understandably, in a preferred example, the number of the “at least one first temperature upper limit UL1”, the “at least one second temperature upper limit UL2”, and the “at least one third temperature upper limit” described in the embodiments of the present application can be the same, for example, the same as the number of the aforementioned at least one functional block, such as the number N of all the functional blocks, i.e., UL1, UL2, and UL3 are configured / set for each functional block individually to improve the performance of each functional block as high as possible, but the present application is not limited thereto. For example, as a variant, in another example, the number of the “at least one first temperature upper limit UL1”, the “at least one second temperature upper limit UL2”, and the “at least one third temperature upper limit” can be different, for example, the number of the “at least one first temperature upper limit UL1” is greater than the number of the “at least one second temperature upper limit UL2” and the “at least one third temperature upper limit”, for example, in the case of an IC including N functional blocks, the number of the “at least one first temperature upper limit UL1” can be the number N of all the functional blocks, while the number of the “at least one second temperature upper limit UL2” and the “at least one third temperature upper limit” can be M (where Mwherein the at least one second temperature upper limit UL2 of the at least one functional block and the at least one third temperature upper limit UL3 of the at least one functional block can be determined according to a first functional block by functional block thermal sensor related characteristic and a second functional block by functional block thermal sensor related characteristic, respectively, and the first functional block by functional block thermal sensor related characteristic and the second functional block by functional block thermal sensor related characteristic can be selected from a set of predetermined functional block by functional block thermal sensor related characteristics (e.g., functional block by functional block thermal sensor accuracy and functional block by functional block thermal sensor detection tolerance).

[0065] Figure 3 is a schematic diagram illustrating an adaptive thermal ceiling point control scheme of a thermal control method according to an embodiment of the present application. For the sake of convenience, an arbitrary functional block 110_n is taken as an example of the at least one functional block, and before the first temperature upper limit UL1 of the functional block 110_n is determined, some other temperature upper limits of the functional block 110_n usually need to be determined in advance, for the sake of brevity, Figure 3upper limits, such as a second temperature upper limit UL2 for the functional block 110_n, a third temperature upper limit UL3 for the functional block 110_n, and a fourth temperature upper limit UL4, etc., where the second temperature upper limit UL2 and the third temperature upper limit UL3 can be determined according to the first functional-block- specific thermal sensor related characteristic and the second functional-block- specific thermal sensor related characteristic, respectively. For example, the fourth temperature upper limit UL4 can be a silicon limited temperature upper limit (labeled as “Silicon limited” in the figure for brevity), which is defined by a fabrication condition provided by a manufacturer (e.g., foundry or wafer foundry) of the IC 100, such as a strict prohibited upper limit defined by the manufacturer of the IC 100 to guarantee normal function, for example. It can be appreciated that the fourth temperature upper limit for different functional blocks within the same IC is the same. For example, as an example, the fourth temperature upper limit UL4 can be determined as 125 °C (labeled as “UL4 = 125 °C” in the figure for brevity), then according to the second functional-block- specific thermal sensor related characteristic, such as a functional-block- specific thermal sensor accuracy (labeled as “Thermal sensor accuracy” in the figure for brevity), the third temperature upper limit UL3 for the functional block 110_n can be determined as 120 °C (labeled as “UL3 = 120 °C” in the figure for brevity), and according to the first functional-block- specific thermal sensor related characteristic, such as a functional-block- specific thermal sensor detection tolerance (labeled as “Thermal sensor detection tolerance” in the figure for brevity), the second temperature upper limit UL2 for the functional block 110_n can be determined as 115 °C (labeled as “UL2 = 115 °C” in the figure for brevity), where the second temperature upper limit UL2 can be a system hardware reboot level for the functional block 110_n to ensure normal function at a reference temperature, but the present application is not limited thereto, for example, once the temperature of the corresponding functional block within the corresponding IC of the electronic device reaches the second temperature upper limit during operation of the electronic device (including the IC of the functional block), the electronic device will be rebooted to avoid damage caused by possible erroneous actions of the electronic device.Further, a best thermal ceiling point BP of the functional block 110_n and a worst thermal ceiling point WP of the functional block 110_n can be determined by silicon design information analysis, e.g., at least one pre-silicon thermal operation capability (TOC) analysis (labeled as "e.g., by pre-silicon TOC analysis" in the figure for brevity), performed prior to the fabrication of the IC 100. Understandably, different functional blocks usually have different silicon thermal operation capabilities, and thus, for different functional blocks, each functional block can correspondingly have its own best thermal ceiling point BP and worst thermal ceiling point WP. For example, with all TOC (thermal operation capability) considerations by the silicon design information analysis, the best thermal ceiling point BP of the functional block 110_n and the worst thermal ceiling point WP of the functional block 110_n can be determined as 105°C and 90°C, respectively (labeled as "BP = 105°C" and "WP = 90°C" in the figure for brevity), but the present application is not limited thereto. Both the best thermal ceiling point BP and the worst thermal ceiling point WP are considered as fixed throttle points, and a first temperature upper limit UL1 of the functional block 110_n (which is located between the worst thermal ceiling point WP and the best thermal ceiling point BP of the functional block 110_n) can be considered as an adaptive throttle point within the interval [WP, BP].

[0066] Typically, chip manufacturing involves stages such as design, manufacturing, packaging, testing, and verification. To determine the first temperature limit UL1 of functional block 110_n, the manufacturing operations of IC 100 can be performed by IC 100 manufacturing tools. For ease of explanation and understanding, in this embodiment of the invention, for example, during the packaging and testing stage, a function block or chip binning flow is performed on IC 100 to identify at least one per-function block thermal operation capability of any functional block 110_n among functional blocks 110_1, 110_2, ..., and 110_N within IC 100. For example, the functional blocks are grouped, but the invention is not limited to this. For example, the grouping flow can be performed in an electronic device / main circuit including IC 100 to determine the per-function block thermal operation capability of each functional block, and then used to determine the first temperature limit of each functional block. Therefore, the first temperature limit UL1 of functional block 110_n can be determined based on at least one per-functional-block thermal operation capability of each functional block identified in the functional block or chip grouping process (also referred to as the "grouping process" or "classification process"). For example... Figure 3 As shown, based on the aforementioned at least one per-function block thermal operation capability, the first temperature limit UL1 can be configured as an adaptive thermal limit point within a predetermined temperature range (e.g., the interval [WP, BP] between the worst-case thermal limit point WP and the best-case thermal limit point BP), and the first temperature limit UL1 (e.g., the adaptive thermal limit point) can be changed according to the chip grouping result of the functional block or chip grouping process. That is, for different functional blocks within the same IC, their corresponding first temperature limit UL1 is not fixed to the worst-case thermal limit point WP, but is an adaptive thermal limit point within the interval [WP, BP] between the worst-case thermal limit point WP and the best-case thermal limit point BP, determined according to their respective thermal operation capabilities. For example, the aforementioned at least one per-function block thermal operation capability may include any of the following per-function block thermal operation capabilities (for simplicity, labeled as "TOC (thermal operation capability) #1, TOC#2, TOC#3, TOC#4, TOC#5 or TOC#6"):

[0067] (1) TOC#1: Power-to-thermal efficiency of IC 100 function block 110_n;

[0068] (2) TOC#2: Maximum voltage budget of IC 100 function block 110_n;

[0069] (3) TOC#3: maximum power budget of the functional block 110_n of the IC 100;

[0070] (4) TOC#4: thermal control efficiency of the functional block 110_n of the IC 100;

[0071] (5) TOC#5: operation power efficiency related to the temperature level of the functional block 110_n of the IC 100; and,

[0072] (6) TOC#6: reliability budget of the functional block 110_n of the IC 100;

[0073] wherein the at least one functional-block-specific thermal operating capability can be selected from a plurality of functional-block-specific thermal operating capabilities, such as TOC#1, TOC#2, TOC#3, TOC#4, TOC#5, and TOC#6, etc.

[0074] As Figure 3As shown in the upper left corner, a maximum value (e.g., the best thermal upper limit point BP) of a predetermined temperature region (e.g., an interval [WP, BP] between a worst thermal upper limit point WP and the best thermal upper limit point BP) is less than a second temperature upper limit UL2 of each functional block (e.g., the functional block 110_n). In addition, the second temperature upper limit UL2 can be determined according to a per-functional block thermal sensor detection tolerance, e.g., a per-functional block thermal sensor detection tolerance associated with a location of one or more temperature sensors 112_n integrated with (e.g., located next to or in) the functional block 110_n (and more particularly, a per-functional block thermal sensor detection tolerance associated with a location of any temperature sensor within the IC 100), such that a temperature region Region_B between the second temperature upper limit UL2 of the functional block 110_n and a third temperature upper limit UL3 of the functional block 110_n corresponds to the per-functional block thermal sensor detection tolerance, where the third temperature upper limit UL3 is generally greater than the second temperature upper limit UL2, and the third temperature upper limit UL3 can represent a temperature upper limit without consideration of the per-functional block thermal sensor detection tolerance. In addition, the third temperature upper limit UL3 can be determined according to a per-functional block thermal sensor accuracy, e.g., a per-functional block thermal sensor accuracy associated with at least one temperature detection accuracy of one or more temperature sensors 112_n integrated with (e.g., located next to or in) the functional block 110_n (and more particularly, a per-functional block thermal sensor accuracy associated with a respective temperature detection accuracy of any temperature sensor within the IC 100), such that a temperature region Region_A between the third temperature upper limit UL3 of the functional block 110_n and a fourth temperature upper limit UL4 of the IC 100 corresponds to the per-functional block thermal sensor accuracy, where the fourth temperature upper limit UL4 is generally greater than the third temperature upper limit UL3, and the fourth temperature upper limit UL4 can represent a temperature upper limit without consideration of the per-functional block thermal sensor accuracy and without consideration of the per-functional block thermal sensor detection tolerance.Therefore, in this embodiment of the invention, the accuracy of the per-function-block thermal sensor of functional block 110_n can be related to the corresponding temperature detection accuracy of at least one temperature sensor integrated with functional block 110_n (including integrated in or next to functional block 110_n) (e.g., directly the corresponding temperature detection accuracy, or, for example, the average, statistical, or worst value of the corresponding temperature detection accuracy), or it can be related to the corresponding temperature detection accuracy of any number of temperature sensors within the IC containing functional block 110_n (e.g., directly the corresponding temperature detection accuracy, or, for example, the average, statistical, or worst value of the corresponding temperature detection accuracy). Specifically, this embodiment of the invention does not impose any limitations, but the former has better performance because, generally speaking, a temperature sensor integrated with a functional block can more accurately reflect the temperature of that functional block. Accordingly, the per-function-block thermal sensor detection tolerance of functional block 110_n can be a per-function-block thermal sensor detection tolerance related to the position of one or more temperature sensors 112_n integrated with functional block 110_n, for example, the smaller tolerance among the one or more temperature sensors 112_n; or, for example, it can be a per-function-block thermal sensor detection tolerance related to the position of any number of temperature sensors within IC 100, for example, the smaller tolerance among the any number of temperature sensors. Specifically, the embodiments of the present invention are not limited.

[0075] Compared to any control scheme that uses the worst-case thermal limit point (WP) (e.g., a fixed throttling point based on pre-silicon worst-case analysis) as the thermal limit point, the adaptive thermal limit point control scheme enables IC 100 (e.g., at least one of the aforementioned functional blocks, such as functional block 110_n) to operate in a region where the system performs better, rather than in a region where the system performs worst, thus significantly improving overall performance. For the sake of brevity, similar descriptions of this embodiment will not be repeated here.

[0076] exist Figure 3 In the illustrated embodiments, the per-function block thermal sensor detection tolerance and per-function block thermal sensor accuracy can be used as examples of the first and second per-function block thermal sensor related characteristics, but the invention is not limited thereto. According to some embodiments, the per-function block thermal sensor accuracy and per-function block thermal sensor detection tolerance can be used as examples of the first and second per-function block thermal sensor related characteristics. For the sake of brevity, similar descriptions of these embodiments will not be repeated in detail here.

[0077] According to some embodiments, the at least one temperature-sensing accuracy includes at least a portion of respective temperature-sensing accuracies of respective temperature sensors (e.g., temperature sensors 112_1, 112_2, …, and 112_N) of the plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N) (e.g., temperature-sensing accuracy corresponding to temperature sensors in functional block 110_n). For example, the at least one temperature-sensing accuracy includes an average temperature-sensing accuracy of respective temperature-sensing accuracies of respective temperature sensors (e.g., temperature sensors 112_1, 112_2, …, and 112_N) of the plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N). For another example, the at least one temperature-sensing accuracy includes a statistic temperature-sensing accuracy of respective temperature-sensing accuracies of respective temperature sensors (e.g., temperature sensors 112_1, 112_2, …, and 112_N) of the plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N). For yet another example, the at least one temperature-sensing accuracy can include a worst temperature-sensing accuracy among respective temperature-sensing accuracies of a plurality of temperature sensors (e.g., temperature sensors 112_1, 112_2, …, and 112_N) of the plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N). Similar descriptions of these embodiments are not repeated here for brevity.

[0078] According to some embodiments, based on the adaptive thermal upper limit point control scheme, the differences in thermal operation capabilities among different functional blocks, different chips, and / or different systems are taken into account during the determination of the thermal upper limit point (e.g., the aforementioned at least one first temperature upper limit UL1), and the performance of the IC 100 will not be hindered by the pessimistic constraints of pre-silicon worst-case analysis. More particularly, the adaptive thermal upper limit point control scheme is capable of providing adaptive thermal upper limits based on different thermal operation capabilities of different chips (e.g., thermal operation capabilities characterized by the corresponding binning results of these chips) to define different throttling points in the manner of each functional block and / or each chip, e.g., by performing thermal operation capability (TOC) analysis and calculation to obtain parameters according to the binning results of silicon to determine the precise throttling points as the aforementioned at least one first temperature upper limit UL1, for controlling the risk of overheating and obtaining performance improvement. For brevity, similar descriptions of these embodiments are not repeated in detail here.

[0079] Figure 4 is a schematic diagram illustrating a functional block-by-functional block adaptive thermal upper limit control scheme of a thermal control method according to an embodiment of the present application. For example, among all thermal operation capabilities of the aforementioned at least one functional block (e.g., the functional block 110_n) of the IC 100, the thermal operation capabilities that can be used in any of the pre-silicon stage, the post-silicon stage, and the system operation stage (also described as the “system running stage”) include:

[0080] (0A) TOC#0A: sensor accuracy (e.g., thermal sensor accuracy, such as functional block-by-functional block thermal sensor accuracy) of the aforementioned at least one functional block (e.g., the functional block 110_n) of the integrated circuit (IC) 100; and

[0081] (0B) TOC#0B: sensor detection capability (e.g., thermal sensor detection tolerance, such as functional block-by-functional block thermal sensor detection tolerance) of the aforementioned at least one functional block (e.g., the functional block 110_n) of the integrated circuit (IC) 100;

[0082] (1) TOC#1: power-thermal efficiency of the aforementioned at least one functional block (e.g., the functional block 110_n) of the integrated circuit (IC) 100;

[0083] (2) TOC#2: maximum voltage budget of the aforementioned at least one functional block (e.g., the functional block 110_n) of the integrated circuit (IC) 100;

[0084] (3) TOC#3: a maximum power budget of the at least one functional block (e.g., functional block 110_n) of the integrated circuit (IC) 100;

[0085] (4) TOC#4: a thermal control efficiency of the at least one functional block (e.g., functional block 110_n) of the integrated circuit (IC) 100;

[0086] (5) TOC#5: an operational power efficiency related to a temperature level of the at least one functional block (e.g., functional block 110_n) of the integrated circuit (IC) 100; and,

[0087] (6) TOC#6: a reliability budget of the at least one functional block (e.g., functional block 110_n) of the integrated circuit (IC) 100;

[0088] Wherein, by performing thermal operation capability (TOC) differentiation analysis and / or determining TOC parameters and formulas, the thermal control method is able to obtain other temperature upper limits of the at least one functional block, such as at least one second temperature upper limit UL2 (e.g., a second temperature upper limit UL2 of the functional block 110_n), at least one third temperature upper limit UL3 (e.g., a third temperature upper limit UL3 of the functional block 110_n), and a fourth temperature upper limit UL4. For another example, by performing parameters binning to determine and store the related thermal operation capability per functional block (labeled as "Parameters binning & stored per-functional-block" for brevity) and by performing formula correlations, the thermal control method is able to provide adaptive thermal upper limits, but the present disclosure is not limited thereto.

[0089] Based on the per-functional-block adaptive thermal upper limit control scheme, IC 100 can operate (or interchangeably describe as “operate”) according to the adaptive thermal upper limit of each functional block during the system operation phase based on at least one first temperature upper limit UL1 of at least one functional block, such as the first temperature upper limit UL1 of functional block 110_n, thereby improving system performance in the per-functional-block manner. For example, in a plurality of IC products of integrated circuit (IC) 100, a batch of IC products (e.g., a first group of IC products, and more particularly, corresponding functional blocks of the first group of IC products) has at least one first temperature limit UL1 configured / set according to at least one per-functional-block thermal operation capability of the aforementioned at least one functional block in the batch of ICs {100} to achieve maximum performance (or interchangeably described as "efficiency") for this batch; and another batch of IC products (e.g., a second group of IC products, and more particularly, corresponding functional blocks of the second group of IC products) has at least one first temperature limit UL1 configured / set according to at least one per-functional-block thermal operation capability of the at least one functional block in the other batch of ICs {100} to achieve maximum performance for that other batch. Compared to related technologies, integrated circuit (IC) 100 can operate correctly under various conditions while achieving maximum efficiency, wherein at least one first temperature limit UL1 is set according to at least one per-functional-block thermal operation capability of at least one functional block within the IC to make at least one first temperature limit UL1 as high as possible. For the sake of brevity, similar descriptions of these embodiments will not be repeated here in detail.

[0090] According to some embodiments, by using Figure 4 The TOC#0A and TOC#0B shown are as follows Figure 4 At least one of the TOCs (e.g., one or more or all of the TOCs) among TOC#1, TOC#2, TOC#3, TOC#4, TOC#5, and TOC#6 shown in the diagram accurately assesses thermal operating capability. The function block-by-function adaptive thermal upper limit control scheme can improve the performance target of at least one function block (e.g., function block 110_n) of IC 100. The performance target of at least one function block (e.g., function block 110_n) represents the performance of at least one function block (e.g., function block 110_n). For example, when at least one function block (e.g., function block 110_n) is in a state such as... Figure 3The at least one functional block (e.g., functional block 110_n) can achieve maximum performance when operating in the system operation better region (rather than the system operation worst region) shown in the lower left corner, but the present application is not limited thereto. According to some embodiments, by using TOC#0A and TOC#0B and at least one TOC (e.g., one or more or all TOCs) of TOC#1, TOC#2, TOC#3, TOC#4, TOC#5 and TOC#6, and by using at least one multiple software architecture segments adaptive ceiling policy and / or at least one multiple hardware architecture levels adaptive ceiling policy to accurately evaluate thermal operating capability, the per-functional block adaptive thermal ceiling control scheme can improve performance metrics of the at least one functional block (e.g., functional block 110_n). For example, the per-functional block adaptive thermal ceiling control scheme can enhance performance metrics of the at least one functional block (e.g., functional block 110_n) by using the aforementioned at least one multiple software architecture segments adaptive ceiling policy (more particularly, applying different thermal ceiling policies at different temperature segments, respectively) to accurately evaluate thermal operating capability. For another example, the per-functional block adaptive thermal ceiling control scheme can enhance performance metrics of the at least one functional block (e.g., functional block 110_n) by using the at least one multiple hardware architecture levels adaptive ceiling policy (and, more particularly, applying different thermal ceiling policies in different blocks (e.g., functional blocks 110_1, 110_2, 110_3 and 110_4, as shown in FIG. 1) and / or different system levels (e.g., functional block level, chip level, circuit board level and whole device level) to accurately evaluate thermal operating capability. Figure 2 For another example, the per-functional block adaptive thermal ceiling control scheme can enhance performance metrics of the at least one functional block (e.g., functional block 110_n) by using the at least one multiple hardware architecture levels adaptive ceiling policy (and, more particularly, applying different thermal ceiling policies in different blocks (e.g., functional blocks 110_1, 110_2, 110_3 and 110_4, as shown in FIG. 1) and / or different system levels (e.g., functional block level, chip level, circuit board level and whole device level) to accurately evaluate thermal operating capability.

[0091] Figure 5 is a schematic diagram illustrating some implementation details of at least one multiple software architecture segments adaptive ceiling policy regarding different level control (e.g., pre-throttle level decision) that can be used in a thermal control method according to an embodiment of the present application. The thermal control method can apply different thermal ceiling policies in different temperature segments (e.g., multiple temperature regions) to provide adaptive thermal ceiling points. As shown in FIG. 3, the thermal control method can apply different thermal ceiling policies in different temperature segments (e.g., multiple temperature regions) to provide adaptive thermal ceiling points. Figure 5As shown, the best thermal upper limit point BP can be considered as a best thermal operation capability budget of the at least one functional block (e.g., the functional block 110_n), and the worst thermal upper limit point WP can be considered as a worst thermal operation capability budget of the at least one functional block (e.g., the functional block 110_n). In addition, as shown, the region for adaptive thermal upper limit points can be divided into a plurality of temperature regions by at least one intermediate thermal upper limit point (e.g., a single intermediate thermal upper limit point IP or a plurality of intermediate thermal upper limit points {IP}) located within an interval (WP, BP) between the worst thermal upper limit point WP and the best thermal upper limit point BP. The at least one intermediate thermal upper limit point (e.g., the single intermediate thermal upper limit point IP or the plurality of intermediate thermal upper limit points {IP}) can be considered as an intermediate thermal operation capability budget of the at least one functional block (e.g., the functional block 110_n). For example, the at least one intermediate thermal upper limit point can include a single intermediate thermal upper limit point IP, and the plurality of temperature regions include: Figure 3

[0092] (1) Region#1: an interval [IP, BP] between the single intermediate thermal upper limit point IP and the best thermal upper limit point BP (labeled as "Region#1 for adaptive thermal operation points" in the figure for better understanding); and

[0093] (2) Region#2: an interval [WP, IP] between the worst thermal upper limit point WP and the single intermediate thermal upper limit point IP (labeled as "Region#2 for adaptive thermal operation points" in the figure for better understanding);

[0094] wherein, in an example, the best thermal upper limit point BP and the worst thermal upper limit point WP can be determined as 105°C and 90°C, respectively (labeled as "BP = 105°C" and "WP = 90°C", respectively, in the figure for brevity), and the single intermediate thermal upper limit point IP can be determined as 97°C (labeled as "IP = 97°C" in the figure for brevity), but the present application is not limited to this example. For another example, the values of the best thermal upper limit point BP, the single intermediate thermal upper limit point IP, and the worst thermal upper limit point WP can be different. For brevity, similar descriptions of this embodiment are not repeated here.

[0095] ​According to some embodiments, the at least one intermediate thermal upper limit point can comprise a plurality of intermediate thermal upper limit points {IP}, e.g., M intermediate thermal upper limit points {IP(1),...,IP(M)}, and the plurality of temperature zones can comprise zones #0, #1, #2,..., #M and #M+1, e.g., an interval [WP,IP(1)] between the worst thermal upper limit point WP and the intermediate thermal upper limit point IP(1), an interval [IP(m),IP(m+1)] between the intermediate thermal upper limit points IP(M) and IP(m+1), an interval [IP(M),BP] between the intermediate thermal upper limit point IP(M) and the best thermal upper limit point BP, where the symbol "M" denotes a positive integer greater than 1 and the symbol "m" denotes an integer falling within the interval [1,(M-1)]. For example, the best thermal upper limit point BP and the worst thermal upper limit point WP can be determined as 105°C and 90°C, respectively, and the plurality of intermediate thermal upper limit points {IP}, e.g., M intermediate thermal upper limit points {IP(1),...,IP(M)}, can be determined as different values within the interval (WP,BP) between the worst thermal upper limit point WP and the best thermal upper limit point, but the present application is not limited thereto. For another example, the respective values of the best thermal upper limit point BP, the M intermediate thermal upper limit points {IP(1),...,IP(M)} and the worst thermal upper limit point WP can be different. For brevity, similar descriptions of these embodiments are not repeated in detail here.

[0096] Figure 6Fig. 1 is a schematic diagram illustrating some implementation details of at least one multi-hardware-architecture-level adaptive upper limit policy that can be used in a thermal control method according to an embodiment of the present application. The thermal control method can apply different thermal upper limit policies in different G-function blocks, e.g., function blocks 110_1, 110_2,... and 110_N (e.g., CPU, GPU, APU and Modem (labeled as "MD" in the figure)), and the thermal control method can apply different thermal upper limit policies in different system levels (e.g., multiple system levels such as function block level, chip level, board level and whole device level) respectively using the same / similar concept. For example, in a chip level embodiment, adaptive thermal upper limit control is performed in units of function blocks within a single integrated circuit (e.g., IC 100), and the temperature upper limit UL1 of each function block located within the same IC is determined according to the thermal operating capability of the function block itself, i.e., each function block has a thermal operating capability corresponding to the function block itself, which is also referred to as "function block-specific thermal operating capability" in the embodiment of the present application, and is used to indicate the thermal operating capability of the corresponding function block that is tested in units of function blocks within the IC, e.g., the function block-specific thermal operating capability of each function block can be identified by performing function block or chip grouping procedures on the IC. The applicant realizes that the thermal operating capability of each function block can be different for function blocks with different functions within the same IC or for function blocks with the same function within different ICs, and thus the temperature upper limit UL1 determined based on the thermal operating capability of the function block can also be different for different function blocks. That is, in the embodiment of the present application, the temperature upper limit UL1 of different function blocks is configurable according to the thermal operating capability of the corresponding function block, rather than being uniformly set to a fixed value such as the worst thermal upper limit point for all function blocks within the IC.

[0097] For better understanding, IC 100 can be regarded as a SoC (System On Chip) IC, which can be installed in a main circuit 200 including IC 100, and the main circuit 200 can be implemented by means of a main circuit board on which a plurality of ICs are installed, wherein, Figure 2 The function blocks 110_1, 110_2, 110_3, 110_4, etc. (e.g., CPU, GPU, APU, Modem (labeled as "MD" in the figure)) in the illustrated IC 100 can be regarded as chip level components; and at least a part (e.g., part or all) of the plurality of temperature sensors within IC 100 can be regarded as chip level temperature sensors, e.g., as illustrated inFigure 2 part of the temperature sensors or all of the temperature sensors TS(1), TS(2), TS(3), TS(4), TS(5), TS(6), TS(7), TS(8), TS(9), TS(10), TS(11), TS(12), TS(13), TS(14), TS(15), TS(16), TS(17), and TS(18) shown in FIG. 1; at least one first temperature upper limit UL1 (e.g., in degrees Celsius) of at least one functional block (e.g., functional block 110_n) of IC 100, e.g., determined according to the thermal operating capability of the corresponding functional block, and Figure 2 IC 100 of the embodiment shown in FIG. 1 has 4 functional blocks, and can have 4 first temperature upper limits {UL1}, each of which corresponds to a respective functional block and is determined according to the thermal operating capability of the corresponding functional block, but the present application is not limited thereto. For example, in addition to IC 100, main circuit 200 can include at least one additional IC (e.g., one or more additional ICs, such as ICs 220, 230, and 240), and main circuit 200 includes a plurality of board-level temperature sensors, e.g., board-level temperature sensors 210_1, 210_2, 210_3, and 210_4 corresponding to ICs 100, 220, 230, and 240, respectively, wherein, Figure 6 ICs 100, 220, 230, and 240 in main circuit 200 shown in FIG. 1 can be regarded as board-level components (i.e., a plurality of ICs mounted on the same board are considered as a plurality of board-level components, so that in the adaptive thermal control scheme of main circuit 200, the temperature upper limit UL1 of each IC is set according to the thermal operating capability of the respective board-level component, i.e., the temperature upper limit UL1 of different ICs on the same board can be different according to the thermal operating capability of the respective IC, and it can be understood that the thermal operating capability of each IC can also be identified by performing the functional block or chip grouping process on the IC). According to this embodiment, IC 220 can be implemented as a power management IC (PMIC) coupled to IC 100 and at least one other IC (e.g., ICs 230 and 240), and the at least one other IC (e.g., ICs 230 and 240) can be implemented as a radio frequency (RF) amplifier and a dynamic random access memory (DRAM), respectively, so that in the adaptive thermal control scheme of main circuit 200, Figure 6 In the embodiment shown in FIG. 1, ICs 220, 230, and 240 can be labeled as “PMIC”, “RF amplifier”, and “DRAM”, respectively, but the present application is not limited thereto.

[0098] At least one other IC (e.g., ICs 230 and 240, such as RF amplifiers and DRAMs) can be arranged to perform at least one other operation (e.g., RF signal amplification operation in RF amplifiers and data access / storage operation in DRAMs) for IC 100. In addition, multiple substrate-level temperature sensors 210_1, 210_2, 210_3 and 210_4 can be respectively located near or beside ICs 100, 220, 230 and 240, and can be configured to perform temperature detection (more particularly, for detecting temperature of each IC respectively) within main circuit 200 to generate corresponding temperature detection results of ICs 100, 220, 230 and 240. In addition, at least one thermal control circuit (e.g., thermal control circuit 120) can be arranged to perform thermal control of ICs 100, 220, 230 and 240 by monitoring the corresponding temperature detection results of ICs 100, 220, 230 and 240 and attempting to prevent the corresponding temperature detection results of ICs 100, 220, 230 and 240 from exceeding at least one first substrate-level temperature upper limit UL1(2) (e.g., one or more first substrate-level temperature upper limits {UL1(2)}) of main circuit 200 (e.g., ICs 100, 220, 230 and 240 therein) in a manner to prevent ICs 100, 220, 230 and 240 from overheating and causing abnormal functional operation, wherein the at least one first substrate-level temperature upper limit UL1(2) is configurable with respect to at least one substrate-level component thermal operating capability of main circuit 200. It can be understood that the substrate-level component / IC thermal operating capability refers to a thermal operating capability (corresponding substrate-level component / IC thermal operating capability) obtained in a basic unit of IC within a substrate-level component (e.g., main circuit 200), for example, by performing chip grouping procedure for each IC. For example, in a preferred embodiment, taking an example of main circuit including M ICs located on the same substrate, M substrate-level component thermal operating capabilities will be obtained for the M ICs, and M first substrate-level temperature upper limits {UL1(2)} can be determined according to the M substrate-level component thermal operating capabilities, wherein each of the M first substrate-level temperature upper limits {UL1(2)} corresponds to a corresponding IC of the M ICs, that is, the first substrate-level temperature upper limit UL1(2) of each IC is configured / determined according to the substrate-level component thermal operating capability of the IC itself (which can also be directly described as "thermal operating capability of the IC itself"). For example, in Figure 6In the embodiment of the four ICs shown, there may be four first substrate-level temperature limits {UL1(2)}, wherein each first substrate-level temperature limit UL1(2) corresponds to the corresponding IC and is determined according to the thermal operating capability of the corresponding IC, but the present invention is not limited thereto. For example, two or more ICs may share the same temperature limit UL1(2). However, it is preferred to have an embodiment in which a temperature limit UL1(2) is set separately for each IC according to its own thermal operating capability, which can perform individual adaptive thermal limit control for each IC, thereby maximizing system performance without affecting each other. In one example, at least one thermal control circuit (such as thermal control circuit 120) may be implemented in hardware and / or software, such as pure hardware or at least one hybrid module of hardware and software (e.g., one or more hybrid modules), and more particularly, may be implemented as a single substrate-level thermal control circuit to collect temperature detection results of all substrate-level components of the main circuit 200 (e.g., all ICs in ICs 100, 220, 230 and 240) and control the components of the main circuit 200 (e.g., ICs 100, 220, 230 and 240) in a centralized substrate-level temperature detection and thermal control architecture, but the invention is not limited thereto.

[0099] like Figure 6 As shown, the main circuit 200 can be located in the electronic device 300 including the main circuit 200, wherein the main circuit 200 can be a main component of the electronic device 300. For example, the electronic device 300 may also include at least one secondary component (e.g., one or more secondary components), such as secondary components 320, 330, 340, 350, and 360. The electronic device 300 includes multiple device-level temperature sensors, such as device-level temperature sensors 310_1, 310_2, 310_3, 310_4, 310_5, and 310_6 corresponding to the main circuit 200 and the secondary components 320, 330, 340, 350, and 360, respectively. Figure 6 The main circuit 200 and secondary components 320, 330, 340, 350, and 360 in the illustrated electronic device 300 can be considered as device-level components. According to this embodiment, secondary components 320, 330, 340, 350, and 360 can be implemented as a battery, a display, at least one camera (e.g., one or more cameras), at least one antenna (e.g., one or more antennas), and a case. Therefore, secondary components 320, 330, 340, 350, and 360 in…Figure 6 The components can be respectively labeled as "battery," "display," "camera," "antenna," and "housing," but the present application is not limited thereto.

[0100] At least one secondary component (e.g., secondary components 320, 330, 340, 350, and 360, such as a battery, a display, at least one camera, at least one antenna, and a housing) can be arranged to operate under the control of the main circuit 200. In addition, a plurality of device-level temperature sensors (e.g., device-level temperature sensors 310_1, 310_2, 310_3, 310_4, 310_5, and 310_6) can be respectively located inside (e.g., on top of) or near / beside the main circuit 200 and the secondary components 320, 330, 340, 350, and 360, and the plurality of device-level temperature sensors can be arranged to perform temperature detection (e.g., measure the temperature of each device-level component, respectively) within the electronic device 300 to generate respective temperature detection results of the main circuit 200 and the secondary components 320, 330, 340, 350, and 360. In addition, the at least one thermal control circuit (e.g., the thermal control circuit 120) described above can be configured to perform thermal control on the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 by monitoring the respective temperature detection results of the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 and attempting to prevent the respective temperature detection results of the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 from exceeding at least one first device-level temperature upper limit UL1(3) (e.g., one or more first device-level temperature upper limits {UL1(3)}) of the electronic device 300 (e.g., the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 therein) to prevent the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 from overheating and causing operational abnormalities. The at least one first device-level temperature upper limit UL1(3) is configurable with respect to at least one device-level component thermal operating capability of the electronic device 300. It can be understood that the device-level component thermal operating capability is a thermal operating capability obtained in the electronic device in a device-level component as a basic unit (i.e., the thermal operating capability of the corresponding device-level component), for example, which can be obtained by simulating, testing the electronic device, and storing and / or configuring / setting / determining the temperature upper limit UL1(3) therefrom for reference during use.For example, at least one thermal control circuit (e.g., the thermal control circuit 120) can be implemented by way of hardware and / or software, such as at least one mixed module of pure hardware or hardware and software (e.g., one or more mixed modules), and more particularly, can be implemented as a single device-level thermal control circuit for collecting temperature detection results of all device-level components (e.g., the main circuit 200 and the secondary components 320, 330, 340, 350, and 360) of the electronic device 300 and controlling the device-level components (e.g., the main circuit 200 and the secondary components 320, 330, 340, 350, and 360) of the electronic device 300 in a centralized device-level temperature detection and thermal control architecture, but the present application is not limited thereto. For brevity, similar descriptions of this embodiment are not repeated here.

[0101] According to some embodiments, Figure 3 The illustrated parameters {WP, BP, UL1, UL2, UL3, UL4, Region_A, Region_B} can be written as chip-level parameters {WP(1), BP(1), UL1(1), UL2(1), UL3(1), UL4(1), Region_A(1), Region_B(1)} to correspond to related (associated) operations at the chip level (e.g., an adaptive thermal ceiling scheme performed in the IC 100 in the manner of each functional block), and more particularly, Figure 5 The illustrated parameters {WP, IP, BP} can be written as chip-level parameters {WP(1), IP(1), BP(1)} to correspond to related operations at the chip level, but the present application is not limited thereto. For another example, Figure 3 The illustrated parameters {WP, BP, UL1, UL2, UL3, UL4, Region_A, Region_B} can be written as substrate-level parameters {WP(2), BP(2), UL1(2), UL2(2), UL3(2), UL4(2), Region_A(2), Region_B(2)} to correspond to related operations at the substrate level (e.g., an adaptive thermal ceiling scheme performed in the main circuit 200 in the manner of each substrate-level component), and more particularly, Figure 5 The illustrated parameters {WP, IP, BP} can be written as substrate-level parameters {WP(2), IP(2), BP(2)} to correspond to related operations at the substrate level. For yet another example, Figure 3The parameters {WP, BP, UL1, UL2, UL3, UL4, Region_A, Region_B} shown in the above embodiment can be written as device-level parameters {WP(3), BP(3), UL1(3), UL2(3), UL3(3), UL4(3), Region_A(3), Region_B(3)} to correspond to the associated operations at the device level (e.g., the adaptive thermal upper limit scheme performed in the electronic device 300 in the manner of each device-level component), and more particularly, Figure 5 The parameters {WP, IP, BP} shown in the above embodiment can be written as device-level parameters {WP(3), IP(3), BP(3)} to correspond to the associated operations at the device level. For brevity, similar descriptions of these embodiments are not repeated in detail here. Understandably, the electronic device 300 is implemented (e.g., assembled) by assembling the device-level components (e.g., the primary circuit 200 and the secondary components 320, 330, 340, 350, and 360) (e.g., an assembly factory); the device-level components are implemented (e.g., assembled) by assembling ICs (e.g., another assembly factory), for example, the primary circuit 200, which can be a device-level component, can be obtained by assembling the ICs 100, 220, 230, and 240; the ICs are usually manufactured by a wafer factory. That is, the structures at each system level (e.g., the device level, the substrate level, the chip level) are completed in different manufacturing processes, and the temperature upper limits of the different manufacturing processes are different. Figure 6

[0102] Figure 7 ​is a schematic diagram illustrating some implementation details of the aforementioned at least one multiple hardware architecture level adaptive upper bound policy that can be used in the thermal control method according to another embodiment of the present application. The main circuit 200 can include a phase-locked loop (PLL) circuit 100CS, where the PLL circuit 100CS can be integrated with (e.g., integrated next to or integrated in) the IC 100, but the present application is not limited thereto. In addition, the aforementioned at least one thermal control circuit (e.g., the thermal control circuit 120) can perform thermal control with the aid of the IC 220 (e.g., a PMIC) and the PLL circuit 100CS. For example, under the control of the thermal control circuit 120, the IC 220 (e.g., a PMIC) can act as a power source (for brevity, labeled as “power source” in the figure) for the IC 100 (e.g., any one of the functional blocks 110_n in the IC 100), and more particularly, for the functional block 110_1 (e.g., a CPU), and the PLL circuit 100CS can act as a clock source (for brevity, labeled as “clock source” in the figure) for the IC 100 (e.g., any one of the functional blocks 110_n in the IC 100), and more particularly, for the functional block 110_1 (e.g., a CPU).

[0103] As Figure 7 As shown in the upper half, the power control loop includes the (one or more) associated paths in at least one control path (e.g., one or more control paths) from the thermal control circuit 120 to the IC 220 (e.g., a PMIC), at least one power path (e.g., one or more power paths) from the IC 220 (e.g., a PMIC) to any functional block 110_n (e.g., the functional block 110_1, such as a CPU) of the IC 100, and at least one feedback path (e.g., one or more feedback paths) from any functional block 110_n (e.g., the functional block 110_1, such as a CPU, and more particularly, one or more temperature sensors in the functional block 110_n) to the thermal control circuit 120. Through the power control loop, the thermal control circuit 120 can control the IC 220 (e.g., a PMIC) to dynamically adjust the power managed by the IC 220 (e.g., a PMIC) and output to any functional block 110_n (e.g., the functional block 110_1, such as a CPU) via the aforementioned at least one power path.

[0104] As Figure 7As shown in the lower half, the clock control loop includes (one or more) associated paths in at least one control path (e.g., one or more control paths) from the thermal control circuit 120 to the PLL circuit 100CS, at least one clock path (e.g., one or more clock paths) from the PLL circuit 100CS to any functional block 110_n (e.g., functional block 110_1, such as a CPU), and at least one feedback path (e.g., one or more feedback paths) from any functional block 110_n (e.g., functional block 110_1, such as a CPU, and more particularly, one or more temperature sensors in the functional block 110_n) to the thermal control circuit 120. Through the clock control loop, the thermal control circuit 120 can control the PLL circuit 100CS to dynamically adjust any clock (e.g., its frequency) in at least one clock (e.g., one or more clocks) maintained by the PLL circuit 100CS and output to any functional block 110_n (e.g., functional block 110_n, such as a CPU) via the at least one clock path.

[0105] For example, the at least one thermal control circuit (e.g., the thermal control circuit 120) described above can be implemented by hardware and / or software, such as a pure hardware or at least one hybrid module (e.g., one or more hybrid modules) of the above-mentioned hardware and software, and more particularly, can be implemented as a single functional block level thermal control circuit for collecting temperature detection results of a plurality of sub-functional blocks (e.g., a primary sub-functional block and a plurality of secondary sub-functional blocks) within a functional block (e.g., functional block 110_1, such as a CPU), and controlling the plurality of sub-functional blocks (e.g., the plurality of secondary sub-functional blocks) within the functional block (e.g., functional block 110_1, such as a CPU) in a centralized functional block level temperature detection and thermal control architecture, but the present application is not limited thereto. For example, the plurality of sub-functional blocks (e.g., the plurality of secondary sub-functional blocks) can also be regarded as functional blocks in the IC 100. For brevity, similar descriptions for the present embodiment are not repeated here.

[0106] According to Figure 7In the illustrated embodiment, the functional block 110_1 (e.g., a CPU) can be an example of any of the aforementioned functional blocks 110_n, and one or more temperature sensors in the functional block 110_1 include temperature sensors TS(1), TS(2), TS(3), TS(4), TS(5), and TS(6) integrated with (e.g., proximate to or within) some sub-functional blocks in the functional block 110_1, where the aforementioned at least one feedback path can include multiple feedback paths from the temperature sensors TS(1), TS(2), TS(3), TS(4), TS(5), and TS(6) to the thermal control circuit 120, but the present disclosure is not limited thereto. In another embodiment, any other functional block in the functional blocks 110_1, 110_2, …, 110_N can be an example of any of the aforementioned functional blocks 110_n. According to some embodiments, the architecture of any functional block 110_n (e.g., the functional block 110_1 such as a CPU) can vary. For example, any temperature sensor of any functional block 110_n (e.g., the functional block 110_1 such as a CPU) can be located proximate to or within some sub-functional block thereof. Similar descriptions of these embodiments are not repeated in detail herein for brevity.

[0107] Figure 8 is a schematic diagram illustrating a thermal operation capability evaluation control scheme of a thermal control method according to a first embodiment of the present disclosure. For example, the aforementioned at least one functional block-specific thermal operation capability can include a TOC#1 of a particular functional block (e.g., any of the functional blocks 110_n) of the IC 100, i.e., a power-to-thermal efficiency of the particular functional block (e.g., the functional block 110_n), such as Figure 8 a power thermal effect as illustrated in FIG. 6. In Figure 8 In FIG. 6, the horizontal axis represents a running time and is measured in milliseconds (ms), and the vertical axis represents a delta temperature (e.g., a temperature difference such as a temperature delta) and is measured in degrees Celsius (°C), but the present disclosure is not limited thereto. According to some embodiments, the relevant units can vary. In addition, Figure 8The two curves shown can correspond to different power consumption behaviors, for example, a high power consumption behavior Power_H and a low power consumption behavior Power_L, where the high power samples of the high power consumption behavior Power_H (e.g., IC products with the high power consumption behavior Power_H) induce higher thermal responses, and the low power samples of the low power consumption behavior Power_L (e.g., IC products with the low power consumption behavior Power_L) induce lower thermal responses. As shown, when a limit such as a predetermined value (e.g., 10 (ms)) on the horizontal axis is predetermined (e.g., assuming that the temperature sensor obtains a temperature detection result every 10 ms), the different targets on the vertical axis corresponding to the high power consumption behavior Power_H and the low power consumption behavior Power_L, respectively, such as Target#2 and Target#1, can be determined according to Figure 8 The two curves shown can correspond to different power consumption behaviors, for example, a high power consumption behavior Power_H and a low power consumption behavior Power_L, where the high power samples of the high power consumption behavior Power_H (e.g., IC products with the high power consumption behavior Power_H) induce higher thermal responses, and the low power samples of the low power consumption behavior Power_L (e.g., IC products with the low power consumption behavior Power_L) induce lower thermal responses. As shown, when a limit such as a predetermined value (e.g., 10 (ms)) on the horizontal axis is predetermined (e.g., assuming that the temperature sensor obtains a temperature detection result every 10 ms), the different targets on the vertical axis corresponding to the high power consumption behavior Power_H and the low power consumption behavior Power_L, respectively, such as Target#2 and Target#1, can be determined according to Figure 8 The two curves shown can correspond to different power consumption behaviors, for example, a high power consumption behavior Power_H and a low power consumption behavior Power_L, where the high power samples of the high power consumption behavior Power_H (e.g., IC products with the high power consumption behavior Power_H) induce higher thermal responses, and the low power samples of the low power consumption behavior Power_L (e.g., IC products with the low power consumption behavior Power_L) induce lower thermal responses. As shown, when a limit such as a predetermined value (e.g., 10 (ms)) on the horizontal axis is predetermined (e.g., assuming that the temperature sensor obtains a temperature detection result every 10 ms), the different targets on the vertical axis corresponding to the high power consumption behavior Power_H and the low power consumption behavior Power_L, respectively, such as Target#2 and Target#1, can be determined according to

[0108] For example, in a packaging test phase (e.g., which can also be performed in an electronic device through a preset program, such as a grouping flow performed when the electronic device is powered on or performed when needed, and the present application does not make any limitation on the specific phase in which the grouping flow is performed), a functions or chip binning flow is performed on the first batch of IC products to identify the thermal operating capabilities of the functions, so as to configure the first temperature upper limit UL1 of the specific function (e.g., any function 110_n in the IC) of the first batch of IC products. More particularly, in an example, the specific function of the first batch of IC products is determined (e.g., classified / categorized) to have the low power consumption behavior Power_L, and the first temperature upper limit UL1 of the specific function of the IC {100} in the first batch of IC products is configured according to the thermal operating capability (e.g., TOC#1) of the specific function of the corresponding IC, so as to achieve the maximum performance of the first batch of IC products, and thus the first temperature upper limit UL1 of the specific function (e.g., function 110_n) of any one IC 100 (e.g., each IC 100) in the IC {100} of the first batch of IC products is set as follows:

[0109] UL1 = UL2 - Target1;

[0110] In the above equation, Target1 (which can also be described as the "first target value") can represent... Figure 8 Target#1 as shown, and can be based on as follows Figure 8 The curve corresponding to the low-power behavior Power_L shown is determined, but the present invention is not limited thereto. Furthermore, a function block or chip grouping process (also referred to as a binning flow) is performed on a second batch of IC products in a plurality of IC products to configure a first temperature limit UL1 for a specific function block (e.g., any function block 110_n in the IC) in the second batch of IC products. More specifically, in one example, a specific function block of a corresponding IC in the second batch of IC products is determined (e.g., classified) as having a high-power behavior Power_H, and a first temperature limit UL1 for the specific function block is configured according to the thermal operating capability (e.g., TOC#1) of the specific function block of IC{100} in the second batch of IC products to achieve the maximum performance of the second batch of IC products. Therefore, the first temperature limit UL1 of a specific function block (e.g., function block 110_n) of any IC 100 (e.g., each IC 100) in the second batch of IC products is set as follows:

[0111] UL1 = UL2 - Target2;

[0112] In the above equation, Target2 (which can also be described as the "second target value") can represent... Figure 8 The Target#2 shown, and, can be based on Figure 8 The curve corresponding to the high power consumption behavior Power_H shown is determined, but the present invention is not limited thereto. Compared with related technologies, specific functional blocks of IC 100 (e.g., functional blocks 110_n) (e.g., functional blocks 110_n of any IC 100 in the first batch of IC products and functional blocks 110_n of any IC 100 in the second batch of IC products) can operate normally under various conditions while achieving maximum performance. The first temperature limit UL1 of the specific functional block is configured for the thermal operating capability (e.g., TOC#1) of that specific functional block to make the first temperature limit UL1 of the specific functional block as high as possible. For the sake of brevity, similar descriptions of this embodiment will not be repeated here.

[0113] Figure 9is a schematic diagram of a thermal operation capability evaluation control scheme of the thermal control method according to the second embodiment of the present application. For example, the at least one functional block-wise thermal operation capability can include a TOC#2 of a particular functional block (e.g., functional block 110_n) of IC 100, i.e., a maximum voltage budget of the particular functional block (e.g., functional block 110_n), e.g., Figure 9 the voltage limit shown in Figure 9 In Figure 9 the horizontal axis represents voltage and is measured in millivolts (mV), and the vertical axis represents temperature and is measured in degrees Celsius (°C), but the present application is not limited thereto. According to some embodiments, the relevant units can be different. In addition, Figure 9 the two curves shown can correspond to different voltage-related behaviors of the same functional block (e.g., functional block 110_n) in different ICs {100}, e.g., a first voltage-related behavior and a second voltage-related behavior (labeled as "Device-A" and "Device-B" in the figure for brevity), where the operating temperature is limited by the maximum voltage budget for system stability, and more particularly, the first sample for the first voltage-related behavior and the first sample for the second voltage-related behavior are limited differently. As Figure 9 shown, when a limit such as a predetermined value (e.g., a maximum voltage budget, 890 (mV)) on the horizontal axis is predetermined, different targets on the vertical axis corresponding to the second voltage-related behavior and the first voltage-related behavior (labeled as "Device-B" and "Device-A" in the figure) respectively, e.g., Target#1 and Target#2, can be determined respectively according to Figure 9

[0114] For example, in the packaging test phase (e.g., which can also be performed in the electronic device through a preset program, such as performing a grouping process when the electronic device is powered on or when needed, and the present application does not make any limitation on the specific phase in which the grouping process is performed), a functional block or chip grouping process is performed on a first batch of IC products in a plurality of IC products of the IC 100, for configuring a first temperature upper limit UL1 of a specific functional block (e.g., any functional block 110_n in the IC) in the IC in the first batch of IC products, and more particularly, in an example, the specific functional block of the first batch of IC products is determined (e.g., classified) to have a second voltage-related behavior (labeled as "Device-B") and the first temperature upper limit UL1 of the specific functional block is configured according to the thermal operating capability (e.g., TOC#2) of the specific functional block of the IC{100} in the first batch of IC products, so that the performance of the first batch of IC products reaches the maximum, and therefore, the first temperature upper limit UL1 of the specific functional block (e.g., functional block 110_n) of any IC 100 (e.g., each IC 100) in the IC{100} in the first batch of IC products is set as follows:

[0115] UL1 = Target1;

[0116] wherein Target1 in the above equation can represent Target#1 shown in Figure 9 and can be determined according to the curve corresponding to the second voltage-related behavior (labeled as "Device-B" in the figure) as shown in Figure 9 , but the present application is not limited thereto. In addition, for example, in the packaging test phase, a functional block or chip grouping process is performed on a second batch of IC products in a plurality of IC products of the IC 100, for configuring a first temperature upper limit UL1 of a specific functional block (e.g., any functional block 110_n in the IC) in the IC, and more particularly, in an example, the specific functional block (e.g., any functional block 110_n in the corresponding IC) of the second batch of IC products is determined (e.g., classified) to have a first voltage-related behavior (labeled as "Device-A" in the figure) and the first temperature upper limit UL1 of the specific functional block is configured according to the thermal operating capability (e.g., TOC#2) of the specific functional block of the IC{100} in the second batch of IC, so that the performance of the second batch of IC products reaches the maximum, and therefore, the first temperature upper limit UL1 of the specific functional block (e.g., functional block 110_n) of any IC 100 (e.g., each IC 100) in the IC{100} in the second batch of IC products is set as follows:

[0117] UL1 = Target2;

[0118] wherein Target2 in the above equation can represent Target#2 shown in Figure 9As shown in Target#2, and can be based on the corresponding as follows Figure 9 The curve showing the first voltage-related behavior (labeled "Device-A" in the figure) is used to determine this, but the invention is not limited thereto. Compared with related technologies, specific functional blocks of IC 100 (e.g., functional blocks 110_n) (e.g., functional blocks 110_n of any IC 100 in the first batch of IC products and functional blocks 110_n of any IC 100 in the second batch of IC products) can operate normally under various conditions while achieving maximum performance, wherein the first temperature limit UL1 of the specific functional block is configured according to the thermal operating capability of the specific functional block (e.g., TOC#2) to make the first temperature limit UL1 of the specific functional block as high as possible. For the sake of brevity, descriptions similar to those in this embodiment will not be repeated here.

[0119] Figure 10 This is a schematic diagram illustrating a thermal operation capability evaluation control scheme for a thermal control method according to a third embodiment of the present invention. For example, the at least one per-function-block thermal operation capability mentioned above may include the TOC#3 of a specific function block (e.g., function block 110_n) of IC 100, i.e., the maximum power budget of the specific function block (e.g., function block 110_n). Figure 10 The power limit is shown. Figure 10 In the diagram, the horizontal axis represents temperature measured in degrees Celsius (°C), and the vertical axis represents power measured in milliwatts (mW), but the invention is not limited thereto. According to some embodiments, the units may differ. Additionally, Figure 10 The two curves shown correspond to different power-related behaviors of the same functional block in different ICs {100} (e.g., functional block 110_n with the same function in different ICs), such as the first power-related behavior and the second power-related behavior (labeled "Device-A" and "Device-B" in the figure for simplicity). For system stability, the operating temperature is limited by the maximum power budget. More specifically, the first sample of the first power-related behavior and the second sample of the second power-related behavior are limited in different ways. Figure 10 As shown, when a predetermined value (e.g., maximum power budget, 1525 (mW)) is predetermined on the vertical axis, it is possible to... Figure 10The two curves shown respectively determine different targets on the horizontal axis corresponding to the second power-related behavior and the first power-related behavior (labeled as "Device-B" and "Device-A" in the figure) of the first temperature upper limit UL1 for different ICs (e.g., different ICs in the same batch or different ICs in different batches) to set the first temperature upper limit UL1 of a specific functional block (e.g., functional block 110_n) respectively.

[0120] For example, in the packaging test phase (e.g., it can also be performed in the electronic device through a preset program, such as performing a grouping process when the electronic device is started or when needed, and the present application does not make any limitation on the specific phase in which the grouping process is performed), a functional block or chip grouping process is performed on the first batch of IC products in the plurality of IC products of IC 100, so as to configure the first temperature upper limit UL1 of the specific functional block (e.g., any functional block 110_n in the IC) for the first batch of IC products. More particularly, in an example, the specific functional block of the corresponding IC in the first batch of IC products is determined (e.g., classified) to have the second power-related behavior (labeled as "Device-B" in the figure) and the first temperature upper limit UL1 of the specific functional block is configured according to the thermal operating capability (e.g., TOC#3) of the specific functional block of the IC{100} in the first batch of IC products, so that the performance of the first batch of IC products reaches the maximum, and therefore, the first temperature upper limit UL1 of the specific functional block (e.g., functional block 110_n) of IC 100 (e.g., each IC 100) in the IC{100} of the first batch of IC products is set as follows:

[0121] UL1 = Target1;

[0122] Wherein, Target1 in the above equation can represent Figure 10 Target#1 shown in FIG. 1, and can be configured according to, for example, Figure 10The second power-related behavior (labeled as "Device-B" in the figure) is determined according to a curve shown in the figure, but the present application is not limited thereto. In addition, the function block or chip grouping process is performed on the second batch of IC products in the plurality of IC products of the IC 100 for configuring the first temperature upper limit UL1 of the specific function block (e.g., any function block 110_n in the IC) in each IC in the second batch of IC products. More particularly, in an example, the specific function block of the corresponding IC in the second batch of IC products is determined (e.g., classified) as having the first power-related behavior (labeled as "Device-A" in the figure) and the first temperature upper limit UL1 of the specific function block is configured according to the thermal operating capability (e.g., TOC#3) of the specific function block of the IC{100} in the second batch of ICs so that the performance of the second batch of IC products reaches the maximum, and thus, the first temperature upper limit UL1 of the specific function block (e.g., function block 110_n) of any IC 100 (e.g., each IC 100) in the IC{100} in the second batch of IC products is set as follows:

[0123] UL1 = Target2;

[0124] wherein Target2 in the above equation can represent Figure 10 Target#2 shown in the figure, and can be determined according to Figure 10 The first power-related behavior (labeled as "Device-A" in the figure) corresponds to a curve shown in the figure, but the present application is not limited thereto. Compared with the related art, the specific function block (e.g., function block 110_n) of the IC 100 (e.g., the function block 110_n of any one of the IC{100} in the first batch of IC products and the function block 110_n of any one of the IC{100} in the second batch of IC products) can work normally in various cases while reaching the maximum performance, in which the first temperature upper limit UL1 of the specific function block is configured according to the thermal operating capability (e.g., TOC#3) of the specific function block so that the first temperature upper limit UL1 of the specific function block is as high as possible. For brevity, similar descriptions of this embodiment are not repeated here.

[0125] Figure 11 is a schematic diagram illustrating a thermal operating capability evaluation control scheme of a thermal control method according to a fourth embodiment of the present application. For example, the at least one function block-specific thermal operating capability can include TOC#4 of a specific function block (e.g., function block 110_n) of an integrated circuit (IC) 100, i.e., a thermal control efficiency of the specific function block (e.g., function block 110_n), such as Figure 11overshoot / undershoot temperature behavior (e.g., the overshoot temperature behavior and / or the undershoot temperature behavior) shown in FIG. 1. In Figure 11 In FIG. 1, the horizontal axis represents time measured in units of milliseconds (ms) and the vertical axis represents temperature measured in units of degrees Celsius (°C), but the present disclosure is not limited thereto. According to some embodiments, the relevant units can be different. In addition, Figure 11 The two curves shown in FIG. 1 can correspond to different overshoot / undershoot temperature behaviors, e.g., a first overshoot / undershoot temperature behavior and a second overshoot / undershoot temperature behavior (labeled as “Device-A” and “Device-B” in the figure for brevity), of the same functional block (e.g., the functional block 110_n) in different ICs {100}, where the operating temperature can be limited to a certain extent to prevent being affected by the overshoot / undershoot temperature behavior, and more particularly, a first sample for the first overshoot / undershoot temperature behavior and a second sample for the second overshoot / undershoot temperature behavior can be limited in different ways, respectively. As shown in FIG. 1, the first sample for the first overshoot / undershoot temperature behavior can be limited to a value (e.g., 112.5 (°C)) that is less than the predetermined value (e.g., 115 (°C)) of the second sample for the second overshoot / undershoot temperature behavior. Figure 11 As shown in FIG. 1, in the case where a limit (e.g., the predetermined value (e.g., 112.5 (°C))) on the vertical axis is predetermined, the first temperature upper limit UL1 for the first batch of IC products can be determined according to Figure 11 As shown in FIG. 1, the two curves can determine different targets on the vertical axis corresponding to the second overshoot / undershoot temperature behavior and the first overshoot / undershoot temperature behavior (labeled as “Device-B” and “Device-A” in the figure), e.g., Target #1 and Target #2, to set the first temperature upper limit UL1 for the specific functional block (e.g., the functional block 110_n) for different batches of IC products in the plurality of IC products of the integrated circuit (IC) 100, respectively.

[0126] For example, the functional block or chip grouping procedure is performed for a first batch of IC products in the plurality of IC products of the IC 100 to configure the first temperature upper limit UL1 for the specific functional block (e.g., any functional block 110_n in the IC) for the first batch of IC products, and more particularly, the specific functional block (e.g., any functional block 110_n in the IC) of the first batch of IC products is determined (e.g., classified) to have the second overshoot / undershoot temperature behavior (labeled as “Device-B” in the figure) and the first temperature upper limit UL1 for the specific functional block is configured according to the thermal operating capability (e.g., TOC #4) of the specific functional block of the IC {100} in the first batch of IC products to maximize the performance of the first batch of IC products, and thus, the first temperature upper limit UL1 for the specific functional block (e.g., the functional block 110_n) of any IC 100 (e.g., each IC 100) in the IC {100} in the first batch of IC products is set as follows:

[0127] UL1 = UL2 - (Limit0 - Target1);

[0128] In the above equation, Target1 can represent Figure 11 As shown in the figure, Target#1, and can be based on the corresponding as follows Figure 11 The curve showing the second overshoot / undershoot temperature behavior (labeled "Device-B" in the figure) is used to determine this, and Limit0 in the above equation can represent... Figure 11 The limitations shown are not limited to these. Furthermore, the manufacturing tool for IC 100 can be configured to perform a function block or chip grouping process on a second batch of IC products from a plurality of IC products of IC 100 to configure a first temperature limit UL1 for a specific function block (e.g., any function block 110_n in the IC) for the second batch of IC products. More specifically, it is determined (e.g., classified) that the second batch of IC products has a first overshoot / undershoot temperature behavior (labeled "Device-A" in the figure) and the first temperature limit UL1 for the specific function block is configured according to the thermal operating capability (e.g., TOC#4) of the specific function block of IC{100} in the second batch of ICs to maximize the performance of the second batch of IC products. Therefore, the first temperature limit UL1 for a specific function block (e.g., function block 110_n) of any IC 100 (e.g., each IC 100) in the second batch of IC products is set as follows:

[0129] UL1 = UL2 - (Limit0 - Target2);

[0130] In the above equation, Target2 can represent Figure 11 As shown in Target#2, and can be based on the corresponding as follows Figure 11 The curve showing the first overshoot / undershoot temperature behavior (labeled "Device-A" in the figure) is used to determine this, and Limit0 in the above equation can represent... Figure 12 The limitations shown are not limited thereto. Compared to related technologies, specific functional blocks of IC 100 (e.g., functional blocks 110_n) (e.g., functional blocks 110_n of any IC 100 in the first batch of IC products and functional blocks 110_n of any IC 100 in the second batch of IC products) can operate normally under various conditions while achieving maximum performance. The first temperature limit UL1 of the specific functional block can be configured according to the thermal operating capability of the specific functional block (e.g., TOC#4) to make the first temperature limit UL1 of the specific functional block as high as possible. For the sake of brevity, descriptions similar to those in this embodiment will not be repeated here.

[0131] Figure 12 This is a schematic diagram illustrating a thermal operation capability evaluation control scheme for a thermal control method according to a fifth embodiment of the present invention. For example, the at least one per-function-block thermal operation capability mentioned above may include the TOC#5 of a specific function block (e.g., function block 110_n) of IC 100, i.e., the operating power efficiency related to the temperature level of the specific function block (e.g., function block 110_n), for example, such as... Figure 12 The relationship between CPU leakage power-dynamic power ratio (e.g., the ratio of CPU leakage power to dynamic power) and temperature is shown. Figure 12 In the diagram, the horizontal axis represents temperature measured in degrees Celsius (°C), and the vertical axis represents the ratio of CPU leakage power to dynamic power measured as a percentage (%). However, the invention is not limited to this. According to some embodiments, the units may differ. Additionally, Figure 12 The two curves shown can correspond to different power-ratio-related behaviors of the same functional block (e.g., functional block 110_n) in different ICs {100}, such as the first power-ratio-related behavior and the second power-ratio-related behavior (labeled "Device-A" and "Device-B" for simplicity), where the operating temperature may be limited by a power-ratio budget of the ratio of CPU leakage power to dynamic power. More specifically, the first sample of the first power-ratio-related behavior and the second sample of the second power-ratio-related behavior may be limited in different ways. Figure 12 As shown, given predetermined constraints such as a fixed value on the vertical axis (e.g., 30.5%), it is possible to... Figure 12 The two curves shown define different targets on the horizontal axis corresponding to the first power ratio related behavior and the second power ratio related behavior (labeled "Device-A" and "Device-B"), such as Target#1 and Target#2, to set the first temperature limit UL1 for a specific functional block (e.g., functional block 110_n) for different batches of IC products among multiple IC products used in integrated circuit (IC) 100.

[0132] For example, the function block or chip grouping flow is performed for a first batch of IC products of the plurality of IC products of ICs 100 for configuring a first temperature upper limit UL1 of a specific function block (e.g., any function block 110_n in the IC) of the first batch of IC products. More particularly, in an example, the specific function block of the first batch of IC products is determined (e.g., classified) to have a first power ratio dependent behavior (labeled as "Device-A" in the figure) and the first temperature upper limit UL1 of the specific function block is configured according to the thermal operating capability (e.g., TOC#5) of the specific function block of the ICs {100} in the first batch of IC products so that the performance of the first batch of IC products is maximized. Thus, the first temperature upper limit UL1 of the specific function block (e.g., function block 110_n) of any IC 100 (e.g., each IC 100) in the ICs {100} of the first batch of IC products is set as follows:

[0133] UL1 = Target1;

[0134] wherein Target1 in the above equation can represent Target#2 as shown in Figure 12 and can be determined according to a curve corresponding to the first power ratio dependent behavior (labeled as "Device-A" in the figure) as shown in Figure 12 but the present application is not limited thereto. Further, the function block or chip grouping flow is performed for a second batch of IC products of the plurality of IC products of ICs 100 for configuring a first temperature upper limit UL1 of a specific function block (e.g., any function block 110_n in the IC) of the second batch of IC products. More particularly, in an example, the specific function block of the second batch of IC products is determined (e.g., classified) to have a second power ratio dependent behavior (labeled as "Device-B" in the figure) and the first temperature upper limit UL1 of the specific function block is configured according to the thermal operating capability (e.g., TOC#5) of the specific function block of the ICs {100} in the second batch of ICs so that the performance of the second batch of IC products is maximized, thus, the first temperature upper limit UL1 of the specific function block (e.g., function block 110_n) of any IC 100 (e.g., each IC 100) in the ICs {100} of the second batch of IC products is set as follows:

[0135] UL1 = Target2;

[0136] wherein Target2 in the above equation can represent Target#2 as shown in Figure 12 and can be determined according to a curve corresponding to the second power ratio dependent behavior (labeled as "Device-B" in the figure) as shown in Figure 13The illustrated second power ratio related behavior (labeled as "Device-B" in the figure) corresponds to a curve determined in this way, but the application is not limited thereto. In comparison with the related art, the specific functional block (e.g., functional block 110_n) of the IC 100 (e.g., the functional block 110_n of any one of the ICs 100 in the first batch of IC products and the functional block 110_n of any one of the ICs 100 in the second batch of IC products) is able to work normally in various cases while achieving maximum performance, where the first upper limit of temperature UL1 of the specific functional block is configured according to the thermal operating capability (e.g., TOC#5) of the specific functional block, so that the first upper limit of temperature UL1 of the specific functional block is as high as possible. For brevity, similar descriptions of this embodiment are not repeated here.

[0137] Figure 13 is a schematic diagram illustrating a thermal operating capability evaluation control scheme of a thermal control method according to a sixth embodiment of the application. For example, the at least one functional block-specific thermal operating capability can include, for example, TOC#6 of the specific functional block (e.g., functional block 110_n) of the IC 100, i.e., a reliability budget of the specific functional block (e.g., functional block 110_n), for example, Figure 13 The illustrated relationship between lifetime and temperature. In Figure 13 the horizontal axis represents temperature and is measured in degrees Celsius (°C), and the vertical axis represents lifetime and is measured in years, but the application is not limited thereto. According to some embodiments, the related units can be different. In addition, Figure 13 The two curves illustrated can correspond to different lifetime-related behaviors of the same functional block (e.g., functional block 110_n) in different ICs 100, respectively, for example, a first lifetime-related behavior and a second lifetime-related behavior (labeled as "Device-A" and "Device-B" in the figure for brevity), where the operating temperature is limited by a reliability budget related to lifetime, and more particularly, a first sample for the first lifetime-related behavior and a second sample for the second lifetime-related behavior are limited in different ways. As Figure 13 As illustrated, when the limit such as a predetermined value (e.g., 4 years) on the vertical axis is predetermined, the specific functional block (e.g., functional block 110_n) of the IC 100 (e.g., the functional block 110_n of any one of the ICs 100 in the first batch of IC products and the functional block 110_n of any one of the ICs 100 in the second batch of IC products) is able to work normally in various cases while achieving maximum performance, where the first upper limit of temperature UL1 of the specific functional block is configured according to the thermal operating capability (e.g., TOC#5) of the specific functional block, so that the first upper limit of temperature UL1 of the specific functional block is as high as possible. For brevity, similar descriptions of this embodiment are not repeated here. Figure 13The two curves shown respectively determine different targets on the horizontal axis corresponding to the second usage period related behavior and the first usage period related behavior (labeled as "Device-B" and "Device-A" in the figure) of the specific functional block (e.g., functional block 110_n) for different ICs (e.g., different ICs in the same batch or different ICs in different batches) to set the first temperature upper limit UL1, for example, Target#1 and Target#2.

[0138] For example, the functional block or chip grouping procedure is performed on a first batch of IC products in the plurality of IC products of IC 100 for configuring the first temperature upper limit UL1 of the specific functional block (e.g., any functional block 110_n in the IC) for the first batch of IC products. More particularly, in an example, the specific functional block of the first batch of IC products is determined (e.g., classified) to have the first usage period related behavior (labeled as "Device-A" in the figure) and the first temperature upper limit UL1 of the specific functional block is configured according to the thermal operating capability (e.g., TOC#6) of the specific functional block of IC{100} in the first batch of IC products so that the performance of the first batch of IC products is maximized, and thus, the first temperature upper limit UL1 of the specific functional block (e.g., functional block 110_n) of IC{100} in any IC 100 (e.g., each IC 100) of the first batch of IC products is set as follows:

[0139] UL1 = Target2;

[0140] wherein Target2 in the above equation can represent Target#2 shown in Figure 13 and can be determined according to the curve corresponding to the first usage period related behavior (labeled as "Device-A" in the figure) as shown in Figure 13 but the present application is not limited thereto. In addition, the functional block or chip grouping procedure is performed on a second batch of IC products in the plurality of IC products of IC 100 for configuring the first temperature upper limit UL1 of the specific functional block (e.g., any functional block 110_n in the IC) for the second batch of IC products. More particularly, in an example, the specific functional block of the second batch of IC products is determined (e.g., classified) to have the second usage period related behavior (labeled as "Device-B" in the figure) and the first temperature upper limit UL1 of the specific functional block is configured according to the thermal operating capability (e.g., TOC#6) of the specific functional block of IC{100} in the second batch of IC products so that the performance of the second batch of IC products is maximized, and thus, the first temperature upper limit UL1 of the specific functional block (e.g., functional block 110_n) of any IC 100 (e.g., each IC 100) of IC{100} in the second batch of IC products is set as follows:

[0141] UL1 = Target1;

[0142] In the above equation, Target1 can represent Figure 14 The Target#1 shown, and, can be based on Figure 14 The curve corresponding to the second usage period-related behavior shown (labeled "Device-B" in the figure) is used to determine this, but the present invention is not limited thereto. Compared with related technologies, specific functional blocks of IC 100 (e.g., functional blocks 110_n) (e.g., functional blocks 110_n of any IC 100 in the first batch of IC products and functional blocks 110_n of any IC 100 in the second batch of IC products) can operate normally under various conditions while achieving maximum performance, wherein the first temperature limit UL1 of the specific functional block is configured according to the thermal operating capability of the specific functional block (e.g., TOC#6) to make the first temperature limit UL1 of the specific functional block as high as possible. For the sake of brevity, similar descriptions of this embodiment will not be repeated here.

[0143] Figure 14 A schematic diagram of the workflow of a thermal control method according to an embodiment of the present invention is shown. The thermal control method can be applied to IC 100, and IC 100 can be configured to perform adaptive thermal upper limit control on a per-function-block basis. According to the thermal control method, multiple phases such as the manufacturing phase PHASE (0) and the user phase PHASE (1) can respectively include the operations of steps S10 and S21 and S22.

[0144] In step S10, at least one first temperature upper limit UL1 can be set according to at least one item of the per-function block thermal operating capability of any function block 110_n among the function blocks 110_1, 110_2, …, and 110_N in the IC 100, e.g., by a production tool of the IC 100. For example, under the control of the production tool, the IC 100 (e.g., a function block 110_1 such as a CPU) can store at least one temperature upper limit UL1 (or TOCs parameters used for UL1 calculation) into a storage unit in the thermal control circuit 120 for use in the user phase PHASE(1), but the present application is not limited thereto, e.g., the first temperature upper limit can also be set or updated after performing a function block or chip grouping procedure (e.g., in the user phase) in an electronic device to obtain the per-function block thermal operating capability of each function block, etc. For another example, under the control of the production tool, the IC 100 (e.g., a function block 110_1 such as a CPU) can store at least one first temperature upper limit UL1 (or TOCs parameters used for UL1 calculation) to another storage unit (e.g., a non-volatile memory) integrated to the IC 100 for loading to the thermal control circuit 120 and use in the user phase PHASE(1). According to the thermal control method, the production tool of the IC 100 can perform a function block or chip grouping procedure on the IC 100 to identify at least one item of the per-function block thermal operating capability of any function block 110_n among the function blocks 110_1, 110_2, …, 110_N in the IC 100, and then use the at least one item of the per-function block thermal operating capability identified in the function block or chip grouping procedure to determine the at least one first temperature upper limit UL1.

[0145] In step S21, the IC 100 can detect / monitor the temperature using at least one temperature sensor associated with (e.g., integrated with) the first function block (e.g., the function block 110_n) to generate at least one temperature detection result of the first function block, e.g., the at least one temperature sensor can be at least one temperature sensor integrated with (e.g., integrated beside or in) a specific function block (e.g., the function block 110_n) among the plurality of function blocks (e.g., the function blocks 110_1, 110_2, …, 110_N) of the IC 100, i.e., at least one temperature sensor associated with the specific function block (e.g., the function block 110_n).

[0146] In step S22, IC 100 can perform thermal control on the plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N), and more particularly, on a first functional block (e.g., functional block 110_n) by monitoring at least one temperature detection result of the first functional block and attempting to prevent the at least one temperature detection result of the first functional block from exceeding a first temperature upper limit UL1 of the first functional block of IC 100, where the first temperature upper limit UL1 of the first functional block (e.g., functional block 110_n) is configured according to at least one item of per-functional-block thermal operating capability of the first functional block, to prevent the first functional block from overheating and causing abnormal (functional) operation. Note that the functional block count N of functional blocks 110_1, 110_2, …, and 110_N can be greater than or equal to 1. For example, when the functional block count N is equal to 1, the first functional block (e.g., any functional block 110_n) represents functional block 110_1 (e.g., CPU), but the present application is not limited thereto.

[0147] As shown in Figure 14 , step S10 can be performed in a production phase PHASE(0), e.g., a mass production phase (further e.g., more particularly, a package testing phase), while steps S21 and S22 can be performed in a user phase PHASE(1) of IC 100, e.g., a phase after electronic device 300 is obtained (a phase in which the user can use electronic device 300). For brevity, similar descriptions of the present embodiment are not repeated here.

[0148] For better understanding, the method is explained with the workflow shown in ​ , but the present application is not limited thereto. According to some embodiments, one or more steps can be added, deleted, or changed in the workflow shown in ​ .

[0149] According to some embodiments, the IC 100 can include a plurality of functional blocks, e.g., functional blocks 110_1, 110_2, …, and 110_N, and the first functional block is a functional block (e.g., functional block 110_n) of the plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N), wherein the plurality of temperature sensors are used (e.g., integrated) with the plurality of functional blocks in pairs to detect temperatures and generate a plurality of temperature detection results of the plurality of functional blocks respectively. In addition, the at least one thermal control circuit (e.g., thermal control circuit 120) described above can be configured to, in a time interval between a start time point when the IC 100 is started and an end time point when the IC 100 is shut down, perform thermal control on the plurality of functional blocks (e.g., functional blocks 110_1, 110_2, …, and 110_N) respectively by monitoring the plurality of temperature detection results of the plurality of functional blocks (e.g., the respective temperature detection results of functional blocks 110_1, 110_2, …, and 110_N) and by trying to prevent the plurality of temperature detection results of the plurality of functional blocks from exceeding a plurality of first temperature upper limits (e.g., a plurality of first temperature upper limits {UL1} corresponding to functional blocks 110_1, 110_2, …, and 110_N) of the plurality of functional blocks in a manner to prevent the plurality of functional blocks from overheating and causing (functional) operation abnormalities, wherein the first temperature upper limit UL1_1 of the first functional block (e.g., functional block 110_n) is one of the plurality of first temperature upper limits {UL1}.

[0150] According to some embodiments, the at least one thermal control circuit (e.g., thermal control circuit 120) described above can be implemented by software running on the first functional block (e.g., functional block 110_n). For brevity, similar descriptions of this embodiment are not repeated here.

[0151] According to some embodiments, the at least one first temperature upper limit UL1 of the at least one functional block (e.g., functional block 110_n) can be implemented as at least one first chip-level temperature upper limit UL1(1). For example, the at least one thermal control circuit (e.g., thermal control circuit 120) can determine the at least one first chip-level temperature upper limit UL1(1) according to the at least one first functional block-level temperature upper limit UL1(0), e.g., the at least one first functional block-level temperature upper limit UL1(0) can be one or more first functional block-level temperature upper limits {UL1(0)}, such as the plurality of first temperature upper limits {UL1} of IC 100, wherein the plurality of first temperature upper limits {UL1} can represent a plurality of thermal upper limit target values (e.g., first temperature upper limits UL1_1, UL1_2, …, and UL1_N) for functional blocks 110_1, 110_2, …, and 110_N, respectively, to prevent functional blocks 110_1, 110_2, …, and 110_N from overheating. Further, the at least one first chip-level temperature upper limit UL1(1) can be equal to the at least one first functional block-level temperature upper limit UL1(0) (e.g., one or more first functional block-level temperature upper limits {UL1(0)}), such as the minimum value of the plurality of first temperature upper limits {UL1} (e.g., first temperature upper limits UL1_1, UL1_2, …, and UL1_N) of IC 100, but the present application is not limited thereto. For brevity, similar descriptions of these embodiments are not repeated in detail here.

[0152] According to some embodiments, the thermal control method is also applicable to a host circuit 200 including an integrated circuit (IC) 100, wherein the at least one first temperature upper limit UL1 of the at least one functional block (e.g., functional block 110_n) can be at least one first chip-level temperature upper limit UL1(1). Further, the thermal control method can also include:

[0153] (1) performing temperature detection within the host circuit 200 using a plurality of substrate-level temperature sensors (e.g., substrate-level temperature sensors 210_1, 210_2, 210_3, and 210_4) to generate respective temperature detection results of ICs 100, 220, 230, and 240 within the host circuit 200; and

[0154] (2) performing thermal control of ICs 100, 220, 230, and 240 by monitoring the respective temperature detection results of ICs 100, 220, 230, and 240 within the host circuit 200 and attempting to prevent the respective temperature detection results of ICs 100, 220, 230, and 240 from exceeding at least one first substrate-level temperature upper limit UL1(2) of the host circuit 200, using at least one thermal control circuit (e.g., thermal control circuit 120), to prevent ICs 100, 220, 230, and 240 from overheating and causing functional operation abnormalities.

[0155] At least one first substrate-level upper temperature limit UL1(2) is set for at least one substrate-level component thermal operating capability of the main circuit 200, but the present application is not limited thereto. For brevity, similar descriptions of these embodiments are not repeated in detail here.

[0156] According to some embodiments, the thermal control method is also applicable to the electronic device 300 comprising the main circuit 200, wherein the main circuit 200 is a main component of the electronic device 300. In addition, the thermal control method can further comprise:

[0157] (1) performing temperature detection within the electronic device 300 by using a plurality of device-level temperature sensors (e.g., device-level temperature sensors 310_1, 310_2, 310_3, 310_4, 310_5, and 310_6) to generate respective temperature detection results of the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 within the electronic device 300; and

[0158] (2) performing thermal control on the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 by using at least one thermal control circuit (e.g., the thermal control circuit 120) to monitor the respective temperature detection results of the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 and attempt to prevent the respective temperature detection results of the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 from exceeding at least one first device-level upper temperature limit UL1(3) of the electronic device 300, so as to prevent the main circuit 200 and the secondary components 320, 330, 340, 350, and 360 from overheating and causing abnormal operation.

[0159] At least one first device-level upper temperature limit UL1(3) is set for at least one device-level thermal operating capability of the electronic device 300, but the present application is not limited thereto. For brevity, similar descriptions of these embodiments are not repeated in detail here.

[0160] The present application has the advantage that, by proper design, the ICs and related devices (e.g., main circuits, electronic devices, etc.) of the present application are equipped with at least one first temperature upper limit, where the at least one first temperature upper limit is configurable with respect to at least one item of per-function block thermal operating capability of at least one functional block, thereby further enhancing system performance in a per-function block manner. In embodiments of the present application, the first temperature upper limit is configured in a per-function block manner, that is, in the case where the IC includes multiple functional blocks, the first temperature upper limit can be equipped for some or all of the functional blocks (i.e., the IC is equipped with one or more first temperature upper limits), where each first temperature upper limit is associated with a corresponding functional block and is configured according to the thermal operating capability of the corresponding functional block. For example, in an example, an IC product can include multiple batches of IC products, one batch of IC products (e.g., a first group of IC products, and more particularly, individual functional blocks of the first group of IC products) is configured with at least one first temperature upper limit according to at least one item of per-function block thermal operating capability of at least one functional block of the batch of ICs to achieve maximum performance of the batch of ICs; and another batch of IC products (e.g., a second group of IC products, and more particularly, individual functional blocks of the second group of IC products) has at least one first temperature upper limit configured according to at least one item of per-function block thermal operating capability of at least one functional block of the other batch of ICs to achieve maximum performance of the other batch of ICs. Compared with the related art, the ICs and related devices (e.g., main circuits, electronic devices, etc.) of the present application can operate correctly and at maximum performance in various situations, where the at least one first temperature upper limit is configured according to at least one item of per-function block thermal operating capability of at least one functional block of the IC to make the at least one first temperature upper limit as high as possible, thereby further enhancing system performance.

[0161] The use of ordinal terms such as "first", "second", "third", etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another, or to the temporal manner of execution of steps of a method, but are used merely as labels to identify elements having the same name.

[0162] While the application has been described by example and in terms of preferred embodiments, it is to be understood that the application is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and equivalent arrangements (as would be apparent to one skilled in the art). It is to be understood that the scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. An integrated circuit (IC) configurable to perform adaptive thermal ceiling control in a per-function block manner, the IC comprising: a plurality of hardware circuits to perform operations of a first function block, wherein at least one temperature sensor is integrated with the first function block to detect a temperature of the first function block and to generate at least one temperature detection result of the first function block; and at least one thermal control circuit to thermally control the first function block by monitoring the at least one temperature detection result of the first function block and by attempting to prevent the at least one temperature detection result of the first function block from exceeding a first temperature ceiling of the first function block of the IC in a manner that prevents the first function block from overheating to cause operational anomalies, wherein the first temperature ceiling is located within a predetermined temperature region and is configured according to at least one per-function block thermal operating capability of the first function block; wherein a maximum value of the predetermined temperature region is less than a second temperature ceiling of the first function block of the IC, the second temperature ceiling is determined according to a first per-function block thermal sensor related characteristic such that a temperature region between the second temperature ceiling and a third temperature ceiling of the first function block of the IC corresponds to the first per-function block thermal sensor related characteristic, wherein the third temperature ceiling is greater than the second temperature ceiling, and the third temperature ceiling represents a temperature ceiling that does not take into account the first per-function block thermal sensor related characteristic.

2. The IC of claim 1, wherein, the IC comprises a plurality of function blocks, the first function block is a function block of the plurality of function blocks, wherein a plurality of temperature sensors respectively detect temperatures and generate a plurality of temperature detection results of the plurality of function blocks; and the at least one thermal control circuit is to thermally control the plurality of function blocks by monitoring the plurality of temperature detection results of the plurality of function blocks and by attempting to prevent each temperature detection result of the plurality of temperature detection results of the plurality of function blocks from exceeding a respective first temperature ceiling of a plurality of first temperature ceilings of the plurality of function blocks in a manner that prevents the plurality of function blocks from overheating to cause operational anomalies.

3. The IC of claim 1, wherein, the at least one per-function block thermal operating capability comprises a power-thermal efficiency of a respective function block within the IC.

4. The IC of claim 1, wherein, the at least one per-function block thermal operating capability comprises a maximum voltage budget of a respective function block within the IC.

5. The IC of claim 1, wherein, the at least one per-function block thermal operating capability comprises a maximum power budget of a respective function block within the IC.

6. The IC of claim 1, wherein, the at least one per-function block thermal operating capability comprises a thermal control efficiency of a respective function block within the IC.

7. The IC of claim 1, wherein, the at least one per-function block thermal operating capability comprises an operational power efficiency related to a temperature level of a respective function block within the IC.

8. The IC of claim 1, wherein, the at least one per-function block thermal operating capability comprises a reliability budget of a respective function block within the IC.

9. The IC of claim 1 or 2, wherein, the first temperature ceiling is configured as an adaptive thermal ceiling point located within a predetermined temperature region according to the at least one per-function block thermal operating capability.

10. The IC of claim 9, wherein, the first per-function block thermal sensor related characteristic represents a per-function block thermal sensor detection tolerance related to a location of the at least one temperature sensor integrated to the respective function block.

11. The IC of claim 9, wherein, The first per-function-block thermal sensor related characteristic represents a per-function-block thermal sensor accuracy related to at least one temperature detection accuracy of at least one temperature sensor integrated to the corresponding function block.

12. The IC of claim 9, wherein, The third temperature upper limit is determined according to the second per-function-block thermal sensor related characteristic, such that a temperature region between the third temperature upper limit and a fourth temperature upper limit corresponds to the second per-function-block thermal sensor related characteristic, wherein the fourth temperature upper limit is greater than the third temperature upper limit, and the fourth temperature upper limit represents a temperature upper limit regardless of the first per-function-block thermal sensor related characteristic and the second per-function-block thermal sensor related characteristic.

13. The IC of claim 12, wherein, The first per-function-block thermal sensor related characteristic represents a per-function-block thermal sensor accuracy related to at least one temperature detection accuracy of at least one temperature sensor integrated to the corresponding function block; and the second per-function-block thermal sensor related characteristic represents a per-function-block thermal sensor detection tolerance related to a position of the at least one temperature sensor integrated to the corresponding function block.

14. The IC of claim 12, wherein, The first per-function-block thermal sensor related characteristic represents a per-function-block thermal sensor accuracy related to at least one temperature detection accuracy of at least one temperature sensor integrated to the corresponding function block; and the second per-function-block thermal sensor related characteristic represents a per-function-block thermal sensor detection tolerance related to a position of the at least one temperature sensor integrated to the corresponding function block.

15. The IC of claim 12, wherein, The fourth temperature upper limit is a strictly prohibited upper limit defined by manufacturing conditions provided by a manufacturer of the IC.

16. The IC of claim 12, wherein, The IC comprises a plurality of function blocks, and the first function block is a function block in the plurality of function blocks, one of the first per-function-block thermal sensor related characteristic and the second per-function-block thermal sensor related characteristic represents a per-function-block thermal sensor accuracy; wherein the per-function-block thermal sensor accuracy is related to at least one temperature detection accuracy of the at least one temperature sensor integrated to the first function block, or the per-function-block thermal sensor accuracy is related to respective temperature detection accuracies of at least a portion of a plurality of temperature sensors associated with the plurality of function blocks.

17. The IC of claim 16, wherein, The per-function-block thermal sensor accuracy is an average of the at least one temperature detection accuracy.

18. The IC of claim 16, wherein, The per-function-block thermal sensor accuracy is a statistical value of the at least one temperature detection accuracy.

19. The IC of claim 16, wherein, The per-function-block thermal sensor accuracy is a worst temperature detection accuracy in the at least one temperature detection accuracy.

20. The IC of claim 1, wherein, The at least one per-function-block thermal operating capability of the first function block within the IC is determined by performing a function block or chip grouping procedure on the IC.

21. The IC of claim 1, wherein, The at least one thermal control circuit is implemented in a manner of at least one of hardware, software running on the first function block, or a mixture of hardware and software.

22. A main circuit, characterized by The IC comprises any one of claims 1-21, wherein the first temperature upper limit is a first chip-level temperature upper limit; and the main circuit further comprises: at least one other IC for performing at least one other operation for the IC; and at least one other IC for performing at least one other operation for the IC; and a plurality of substrate-level temperature sensors for performing temperature detection within the main circuit to generate respective temperature detection results of the IC and the at least one other IC; wherein the at least one thermal control circuit is configured to thermally control the IC and the at least one other IC by monitoring the respective temperature detection results of the IC and the at least one other IC and attempting to prevent the respective temperature detection results of the IC and the at least one other IC from exceeding at least one first substrate-level temperature upper limit of the main circuit in a manner that prevents the IC and the at least one other IC from overheating to cause operational abnormality, wherein the at least one first substrate-level temperature upper limit is configured according to at least one per-substrate-level component thermal operating capability of the main circuit.

23. An electronic device, comprising: a main circuit as claimed in claim 22, wherein the main circuit is a primary component of the electronic device, and the electronic device further comprises: at least one secondary component arranged to operate under control of the main circuit; and a plurality of device-level temperature sensors for performing temperature detection within the electronic device to generate respective temperature detection results of the main circuit and the at least one secondary component, respectively; wherein the at least one thermal control circuit is configured to thermally control the main circuit and the at least one secondary component by monitoring the respective temperature detection results of the main circuit and the at least one secondary component and attempting to prevent the respective temperature detection results of the main circuit and the at least one secondary component from exceeding at least one first device-level temperature upper limit of the electronic device in a manner that prevents the main circuit and the at least one secondary component from overheating to cause operational abnormality, wherein the at least one first device-level temperature upper limit is configured according to at least one per-device-level component thermal operating capability of the electronic device.

24. A thermal control method applicable to at least one functional block of an integrated circuit (IC) configurable to perform adaptive thermal upper limit control on a per-functional block basis, the thermal control method comprising: detecting temperature using at least one temperature sensor integrated with a first functional block of the at least one functional block of the IC to generate at least one temperature detection result of the first functional block; and the first functional block is thermally controlled by monitoring the at least one temperature detection result of the first functional block and in a manner that seeks to prevent the at least one temperature detection result from exceeding a first temperature upper limit of the first functional block of the IC, to prevent the first functional block from overheating and causing operational abnormalities, wherein, the first temperature upper limit is within a predetermined region and is configured according to at least one per-functional block thermal operating capability of the first functional block; wherein a maximum value of the predetermined temperature region is less than a second temperature upper limit of the first functional block of the IC; the second temperature upper limit is determined according to a first per-functional block thermal sensor related characteristic such that a temperature region between the second temperature upper limit and a third temperature upper limit of the first functional block of the IC corresponds to the first per-functional block thermal sensor related characteristic, wherein the third temperature upper limit is greater than the second temperature upper limit, and the third temperature upper limit represents a temperature upper limit that does not take into account the first per-functional block thermal sensor related characteristic.

25. The thermal control method of claim 24, wherein, The steps of detecting temperature and generating at least one temperature detection result of a first functional block of the IC using at least one temperature sensor integrated with the first functional block of the at least one functional block of the IC and the steps of thermally controlling the first functional block by monitoring the at least one temperature detection result of the first functional block and attempting to prevent the at least one temperature detection result from exceeding a first temperature upper limit of the first functional block of the IC to prevent the first functional block from overheating and causing operational abnormality are performed in a user phase of the IC, wherein the at least one functional-block-specific thermal operating capability is determined by performing a functional block or chip grouping procedure on the IC.

26. The thermal control method of claim 24, wherein, The thermal control method is further applicable to a host circuit including the IC, the first temperature upper limit is a first chip-level temperature upper limit, and the thermal control method further comprises: performing temperature detection within the host circuit using a plurality of substrate-level temperature sensors to generate respective temperature detection results of the IC and at least one other IC within the host circuit; and thermally controlling the IC and the at least one other IC by monitoring the respective temperature detection results of the IC and the at least one other IC and attempting to prevent the respective temperature detection results of the IC and the at least one other IC from exceeding at least one first substrate-level temperature upper limit of the host circuit to prevent the IC and the at least one other IC from overheating and causing operational abnormality, wherein the at least one first substrate-level temperature upper limit is configured according to at least one substrate-level component thermal operating capability of the host circuit.

27. The thermal control method of claim 26, wherein, The thermal control method is further applicable to an electronic device including the host circuit, wherein the host circuit is a primary component of the electronic device, and the thermal control method further comprises: performing temperature detection within the electronic device using a plurality of device-level temperature sensors to generate respective temperature detection results of the host circuit and at least one secondary component within the electronic device; and thermally controlling the host circuit and the at least one secondary component by monitoring the respective temperature detection results of the host circuit and the at least one secondary component and attempting to prevent the respective temperature detection results of the host circuit and the at least one secondary component from exceeding at least one first device-level temperature upper limit of the electronic device to prevent the host circuit and the at least one secondary component from overheating and causing operational abnormality, wherein the at least one first device-level temperature upper limit is configured according to at least one device-level component thermal operating capability of the electronic device.

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