Fabrication method of VDMOS device resistant to single-particle radiation based on polysilicide interconnects

Abstract

This invention discloses a method for manufacturing a single-particle radiation-resistant VDMOS device based on polysilicide interconnects, belonging to the field of power switching devices. First, a silicon wafer material is provided, and then P... + Injection to form P + Low resistance; then at P + Polycrystalline materials and polysilicides are fabricated on low-resistivity surfaces to reduce the interconnect line width of the polysilicides; then contact holes and silicon via structures are fabricated; finally, P-type silicon vias are implemented after the silicon vias are formed. ++ The process involves injection, followed by the fabrication of the metal structure. This invention improves and optimizes the polycrystalline interconnect structure of radiation-hardened VDMOS devices by using polycrystalline silicide instead of polycrystalline silicide, reducing the width of the polycrystalline silicide interconnect lines to 0.1 times that of the polycrystalline interconnect lines. This reduces the silicon surface voltage when a single particle passes through the device, thus achieving single-particle hardening of the VDMOS device.

Description

Technical Field

[0001] This invention relates to the field of power switching device technology, and in particular to a method for manufacturing a VDMOS device resistant to single-particle radiation based on polysilicide interconnects. Background Technology

[0002] VDMOS (Vertical Diffused Metal-Oxide Semiconductor field effect transistor) has advantages such as low power consumption, fast switching speed, strong drive capability, and negative temperature coefficient, and is widely used in power modules of satellite electronic systems. In the space ionizing radiation environment, the radiation effects on VDMOS devices mainly include SEB (Single Event Burnout), SEGR (Single Event Gate Rupture), and total dose effects. Compared to conventional VDMOS device structures, radiation-hardened VDMOS device structures require special ruggedization designs.

[0003] Single-particle burnout occurs when a charged particle enters a VDMOS device, generating a large number of electron-hole pairs along its trajectory. Under the influence of an applied voltage, electrons move towards the drain and holes move towards the source. In the region where high-density current and high voltage coexist, the silicon lattice temperature rises sharply, leading to device burnout.

[0004] When a single particle is incident on the inside of a VDMOS device, the high voltage applied to the drain on the back of the power chip couples to the device surface via the high-density charge on the incident trajectory. The polysilicon interconnect lines of a VDMOS are typically 50–100 μm wide and located above the field region between cells. The distance from the midpoint of the polysilicon interconnect line to the nearest ground via is greater than 30 μm. Assuming a single particle is incident on the VDMOS device from the midpoint of the polysilicon interconnect line in the field region, the distance the charge on the incident trajectory travels to the ground via is greater than 30 μm. The larger the distance between the incident point and the ground via, the greater the surface voltage coupled from the drain high voltage to the silicon surface, the greater the heat dissipation generated by the irradiation current, and the more susceptible the device is to single-particle burn-out. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing VDMOS devices based on polysilicide interconnects that are resistant to single-event radiation, so as to improve the single-event burn-out and single-event gate breakdown capabilities of medium and high voltage radiation-resistant VDMOS products.

[0006] To address the aforementioned technical problems, this invention provides a method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects, comprising:

[0007] Provide silicon wafer materials, through P + Injection to form P + Low resistance;

[0008] In P + Low-resistivity surfaces are used to fabricate polycrystalline and polysilicides, and the interconnect line width of polysilicides is reduced;

[0009] Fabrication of contact holes and silicon via structures;

[0010] P is performed after silicon pores are formed. ++ Injection, and finally, the metal structure is fabricated.

[0011] In one embodiment, a silicon wafer material is provided, via P + Injection to form P + Low resistance includes:

[0012] A photoresist is coated onto a silicon wafer and a patterned window is exposed. Boron ions are implanted into the silicon at the polycrystalline interconnect locations to form P0. + Low resistance, with an injection energy of 50–100 keV and an injection dose of 3 × 10⁻⁶. 15 ~6×10 15 cm -2 The conditions for bonding are 1100℃ for 60 minutes;

[0013] After pushing, P is formed. + The volume concentration of low-resistivity is 1×10 19 ~1×10 20 cm -3 P + The resistivity of low resistance is 1–10 mohm·cm.

[0014] In one implementation, at P + Fabricating polycrystalline and polysilicides on low-resistivity surfaces and reducing the interconnect line width of polysilicides includes:

[0015] P + After implantation, a gate oxide layer with a thickness of 80–120 nm is grown by thermal oxidation, followed by deposition of a polycrystalline material with a thickness of 500–1000 nm. The phosphorus implantation dose is 3 × 10⁻⁶. 15 ~8×10 15 cm -2 Anneal at 850–900℃ for 30–60 minutes;

[0016] Ti with a thickness of 30-100 nm is deposited and then annealed at an RTP temperature of 800-900 °C for 30-90 seconds to form polycrystalline silicide TiSi2.

[0017] A patterned window is created by coating a silicon wafer with photoresist and exposing it. Polysilicide TiSi2 and polysilicon are then etched to form the MOS gate and interconnects of the polysilicide.

[0018] In one embodiment, fabricating the contact hole and silicon via structure includes:

[0019] SiO2 with a thickness of 500–1000 nm is deposited, covering polycrystalline and polycrystalline silicides;

[0020] A resist is coated onto a silicon wafer and a patterned window is exposed, followed by etching of SiO2.

[0021] After finding the Si / SiO2 endpoint, Si is etched at regular intervals. The etching depth of Si is 200-500 nm, which means that the depth of the silicon hole is 200-500 nm.

[0022] In one implementation, P is performed after silicon vias are formed. ++ The final fabrication of the metal structure involves:

[0023] A photoresist is coated onto a silicon wafer, and a patterned window is exposed. Boron ions are then implanted at an energy of 30–60 keV and a dose of 3 × 10⁻⁶. 15 ~6×10 15 cm -2 The annealing conditions are: RTP temperature 800–900℃ and time 30–90 seconds;

[0024] After annealing P ++ The surface concentration at contact is 1×10 20 ~5×10 20 cm -3 This enables low-resistance ohmic contact between metal and silicon;

[0025] A photoresist is coated and patterned windows are exposed on a silicon wafer, and aluminum with a thickness of 3 to 6 μm is deposited. The photoresist is coated and patterned windows are exposed, and aluminum is etched to form gate and source metal electrodes. Metal TiNiAg is deposited on the back side of the silicon wafer, where the thickness of Ag is 1 to 2 μm.

[0026] In one embodiment, the thickness and doping concentration of the n-epitaxial layer are selected according to the voltage value designed for the device;

[0027] The n+ silicon substrate is low resistivity, with a doping concentration greater than 1.5 × 10⁻⁶. 19 cm -3 ,

[0028] The doping concentration distribution of the n-buffer layer is uniform, and the doping concentration at the bottom of the n-buffer layer is 1×10⁻⁶. 17 ~1×10 18 cm -3The doping concentration at the top of the n-buffer layer is 3 to 10 times that of the n-epitaxial layer, and the thickness of the n-buffer layer is 0.5 to 3 times that of the n-epitaxial layer.

[0029] In one embodiment, the silicon wafer includes an n+ silicon substrate, an n buffer layer, and an n- epitaxial layer stacked sequentially from bottom to top;

[0030] The n+ silicon substrate has low resistance, with a resistivity of 0.002–0.004 Ω·cm;

[0031] The resistivity of the n-epitaxial layer is 5–15 Ω·cm, and the thickness of the n-epitaxial layer is 20–60 μm;

[0032] The resistivity of the n-buffer layer increases proportionally from bottom to top. The resistivity of the bottom of the n-buffer layer is 0.05–0.15 Ω·cm, the resistivity of the top of the n-buffer layer is 0.5–1.5 Ω·cm, and the thickness of the n-buffer layer is 20–60 μm.

[0033] In the method for manufacturing a single-particle radiation-resistant VDMOS device based on polysilicide interconnects provided by the present invention, the polysilicide interconnect structure of the radiation-resistant VDMOS device is improved and optimized by using polysilicide (TiSi2) instead of polysilicide, reducing the width of the polysilicide interconnect line to 0.1 times that of the polysilicide interconnect line, thereby reducing the silicon surface voltage when a single particle passes through the device and realizing single-particle hardening of the VDMOS device. Attached Figure Description

[0034] Figure 1 It is P + A schematic diagram of the injection process;

[0035] Figure 2 This is a schematic diagram of the fabrication of polycrystalline and TiSi2 structures;

[0036] Figure 3 This is a schematic diagram of the fabrication of contact holes and silicon via structures;

[0037] Figure 4 It is the formation of P ++ A schematic diagram of the structure;

[0038] Figure 5 This is a schematic diagram of the fabrication of a metal structure. Detailed Implementation

[0039] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects, according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0040] This invention provides a method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects, comprising the following steps:

[0041] Step 1, Implement P + injection.

[0042] First, a silicon wafer material is provided, comprising, from bottom to top, an n+ silicon substrate, an n-buffer layer, and an n-epitaxial layer stacked together. The thickness and doping concentration of the n-epitaxial layer are selected according to the voltage value designed for the device; the n+ silicon substrate is low-resistivity and has a doping concentration greater than 1.5 × 10⁻⁶. 19 cm -3 The resistivity of the n-epitaxy layer is 0.002–0.004 Ω·cm; the resistivity of the n-epitaxy layer is 5–15 Ω·cm, and the thickness of the n-epitaxy layer is 20–60 μm; the doping concentration distribution of the n-buffer layer is preferably uniform, and the doping concentration at the bottom of the n-buffer layer (i.e., adjacent to the n+ substrate) is 1 × 10⁻⁶. 17 ~1×10 18 cm -3 The doping concentration at the top of the n-buffer layer (adjacent to the n-epitaxial layer) is 3 to 10 times that of the n-epitaxial layer, and the thickness of the n-buffer layer is 0.5 to 3 times that of the n-epitaxial layer. The resistivity of the n-buffer layer increases proportionally from bottom to top, with the resistivity at the bottom of the n-buffer layer (adjacent to the n+ substrate) being 0.05 to 0.15 Ω·cm, the resistivity at the top of the n-buffer layer (adjacent to the n-epitaxial layer) being 0.5 to 1.5 Ω·cm, and the thickness of the n-buffer layer being 20 to 60 μm.

[0043] A photoresist is coated onto a silicon wafer and a patterned window is exposed. Boron ions are implanted into the silicon at the polycrystalline interconnect locations to form P0. + Low resistance, injection energy of 50–100 keV, injection dose of 3 × 10⁻⁶ 15 ~6×10 15 cm -2 The conditions for bonding are 1100℃ for 60 minutes, such as... Figure 1 As shown, after the push-knot, P is formed. + The volume concentration of low-resistivity is 1×10 19 ~1×10 20 cm -3 P + The resistivity of low resistance is 1–10 mohm·cm.

[0044] Step 2: Fabricate polycrystalline and TiSi2 structures.

[0045] P +After implantation, a SiO2 layer with a thickness of 80–120 nm is grown by thermal oxidation to form gate oxide, followed by deposition of a polycrystalline layer with a thickness of 500–1000 nm. The phosphorus implantation dose is 3 × 10⁻⁶. 15 ~8×10 15 cm -2 Annealing at 850–900℃ for 30–60 minutes; depositing Ti with a thickness of 30–100 nm; RTP annealing at 800–900℃ for 30–90 seconds to form polycrystalline silicide TiSi2; coating with photoresist and exposing patterned windows on a silicon wafer; etching the polycrystalline silicide TiSi2 and polycrystalline materials, such as… Figure 2 As shown, the MOS gate and interconnects formed by polysilicides reduce the line width of the polysilicide interconnects to 1 / 10 of the line width of the polysilicide interconnects, thereby reducing the silicon surface voltage when a single particle passes through the device.

[0046] Step 3: Fabricate the contact holes and silicon via structures.

[0047] A layer of SiO2 with a thickness of 500–1000 nm is deposited, covering polycrystalline and polycrystalline silicides. A resist is coated on a silicon wafer, and patterned windows are exposed. SiO2 is etched, and after finding the Si / SiO2 endpoint, Si (i.e., the silicon substrate) is etched at regular intervals. The Si etching depth is 200–500 nm, meaning the depth of the silicon vias is 200–500 nm. Figure 3 As shown.

[0048] Step 4, forming P ++ structure.

[0049] After the silicon etching is completed, a photoresist is coated onto the silicon wafer and a patterned window is exposed. Boron ions are then implanted at an energy of 30–60 keV and an implantation dose of 3 × 10⁻⁶. 15 ~6×10 15 cm -2 The annealing conditions are: RTP temperature 800–900℃, time 30–90 seconds. After annealing, P… ++ The surface concentration at contact is 1×10 20 ~5×10 20 cm -3 , forming as Figure 4 P shown ++ The mask structure enables low-resistance ohmic contact between the metal and silicon.

[0050] Step 5: Construct the metal structure.

[0051] A photoresist is coated and patterned windows are exposed on a silicon wafer, and aluminum with a thickness of 3-6 μm is deposited. The photoresist is coated and patterned windows are exposed, and aluminum is etched to form gate and source metal electrodes. TiNiAg metal is deposited on the back of the silicon wafer as drain metal, where the thickness of Ag is 1-2 μm.

[0052] This invention improves and optimizes the polycrystalline interconnect structure of radiation-hardened VDMOS devices by using polysilicon (TiSi2) instead of polycrystalline. The sheet resistance of polysilicon is 0.1 times that of polycrystalline. By reducing the interconnect line width of polysilicon to 0.1 times that of polycrystalline interconnect, the silicon surface voltage is reduced, achieving single-event hardening of the VDMOS device. The single-event hardened VDMOS device provided by this invention can be used in the design and manufacture of power devices in electric propulsion systems and power supply systems in the aerospace field, achieving efficient power electronic conversion in radiation environments.

[0053] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects, characterized in that, include: Provide silicon wafer materials, through P + Injection to form P + Low resistance; In P + Low-resistivity surfaces are used to fabricate polycrystalline and polysilicides, reducing the interconnect width of polysilicides. Fabrication of contact holes and silicon via structures; P is performed after silicon pores are formed. ++ Injection, followed by fabrication of the metal structure; among which, In P + Fabrication of polycrystalline and polysilicide surfaces with low resistivity, and reduction of interconnect line width in polysilicides, include: P + After implantation, a gate oxide layer with a thickness of 80–120 nm is grown by thermal oxidation, followed by deposition of a polycrystalline layer with a thickness of 500–1000 nm. The phosphorus implantation dose is 3 × 10⁻⁶. 15 ~8×10 15 cm -2 Anneal at 850~900℃ for 30~60 minutes; Ti with a thickness of 30~100nm is deposited, and polycrystalline silicide TiSi2 is formed by RTP annealing at a temperature of 800~900℃ for 30~90 seconds. A patterned window is created by coating a silicon wafer with photoresist and exposing it. Polysilicide TiSi2 and polysilicon are then etched to form the MOS gate and interconnects of the polysilicide.

2. The method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects as described in claim 1, characterized in that, Provide silicon wafer materials, through P + Injection to form P + Low resistance includes: A photoresist is coated onto a silicon wafer and a patterned window is exposed. Boron ions are implanted into the silicon at the polycrystalline interconnect locations to form P0. + Low resistance, with an injection energy of 50~100keV and an injection dose of 3×10⁻⁶. 15 ~6×10 15 cm -2 The conditions for bonding are 1100℃ for 60 minutes; After pushing, P is formed. + The volume concentration of low-resistivity is 1×10 19 ~1×10 20 cm -3 P + The resistivity of low resistance is 1~10 mohm•cm.

3. The method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects as described in claim 2, characterized in that, Fabrication of contact holes and silicon via structures includes: SiO2 with a thickness of 500~1000nm is deposited, covering polycrystalline and polycrystalline silicides; A resist is coated onto a silicon wafer and a patterned window is exposed, followed by etching of SiO2. After finding the Si / SiO2 endpoint, Si is etched at regular intervals. The etching depth of Si is 200~500nm, which means that the depth of the silicon hole is 200~500nm.

4. The method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects as described in claim 3, characterized in that, P is performed after silicon pores are formed. ++ The final fabrication of the metal structure involves: A photoresist is coated onto a silicon wafer, and a patterned window is exposed. Boron ions are then implanted at an energy of 30–60 keV and a dose of 3 × 10⁻⁶ keV. 15 ~6×10 15 cm -2 The annealing conditions are: RTP temperature 800~900℃ and time 30~90 seconds; After annealing P ++ The surface concentration at contact is 1×10 20 ~5×10 20 cm -3 This enables low-resistance ohmic contact between metal and silicon; A photoresist is coated and patterned windows are exposed on a silicon wafer, and aluminum with a thickness of 3~6μm is deposited. The photoresist is coated and patterned windows are exposed to complete aluminum etching and form gate and source metal electrodes. Metal TiNiAg is deposited on the back side of the silicon wafer, where the thickness of Ag is 1~2μm.

5. The method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects as described in claim 1, characterized in that, The silicon wafer comprises, from bottom to top, an n+ silicon substrate, an n buffer layer, and an n- epitaxial layer, stacked sequentially; the thickness and doping concentration of the n- epitaxial layer are selected according to the voltage value designed for the device. The n+ silicon substrate is low resistivity, with a doping concentration greater than 1.5 × 10⁻⁶. 19 cm -3 , The doping concentration distribution of the n-buffer layer is uniform, and the doping concentration at the bottom of the n-buffer layer is 1×10⁻⁶. 17 ~1×10 18 cm -3 The doping concentration at the top of the n-buffer layer is 3 to 10 times that of the n-epitaxy layer, and the thickness of the n-buffer layer is 0.5 to 3 times that of the n-epitaxy layer.

6. The method for manufacturing a single-event radiation-resistant VDMOS device based on polysilicide interconnects as described in claim 5, characterized in that, The n+ silicon substrate is low-resistivity, with a resistivity of 0.002~0.004 Ω•cm; The resistivity of the n-epitaxial layer is 5~15Ω•cm, and the thickness of the n-epitaxial layer is 20~60μm; The resistivity of the n-buffer layer increases proportionally from bottom to top, with the resistivity at the bottom of the n-buffer layer being 0.05~0.15Ω•cm, the resistivity at the top of the n-buffer layer being 0.5~1.5Ω•cm, and the thickness of the n-buffer layer being 20~60μm.

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