Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a pass-through word line and a dielectric structure. The pass-through word line is in the substrate. The dielectric structure surrounds the pass-through word line, wherein the dielectric structure has an enlarged portion at a bottom of the dielectric structure, and a maximum width of the enlarged portion of the dielectric structure is wider than a width of a top of the dielectric structure. The dielectric structure with the enlarged portion at the bottom can reduce interference caused by the pass-through word line. Therefore, performance of the semiconductor device is also improved.

Description

Technical Field

[0001] Some embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Many types of semiconductor memory devices are widely used in consumer products. Exemplary examples of memory devices include dynamic random access memory (DRAM) and memory arrays. As semiconductor memory devices have evolved to the nanotechnology stage, the size of semiconductor memory devices and their components has also decreased. There is a need for improved contact structures that can be placed within memory arrays and used to connect active regions. Summary of the Invention

[0003] Some embodiments of the present invention provide a semiconductor device comprising a substrate, through-word lines, and a dielectric structure. The through-word lines are located in the substrate. The dielectric structure surrounds the through-word lines, wherein the dielectric structure has an enlarged portion at its bottom, and the maximum width of the enlarged portion is wider than the width of the top of the dielectric structure.

[0004] In some embodiments, the dielectric structure has sidewalls that are substantially perpendicular to the top of the dielectric structure, and the sidewalls extend outward at a height above the bottom of the word line, and the height is about 10 nanometers to about 20 nanometers above the bottom of the word line.

[0005] In some embodiments, the maximum width of the enlarged portion of the dielectric structure is about 1 nanometer to about 10 nanometers wider than the width of the top of the dielectric structure.

[0006] In some implementations, the bottom of the character line is flush with the maximum width of the enlarged portion.

[0007] In some implementations, the top of the dielectric structure becomes wider towards the bottom of the dielectric structure.

[0008] In some embodiments, the semiconductor device further includes active word lines and adjacent dielectric structures, wherein the active word lines are separated from the dielectric structures by a substrate.

[0009] In some implementations, the semiconductor device also includes a dielectric layer passing through the character lines.

[0010] Some embodiments of the present invention provide a method of manufacturing a semiconductor device, comprising forming a hard mask layer on a substrate. A first etching operation is performed through the hard mask layer to form a trench in the substrate. A sacrificial layer is formed at the bottom of the trench. A protective layer is formed along the sidewalls at the top of the trench. The sacrificial layer at the bottom of the trench is removed to expose the sidewalls at the bottom of the trench. A second etching operation is performed to widen the bottom of the trench. The hard mask layer and the protective layer along the sidewalls at the top of the trench are removed from the substrate. A dielectric structure is formed in the trench. And, word lines are formed in the dielectric structure.

[0011] In some embodiments, forming a protective layer along the sidewalls of the trench includes conformally forming a dielectric layer on the hard masking layer and the sacrificial layer and along the sidewalls at the top of the trench. Etching back the dielectric layer on the hard masking layer and the sacrificial layer leaves a dielectric layer along the sidewalls at the top of the trench, which then serves as a protective layer along the sidewalls at the top of the trench.

[0012] In some embodiments, the method further includes forming a photoresist layer on a hard mask layer, and exposing the protective layer and the sacrificial layer in the trench before removing the sacrificial layer at the bottom of the trench.

[0013] In some implementations, the trench is widened starting from the protective layer along the sidewalls of the trench.

[0014] In some embodiments, forming a sacrificial layer at the bottom of the trench involves depositing sacrificial material in the trench. Additionally, the sacrificial material is etched back to remove a portion of the sacrificial material at the top of the trench, resulting in a sacrificial layer formed at the bottom of the trench.

[0015] In some embodiments, the method further includes forming active word lines during the formation of word lines, the active word lines being adjacent to a dielectric structure, wherein the active word lines are separated from the dielectric structure by a substrate.

[0016] In some implementations, the second etching operation is a wet etching process.

[0017] In some implementations, the bottom of the trench is widened such that the maximum width of the bottom of the trench is about 1 nanometer to about 10 nanometers wider than the width of the top of the trench.

[0018] In some implementations, the method further includes forming a dielectric layer on the word line.

[0019] The dielectric structure with an amplification section at the bottom reduces interference caused by word lines. As a result, the performance of the semiconductor device is improved. Attached Figure Description

[0020] Figures 1 to 14 A cross-sectional view illustrating an intermediate stage of a process for forming a semiconductor device according to some embodiments of the present invention is shown.

[0021] Figure 15 A cross-sectional view illustrating an intermediate stage of a process for forming a semiconductor device according to some other embodiments of the present invention is shown. Detailed Implementation

[0022] Several embodiments of the present invention will be disclosed below with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be illustrated in the drawings in a simple schematic manner.

[0023] Some embodiments of the present invention relate to forming a dielectric structure surrounding a passing word line, this dielectric structure having an enlarged portion at the bottom of the dielectric structure. The dielectric structure with the enlarged portion at the bottom can reduce interference caused by the passing word line to adjacent active word lines. Therefore, the performance of the resulting semiconductor device can be improved.

[0024] Figures 1 to 14 A cross-sectional view illustrating an intermediate stage of a process for forming a semiconductor device according to some embodiments of the present invention is shown. (Reference) Figure 1 A substrate 102 is provided. The substrate 102 can be formed of any suitable material, such as a semiconductor material. In some embodiments, the substrate 102 is a silicon substrate. Alternatively, the substrate 102 may contain other elemental semiconductors, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; and / or alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, the substrate 102 is doped with dopants to form p-type active regions and / or n-type active regions in the substrate 102.

[0025] refer to Figure 2A hard mask layer 104 is formed on the substrate 102. The hard mask layer 104 serves to protect the underlying substrate 102 from damage by subsequent processes and is made of a different material than the substrate 102. The hard mask layer 104 can be made of any suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or similar materials. The hard mask layer 104 can be formed by any suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or similar methods.

[0026] refer to Figure 3 A first etching operation is performed using a hard mask layer 104 as a mask to form a trench T in the substrate 102. More specifically, a photoresist layer is first formed on the hard mask layer 104. The photoresist layer is patterned using a photolithography process to form a patterned photoresist layer, and then the hard mask layer 104 is patterned using the patterned photoresist layer to form a pattern in the hard mask layer 104. The pattern of the hard mask layer 104 is then transferred to the underlying substrate 102 by a first etching operation. The first etching operation is anisotropic etching, such that the substrate 102 is etched perpendicularly to form the trench T. In some embodiments, the first etching operation is a dry etching operation. After the trench T is formed in the substrate 102, the patterned photoresist layer can be removed by any suitable method, such as ashing or stripping. It should be noted that although... Figure 3 Only one groove T is drawn. The number of grooves T is not limited and can be two or more.

[0027] refer to Figure 4 Sacrificial material 106 is filled into the trench T. More specifically, sacrificial material 106 may first be deposited on the hard mask layer 104 and in the trench T. A planarization process is then performed to remove excess sacrificial material 106 on the hard mask layer 104. Thus, sacrificial material 106 fills the trench T. The sacrificial material 106 is a suitable dielectric material and is made of a different material than the hard mask layer 104. Therefore, the sacrificial material 106 has etch selectivity relative to the hard mask layer 104 and the substrate 102. In some embodiments, the sacrificial material 106 may comprise silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or the like. For example, the sacrificial material 106 may be an oxide, while the hard mask layer 104 may be a nitride, or vice versa.

[0028] refer to Figure 5 A sacrificial layer 108 is formed at the bottom of trench T. More specifically, etchback... Figure 4Sacrificial material 106 is removed from the top of trench T, leaving a sacrificial layer 108 formed at the bottom of trench T. Therefore, the upper part of trench T is exposed in substrate 102. The etch-back process is anisotropic etching to vertically remove the upper part of sacrificial material 106. Due to the etch selectivity between sacrificial material 106 and substrate 102 and hard masking layer 104, substrate 102 and hard masking layer 104 are not etched or are barely etched during the etch-back process. The height of sacrificial layer 108 defines the location of the enlarged portion of the dielectric structure formed in subsequent processes and will be... Figure 9 The discussion is ongoing.

[0029] refer to Figure 6 A dielectric layer 112 is conformally formed on the hard mask layer 104 and the sacrificial layer 108, and along the sidewalls of the top of the trench T. The top of the trench T refers to the portion of the trench T not covered by the sacrificial layer 108. The dielectric layer 112 can be made of any suitable dielectric material. In some embodiments, the dielectric layer 112 may comprise silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or the like, and the dielectric layer 112 and the hard mask layer 104 may comprise the same material. For example, both the dielectric layer 112 and the hard mask layer 104 are formed of nitride. The dielectric layer 112 can be formed by any suitable process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.

[0030] refer to Figure 7 A protective layer 114 is formed along the top sidewalls of the trench T. More specifically, the dielectric layer 112 on the hard mask layer 104 and the sacrificial layer 108 is etched back, such that the dielectric layer 112 left along the top sidewalls of the trench T becomes the protective layer 114 along the top sidewalls of the trench T. In some embodiments, the etch-back process of the dielectric layer 112 is an anisotropic process, so the dielectric layer 112 along the top sidewalls of the trench T is not etched. After the protective layer 114 along the top sidewalls of the trench T is formed, the top surface of the sacrificial layer 108 is exposed.

[0031] refer to Figure 8 Remove the sacrificial layer 108 at the bottom of trench T (see...) Figure 7The photoresist layer 116 is formed on the hard mask layer 104 to expose the protective layer 114 and the sacrificial layer 108 in the trench T before the sacrificial layer 108 at the bottom of the trench T is removed. In some embodiments, the opening of the photoresist layer 116 is wider than the width of the trench T, so the photoresist layer 116 also exposes a portion of the hard mask layer 104. The sacrificial layer 108 at the bottom of the trench T is then removed by a combination of dry and wet etching. More specifically, dry etching is first used to vertically remove the portion of the sacrificial layer 108 directly exposed in the trench T, where this portion of the sacrificial layer 108 is not covered by the protective layer 114. Wet etching is then performed to remove the remaining sacrificial layer 108, such as the sacrificial layer 108 under the protective layer 114. In some embodiments, a solvent, such as hydrofluoric acid, is used in the wet etching.

[0032] refer to Figure 9 A second etching operation is performed to widen the bottom of the trench T. More specifically, after the sacrificial layer 108 is removed, the protective layer 114 still covers the top sidewalls of the trench T. The second etching operation is a wet isotropic etching, and the substrate 102 can be etched but the protective layer 114 cannot. Therefore, the substrate 102 exposed in the trench T is etched to widen the trench T from the protective layer 114 along the sidewalls of the trench T. Thus, the width of the trench T is increased laterally, and the bottom of the trench T becomes relatively rounded. In some embodiments, an etchant such as an ammonia peroxide mixture (APM) is used in the second etching operation.

[0033] refer to Figure 10 After widening the bottom of the trench T, the photoresist layer 116 is removed. In some embodiments, the photoresist layer 116 is removed by stripping, such as oxygen ashing.

[0034] refer to Figure 11 The hard mask layer 104 and the protective layer 114 along the sidewalls of the trench T are removed from the substrate 102. In some embodiments, the hard mask layer 104 and the protective layer 114 are made of similar or identical materials, so the hard mask layer 104 and the protective layer 114 can be removed in the same process. In some embodiments, the hard mask layer 104 and the protective layer 114 can be removed by hot phosphoric acid. Because the protective layer 114 prevents the top of the trench T from being etched, after the protective layer 114 is removed, the top of the sidewalls of the trench T remains substantially perpendicular to the top surface of the substrate 102.

[0035] refer to Figure 12A dielectric structure 118 is formed in the trench T. More specifically, a dielectric material layer may be formed on the substrate 102 and in the trench T. A planarization process is then performed to remove excess dielectric material layer on the substrate 102 to form the dielectric structure 118 in the trench T. The dielectric structure 118 may be made of any suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or similar. The dielectric structure 118 includes an enlarged portion 118E at the bottom of the trench T. The enlarged portion 118E has a maximum width MW that is wider than the width W at the top of the dielectric structure 118. The enlarged portion 118E of the dielectric structure 118 is used to eliminate interference caused by subsequently formed through character lines.

[0036] refer to Figure 13 Through word lines 122 are formed in dielectric structure 118. More specifically, trenches are first formed in dielectric structure 118. The bottom of the trenches is in the enlarged portion 118E of dielectric structure 118. Gate oxide layer 119 may be formed along the sidewalls of the trenches in dielectric structure 118. Then, conductive material, such as metal, is filled into the trenches in dielectric structure 118 to form through word lines 122. During the formation of through word lines 122, active word lines 124 adjacent to dielectric structure 118 are simultaneously formed in substrate 102. For example, when trenches are formed in dielectric structure 118, some trenches are formed in substrate 102. Gate oxide layer 119 may be formed along the sidewalls of the trenches in substrate 102, and then conductive material is filled into the trenches in substrate 102 to form active word lines 124. Active word lines 124 are separated from dielectric structure 118 by substrate 102. The amplification portion 118E of the dielectric structure 118 can reduce the electric field caused by the word line 122, thereby eliminating the influence on the adjacent active word line 124. This can improve the performance of the resulting semiconductor device.

[0037] refer to Figure 14 A dielectric layer 126 is formed on the character line 122 and the active character line 124. In some embodiments, the dielectric layer 126 is made of silicon nitride or other suitable dielectric material. In some embodiments, the dielectric layer 126 is formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable processes.

[0038] In some embodiments, the method of forming dielectric layer 126 may include performing an etch-back process to remove the tops of through-word lines 122 and active word lines 124, forming dielectric material to cover the etched through-word lines 122 and etched active word lines 124, and performing a planarization process, such as chemical mechanical planarization (CMP), to remove excess dielectric material outside the trench, thereby forming dielectric layers 126 on the etched through-word lines 122 and etched active word lines 124, respectively.

[0039] The resulting semiconductor device is illustrated in Figure 14 The semiconductor device includes a substrate 102, through word lines 122 in the substrate 102, and a dielectric structure 118 surrounding the through word lines 122. The dielectric structure 118 has an enlarged portion 118E at its bottom, and the maximum width MW of the enlarged portion 118E is wider than the width W of the top of the dielectric structure 118. In some embodiments, the maximum width MW of the enlarged portion 118E is about 1 nanometer to about 10 nanometers wider than the width W of the top of the dielectric structure 118. If the maximum width MW exceeds the range of the invention, the enlarged portion 118E of the dielectric structure 118 may not effectively reduce the electric field caused by the through word lines 122, or the dielectric structure 118 may contact the active word lines 124 and negatively affect the active word lines 124.

[0040] The dielectric structure 118 has a sidewall substantially perpendicular to the top of the dielectric structure 118, and the sidewall extends outward at a height H above the bottom of the through-word line 122, with the height H being approximately 10 nanometers to approximately 20 nanometers above the bottom of the through-word line 122. If the height H is less than approximately 10 nanometers, the amplified portion 118E of the dielectric structure 118 may not effectively reduce the electric field caused by the through-word line 122. If the height H is greater than approximately 20 nanometers, the size of the active region between the active word line 124 and the dielectric structure 118 may be reduced. In some other embodiments, the bottom of the through-word line 122 is flush with the maximum width MW of the amplified portion 118E. In this way, the electric field caused by the through-word line 122 can be reduced, thereby eliminating the interference of the through-word line 122 on the adjacent active word line 124.

[0041] The semiconductor device also includes an active word line 124 adjacent to the dielectric structure 118. The active word line 124 is separated from the dielectric structure 118 by a substrate 102. The semiconductor device also includes a dielectric layer 126 passing through the word line 122 and the active word line 124.

[0042] Figure 15A cross-sectional view illustrating an intermediate stage of a process for forming a semiconductor device according to some other embodiments of the present invention is shown. Figure 15 Semiconductor devices in the middle are similar to Figure 14 Semiconductor devices in the process. Figure 15 Zhongyu Figure 14 The difference in the semiconductor device lies in the shape of the dielectric structure 118. Figure 14 In the middle, the sidewall at the top of the dielectric structure 118 is substantially perpendicular to the top of the dielectric structure 118. On the other hand, in Figure 15 In the dielectric structure 118, the top of the dielectric structure 118 becomes wider towards the bottom of the dielectric structure 118. When the dielectric structure 118 reaches its maximum width, the dielectric structure 118 becomes narrower towards the bottom of the dielectric structure 118.

[0043] In some implementations, the process is achieved through a two-stage etching operation. Figure 15 In semiconductor devices. For example, anisotropic etching is performed first, followed by isotropic etching to form... Figure 15 The shape of the dielectric structure 118 in the middle. In some other embodiments, in the hard mask layer 104 (reference 118) Figure 3 A patterned photoresist layer is formed on the hard mask layer 104, and the patterned photoresist layer has an undercut-shaped opening. That is, the opening of the patterned photoresist layer becomes wider as it gets closer to the hard mask layer 104. When the patterned photoresist layer with the undercut-shaped opening is used to perform the first etching operation, Figure 3 The trench T in the middle can be shaped to have a bottom with a relatively large width. The resulting dielectric structure 118 can be formed to have, for example, a bottom with a wide bottom. Figure 15 The shape shown.

[0044] As described above, some embodiments of the present invention offer several advantages. For example, a dielectric structure with an amplified portion at the bottom can reduce the high electric field caused by the word lines. Therefore, the electric field can be reduced without affecting or only slightly affecting the active word lines of adjacent dielectric structures. The performance of the semiconductor device is also improved as a result.

[0045] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

[0046] [Symbol Explanation]

[0047] 102: Substrate

[0048] 104: Hard mask layer

[0049] 106: Sacrificial Materials

[0050] 108: Sacrificial Layer

[0051] 112: Dielectric layer

[0052] 114: Protective layer

[0053] 116: Photoresist layer

[0054] 118: Dielectric Structure

[0055] 118E: Enlarged section

[0056] 119: Gate oxide layer

[0057] 122: Through character lines

[0058] 124: Active character line

[0059] 126: Dielectric layer

[0060] H: Height

[0061] MW: Maximum Width

[0062] T: Trench

[0063] W: Width.

Claims

1. A semiconductor device, characterized in that, Include: substrate; Through the character lines, in this substrate; A dielectric structure surrounding the through character line, wherein the dielectric structure has an enlarged portion at the bottom of the dielectric structure, and the maximum width of the enlarged portion of the dielectric structure is wider than the width of the top of the dielectric structure, wherein the enlarged portion includes an upper portion and a lower portion, the upper portion and the lower portion intersect at the maximum width, the width of the upper portion of the enlarged portion gradually increases downward to the maximum width, the width of the lower portion of the enlarged portion gradually decreases downward, and the bottom of the through character line is flush with the maximum width of the enlarged portion.

2. The semiconductor device according to claim 1, characterized in that, The dielectric structure has a sidewall that is substantially perpendicular to the top of the dielectric structure, and the sidewall extends outward at a height above the bottom of the through character line, and the height is about 10 nanometers to about 20 nanometers above the bottom of the through character line.

3. The semiconductor device according to claim 1, characterized in that, The maximum width of the enlarged portion of the dielectric structure is about 1 nanometer to about 10 nanometers wider than the width of the top of the dielectric structure.

4. The semiconductor device according to claim 1, characterized in that, The top of the dielectric structure becomes wider towards the bottom of the dielectric structure.

5. The semiconductor device according to claim 1, characterized in that, It also includes active word lines adjacent to the dielectric structure, wherein the active word lines are separated from the dielectric structure by the substrate.

6. The semiconductor device according to claim 1, characterized in that, It also includes a dielectric layer on the character lines.

7. A method for manufacturing a semiconductor device, characterized in that, Include: A hard masking layer is formed on the substrate; The first etching operation is performed through the hard mask layer to form trenches in the substrate; A sacrificial layer is formed at the bottom of the trench; A protective layer is formed along the sidewalls at the top of the trench; Remove the sacrificial layer at the bottom of the trench to expose the sidewalls at the bottom of the trench; Perform a second etching operation to widen the bottom of the trench; Remove the hard masking layer on the substrate and the protective layer along the sidewall of the top of the trench; A dielectric structure is formed in the trench, the dielectric structure having an enlarged portion at the bottom of the dielectric structure, and the maximum width of the enlarged portion is wider than the width of the top of the dielectric structure, wherein the enlarged portion includes an upper portion and a lower portion, the upper portion and the lower portion meeting at the maximum width, the width of the upper portion of the enlarged portion gradually increasing downwards to the maximum width, and the width of the lower portion of the enlarged portion gradually decreasing downwards; and A through-word line is formed in the dielectric structure, and the bottom of the through-word line is flush with the maximum width of the amplified portion.

8. The method according to claim 7, characterized in that, The protective layer forming along the sidewall of the trench comprises: A dielectric layer is conformally formed on the hard mask layer and the sacrificial layer, and on the sidewall of the top of the trench; The dielectric layer on the hard shielding layer and the sacrificial layer is etched back, such that the dielectric layer left along the sidewall of the top of the trench becomes the protective layer along the sidewall of the top of the trench.

9. The method according to claim 7, characterized in that, Also includes: A photoresist layer is formed on the hard mask layer, and the photoresist layer exposes the protective layer and the sacrificial layer in the trench before the sacrificial layer at the bottom of the trench is removed.

10. The method according to claim 7, characterized in that, The trench is widened starting from the protective layer along the sidewall of the trench.

11. The method according to claim 7, characterized in that, The sacrificial layer formed at the bottom of the trench includes: Deposit sacrificial material in the trench; as well as The sacrificial material is etched back to remove a portion of the sacrificial material at the top of the trench, so that the sacrificial layer is formed at the bottom of the trench.

12. The method according to claim 7, characterized in that, It also includes forming an active character line during the formation of the through character line, the active character line being adjacent to the dielectric structure, wherein the active character line is separated from the dielectric structure by the substrate.

13. The method according to claim 7, characterized in that, The second etching operation is a wet etching process.

14. The method according to claim 7, characterized in that, The bottom of the trench is widened such that the maximum width of the bottom of the trench is about 1 nanometer to about 10 nanometers wider than the width of the top of the trench.

15. The method according to claim 7, characterized in that, It also includes forming a dielectric layer on the through-word line.

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