A successive approximation analog-to-digital converter and a control method thereof

Abstract

The application discloses a successive approximation type analog-digital converter and a control method thereof, relates to the technical field of analog-digital conversion, and comprises a dynamic comparison unit, a capacitor array synchronizer, an output register and a logic unit, wherein the dynamic comparison unit comprises a dynamic comparator and an array capacitor circuit, the positive and negative terminals of the dynamic comparator are connected with one array capacitor circuit respectively, the output terminal of the dynamic comparator is connected with the logic unit, the output of the logic unit is connected with the output register, the array capacitor circuit and the capacitor array synchronizer, and the capacitor array synchronizer is connected with the dynamic comparator. In view of the technical problem of slow conversion speed of the existing high-speed asynchronous SAR ADC circuit, the application reduces the time waste of the array dac in the traditional scheme, greatly reduces the conversion time, and thus improves the high-speed characteristics of the asynchronous SAR ADC.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital conversion, in particular to a successive approximation analog-to-digital converter and a control method thereof. BACKGROUND

[0002] Currently, in a traditional high-speed asynchronous SAR ADC circuit, a dynamic comparator and a logic module are main working elements. When a sample is high, a sampling switch is opened to start sampling. When the sample is low, data conversion of the SAR ADC is started, and work of an asynchronous clock compclk is started, as shown in the following formula. Figure 1

[0003] Data conversion process:

[0004] 1. When compclk is high, the comparator works. After a delay tc of the comparator, a comparison result is output and transmitted to the SAR logic.

[0005] 2. The SAR logic obtains the result of the comparator. First, B9 and B9P / N are latched and output to control the switch S9P / N of the array DAC to realize setting of C9. Meanwhile, an rd signal is output to pull down compclk of the comparator, reset the comparator, and wait for establishment of the array DAC capacitor.

[0006] 3. After compclk is pulled down, a delay composed of an inverter is started. After a delay of the delay, compclk is pulled up. During this period, setting and establishment of the capacitor array need to be completed, that is, the delay time is greater than or equal to tsarlogic+tcdac9. Then, delay of the 8th bit is started. Similarly, delay of the last bit is started. B9B8…B0 output by the SAR logic is transmitted to the CPU. After coding and decoding processing of the CPU, final output D9, D8, …, D0 of the ADC is obtained. Wherein tc is a setting delay of the comparator, tsarlogic is a delay of the SAR logic, and tcdac is a delay of establishment time of the capacitor in the left capacitor group. Wherein C9=2^8c, …, C1=2^0c, and C0=2^0c.

[0007] ​In the prior art, the delay of tcdac depends on the largest capacitor C9 in the DAC array, so the settling time of the polarity from vref to gnd for C9 is Tcdac, and the data conversion for other smaller capacitors is also converted according to the time of Tcdac, resulting in a waste of time, because the smaller the capacitor, the shorter the settling time. For a 10-bit setting, the total data conversion time Tdata = 10tc + 10tsarlogic + 10tcdac; at the same time, due to the influence of process and temperature, the delay clock delay composed of inverters must be slightly larger than the sum of the sar logic delay and the C9 settling time, so as to ensure the accuracy, but also further reduce the conversion speed of the saradc. Finally, Tdata = 10tc + 10tl9, wherein tl9 > 1.2 * (tsarlogic + tcdac9), which is the delay clock delay composed of inverters. SUMMARY

[0008] In view of the technical problem of slow conversion speed of the prior art high-speed asynchronous SAR ADC circuit, the application provides a successive approximation analog-to-digital converter and a control method thereof, which reduces the time waste of the array dac in the traditional scheme, greatly reduces the conversion time, and thus improves the high-speed characteristics of the asynchronous saradc.

[0009] To solve the above problems, the technical scheme provided by the application is as follows:

[0010] A successive approximation analog-to-digital converter comprises a dynamic comparison unit, a capacitor array synchronizer, an output register and a logic unit, the dynamic comparison unit comprises a dynamic comparator and an array capacitor circuit, the positive and negative terminals of the dynamic comparator are connected with an array capacitor circuit respectively, the output terminal of the dynamic comparator is connected with the logic unit, the output of the logic unit is connected with the output register, the array capacitor circuit and the capacitor array synchronizer, and the capacitor array synchronizer is connected with the dynamic comparator.

[0011] Optionally, the capacitor array synchronizer comprises capacitors c9', c8', …, c1' and c0', one end of each of the capacitors c9', c8', …, c1' and c0' is grounded, the other end of each of the capacitors c9', c8', …, c1' and c0' is connected with the first wiring terminal of a double-setting switch, the second wiring terminal of the double-setting switch is grounded, the third wiring terminal of the double-setting switch is connected with a reference voltage vref, the other end of each of the capacitors c9', c8', …, c1' and c0' is connected with an inverter, the output of the inverter is connected with a clock logic unit, the clock logic unit outputs a compclk signal to the dynamic comparator, and the output rd of the logic unit is connected with the clock logic unit.

[0012] Optionally, the outputs B9P, B8P, B7P, B6P, B5P, B4P, B3P, B2P, B1P, B0P of the logic unit are connected to mux logic units, and the outputs E9-E0 of the mux logic units control the other ends of the capacitors c9', c8', c7', c6', c5', c4', c3', c2', c1', c0' respectively.

[0013] Optionally, the inverters are connected to ground and reference voltage vref respectively.

[0014] Optionally, the input terminal VIP is connected to one end of bootstrap switch one, and the other end of the bootstrap switch one is connected to one end of the capacitors c9, c8, c7, c6, c5, c4, c3, c2, c1, c0 and the positive terminal of the dynamic comparator, and the other ends of the capacitors c9, c8, c7, c6, c5, c4, c3, c2, c1, c0 are connected to the first terminals of the switches S9P, S8P, S7P, S6P, S5P, S4P, S3P, S2P, S1P, S0P respectively, the second terminals of the switches S9P, S8P, S7P, S6P, S5P, S4P, S3P, S2P, S1P, S0P are connected to ground, and the third terminals of the switches S9P, S8P, S7P, S6P, S5P, S4P, S3P, S2P, S1P, S0P are connected to reference voltage vref.

[0015] Optionally, the input terminal VIN is connected to one end of bootstrap switch two, and the other end of the bootstrap switch two is connected to one end of the capacitors c9, c8, c7, c6, c5, c4, c3, c2, c1, c0 and the negative terminal of the dynamic comparator, and the other ends of the capacitors c9, c8, c7, c6, c5, c4, c3, c2, c1, c0 are connected to the first terminals of the switches S9N, S8N, S7N, S6N, S5N, S4N, S3N, S2N, S1N, S0N respectively, the second terminals of the switches S9N, S8N, S7N, S6N, S5N, S4N, S3N, S2N, S1N, S0N are connected to ground, and the third terminals of the switches S9N, S8N, S7N, S6N, S5N, S4N, S3N, S2N, S1N, S0N are connected to reference voltage vref.

[0016] Optionally, the outputs B9P-B0P of the logic unit control the switches S9P, S8P, S7P, S6P, S5P, S4P, S3P, S2P, S1P, S0P respectively.

[0017] Optionally, the outputs B9N-B0N of the logic unit control the switches S9N, S8N, S7N, S6N, S5N, S4N, S3N, S2N, S1N, S0N respectively.

[0018] A control method of a successive approximation type analog-digital converter, comprising: S101. When a sampling signal sample is high, a bootstrap switch one and a bootstrap switch two are closed, a capacitor c9 samples, the sampling signal sample becomes low, the bootstrap switch one and the bootstrap switch two are disconnected, and the signal sampled by the capacitor c9 is kept and data conversion is performed; S102. A capacitor array synchronizer output signal compclk changes from low to high, a dynamic comparator starts comparing the signals sampled by capacitors c9, c8, c0, a comparison result of the dynamic comparator is outputted after tc, and the result is transmitted to a logic unit; S103. The logic unit latches the comparison result and outputs signals B9P, B9N, B9, and rd; wherein B9P and B9N control S9P and S9N, which are used for setting C9, B9 is outputted to a CPU as the highest bit of ADC decoding, and B9P and B9N and rd enter the capacitor array synchronizer; S104. The discrimination signal rd of the dynamic comparator pulls down compclk, the dynamic comparator is reset, B9P and B9N pass through the capacitor array synchronizer and control capacitors C9' and C9 to be set synchronously, an inverter is used as a voltage detector to detect the port voltage of the capacitor C9', when one end of the capacitor C9' drops to the flip voltage of the inverter, the dynamic comparator flips the output clock control signal and controls compclk to change from low to high, after the c9 capacitor settling time tcdac9, the dynamic comparator starts the data conversion operation of the next bit, and steps S101-S104 are repeated to circulate until the last bit is compared.

[0019] The successive approximation type analog-digital converter and the control method thereof provided by the embodiment of the application have the following beneficial effects: 1) the time waste of the array dac in the traditional scheme is reduced, the settling time of each bit of the array dac is reasonably utilized, and the settling time is not wasted at all, so that the conversion time is greatly reduced, and the high-speed characteristic of the asynchronous saradc is improved; 2) the settling time of each bit is stably settled, so that the voltage is stable, the effective number of bits is increased, and the precision reduction and inaccuracy of the ADC conversion data caused by comparison before the settling is completed are avoided; and then the precision reduction of the ADC caused by the dac is reduced; 3) compared with other modes, the embodiment reduces the chip design area and has low cost; and 4) compared with other modes, the embodiment reduces power consumption and does not increase power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is a structure schematic diagram of an existing successive approximation type analog-digital converter.

[0021] Figure 2 It is a structure schematic diagram of the successive approximation type analog-digital converter provided by the embodiment of the application.

[0022] Figure 3A clock signal diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application.

[0023] Figure 4 A capacitor array synchronizer structure diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] For further understanding of the present application, the application will be described in detail with reference to the drawings and embodiments.

[0025] The application will be described in further detail with reference to the drawings and embodiments. It is understood that the specific embodiments described herein are intended to be illustrative only and not limiting of the application. Additionally, it is understood that the drawings are not necessarily to scale and that the specific embodiments described herein are presented for the purpose of clarity and description, and are not intended to limit the scope of the application. It is further understood that the specific embodiments described herein are not intended to limit the scope of the application, which is defined by the appended claims. It is further understood that the embodiments and features described herein can be combined with one another, unless specifically noted otherwise. In the description of the application, it is to be understood that the terminology used is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless specifically defined herein, all technical and scientific terms used have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It will be further understood that the boundaries of the claimed subject matter designated by the

[0026] Example 1

[0027] In conjunction with the Figures 2-4The embodiment provides a successive approximation type analog-digital converter, comprising a dynamic comparison unit, a capacitor array synchronizer, an output register and a logic unit, the dynamic comparison unit comprises a dynamic comparator and an array capacitor circuit, the positive and negative terminals of the dynamic comparator are connected with one array capacitor circuit respectively, the output terminal of the dynamic comparison unit is connected with the logic unit, the output of the logic unit is connected with the output register, the array capacitor circuit and the capacitor array synchronizer, and the capacitor array synchronizer is connected with the dynamic comparator.

[0028] The capacitor array synchronizer comprises capacitors c9', c8', c7', c6', c5', c4', c3', c2', c1' and c0', one end of each of the capacitors c9', c8', c7', c6', c5', c4', c3', c2', c1' and c0' is grounded, the other end of each of the capacitors c9', c8', c7', c6', c5', c4', c3', c2', c1' and c0' is connected with the first wiring terminal of a double-position switch, the second wiring terminal of the double-position switch is grounded, the third wiring terminal of the double-position switch is connected with a reference voltage vref, and the other end of each of the capacitors c9', c8', c7', c6', c5', c4', c3', c2', c1' and c0' is connected with an inverter. Figure 4 The output of the inverter (that is, the comparator in the inv) is connected with a clock logic unit, the clock logic unit outputs a compclk signal to the dynamic comparator, and the output rd of the logic unit is connected with the clock logic unit.

[0029] The outputs B9P, B8P, B7P, B6P, B5P, B4P, B3P, B2P and B0P of the logic unit are connected with a mux logic unit, the outputs E9-E0 of the mux logic unit control the double-position switches connected with the other ends of the capacitors c9', c8', c7', c6', c5', c4', c3', c2' and c0' respectively, and the inverter is grounded and connected with the reference voltage vref.

[0030] The input wiring terminal VIP is connected with one end of a bootstrap switch, the other end of the bootstrap switch is connected with the other ends of capacitors c9, c8, c7, c6, c5, c4, c3, c2 and c0 and the positive terminal of the dynamic comparator, the other ends of the capacitors c9, c8, c7, c6, c5, c4, c3, c2 and c0 are connected with the first wiring terminals of switches S9P, S8P, S7P, S6P, S5P, S4P, S3P, S2P and S0P respectively, the second wiring terminals of the switches S9P, S8P, S7P, S6P, S5P, S4P, S3P, S2P and S0P are grounded, and the third wiring terminals of the switches S9P, S8P, S7P, S6P, S5P, S4P, S3P, S2P and S0P are connected with the reference voltage vref.

[0031] The input terminal VIN is connected to one end of a bootstrap switch two, the other end of the bootstrap switch two is connected to one end of a capacitor c9, c8, c0 and a negative terminal of a dynamic comparator, the other end of the capacitor c9, c8, c0 is respectively connected to a first terminal of a switch S9N, S8N, S0N, the second terminal of the switch S9N, S8N, S0N is grounded, and the third terminal of the switch S9N, S8N, S0N is connected to a reference voltage vref. The output B9N-B0N of the logic unit controls the switch S9N, S8N, S0N respectively. The values of the capacitors c9', c8', c1', c0' are half of the values of the capacitors c9, c8, c0 respectively.

[0032] Embodiment 2

[0033] The embodiment provides a control method of a successive approximation type analog-to-digital converter, comprising the following steps:

[0034] In step S101, the sampling signal sample is high, the bootstrap switch one and the bootstrap switch two are closed, the capacitor c9 samples, the sampling signal sample becomes low, the bootstrap switch one and the bootstrap switch two are disconnected, the signal sampled by the capacitor c9 is kept and data conversion is performed.

[0035] In step S102, the output signal compclk of the capacitor array synchronizer changes from low to high, the dynamic comparator starts to compare the signals sampled by the capacitors c9, c8, c0, the comparison result is output by the dynamic comparator after tc, and the result is transmitted to the logic unit.

[0036] In step S103, the logic unit latches the comparison result and outputs the signals B9P, B9N, B9, rd, wherein B9P and B9N control S9P and S9N, which are used for setting C9, B9 is output to a CPU as the highest bit of ADC decoding, and B9P, B9N and rd enter the capacitor array synchronizer.

[0037] In step S104, the discrimination signal rd of the dynamic comparator pulls compclk low, the dynamic comparator is reset, B9P and B9N pass through the capacitor array synchronizer and control the capacitors C9' and C9 to be set synchronously, the inverter is used as a voltage detector to detect the port voltage of the capacitor C9', when the one end of the capacitor C9' drops to the flip voltage of the inverter, the dynamic comparator flips the output clock control signal and controls compclk to change from low to high, after the capacitor c9 of tcdac9 establishes time, the dynamic comparator starts the data conversion operation of the next bit, and steps S101-S104 are repeated until the last bit is compared.

[0038] Embodiment 3

[0039] The accompanying drawings are incorporated into the present application Figures 2-4The successive approximation analog-to-digital converter of the embodiment is similar to the technical solution of the embodiment 1,

[0040] When the circuit starts to work, the sample signal is high, the bootstrap switches of the VIP and the VIN are closed, the sampling capacitor samples, then the sample signal becomes low, the bootstrap switches are opened, the sampled signal is kept and data conversion is performed:

[0041] 1. The compclk signal changes from low to high, the comparator comp starts to compare the sampled signal, after a tc delay, the comparator outputs the comparison result and transmits the result to the sarlogic.

[0042] 2. The sarlogic latches the comparison result and outputs the signals B9P, B9N, B9 and rd. Among them, B9P and B9N control S9P and S9N, which are used to set C9, B9 is output to the CPU as the highest bit of ADC decoding, and B9P and B9N and rd enter the CDAC synchronizer.

[0043] 3. The discrimination signal rd of the comparator pulls down the compclk, the comparator is reset, and B9P and B9N control the capacitors C9' and C9 to be set synchronously through the synchronizer. The inverter is used as a voltage detector to detect the voltage at the port of the capacitor. When one end of the capacitor C9' drops to the flip-flop voltage of the inverter, it indicates that C9' is stably established. The comparator flips the clock control signal and controls the compclk to change from low to high. Since C9 and C9' are synchronously opened, when C9' is stably established, C9 is also stably established. After the c9 capacitor establishment time of tcdac9, the comparator starts the data operation of the next bit, and the cycle continues until the last bit is compared. The technical effects brought by the work of the CDAC synchronizer are: 1) The establishment time of each bit of the array dac is reasonably utilized and is not wasted, thereby greatly improving the data conversion speed. 2) The establishment time of each bit is stably established, thereby the voltage is stable, the effective number of bits is increased, and the precision reduction and inaccuracy of ADC conversion data caused by comparison before stable establishment are avoided; and the precision reduction of ADC caused by DAC is further reduced. 3) Compared with other ways, the chip design area is reduced, and the cost is low. 4) Compared with other ways, the power consumption is reduced, and the power consumption is not increased.

[0044] Finally, the data conversion time after comparing 10 bits is shortened to:

[0045] Tdata new = 10tc+tl9+tl8+…+tl0, wherein tl9=tsarlogic+tcdac9, tl8=tsarlogic+tcdac8, tl0=tsarlogic+tcdac0.

[0046] C9', C8'...C0' are respectively 1 / 2 of C9, C8,...C0, due to the halving of the capacitance, in order to ensure the array capacitance setup time of the synchronizer is equal to C9, C8...C0, the voltage value of the capacitance switching also needs to be halved, so that the voltage detection unit in the synchronizer can be realized by an inverter, when C9' C8'...C0' are respectively established to 1 / 2vref, the inverter flips, as a capacitance establishment stable discrimination signal, thereby pulling up compclk, so that the comp comparator starts to work. Since the inverter is used to realize the voltage detection, the voltage detection speed is also greatly improved.

[0047] The array capacitance setup time of the traditional asynchronous SAR ADC circuit depends on the setup time of the highest bit capacitance, since the highest bit capacitance value is the largest, the setup time is the longest, and the setup time of each bit array is determined according to the setup time of the highest bit capacitance, which will cause a lot of time waste, at the same time, considering the influence of temperature process, the delay of the clock must be slightly higher than 20% of the sum of the delay of the SAR logic and the setup time of the highest bit capacitance, which greatly reduces the conversion rate. Our design makes the delay of the clock completely according to the setup time of each bit capacitance, without using the inverter delay as the clock delay scheme as in the traditional scheme, which can also greatly reduce the influence of process temperature and speed up the conversion rate and ensure the precision. The circuit of the embodiment adds a capacitance array synchronizer to replace the traditional inv group clock delay, realizes the improvement of the conversion rate, and the circuit logic is simple and easy to realize.

[0048] The above describes the present application and its embodiments in a schematic manner, which is not restrictive, and the embodiments shown in the drawings are only one of the embodiments of the present application, and the actual structure is not limited thereto. Therefore, if a person skilled in the art is inspired thereby, without departing from the purpose of the present application, similar structural modes and embodiments can be designed without creativity, which shall belong to the protection scope of the present application.

Claims

1. A successive approximation analog-to-digital converter, characterized by, The dynamic comparison unit includes a dynamic comparator and an array capacitor circuit, the positive and negative terminals of the dynamic comparator are connected with an array capacitor circuit respectively, the output terminal of the dynamic comparison unit is connected with a logic unit, the output of the logic unit is connected with an output register, an array capacitor circuit and a capacitor array synchronizer, and the capacitor array synchronizer is connected with the dynamic comparator; The capacitor array synchronizer includes capacitors c9', c8',..., c1', and c0', one end of each of the capacitors c9', c8',..., c1', and c0' is grounded, the other end of each of the capacitors c9', c8',..., c1', and c0' is connected with the first terminal of a double-position switch, the second terminal of the double-position switch is grounded, the third terminal of the double-position switch is connected with a reference voltage vref, and the other end of each of the capacitors c9', c8',..., c1', and c0' is connected with an inverter, the output of the inverter is connected with a clock logic unit, the clock logic unit outputs a compclk signal to the dynamic comparator, and the output rd of the logic unit is connected with the clock logic unit. The outputs B9P,..., and B0P of the logic unit are connected with a mux logic unit, the outputs E9-E0 of the mux logic unit control the double-position switches connected with the other end of each of the capacitors c9', c8',..., c1', and c0' respectively. The inverters are grounded and connected with the reference voltage vref.

2. A successive approximation type analog-digital converter according to claim 1, characterized in that The input terminal VIP is connected with one end of a bootstrap switch, the other end of the bootstrap switch is connected with one end of capacitors c9,..., and c0, and the positive terminal of the dynamic comparator, the other end of each of the capacitors c9,..., and c0 is connected with the first terminal of a switch S9P,..., and S0P, the second terminal of each of the switches S9P,..., and S0P is grounded, and the third terminal of each of the switches S9P,..., and S0P is connected with the reference voltage vref.

3. A successive approximation type analog-digital converter according to claim 1, characterized in that, The input terminal VIN is connected with one end of a bootstrap switch, the other end of the bootstrap switch is connected with one end of capacitors c9,..., and c0, and the negative terminal of the dynamic comparator, the other end of each of the capacitors c9,..., and c0 is connected with the first terminal of a switch S9N,..., and S0N, the second terminal of each of the switches S9N,..., and S0N is grounded, and the third terminal of each of the switches S9N,..., and S0N is connected with the reference voltage vref.

4. A successive approximation type analog-digital converter according to claim 2, characterized in that, The outputs B9P,..., and B0P of the logic unit control the switches S9P,..., and S0P respectively.

5. A successive approximation type analog-digital converter according to claim 3, characterized in that, The outputs B9N,..., and B0N of the logic unit control the switches S9N,..., and S0N respectively.

6. A control method of a successive approximation type analog-digital converter, characterized in that, The method comprises the following steps: S101. When the sampling signal sample is high, the bootstrap switch one and the bootstrap switch two are closed, the capacitor c9 samples, the sampling signal sample becomes low, the bootstrap switch one and the bootstrap switch two are disconnected, the signal sampled by the capacitor c9 is kept and is converted into data: S102. The output signal compclk of the capacitor array synchronizer changes from low to high, the dynamic comparator starts to compare the signals sampled by the capacitors c9,..., and c0, the dynamic comparator outputs the comparison result after tc, and the result is transmitted to the logic unit; S103. The logic unit latches the comparison result and outputs signals B9P, B9N, B9, rd; Wherein B9P and B9N control S9P and S9N for setting C9, B9 is output to the CPU as the highest bit of ADC decoding, while B9P and B9N and rd enter the capacitor array synchronizer; S104. The discrimination signal rd of the dynamic comparator pulls down compclk, the dynamic comparator resets, while B9P and B9N pass through the capacitor array synchronizer to control the synchronous setting of capacitor C9' and C9, the inverter serves as a voltage detector to detect the port voltage of capacitor C9', when one end of capacitor C9' drops to the flip voltage of the inverter, the dynamic comparator flips the output clock control signal and controls compclk to change from low to high, after the c9 capacitor settling time of tcdac9, the dynamic comparator starts the next bit data conversion operation, and repeats steps S101-S104, until the last bit is compared, the output B9P…B0P and the output B9N…B0N of the logic unit are connected to the mux logic unit, and the output E9-E0 of the mux logic unit respectively controls the double setting switch connected to the other end of the capacitor c9', c8', c1', c0'.

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