MOS bias circuit for improving voltage resistance of circuit, analog circuit, digital circuit and chip

Abstract

The application provides a MOS bias circuit with improved circuit voltage resistance, an analog circuit, a digital circuit and a chip. The MOS bias circuit with improved circuit voltage resistance comprises a starting branch, a PMOS bias voltage generation branch and an NMOS bias voltage generation branch. The starting branch, the PMOS bias voltage generation branch and the NMOS bias voltage generation branch are connected in parallel between a power supply end and a ground end. The PMOS bias voltage generation branch comprises a first bias generation module with at least two PMOS tubes connected in series. The PMOS tubes are connected in a diode connection mode. The NMOS bias voltage generation branch comprises a second bias generation module with at least two NMOS tubes connected in series. The NMOS tubes are connected in a diode connection mode. The analog circuit uses the MOS bias circuit. The digital circuit uses the MOS bias circuit. The chip uses the analog circuit or the digital circuit. The MOS bias circuit can generate a stable output voltage within a certain fluctuating power supply voltage range and improve the circuit voltage resistance performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog and digital mixed circuit design, in particular, to a MOS biasing circuit for improving circuit voltage resistance, and further relates to an analog circuit based on MOS tube voltage resistance protection using the MOS biasing circuit for improving circuit voltage resistance, and further relates to a digital circuit based on MOS tube voltage resistance protection using the MOS biasing circuit for improving circuit voltage resistance, and further relates to a chip using the analog circuit or the digital circuit. BACKGROUND

[0002] At present, the demand for improving the computing power and energy efficiency ratio of SoC (System on Chip) promotes the use of more low-voltage devices such as 0.8V and 1.8V in advanced processes. The IO, ADC and other modules designed using the above devices are difficult to directly meet the application of high-voltage power supply domain such as 3.3V. In addition, power chips are often damaged due to EOS caused by front-stage surge or high-voltage misplug, and it is urgent to improve the reliability of ICs, or there are risks of working under high voltage in some protection modules. Therefore, it is necessary to improve the overall voltage resistance of the circuit, and to solve various voltage resistance problems including MOS tubes, such as Source-Drain voltage resistance, Gate-to-Source / Drain / Body voltage resistance, etc.

[0003] In the prior art, the main solution is to replace the architecture of part of the circuit, such as using Cascode circuit module for operational amplifier, or using higher voltage resistance LDMOS such as 6V, 12V, 30V and 40V high-voltage tube in the process. However, using Casecode architecture to improve the voltage resistance of operational amplifier will have the problem of limited working voltage and output swing, which will affect the performance of the circuit, and if high-voltage devices are used, the chip area and Mask will be increased, which will increase the cost.

[0004] Therefore, it is necessary to consider a more economical and reliable voltage resistance circuit design. SUMMARY

[0005] The first object of the present application is to provide a MOS biasing circuit for improving circuit voltage resistance, which can generate a stable output voltage within a certain fluctuating power supply voltage range.

[0006] The second object of the present application is to provide an analog circuit based on MOS tube voltage resistance protection for improving circuit voltage resistance performance.

[0007] The third object of the present application is to provide a digital circuit for improving circuit voltage resistance performance.

[0008] The fourth object of the present application is to provide a chip for improving circuit voltage resistance performance.

[0009] In order to achieve the above-mentioned first object, the MOS biasing circuit for improving the voltage resistance of the circuit provided by the application comprises a starting branch, a PMOS biasing voltage generating branch and an NMOS biasing voltage generating branch, the starting branch, the PMOS biasing voltage generating branch and the NMOS biasing voltage generating branch are connected in parallel between a power supply end and a grounding end; the PMOS biasing voltage generating branch comprises a first controlled switch circuit, a first biasing generating module with at least two PMOS tubes connected in series, a PMOS biasing voltage output end, the PMOS tubes are arranged in a diode connection mode, a first end of the first biasing generating module is electrically connected with the power supply end, a second end of the first biasing generating module is electrically connected with the grounding end through the first controlled switch circuit, and the second end of the first biasing generating module is also electrically connected with the PMOS biasing voltage output end; the NMOS biasing voltage generating branch comprises a second controlled switch circuit, a second biasing generating module with at least two NMOS tubes connected in series, an NMOS biasing voltage output end, the NMOS tubes are arranged in a diode connection mode, a first end of the second biasing generating module is electrically connected with the power supply end through the second controlled switch circuit, a second end of the second biasing generating module is electrically connected with the grounding end, and the first end of the second biasing generating module is also electrically connected with the NMOS biasing voltage output end; the starting branch provides a starting voltage to the first controlled switch circuit and / or the second controlled switch circuit.

[0010] As can be seen from the above scheme, the MOS biasing circuit for improving the voltage resistance of the circuit provided by the application can output biasing voltage according to the change of the power supply voltage by arranging the PMOS biasing voltage generating branch and the NMOS biasing voltage generating branch, and provide biasing voltage to the PMOS tubes and the NMOS tubes which play a protective role. Meanwhile, the PMOS tubes and the NMOS tubes connected in series in a diode connection mode in the PMOS biasing voltage generating branch and the NMOS biasing voltage generating branch can divide voltage when the power supply voltage is relatively high and stabilize voltage when the power supply voltage is relatively low, so that relatively stable output voltage can be generated within a certain fluctuation range of the power supply voltage.

[0011] In a further scheme, the starting branch comprises a first resistor, a second resistor, a first PMOS and a first NMOS, the first end of the first resistor is electrically connected to the power supply end, the second end of the first resistor is electrically connected to the first end of the second resistor, the second end of the second resistor is electrically connected to the source of the first PMOS, the gate of the first PMOS is electrically connected to the gate of the first NMOS, the drain of the first PMOS is electrically connected to the drain of the first NMOS, the gate of the first PMOS is electrically connected to the drain of the first PMOS, and the source of the first NMOS is electrically connected to the ground end; the first controlled switch circuit comprises a second NMOS and a third NMOS, the drain of the second NMOS is electrically connected to the second end of the first bias generation module, the gate of the second NMOS is electrically connected to the first end of the second resistor, the source of the second NMOS is electrically connected to the drain of the third NMOS, the gate of the third NMOS is electrically connected to the source of the first PMOS, and the source of the third NMOS is electrically connected to the ground end.

[0012] Therefore, the starting branch can generate a relatively stable starting voltage by connecting the first PMOS and the first NMOS in series, which can be used to start the PMOS bias voltage generation branch and the NMOS bias voltage generation branch to work. At the same time, the second NMOS and the third NMOS of the first controlled switch circuit can play a certain voltage reduction role, thereby improving the voltage resistance of the circuit.

[0013] In a further scheme, the second controlled switch circuit comprises a second PMOS and a third PMOS, the source of the second PMOS is electrically connected to the power supply end, the drain of the second PMOS is electrically connected to the source of the third PMOS, and the drain of the third PMOS is electrically connected to the first end of the second bias generation module; the first bias generation module further comprises a first voltage output end and a second voltage output end, the gate of the second PMOS is electrically connected to the first voltage output end, the gate of the third PMOS is electrically connected to the second voltage output end, and the voltage output by the first voltage output end is greater than the voltage output by the second voltage output end.

[0014] Therefore, the first bias generation module further comprises a first voltage output end and a second voltage output end, which can be used to provide a starting voltage to the second controlled switch circuit, thereby simplifying the circuit structure.

[0015] In a further scheme, in the first bias generation module, at least one of the PMOS connected in series is connected in parallel with at least one PMOS and / or at least one resistor.

[0016] Therefore, at least one of the PMOS connected in series is connected in parallel with a PMOS or a resistor, which can further improve the shunt effect of the first bias generation module and stabilize the output.

[0017] In a further aspect, at least one of the series-connected NMOS transistors is connected in parallel with at least one NMOS transistor and / or at least one resistor.

[0018] Therefore, at least one of the series-connected NMOS transistors is connected in parallel with an NMOS transistor or a resistor, which can further improve the shunt effect of the second bias generation module and stabilize the output.

[0019] In a further aspect, a resistor is further arranged between the first end of the first bias generation module and the power supply end.

[0020] In a further aspect, a resistor is further arranged between the second controlled switch circuit and the power supply end.

[0021] Therefore, a resistor is further arranged between the first end of the first bias generation module and the power supply end, and a resistor is further arranged between the second controlled switch circuit and the power supply end, which can limit current and voltage division, reduce the risk of breakdown, and reduce power consumption.

[0022] In order to achieve the above-mentioned second purpose, the MOS tube voltage withstand protection-based analog circuit provided by the present application comprises a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and a MOS tube bias circuit. The PMOS tube for protection is connected in series at the drain of the PMOS tube to be protected, and the NMOS tube for protection is connected in series at the drain of the NMOS tube to be protected. The MOS tube bias circuit adopts the MOS tube bias circuit described above, the PMOS bias voltage output end is electrically connected with the gate of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the gate of the NMOS tube for protection.

[0023] As can be seen from the above-mentioned aspect, the MOS tube voltage withstand protection-based analog circuit of the present application inserts a voltage withstand MOS tube of the same type at a circuit node provided with a PMOS tube to be protected and an NMOS tube to be protected, which plays a protective role for surrounding devices under high voltage. At the same time, the MOS tube bias circuit for improving the voltage withstand of the circuit is combined to generate two bias voltages that can change according to the power supply voltage, so as to place the inserted voltage withstand PMOS tube and NMOS tube in different working states, realize the functions of low-voltage straight-through and high-voltage protection for surrounding devices, comprehensively improve the voltage withstand of the MOS tube, and achieve the purpose of improving the overall voltage withstand of the circuit module.

[0024] In order to achieve the third purpose, the application provides a digital circuit based on MOS tube voltage resistance protection, which comprises a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and a MOS tube biasing circuit.

[0025] Therefore, the digital circuit based on MOS tube voltage resistance protection can protect the surrounding devices when high voltage is applied by inserting the same type of voltage resistance MOS tube at the circuit node provided with the PMOS tube to be protected and the NMOS tube to be protected; meanwhile, the MOS biasing circuit for improving the circuit voltage resistance is combined to generate two biasing voltages which can change according to the power voltage, so as to place the inserted voltage resistance PMOS tube and NMOS tube in different working states, realize the low voltage straight-through and high voltage protection of the surrounding devices, comprehensively improve the voltage resistance of the MOS tube, and achieve the purpose of improving the overall voltage resistance of the circuit module. In addition, when the MOS biasing circuit for improving the circuit voltage resistance and the voltage resistance MOS tube are combined and applied to the digital circuit, not only the VDS (source-end-drain-end) voltage resistance of the MOS tube is protected, but also the VGS (gate-end-source-end) voltage is reduced to two levels due to the characteristics of the digital circuit, so as to prevent the gate of the MOS tube from being overvoltage breakdown.

[0026] In order to achieve the fourth purpose, the application provides a chip, which is provided with an analog circuit based on MOS tube voltage resistance protection or a digital circuit based on MOS tube voltage resistance protection. The analog circuit based on MOS tube voltage resistance protection applies the analog circuit described above. The digital circuit based on MOS tube voltage resistance protection applies the digital circuit described above. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a circuit principle diagram of the MOS biasing circuit for improving the circuit voltage resistance of the application.

[0028] Figure 2 is a circuit principle diagram of the analog circuit based on MOS tube voltage resistance protection applied to the full-symmetrical operational amplifier circuit in the embodiment of the application.

[0029] Figure 3 is a circuit principle diagram of the analog circuit based on MOS tube voltage resistance protection applied to the comparator circuit in the embodiment of the application.

[0030] Figure 4 is a circuit principle diagram of the digital circuit based on MOS tube voltage resistance protection applied to the inverter in the embodiment of the application.

[0031] Figure 5 is the circuit schematic diagram applied to NAND gate circuit in the MOS tube voltage withstand protection based digital circuit embodiment of the present application.

[0032] Figure 6 is the circuit schematic diagram applied to NAND gate circuit in the MOS tube voltage withstand protection based digital circuit embodiment of the present application.

[0033] The present application is further described below in conjunction with the drawings and embodiments. DETAILED DESCRIPTION

[0034] MOS bias circuit embodiment for improving circuit voltage withstand:

[0035] As shown in the present embodiment, the MOS bias circuit for improving circuit voltage withstand includes start branch 1, PMOS bias voltage generation branch 2 and NMOS bias voltage generation branch 3, and the start branch 1, PMOS bias voltage generation branch 2 and NMOS bias voltage generation branch 3 are connected in parallel between power supply end VDD and ground end GND. Figure 1 The PMOS bias voltage generation branch 2 includes first controlled switch circuit 21, first bias generation module 22 with at least two PMOS tubes in series, PMOS bias voltage output end HVBP, the PMOS tubes are arranged in diode connection mode, the first end of the first bias generation module 22 is electrically connected with the power supply end VDD, the second end of the first bias generation module 22 is electrically connected with the ground end GND through the first controlled switch circuit 21, and the second end of the first bias generation module 22 is also electrically connected with the PMOS bias voltage output end HVBP. The number of PMOS tubes in the first bias generation module 22 can be set according to actual needs, and in the present embodiment, the number of PMOS tubes in the first bias generation module 22 is four.

[0036] The NMOS bias voltage generation branch 3 includes second controlled switch circuit 31, second bias generation module 32 with at least two NMOS tubes in series, NMOS bias voltage output end HVBN, the NMOS tubes are arranged in diode connection mode, the first end of the second bias generation module 32 is electrically connected with the power supply end VDD through the second controlled switch circuit 31, the second end of the second bias generation module 32 is electrically connected with the ground end GND, and the first end of the second bias generation module 32 is also electrically connected with the NMOS bias voltage output end HVBN. The number of NMOS tubes in the second bias generation module 32 can be set according to actual needs, and in the present embodiment, the number of NMOS tubes in the first bias generation module 22 is four.

[0037]

[0038] ​The starting branch 1 provides a starting voltage for the first controlled switch circuit 21 and / or the second controlled switch circuit 31, so that the PMOS bias voltage generating branch 2 and the NMOS bias voltage generating branch 3 work.

[0039] In the embodiment, the starting branch 1 includes a first resistor R1, a second resistor R2, a first PMOS P1 and a first NMOS N1. The first end of the first resistor R1 is electrically connected with the power supply end VDD, the second end of the first resistor R1 is electrically connected with the first end of the second resistor R2, the second end of the second resistor R2 is electrically connected with the source of the first PMOS P1, the gate of the first PMOS P1 is electrically connected with the gate of the first NMOS N1, the drain of the first PMOS P1 is electrically connected with the drain of the first NMOS N1, the gate of the first PMOS P1 is electrically connected with the drain of the first PMOS P1, and the source of the first NMOS N1 is electrically connected with the ground end GND.

[0040] The first controlled switch circuit 21 includes a second NMOS N2 and a third NMOS N3. The drain of the second NMOS N2 is electrically connected with the second end of the first bias generating module 22, the gate of the second NMOS N2 is electrically connected with the first end of the second resistor R2, the source of the second NMOS N2 is electrically connected with the drain of the third NMOS N3, the gate of the third NMOS N3 is electrically connected with the source of the first PMOS P1, and the source of the third NMOS N3 is electrically connected with the ground end GND.

[0041] The second controlled switch circuit 31 includes a second PMOS P2 and a third PMOS P3. The source of the second PMOS P2 is electrically connected with the power supply end VDD, the gate of the second PMOS P2 is electrically connected with the power supply end VDD through the first capacitor C1, the drain of the second PMOS P2 is electrically connected with the source of the third PMOS P3, the drain of the third PMOS is electrically connected with the first end of the second bias generating module 32, and the gate of the third PMOS is electrically connected with the power supply end VDD through the second capacitor C2.

[0042] The first bias generation module 22 is further provided with a first voltage output end and a second voltage output end. The first voltage output end is electrically connected with the gate of the second PMOS P2, and the second voltage output end is electrically connected with the gate of the third PMOS. The voltage output by the first voltage output end is greater than the voltage output by the second voltage output end. The first voltage output end and the second voltage output end can be set as required, as long as the voltage output by the first voltage output end is greater than the voltage output by the second voltage output end, and the difference is at least one threshold voltage Vth of the second PMOS P2 or the third PMOS P3. In the embodiment, in order to simplify the circuit, in the first bias generation module 22, the drain of the second PMOS in the direction from the first end to the second end is electrically connected with the first voltage output end, and the second voltage output end is a PMOS bias voltage output end HVBP.

[0043] In the embodiment, a resistor R3 is further arranged between the first end of the first bias generation module 22 and the power supply end VDD. A resistor R4 is further arranged between the second controlled switch circuit 31 and the power supply end VDD. By arranging the resistor R3 and the resistor R4, current limiting and voltage division can be performed to reduce the risk of breakdown and reduce power consumption.

[0044] In this embodiment, when the power supply terminal VDD is not powered, the MOS biasing circuit for improving the voltage resistance of the circuit does not work. When the power supply terminal VDD is powered, the drain output voltage V2 of the first PMOS P1 in the starting branch 1 is Vtp+Vtn, Vtp is the threshold voltage of the first PMOS P1, and Vtn is the threshold voltage of the first NMOS N1. The current of the starting branch 1 is (VDD-Vtp-Vtn) / (R1+R2), and the first end output voltage V1 of the second resistor R2 is V2+I×R2, thereby generating two relatively stable voltages V1 and V2 to provide voltage bias for the second NMOS N2 and the third NMOS N3 in the first controlled switch circuit 21. After receiving V2 and V1, the second NMOS N2 and the third NMOS N3 start to conduct, and balance with the four PMOS in the first bias generation module 22, so that the first voltage output terminal generates a relatively fixed voltage V3=VDD-2×Vgs1, wherein Vgs1 is the voltage between the gate and the source of the PMOS in the first bias generation module 22 (also equal to the threshold voltage of the PMOS in the diode connection), the voltage of the PMOS bias voltage output terminal HVBP is HVBP=VDD-4×Vgs1, thereby establishing the voltage of the PMOS bias voltage output terminal HVBP. After obtaining the voltage V3 and the voltage HVBP, the second PMOS P2 and the third PMOS P3 in the second controlled switch circuit 31 are provided with voltage bias, so that the second PMOS P2 and the third PMOS P3 are turned on, and the NMOS bias voltage output terminal HVBN outputs the voltage HVBN=4×Vgs2, wherein Vgs2 is the voltage between the gate and the source of the NMOS in the second bias generation module 32 (also equal to the threshold voltage of the NMOS in the diode connection). Due to the setting of the first bias generation module 22 and the second bias generation module 32, the voltage range of the PMOS bias voltage output terminal HVBP is 0 to VDD-N×Vgs1 (N is the number of PMOS in the first bias generation module 22), and the voltage range of the NMOS bias voltage output terminal HVBN is N×Vgs2 to VDD (N is the number of NMOS in the second bias generation module 32), thereby generating a relatively stable bias voltage within a certain fluctuation range of the power supply voltage VDD.

[0045] It should be noted that in the first bias generation module 22, at least one of the PMOS tubes in series is connected in parallel with at least one PMOS tube and / or at least one resistor, and in the second bias generation module 32, at least one of the NMOS tubes in series is connected in parallel with at least one NMOS tube and / or at least one resistor. On the basis of the series connection of the first bias generation module 22 or the second bias generation module 32, individual MOS tubes can be connected in series, parallel, or connected with resistors or MOS tubes in various combinations. This way is only a derived implementation of the present application, and belongs to the scope of the invention, but the additional way does not significantly improve the voltage division effect, and only improves the establishment speed of the output HVBP and HVBN.

[0046] Analog circuit embodiment based on MOS tube voltage resistance protection:

[0047] In this embodiment, the analog circuit based on MOS tube voltage resistance protection includes a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and a MOS tube bias circuit. The PMOS tube for protection is connected in series at the drain of the PMOS tube to be protected, and the NMOS tube for protection is connected in series at the drain of the NMOS tube to be protected.

[0048] The MOS tube bias circuit adopts the MOS tube bias circuit in the above embodiment, the PMOS bias voltage output end is electrically connected with the gate of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the gate of the NMOS tube for protection.

[0049] In order to better illustrate the analog circuit based on MOS tube voltage resistance protection of the present application, examples are given below.

[0050] In one embodiment, the analog circuit based on MOS tube voltage resistance protection is a full-symmetry operational amplifier circuit. The full-symmetry operational amplifier circuit is improved by inserting a voltage resistance protection MOS tube of the same type at the circuit node of the PMOS tube to be protected and the NMOS tube to be protected, as shown in the following figure. Figure 2As shown, removing the three PMOS tubes in the PMOS tube group 4 for protection and the two NMOS tubes in the NMOS tube group 5 for protection, the remaining part is a full symmetry operational amplifier circuit known for amplifying the input Vp, Vn and outputting through EA_OUT. In this embodiment, the gate of each PMOS tube in the PMOS tube group 4 for protection is electrically connected with the PMOS bias voltage output terminal in the MOS bias circuit for improving the voltage endurance of the circuit, and the gate of each NMOS tube in the NMOS tube group 5 for protection is electrically connected with the NMOS bias voltage output terminal in the MOS bias circuit for improving the voltage endurance of the circuit. By inserting the PMOS tube group 4 for protection and the NMOS tube group 5 for protection, the voltage division of the original MOS tube (including one or more PMOS and NMOS) subjected to VDD voltage is performed again, the breakdown probability of the original MOS tube is reduced, and the voltage endurance of the overall circuit is improved.

[0051] In another embodiment, the analog circuit based on MOS tube voltage endurance protection is a comparator circuit. The comparator circuit is improved by using the comparator circuit known to those skilled in the art, and the voltage endurance protection is inserted into the circuit node of the PMOS tube to be protected and the NMOS tube to be protected with the voltage endurance protection MOS tube of the same type. As shown in the figure, Figure 3 As shown, removing the two PMOS tubes in the PMOS tube group 6 for protection and the four NMOS tubes in the NMOS tube group 7 for protection, the remaining part is a comparator circuit known for comparing the input Vp, Vn and outputting high or low level through CMPO-H and CMPO-L. In this embodiment, the gate of each PMOS tube in the PMOS tube group 6 for protection is electrically connected with the PMOS bias voltage output terminal in the MOS tube bias circuit, and the gate of each NMOS tube in the NMOS tube group 7 for protection is electrically connected with the NMOS bias voltage output terminal in the MOS tube bias circuit. By inserting the PMOS tube group 6 for protection and the NMOS tube group 7 for protection, the voltage division of the MOS tube subjected to VDD voltage is performed again, the breakdown probability is reduced, and the voltage endurance of the overall circuit is improved.

[0052] It should be noted that in this embodiment inserted into the comparator circuit, due to the insertion of the PMOS tube group 6 and the NMOS tube group 7, the original CMPO output stage is split into two high and low different level CMPO-H and CMPO-L, but CMPO-H and CMPO-L still have the same unified logic 1 or 0 expression and can be simultaneously used as the input of the subsequent double-level INV (inverter) module.

[0053] Digital circuit embodiment based on MOS tube voltage endurance protection:

[0054] In this embodiment, the digital circuit based on MOSFET withstand voltage protection includes a PMOS transistor to be protected, an NMOS transistor to be protected, a PMOS transistor for protection, an NMOS transistor for protection, and a MOSFET bias circuit. The PMOS transistor for protection is connected in series with the drain of the PMOS transistor to be protected, and the NMOS transistor for protection is connected in series with the drain of the NMOS transistor to be protected.

[0055] The MOS transistor biasing circuit adopts the MOS transistor biasing circuit in the above embodiment. The PMOS bias voltage output terminal is electrically connected to the gate of the PMOS transistor used for protection, and the NMOS bias voltage output terminal is electrically connected to the gate of the NMOS transistor used for protection.

[0056] The digital circuit based on MOSFET withstand voltage protection of the present invention can be a digital unit such as NOR, NAND, DFF, or inverter. To better illustrate the digital circuit based on MOSFET withstand voltage protection of the present invention, examples are provided below.

[0057] In one embodiment, see Figure 4 , Figure 4 The circuit diagram shows a digital circuit consisting of a dual-input inverter with both high and low levels. The high-low level dual-input inverter includes PMOS transistors P4, PMOS transistor P5, NMOS transistor N4, and NMOS transistor N5. The source of PMOS transistor P4 is electrically connected to the power supply terminal VDD, the gate of PMOS transistor P4 is electrically connected to the level input terminal INH, the drain of PMOS transistor P4 is electrically connected to the output terminal OUT-H, the drain of PMOS transistor P4 is also electrically connected to the source of PMOS transistor P5, the gate of PMOS transistor P5 is electrically connected to the PMOS bias voltage output terminal in the voltage-resistant MOS bias circuit of the boost circuit, the drain of PMOS transistor P5 is electrically connected to the drain of NMOS transistor N4, the source of NMOS transistor N4 is electrically connected to the output terminal OUT-L, the source of NMOS transistor N4 is also electrically connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5 is electrically connected to the NMOS bias voltage output terminal in the voltage-resistant MOS bias circuit of the boost circuit, and the source of NMOS transistor N5 is grounded.

[0058] When the inverter is operating, if the input INH is a slightly high logic 0 and INL is a low logic 0 (actually GND), then the output OUT-H is VDD and OUT-L is a slightly low logic 1. If the input INH is a slightly high logic 1 or VDD and INL are a slightly low logic 1, then the output OUT-H is a slightly high logic 0 and OUT-L is 0 (actually GND). Through the voltage-resistant transistor and dual-level technology of this invention, not only is the VDS withstand voltage of the MOSFET protected, but also, due to the characteristic of digital circuits that are either VDD or 0, the dual-level technology reduces the VGS voltage, preventing the MOSFET gate from being overvoltage-damped.

[0059] In another embodiment, see Figure 5 , Figure 5 The digital circuit shown is a NAND gate circuit schematic. The NAND gate circuit includes PMOS transistors P6, P7, P8, NMOS transistors N6, N7, and N8. The sources of PMOS transistors P7 and P8 are electrically connected to the power supply terminal VDD. The gate of PMOS transistor P7 is electrically connected to the first-level input terminal AH, and the gate of PMOS transistor P8 is electrically connected to the second-level input terminal BH. The drains of PMOS transistors P7 and P8 are electrically connected to the source of PMOS transistor P6. The source of PMOS transistor P6 is also electrically connected to the output terminal OUT-H. The gate of PMOS transistor P6 is connected to the MOS bias circuit in the boost circuit. The PMOS bias voltage output terminal HVBP is electrically connected. The drain of PMOS transistor P6 is electrically connected to the drain of NMOS transistor N6. The gate of NMOS transistor N6 is electrically connected to the NMOS bias voltage output terminal HVBN in the MOS bias circuit with voltage withstand capability of the boost circuit. The source of NMOS transistor N6 is electrically connected to the output terminal OUT-L. The source of NMOS transistor N6 is also electrically connected to the drain of NMOS transistor N7. The gate of NMOS transistor N7 is electrically connected to the third level input terminal AL. The source of NMOS transistor N7 is electrically connected to the drain of NMOS transistor N8. The gate of NMOS transistor N8 is electrically connected to the fourth level input terminal BL. The source of NMOS transistor N8 is grounded.

[0060] for Figure 5 If the PMOS transistor P6 and NMOS transistor N6 are omitted from the NAND gate circuit, it is a standard NAND gate structure. AH and AL are unified into one input A, BH and BL are unified into one input B, and OUT-H and OUT-L are unified into one output OUT. Its logic is as follows: As described above, after adding the PMOS transistor P6 and NMOS transistor N6 with withstand voltage protection, and the corresponding bias voltages HVBP and HVBN, input A is split into AH and AL (AH and AL have the same logic, only the level differs), input B is split into BH and BL (BH and BL have the same logic, only the level differs), and output OUT is split into output OUT-H and output OUT-L (OUT-H and OUT-L have the same logic, only the level differs). The logic of OUT-H and OUT-L remains the same. All the split input and output digital signals must be used in conjunction with the high-low level dual-input inverter or other similar digital units in the aforementioned examples, or with analog circuits such as the dual-level comparator circuit in the aforementioned examples. Based on the standard NAND gate structure, it further improves the withstand voltage between the source-drain and gate-source / drain / body, enabling the digital circuit to operate at several times the original VDD voltage.

[0061] In another embodiment, seeFigure 6 , Figure 6 The circuit diagram for the NOR gate circuit is shown below. The NOR gate circuit includes PMOS transistors P9, P10, P11, NMOS transistors N9, N10, and N11. The source of PMOS transistor P11 is electrically connected to the power supply terminal VDD, the gate of PMOS transistor P11 is electrically connected to the first level input terminal AH, the drain of PMOS transistor P11 is electrically connected to the source of PMOS transistor P10, the gate of PMOS transistor P10 is electrically connected to the second level input terminal BH, the drain of PMOS transistor P10 is electrically connected to the source of PMOS transistor P9, and the drain of PMOS transistor P10 is also electrically connected to the output terminal OUT-H. The gate of PMOS transistor P10 is connected to the bias gate of the boost circuit. The PMOS bias voltage output terminal HVBP in the bias circuit is electrically connected. The drain of PMOS transistor P10 is electrically connected to the drain of NMOS transistor N9. The gate of NMOS transistor N9 is electrically connected to the NMOS bias voltage output terminal HVBN in the boost circuit's withstand voltage MOS bias circuit. The source of NMOS transistor N9 is electrically connected to the output terminal OUT-L. The drains of NMOS transistor N9 and NMOS transistor N10 are both electrically connected to the source of NMOS transistor N9. The gate of NMOS transistor N9 is electrically connected to the third level input terminal AL. The gate of NMOS transistor N10 is electrically connected to the fourth level input terminal BL. The sources of NMOS transistor N9 and NMOS transistor N10 are both grounded.

[0062] for Figure 6 If PMOS transistor P9 and NMOS transistor N9 are omitted, it becomes a standard NOR gate structure. AH and AL are unified into one input A, BH and BL into one input B, and OUT-H and OUT-L into one output OUT. Its logic is as follows: As described above, after adding the PMOS transistor P9 and NMOS transistor N9 with withstand voltage protection, and the corresponding bias voltages HVBP and HVBN, input A is split into AH and AL (AH and AL have the same logic, only the level differs), input B is split into BH and BL (BH and BL have the same logic, only the level differs), and output OUT is split into OUT-H and OUT-L outputs (OUT-H and OUT-L have the same logic, only the level differs). The logic of OUT-H and OUT-L remains the same. All the split input and output digital signals must be used in conjunction with the high-low level dual-input inverter or other similar digital units in the aforementioned examples, or with analog circuits such as the dual-level comparator circuit in the aforementioned examples. It further improves the source-drain and gate-source / drain / body withstand voltages on top of the standard NOR gate structure, enabling digital circuits to operate at several times the original VDD voltage.

[0063] Chip Example:

[0064] In this embodiment, the chip is provided with a MOS tube voltage resistance protection-based analog circuit or a MOS tube voltage resistance protection-based digital circuit, the MOS tube voltage resistance protection-based analog circuit applies the analog circuit in the above embodiment, and the MOS tube voltage resistance protection-based digital circuit applies the digital circuit in the above embodiment.

[0065] It should be noted that the above is only a preferred embodiment of the present application, but the inventive design concept is not limited thereto, and any non-essential modification of the present application using this concept also falls within the protection scope of the present application.

Claims

1. A MOS bias circuit for improving circuit withstand voltage, characterized in that: The starting branch, the PMOS bias voltage generating branch and the NMOS bias voltage generating branch are connected in parallel between a power supply end and a ground end; The PMOS bias voltage generating branch comprises a first controlled switch circuit, a first bias generating module with at least two PMOS tubes connected in series, and a PMOS bias voltage output end, the PMOS tubes are arranged in a diode connection mode, a first end of the first bias generating module is electrically connected with the power supply end, a second end of the first bias generating module is electrically connected with the ground end through the first controlled switch circuit, and the second end of the first bias generating module is also electrically connected with the PMOS bias voltage output end; The NMOS bias voltage generating branch comprises a second controlled switch circuit, a second bias generating module with at least two NMOS tubes connected in series, and an NMOS bias voltage output end, the NMOS tubes are arranged in a diode connection mode, a first end of the second bias generating module is electrically connected with the power supply end through the second controlled switch circuit, a second end of the second bias generating module is electrically connected with the ground end, and the first end of the second bias generating module is also electrically connected with the NMOS bias voltage output end; The starting branch provides a starting voltage to the first controlled switch circuit and / or the second controlled switch circuit; The starting branch comprises a first resistance, a second resistance, a first PMOS tube and a first NMOS tube, a first end of the first resistance is electrically connected with the power supply end, a second end of the first resistance is electrically connected with a first end of the second resistance, a second end of the second resistance is electrically connected with a source electrode of the first PMOS tube, a gate electrode of the first PMOS tube is electrically connected with a gate electrode of the first NMOS tube, a drain electrode of the first PMOS tube is electrically connected with a drain electrode of the first NMOS tube, the gate electrode of the first PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and a source electrode of the first NMOS tube is electrically connected with the ground end; The first controlled switch circuit comprises a second NMOS tube and a third NMOS tube, a drain electrode of the second NMOS tube is electrically connected with the second end of the first bias generating module, a gate electrode of the second NMOS tube is electrically connected with the first end of the second resistance, a source electrode of the second NMOS tube is electrically connected with a drain electrode of the third NMOS tube, a gate electrode of the third NMOS tube is electrically connected with the source electrode of the first PMOS tube, and a source electrode of the third NMOS tube is electrically connected with the ground end.

2. The MOS bias circuit for improving the voltage resistance of the circuit according to claim 1, wherein: The second controlled switch circuit comprises a second PMOS tube and a third PMOS tube, a source electrode of the second PMOS tube is electrically connected with the power supply end, a drain electrode of the second PMOS tube is electrically connected with a source electrode of the third PMOS tube, and a drain electrode of the third PMOS is electrically connected with the first end of the second bias generating module. The first bias generation module is further provided with a first voltage output end and a second voltage output end, the first voltage output end is electrically connected with the gate of the second PMOS, the second voltage output end is electrically connected with the gate of the third PMOS, and the voltage output by the first voltage output end is greater than the voltage output by the second voltage output end.

3. The MOS bias circuit for improving the voltage resistance of the circuit according to claim 1 or 2, characterized in that: In the first bias generation module, at least one of the PMOS tubes in series is connected in parallel with at least one PMOS tube and / or at least one resistor.

4. The MOS bias circuit for improving the voltage resistance of the circuit according to claim 1 or 2, characterized in that: In the second bias generation module, at least one of the NMOS tubes in series is connected in parallel with at least one NMOS tube and / or at least one resistor.

5. The MOS bias circuit for improving the voltage resistance of the circuit according to claim 1 or 2, characterized in that: A resistor is further arranged between the first end of the first bias generation module and the power supply end.

6. The MOS bias circuit for improving the voltage resistance of the circuit according to claim 1 or 2, characterized in that: A resistor is further arranged between the second controlled switch circuit and the power supply end.

7. An analog circuit based on MOS transistor voltage withstand protection, characterized by: The MOS bias circuit for improving the voltage resistance of the circuit comprises a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and a MOS bias circuit for improving the voltage resistance of the circuit, the PMOS tube for protection is connected in series at the drain of the PMOS tube to be protected, and the NMOS tube for protection is connected in series at the drain of the NMOS tube to be protected. The MOS bias circuit for improving the voltage resistance of the circuit adopts the MOS bias circuit for improving the voltage resistance of the circuit according to any one of claims 1 to 6, the PMOS bias voltage output end is electrically connected with the gate of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the gate of the NMOS tube for protection.

8. A digital circuit based on MOS transistor voltage withstand protection, characterized in that: The MOS bias circuit for improving the voltage resistance of the circuit comprises a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and a MOS bias circuit for improving the voltage resistance of the circuit, the PMOS tube for protection is connected in series at the drain of the PMOS tube to be protected, and the NMOS tube for protection is connected in series at the drain of the NMOS tube to be protected. The MOS bias circuit for improving the voltage resistance of the circuit adopts the MOS bias circuit for improving the voltage resistance of the circuit according to any one of claims 1 to 6, the PMOS bias voltage output end is electrically connected with the gate of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the gate of the NMOS tube for protection.

9. A chip provided with an analog circuit based on MOS transistor voltage resistance protection or a digital circuit based on MOS transistor voltage resistance protection, characterized in that: The analog circuit based on the MOS tube voltage resistance protection applies the analog circuit according to claim 7. The digital circuit based on the MOS tube voltage resistance protection applies the digital circuit according to claim 8.

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