A SiC-LDMOS device
By introducing a field plate structure that spans the gate and drift region in SiC-LDMOS devices, the problem of the termination region breaking down earlier than the intrinsic region is solved, achieving higher breakdown voltage and withstand voltage capability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU WATECH ELECTRONICS CO LTD
- Filing Date
- 2022-12-28
- Publication Date
- 2026-07-24
Smart Images
Figure CN116469932B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor power device technology, and more specifically, to a SiC-LDMOS device. Background Technology
[0002] A top view of a traditional SiC-LDMOS device, such as Figure 1 As shown, the region to the left of the dashed line is the intrinsic region, and the region to the right is the termination region. Source region 12 forms only the intrinsic region, and gate 13 surrounds the end of source region 12. Drain region 11 surrounds the end of gate 13 in the termination region. In the termination region, the electric field lines in the drain region 11 concentrate inwards, i.e., towards gate 13, resulting in a higher electric field strength in the termination region than in the intrinsic region. This leads to a significantly lower actual breakdown voltage in the termination region of the SiC-LDMOS device compared to the intrinsic region, ultimately causing the termination region to break down earlier than the intrinsic region, resulting in a lower actual breakdown voltage (BV) for the SiC-LDMOS device. The electric field strength of the SiC-LDMOS device is much higher than that of the SiC-LDMOS device.
[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention
[0004] This application provides a SiC-LDMOS device to solve the technical problem that the terminal region of a traditional SiC-LDMOS device breaks down earlier than the intrinsic region.
[0005] A SiC-LDMOS device according to an embodiment of this application includes:
[0006] Substrate;
[0007] The gate is located above the substrate in the vertical direction and spans the intrinsic region and termination region of the SiC-LDMOS device in the lateral direction.
[0008] The drift region is located within the substrate in the vertical direction and is formed outside the outer edge of the gate in the lateral direction, spanning the intrinsic region and the termination region.
[0009] The drain region is formed in the substrate in the vertical direction and outside the drift region in the lateral direction;
[0010] The first oxide layer is an insulating medium filling the space between the semiconductor and the metal between the gate and the drain region;
[0011] The field plate structure is vertically connected above the gate and the drift region respectively, and horizontally surrounds the outer edge of the gate and spans the intrinsic region and the termination region.
[0012] The electric field lines of the leakage area connected to the high voltage converge towards the field plate structure and terminate at the field plate structure.
[0013] The embodiments of this application, by adopting the above technical solutions, have the following technical effects:
[0014] The field plate structure is not only located within the intrinsic region but also within the termination region, and it vertically spans above both the gate and the drift region. This concentrates the electric field lines of the drain region, which is connected to the high voltage, towards the field plate structure, terminating at it in both the termination and intrinsic regions. The electric field lines decrease in distance in the termination region, reducing the risk of breakdown of the first oxide layer. Simultaneously, the difference in the decrease in distance between the electric field lines in the termination and intrinsic regions is small, resulting in a smaller difference in the electric field strength between the termination and intrinsic regions. Consequently, the actual breakdown voltage of the SiC-LDMOS device in the termination region is smaller than that in the intrinsic region, preventing premature breakdown of the termination region and thus resulting in a higher actual breakdown voltage (BV) for the SiC-LDMOS device. Attached Figure Description
[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0016] Figure 1 This is a top view of a traditional SiC-LDMOS device in the background art;
[0017] Figure 2 This is a top view of the SiC-LDMOS device according to an embodiment of this application;
[0018] Figure 3 for Figure 2 AA sectional view.
[0019] Figure label:
[0020] Gate 20, gate oxide layer 21, source region 22, drain region 23, first layer body region 24, body region contact region 25, drift region 26, drift buffer region 27, first field plate 28, fourth via 29, first metal layer 210, first via 211, second via 212, third via 213, second layer body region 214, epitaxial layer 215, epitaxial layer lateral bearing region 215-1, first doped substrate 216, back metal 217. Detailed Implementation
[0021] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0022] Example 1
[0023] like Figure 2 and Figure 3 As shown, the SiC-LDMOS device in this embodiment includes:
[0024] Substrate;
[0025] Gate 20 is located above the substrate in the vertical direction and spans the intrinsic region and termination region of the SiC-LDMOS device in the lateral direction. Figure 2 The region to the left of the dashed line is the intrinsic region, and the region to the right of the dashed line is the terminal region;
[0026] Drift region 26 is located within the substrate in the vertical direction and is formed outside the outer edge of the gate 20 in the lateral direction, spanning the intrinsic region and the termination region.
[0027] Drain region 23 is formed in the substrate in the vertical direction and outside the drift region 26 in the lateral direction;
[0028] The first oxide layer is an insulating medium filling all semiconductors and metals between the gate 20 and the drain region 23;
[0029] The field plate structure is vertically connected above the gate 20 and the drift region 26 respectively, and horizontally surrounds the outer edge of the gate 20 and spans the intrinsic region and the terminal region.
[0030] The electric field lines of the leakage area connected to the high voltage converge towards the field plate structure and terminate at the field plate structure.
[0031] In the SiC-LDMOS device of this application embodiment, the field plate structure is disposed not only in the intrinsic region but also in the termination region, and the field plate structure is vertically connected above the gate 20 and the drift region 26. Thus, the electric field lines of the drain region connected to the high voltage are concentrated towards the field plate structure, terminating at the field plate structure in both the termination and intrinsic regions. The electric field lines decrease in distance in the termination region, reducing the risk of breakdown of the first oxide layer. Simultaneously, the difference in the decrease in distance between the electric field lines in the termination and intrinsic regions is small, resulting in a smaller difference between the electric field strength in the termination region and the intrinsic region. Consequently, the actual breakdown voltage of the SiC-LDMOS device in the termination region is smaller than that in the intrinsic region, preventing premature breakdown of the termination region and resulting in a higher actual breakdown voltage (BV) of the SiC-LDMOS device.
[0032] Specifically, the vertical direction refers to the thickness direction of the SiC-LDMOS device, corresponding to... Figure 3 The vertical direction is the direction of the plane perpendicular to the vertical direction; the horizontal direction is the direction of the plane perpendicular to the vertical direction. Figure 3 The direction perpendicular to the paper.
[0033] Specifically, the substrate is a silicon carbide (chemical formula SiC) substrate, and the gate 20 is a polysilicon gate.
[0034] Specifically, such as Figure 3 As shown, gate oxide layer 21 is formed beneath gate 20. Gate oxide layer 21 is a silicon dioxide gate oxide layer, serving as an insulating medium between the semiconductor, which is the source region 22, and the metal, which is the gate 20. Gate oxide layer 21 is a portion of the first oxide layer 215-1. The field plate structure is also a metallic structure, and an insulating medium is formed around the field plate structure. The first oxide layer also includes an insulating medium filled between the drain region 23 and the first metal layer 210. That is, the first oxide layer fills all the spaces between the semiconductor and the metal between the gate 20 and the drain region 23.
[0035] In implementation, the gate 20, source region 22, and drain region 23 are located in the same plane. That is, the SiC-LDMOS device in this embodiment is a planar SiC-LDMOS device. It is particularly suitable for high-voltage planar SiC-LDMOS devices.
[0036] During implementation, such as Figure 2 and Figure 3As shown, the lower portion of the substrate forms a first-doped substrate 216, and the upper portion of the substrate forms a first-doped epitaxial layer 215; wherein, the drift region 26 is formed within the epitaxial layer, and the drift region 26 maintains a distance from the outer edge of the gate 20 to expose the epitaxial layer lateral pressure bearing region 215-1, the epitaxial layer lateral pressure bearing region 215-1 being the portion of the epitaxial layer located between the gate 20 and the drift region 26;
[0037] SiC-LDMOS devices also include:
[0038] Source region 22 is formed in the epitaxial layer in the vertical direction, and the first end side of source region 22 serves as the boundary between intrinsic region and terminal region;
[0039] Wherein, the lateral pressure-bearing region 215-1 of the epitaxial layer is kept at a distance from the outer edge of the source region 22 such that the lateral pressure-bearing region 215-1 of the epitaxial layer is only located in the terminal region and does not enter the intrinsic region. The side of the lateral pressure-bearing region 215-1 of the epitaxial layer facing the drain region is located below the field plate structure. The drift region and the drain region are formed in the epitaxial layer.
[0040] The transverse bearing region of the epitaxial layer is located only in the terminal region and does not enter the intrinsic region, corresponding to Figure 2 The reason why the left side of the epitaxial layer lateral pressure-bearing region 215-1 does not enter the intrinsic region is that if the lateral pressure-bearing region of the epitaxial layer enters the intrinsic region, it will increase the on-resistance of the SiC-LDMOS device. It is recommended that the source region not enter the annular region of the termination region. If it does enter the annular region of the termination region, the termination region will also conduct when the SiC-LDMOS device is operating. The requirement for the termination region is that it should not conduct, but only bear voltage.
[0041] The side of the epitaxial layer's lateral pressure-bearing region furthest from the source region is located below the field plate structure. That is, the edge of the field plate structure in the drain direction covers the lateral pressure-bearing region of the epitaxial layer. This arrangement further increases the breakdown voltage of the SiC-LDMOS device's termination region. The principle is to utilize the strong junction electric field formed by the lateral pressure-bearing region and the drift region of the epitaxial layer to raise the electric field intensity in the vicinity of this PN junction, thereby further improving the voltage withstand capability of the SiC-LDMOS device's termination region.
[0042] The drift region is not formed around the entire outer edge of the gate; instead, a portion of the epitaxial layer is exposed where no drift region is formed in the lateral bearing region. That is, the shape of the drift region in the termination region is specific. The lateral bearing region of the epitaxial layer, acting as an additional termination bearing area, can withstand more voltage, forming a lateral PP (Positioning Probe). - N -The N-gradient junction, also known as the body contact region / epitaxy layer lateral bearing region / drift buffer / drain region, is beneficial for smoothing the electric field distribution and solving the problem of reduced BV caused by electric field concentration in the terminal region. The principle is that the junction electric field of an abrupt PN junction is very strong, and SiC-LDMOS devices may preferentially break down at the junction interface. The reason why the epitaxial layer lateral bearing region cannot extend beyond the edge of the field plate structure in the drain direction is that if it extends beyond the field plate structure, the PN junction electric field, without the field plate structure to disperse the electric field lines, will generate a strong electric field concentration at the right-angle edge with the drift region, potentially causing the device to break down very early at this point. By keeping the lateral bearing region within the edge of the field plate structure, the electric field strength at the PN junction interface will generally not be higher than that at the edge of the field plate structure.
[0043] During implementation, such as Figure 2 As shown, the portion of the gate 20 located in the terminal region is semi-circular;
[0044] The epitaxial layer lateral pressure-bearing region 215-1 is semi-annular, surrounding the outer edge of the gate 20 located in the terminal region;
[0045] The drift region 26 surrounds the outer edge of the gate 20 and the epitaxial layer lateral pressure-bearing region 215-1.
[0046] The gate 20 in the termination region is semi-ringed, and the epitaxial layer lateral bearing region 215-1 is also semi-ringed. This semi-ringed structure effectively mitigates the electric field concentration effect at the gate edge in the termination region. The principle is similar to tip discharge; the sharper the structure, the more easily charge concentration occurs under the induction of a high external potential, and the resulting high electric field may break down the dielectric at that point. The semi-ringed structure effectively alleviates the tip charge concentration phenomenon, making it more difficult for the dielectric to break down or for semiconductor avalanche breakdown to occur at the termination point.
[0047] like Figure 2 and Figure 3 As shown, the field plate structure includes:
[0048] The first field plate 28 is shaped like a Z, with its upper lateral arm spaced apart from the upper surface of the gate 20, its vertical arm spaced apart from the gate, and its lower lateral arm spaced apart from the upper surface of the drift region 26.
[0049] The first field plate disperses the high electric field intensity at the gate edge, reducing the risk of the first oxide layer being broken down and improving the reliability of the first oxide layer.
[0050] In implementation, the field plate structure also includes:
[0051] The second field plate is shaped like a Z, and the upper transverse arms of the second field plate are arranged above the upper transverse arms of the first field plate in a partially stacked manner.
[0052] The arrangement of the first and second field plates, with its multi-layer field plates, disperses the high electric field intensity at the gate edge, reduces the risk of the first oxide layer being broken down, and improves the reliability of the first oxide layer.
[0053] In practice, SiC-LDMOS devices also include:
[0054] The first body region 24 and the second body region 214 are formed from top to bottom, and the doping concentration of the first body region 24 and the second body region 214 increases sequentially from top to bottom.
[0055] The body region contact area 25, the source area and the first layer body region are arranged in the same layer in the lateral direction, and the second layer body region 214 is formed below the body region contact area 25, the source area and the first layer body region in the vertical direction.
[0056] The channel is located between the source and drain regions and below the gate. A first body region 24 and a second body region 214 are formed from top to bottom at the channel location, with the doping concentration of the first and second body regions 24 increasing sequentially from top to bottom; that is, the first body region 24 has a lower doping concentration, and the second body region 214 has a higher doping concentration. The lower doping concentration of the first body region 24 allows the threshold voltage Vt to remain within a reasonable range by adjusting its doping concentration. The lower doping concentration of the first body region 24 prevents further reduction in mobility due to carrier scattering caused by channel doping, thus improving channel mobility. The higher doping concentration of the second body region 214 results in a lower electric field intensity at the pn junction (the pn junction formed by the structure between the source and drain regions) at the channel edge under high voltage, preventing the depletion region from excessively widening into the second-doped source region, thus restraining depletion region expansion and preventing short-channel punch-through under high voltage, thereby increasing the breakdown voltage BV.
[0057] During implementation, such as Figure 3 As shown, the SiC-LDMOS device also includes:
[0058] Drift buffer 27 is located within the drift region 26 in the vertical direction and surrounds the drain 23.
[0059] During implementation, such as Figure 3 As shown, the SiC-LDMOS device also includes:
[0060] Backside metal 217 is formed on the lower surface of the substrate 216;
[0061] Two first metal layers 210, one located above the source region and the other above the drain region;
[0062] The first through-hole 211 and the metal filled in the first through-hole connect the source region, the body region contact area and the first metal layer above the source region.
[0063] The second through-hole 212 and the metal filled in the second through-hole connect the drain area and the first metal layer above the drain area.
[0064] The third via 213 and the metal filled in the third via connect the back metal 217, the substrate 216, the epitaxial layer 215, the second body region 214 and the first metal layer above the source region.
[0065] During implementation, such as Figure 3 As shown, the SiC-LDMOS device also includes:
[0066] The fourth through hole 29 and the metal filled in the fourth through hole are arranged such that the upper lateral arm of the first field plate 28 is spaced apart from the upper surface of the gate, the vertical arm of the first field plate 28 is spaced apart from the gate, and the lower lateral arm of the first field plate 28 is spaced apart from the upper surface of the drift region.
[0067] During implementation, such as Figure 3 As shown, the gate 20, source region 22, and drain region 23 are located in the same plane. The source region is grounded, and the drain region is connected to the operating voltage. Different voltages are applied to the gate to control the switching of the device.
[0068] In the description of this application and its embodiments, it should be understood that the terms "top", "bottom", "height", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0069] In this application and its embodiments, unless otherwise expressly specified and limited, the terms "set," "install," "connect," "link," "fix," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0070] In this application and its embodiments, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0071] The foregoing disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0072] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0073] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A SiC-LDMOS device, characterized in that, include: Substrate; The gate is located above the substrate in the vertical direction and spans the intrinsic region and termination region of the SiC-LDMOS device in the lateral direction. The drift region is located within the substrate in the vertical direction and is formed outside the outer edge of the gate in the lateral direction, spanning the intrinsic region and the termination region. The drain region is formed in the substrate in the vertical direction and outside the drift region in the lateral direction; The first oxide layer is an insulating medium filling the space between the semiconductor and the metal between the gate and the drain region; The field plate structure is vertically connected above the gate and the drift region respectively, and horizontally surrounds the outer edge of the gate and spans the intrinsic region and the termination region. The electric field lines of the leakage area connected to the high voltage converge towards the field plate structure and terminate at the field plate structure.
2. The SiC-LDMOS device according to claim 1, characterized in that, An epitaxial layer is formed on the upper portion of the substrate; wherein the drift region is formed within the epitaxial layer, and the drift region is kept at a distance from the outer edge of the gate to expose the lateral pressure bearing region of the epitaxial layer, the lateral pressure bearing region of the epitaxial layer being the portion of the epitaxial layer located between the gate and the drift region; SiC-LDMOS devices also include: A source region is formed in the epitaxial layer in the vertical direction, and the first end of the source region serves as the boundary between the intrinsic region and the terminal region. Wherein, the lateral pressure-bearing region of the epitaxial layer is kept at a distance from the outer edge of the source region, such that the lateral pressure-bearing region of the epitaxial layer is located only in the terminal region and does not enter the intrinsic region, and the side of the lateral pressure-bearing region of the epitaxial layer away from the source region is located below the field plate structure, and the drift region and the leakage region are formed in the epitaxial layer.
3. The SiC-LDMOS device according to claim 2, characterized in that, The gate is a racetrack-shaped gate; The shape of the lateral pressure-bearing region of the epitaxial layer is a racetrack, which surrounds the outer edge of the gate located in the terminal region; The drift region surrounds the outer edge of the gate and the lateral pressure-bearing region of the epitaxial layer.
4. The SiC-LDMOS device according to claim 2, characterized in that, The field plate structure includes: The first field plate is shaped like a Z, with its upper lateral arm spaced apart from the upper surface of the gate, its vertical arm spaced apart from the gate, and its lower lateral arm spaced apart from the upper surface of the drift region.
5. The SiC-LDMOS device according to claim 4, characterized in that, The field plate structure also includes: The second field plate is shaped like a Z, and the upper transverse arms of the second field plate are arranged above the upper transverse arms of the first field plate in a partially stacked manner.
6. The SiC-LDMOS device according to any one of claims 4 to 5, characterized in that, Also includes: The first layer body region (24) and the second layer body region (214) are formed from top to bottom, and the doping concentration of the first layer body region (24) and the second layer body region (214) increases sequentially from top to bottom; The body region contact area (25), the source area and the first layer body region are arranged in the same layer in the lateral direction, and the second layer body region (214) is formed below the body region contact area (25), the source area and the first layer body region in the vertical direction.
7. The SiC-LDMOS device according to claim 6, characterized in that, Also includes: A drift buffer (27) is located within the drift area (26) in the vertical direction and surrounds the leak area (23).
8. The SiC-LDMOS device according to claim 6, characterized in that, Also includes: Backside metal (217) is formed on the lower surface of the substrate (216); Two first metal layers (210), one located above the source region and the other above the drain region; The first through hole (211) and the metal filled in the first through hole connect the source region, the body region contact area and the first metal layer above the source region; The second through hole (212) and the metal filled in the second through hole connect the drain area and the first metal layer above the drain area; The third via (213) and the metal filled in the third via connect the back metal (217), the substrate (216), the epitaxial layer (215), the second body region (214) to the first metal layer above the source region.
9. The SiC-LDMOS device according to claim 8, characterized in that, Also includes: The fourth through hole (29) and the metal filled in the fourth through hole, the upper lateral arm of the first field plate (28) is spaced apart from the upper surface of the gate, the vertical arm of the first field plate (28) is spaced apart from the gate, and the lower lateral arm of the first field plate (28) is spaced apart from the upper surface of the drift region.
10. The SiC-LDMOS device according to claim 9, characterized in that, The gate (20), source (22) and drain (23) are located in the same plane.