Adaptive alignment of sample clock within analog-to-digital converter

Abstract

The present disclosure relates to adaptive alignment of a sample clock within an analog-to-digital converter. An apparatus can include a first clock generator configured to receive an input clock signal and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signal, where the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, where a relative relationship of phases of the two or more second-level clock signals to phases of respective first-level clock signals is determined at least in part by a phase of the interpolated clock signal.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office, Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. TECHNICAL FIELD

[0003] The present disclosure relates generally to methods, systems, and apparatuses for sample clock alignment in an analog-to-digital converter. BACKGROUND

[0004] Time-interleaved analog-to-digital converters (TI-ADCs) have been widely used in various systems. A TI-ADC includes a large number of individual cell-ADCs, which require multi-level sampling stages to capture and demultiplex a wideband input signal for digitization by the cell-ADCs. Given the large number of cell-ADCs within a TI-ADC, it is often required to have multi-level sampling stages to capture and demultiplex a wideband input signal for digitization by the cell-ADCs. The alignment of high-speed sample clocks between different levels directly impacts the signal conversion quality from the analog-to-digital domain. Due to the logic depth difference of the clock generators for the sample clocks of different levels, the delay time along different clock paths exhibits both different values and large process / voltage / temperature / parasitic extraction (PVTE) variations.

[0005] Accordingly, methods, systems, and apparatuses for sample clock alignment in an ADC are provided. SUMMARY

[0006] In one aspect, the disclosure relates to a method comprising: generating, via a first clock generator, two or more first level clock signals of a track-and-hold circuit based on an input clock signal, each of the two or more first level clock signals separated from a respective first level clock signal of an adjacent phase by a phase offset of lxT; generating an interpolated clock signal via a phase interpolator, wherein generating the interpolated clock signal further comprises: selecting an even first level clock signal of the two or more clock signals; selecting an odd first level clock signal of the two or more clock signals, the odd first level clock signal having a phase adjacent to a phase of the even first level clock signal; generating the interpolated clock signal based on the even first level clock signal and the odd first level clock signal, wherein the interpolated clock signal has a phase within the lxT phase offset between the even and odd first level clock signals; and generating two or more second level clock signals via a second clock generator based on the interpolated clock signal, wherein a relative relationship of phases of the two or more second level clock signals to phases of respective first level clock signals is determined at least in part by a phase of the interpolated clock signal.

[0007] In one aspect, the disclosure relates to a clock generator comprising: a first clock generator configured to receive an input clock signal and generate two or more first level clock signals of a track-and-hold circuit; a phase interpolator configured to generate an interpolated clock signal, wherein the interpolated clock signal is generated based on the two or more first level clock signals, wherein the phase interpolator comprises: a first multiplexer configured to receive an even first level clock signal of the two or more first level clock signals; a second multiplexer configured to receive an odd first level clock signal of the two or more first level clock signals; and a second clock generator configured to generate two or more second level clock signals based on the interpolated clock signal, wherein a relative relationship of phases of the two or more second level clock signals to phases of respective first level clock signals is determined at least in part by a phase of the interpolated clock signal.

[0008] In one aspect, the disclosure relates to an analog-to-digital converter comprising: a first clock generator configured to receive an input clock signal and generate two or more first-level clock signals for a track-and-hold circuit; a phase interpolator configured to generate two or more respective interpolated clock signals, wherein each respective interpolated clock signal is generated based on the two or more first-level clock signals, wherein the phase interpolator further comprises two or more phase interpolator slices, each respective phase interpolator slice further comprising: a first multiplexer configured to receive even first-level clock signals of the two or more first-level clock signals; a second multiplexer configured to receive odd first-level clock signals of the two or more first-level clock signals; two or more analog-to-digital converter slices, each respective analog-to-digital converter slice comprising: a second clock generator configured to generate two or more second-level clock signals based on the respective interpolated clock signal, wherein a relative relationship of phases of the two or more second-level clock signals to phases of a respective first-level clock signal is determined at least in part by a phase of the respective interpolated clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0009] A further understanding of the nature and advantages of certain embodiments can be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to designate similar components throughout the various figures. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification of a sub-label, it is intended to refer to all such multiple similar components.

[0010] Figure 1 is a schematic block diagram of an adaptive alignment sample clock system architecture in accordance with various embodiments;

[0011] Figure 2 is a schematic diagram of an M-phase in / out (M-phase in / out) phase interpolator in accordance with various embodiments;

[0012] Figure 3 is a schematic diagram of a 2-bit phase detector for time margin setting in accordance with various embodiments;

[0013] Figure 4 is a schematic diagram of an adaptive engine in accordance with various embodiments;

[0014] Figure 5 is a schematic diagram of an adaptive finite state machine in accordance with various embodiments; and

[0015] Figure 6 is a flowchart of a method for adaptive alignment of a sample clock in accordance with various embodiments. DETAILED DESCRIPTION

[0016] Various embodiments provide tools and techniques for adaptive alignment of a sample clock in an ADC.

[0017] In some embodiments, a method for adaptive alignment of a sample clock in an ADC is provided. The method can include generating, via a first clock generator, two or more first level clock signals of a track-and-hold circuit based on an input clock signal, each of the two or more first level clock signals separated from a respective first level clock signal of an adjacent phase by a phase offset of lxT; and generating an interpolated clock signal via a phase interpolator. Generating the interpolated clock signal can further include selecting an even first level clock signal of the two or more clock signals; selecting an odd first level clock signal of the two or more clock signals, the odd first level clock signal having a phase adjacent to a phase of the even first level clock signal; weighting the even first level clock signal with a first weighting factor to generate a weighted even first level clock signal; and weighting the odd first level clock signal with a second weighting factor to generate a weighted odd first level clock signal. The method can continue by generating the interpolated clock signal based on the weighted even first level clock signal and the weighted odd first level clock signal, where the interpolated clock signal has a phase within the lxT phase offset between the even and odd first level clock signals. The method further includes generating, via a second clock generator, two or more second level clock signals based on the interpolated clock signal, where a relative relationship of phases of the two or more second level clock signals to phases of respective first level clock signals is determined at least in part by a phase of the interpolated clock signal.

[0018] In some embodiments, an apparatus for adaptive alignment of a sample clock in an ADC is provided. The apparatus can include a first clock generator configured to receive an input clock signal and generate two or more first level clock signals of a track-and-hold circuit, and a phase interpolator configured to generate an interpolated clock signal, where the interpolated clock signal is based on the two or more first level clock signals. The phase interpolator can include a first multiplexer configured to receive even first level clock signals of the two or more first level clock signals, and a second multiplexer configured to receive odd first level clock signals of the two or more first level clock signals. The phase interpolator can further include a first digital-to-analog converter configured to generate a first vector of selected even first level clock signals from the first multiplexer weighted with a first weighting factor, and a second digital-to-analog converter configured to generate a second vector of selected odd first level clock signals from the second multiplexer weighted with a second weighting factor. The outputs of the first and second digital-to-analog converters can be configured to be added, where the added first and second vectors form the interpolated clock signal, and where the respective interpolated clock signal has a phase within the lxT phase offset between the even and odd first level clock signals. The apparatus can further include a second clock generator configured to generate two or more second level clock signals based on the interpolated clock signal, where a relative relationship of phases of the two or more second level clock signals to phases of respective first level clock signals is determined at least in part by a phase of the interpolated clock signal.

[0019] In another embodiment, a system for adaptive alignment of a sample clock in an ADC is provided. The system can include a first clock generator configured to receive an input clock signal and generate two or more first-level clock signals for a track-and-hold circuit, and a phase interpolator configured to generate two or more respective interpolated clock signals, where each respective interpolated clock signal is based on the two or more first-level clock signals, where the phase interpolator further comprises two or more phase interpolator slices. Each respective phase interpolator slice can further include a first multiplexer configured to receive even first-level clock signals of the two or more first-level clock signals, and a second multiplexer configured to receive odd first-level clock signals of the two or more first-level clock signals. Each respective phase interpolator slice can further include a first digital-to-analog converter configured to generate a first vector of selected even first-level clock signals from the first multiplexer weighted by a first weighting factor, and a second digital-to-analog converter configured to generate a second vector of selected odd first-level clock signals from the second multiplexer weighted by a second weighting factor. The outputs of the first and second digital-to-analog converters are configured to be added, where the added first and second vectors form a respective interpolated clock signal, where the respective interpolated clock signal has a phase within the lxT phase offset between the even and odd first-level clock signals. The system can further include two or more analog-to-digital converter slices. Each respective analog-to-digital converter slice can further include a second clock generator configured to generate two or more second-level clock signals based on the respective interpolated clock signal, where a relative relationship of phases of the two or more second-level clock signals to phases of respective first-level clock signals is determined at least in part by a phase of the respective interpolated clock signal.

[0020] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments. It will be apparent, however, to one skilled in the art that the embodiments can be practiced without some of these specific details. In other instances, structures and devices are shown in block diagram form. Several embodiments are described herein, and while several features are attributed to different embodiments, it will be appreciated that features from one embodiment can be combined with features of another embodiment. However, through the same token, no single feature or several features of any described embodiment should be considered essential to every embodiment of the application, as other embodiments of the application can omit such features.

[0021] Similarly, when an element is referred to as being "connected" or "coupled" to another element, it should be understood that the element can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood that no intervening elements are present. However, the presence of intervening elements does not preclude the use of the term "directly connected" or "directly coupled".

[0022] Furthermore, the processes and logic flows described herein can be described in terms of specific sequences of actions, procedures, or programs. However, it will be understood that the described processes and logic flows can be carried out in any order as the context can dictate, unless otherwise indicated, and that the various processes can be reordered, added to, or omitted, as necessary.

[0023] Unless otherwise indicated, all numbers expressing quantities, dimensions, and so forth used herein are to be understood as being modified in all instances by the term "about." In this description, unless otherwise indicated, singular forms "a," "an," and "the" include plural referents. Unless otherwise indicated, the use of "or" means "and / or" when used in a list of elements. Furthermore, the terms "comprise" and "comprising" and the like are to be construed as non-exclusive, unless otherwise indicated. Also, the use of "including" and "comprising" and "having" and "involving" and "characterized by" and "comprises" and "comprising" and the like are not meant to be limiting. Moreover, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0024] Conventional methods for clock alignment exhibit drawbacks, such as clock signal degradation, inability to control or scale PVTE variations, and increased power requirements. These techniques focus on additional components, such as stacked delay elements or fixed phase selection, which otherwise introduce additional complexity and inefficiency, increase power consumption, or lack the ability to scale in real-time under in-situ conditions.

[0025] Accordingly, the embodiments set forth below allow for a more robust, scalable, and power-efficient way to align sample clock signals. In particular, the embodiments below describe the design and use of an M-phase input / M-phase output phase interpolator for generating and adjusting a second-level clock signal in a track-and-hold circuit, and adaptive logic for adjusting the alignment of a corresponding sample clock signal.

[0026] To the extent there are any abstract concepts in the various embodiments, those concepts can be implemented by apparatuses, logic, systems, and methods that involve novel functionality (e.g., adaptive alignment of sample clocks within an ADC with an M-phase input / output phase interpolator), as described herein. Advantages of the methods set forth below can include a highly power and area efficient approach for sample clock alignment. The proposed embodiments can utilize an M-phase input / output phase interpolator as both an adaptive sample clock alignment circuit and an internal clock lane driver. In some examples, no additional power consumption or silicon area can be needed on the high-speed clock path by replacing the original lane driver. Furthermore, the embodiments below can provide multi-level sample clock alignment, with coverage of the entire sample window and very fine adjustment steps. The embodiments can advantageously provide accurate detection of alignment errors and create a stable time margin for performance degradation introduced by sample timing. Furthermore, the time margin can be flexibly redefined on-the-fly for performance optimization. For example, as will be described in greater detail below, the system adaptively adjusts the sample clock alignment for any PVTE variation and data rate variation.

[0027] Furthermore, some of the embodiments set forth below can run in the background without interfering with the normal operation of the distributed TI-ADC and DSP, avoiding any increase in computational overhead. Some examples set forth below can also allow time-interleaved ADCs to push the maximum sampling speed while mitigating timing-related sample errors. For example, in a trial test, a new design has reached >180GS / s. Additional examples can allow time-interleaved ADCs to cover a much wider data rate range, which is critical for multi-standard compliant SerDes applications. For example, in a latest generation of ADC-DSP based SerDes chips at 5nm, a data range as large as 40GS / s to 56GS / s can be covered, and it can support as low as 10GS / s mode in future generations.

[0028] Figure 1 is a schematic block diagram of a system 100 for sample clock alignment in an ADC. The system 100 includes an ADC 105 (which includes one or more ADC slices 105a-105m), one or more sub-ADCs 110a-110m, a first level clock signal 115, a clock generator 120, a slice re-timer circuit 125, an M-phase in / out phase interpolator 130, a clock divider 135, a skew adjustment circuit 140, a track-and-hold replica circuit 145, an ADC replica circuit 150, a 2-bit phase detector 155, an adaptive engine 160, and an ADC re-timer circuit 165. It should be noted that the various components of the system 100 are schematically illustrated in Figure 1 and modifications to the various components of the system 100 and other arrangements can be possible according to various embodiments.

[0029] In various embodiments, the ADC 105 may include one or more ADC slices 105a to 105m, which may include a first ADC slice 105a(I0) to an m-th ADC slice 105m(I0). M-1 ), where "m" is an integer. Therefore, in various embodiments, ADC 105 may be a time-interleaved ADC comprising one or more ADC slices. The first ADC slice 105a may include a first-level clock signal 115 (φ) of a track-and-hold (T&H) circuit (e.g., a multi-level T&H circuit). 1,0 In some embodiments, this can be generated by a clock generator, such as a first clock generator. In various examples, the T&H circuit, also referred to as the "sample and hold" circuit, can be the input sampling circuit of the ADC 105. Figure 1 As shown, the T&H circuit can be represented as an analog switch and capacitor. When the switch is closed, the circuit operates in "track" mode to track the input signal (e.g., the first-level clock signal 115), and when the switch is open, the circuit operates in "hold" mode to hold the last instantaneous value of the input signal held at the capacitor.

[0030] In some instances, clock generator 120 may include a first clock generator. In various instances, one or more second-level ADC clock signals (φ) 2,0,0 φ 2,0,1 、…、φ 2,0,N-1 The clock signal can be generated by clock generator 120 based on the corresponding interpolated clock signal ck_pi<0:M-1>, and in the illustrated example, the second-level ADC clock signal can be based on the first interpolated clock signal ck_pi. <0> In some instances, clock generator 120 may be a second clock generator configured to generate a second-level clock signal for the T&H circuit. The first ADC slice 105a may further include one or more sub-ADCs 110a to 110n, which may include a first sub-ADC 110a to an nth sub-ADC 110n, where "n" is an integer. The output of each of the sub-ADCs 110a to 110n may be output to a slice retimer circuit 125, which may be configured to align the output of each sub-ADC to the same clock phase, such that ADC slice 105a may output data to an ADC retimer circuit 165 for further retiming of each corresponding ADC slice 105a to 105m. Each ADC slice 105a to 105m may include several sets of similar corresponding components corresponding to the components of the first ADC slice 105a.

[0031] In various examples, an input clock signal, such as an I / IB / Q / QB clock from a receiver phase-locked loop (PLL), can be divided via divider 135. Divider 135 can be a clock divider configured to divide an input clock into M divided clocks corresponding to each channel (e.g., ADC slices 105a-105m) of ADC 105. The divided clock signals are then provided to skew adjustment circuit 140, which can be configured to remove sampling time mismatches at the T&H. In some examples, clock skew can be adjusted by adjusting the number of clock inverters turned on. Thus, in various examples, a first level clock signal 115 can be generated and provided to respective ADC slices 105a-105m and further provided to M-phase in / out phase interpolator 130.

[0032] In various embodiments, M-phase in / out phase interpolator 130 can include M interpolator slices, each accepting M-phase inputs (ck<0:M-l>) and generating M-phase outputs (ck pi<0:M-l>). The first level clock signal can be extracted and replicated for adaptation of a second level clock signal via M-phase in / out phase interpolator 130 via TH replication circuit 145. The second level ADC clock signal can similarly be extracted from clock generator 120 via ADC replication circuit 150 and replicated. In various examples, ADC replication circuit 150 can include respective circuitry to extract each respective second level clock signal for each sub-ADC. The outputs of TH replication circuit 145 and ADC replication circuit 150 can be provided to 2-bit phase detector 155. In some examples, 2-bit phase detector 155 can be configured to detect the relative position of the sample clocks of each of the first level clock signal and respective second level ADC clock signals. The output of 2-bit phase detector 155 can be coupled to adaptive engine 160.

[0033] In various embodiments, adaptive engine 160 can be configured to adapt clock rate variations and process, voltage, temperature, and extraction (PVTE) variations based on the detected relative position of the sample clocks. Thus, adaptive engine can output phase interpolator control signals to adjust the output of M-phase in / out interpolator 130, which in turn can adjust the input clock of clock generator 120.

[0034] The M-phase input / M-phase output phase interpolator (e.g., M-phase input / output phase interpolator 130) generates an adjusted second-level ADC clock (e.g., a sample clock) within each ADC slice 105a to 105m of the ADC 105 via a background adaptive control algorithm controlled by the adaptive engine 160. The M-phase input / output phase interpolator is used both to adjust the timing between the first-level and second-level sample clocks (e.g., the first-level clock signal and the second-level ADC clock signal) and to drive the long-route clock distribution path within the ADC 105. Furthermore, adjustment via the M-phase input / output phase interpolator 130 allows adjustment in M-step resolution over the entire cycle of the first-level sample clock, thereby allowing alignment of the second-level sample clock (e.g., the second-level ADC clock signal). The sample clock alignment resolution inherently scales with the input data rate, thus alignment via the M-phase input / output phase interpolator 130 further supports a wide data rate range.

[0035] In another embodiment, the time margin of the second-level ADC clock signal can be adjusted via the M-phase in / out phase interpolator 130. Specifically, the relative positions of the sample clocks of the first-level tracking and holding (e.g., the first-level clock signal) and the second-level ADC (e.g., the second-level ADC clock signal) can be extracted and / or copied via the copy circuit, the TH copy circuit 145, and the ADC copy circuit 150, respectively. As previously described, the relative positions (e.g., phases) of the sample clocks can be detected via a 2-bit phase detector 155, while the first-level clock signal remains undisturbed. The sample clock alignment time margin is defined using phase and therefore inherently scales with changes in the input data rate and can be redefined on demand.

[0036] Therefore, the adaptive engine 160 can be configured to combine the control of the M-phase in / out phase interpolator 130 with a 2-bit alignment error detection scheme and a background adaptive algorithm to provide real-time online tracking of clock rate changes and PVTE changes. Utilizing the fine unit-time steps provided by the M-phase in / out phase interpolator 130, real-time and in-situ adaptation are supported without interfering with the timing requirements within the ADC 105 digital logic or the interface between the ADC 105 and the DSP core.

[0037] Figure 2 This is a schematic diagram of an M-phase in / out phase interpolator 200 (hereinafter “PI 200”) according to various embodiments. PI 200 includes one or more PI slices 205a to 205m, which may include a first PI slice 205a (I0) to an m-th PI slice 205m (I... M-1). The first PI slice 205a can include a first multiplexer 210 and a second multiplexer 215 coupled to a first digital-to-analog converter (DAC) 220 and a second DAC 225, respectively. It should be noted that various components of the PI 200 are illustrated schematically in Figure 2 and modifications to the various components of the PI 200 and other arrangements can be possible in accordance with various embodiments.

[0038] Accordingly, in various embodiments, each PI slice 205a-205m can take in M-phase inputs (with 1xT space between each adjacent phase) and produce M-phase outputs. Each PI slice 205a-205m is coupled to an M-phase input clock (e.g., a first level clock signal) such that it advances 1 phase from the previous slice in a circular fashion, thereby enforcing the phase relationship of the output M-phase signal ck pi. The output of the PI 200 can be M clock signals ck pi <0:M-1>, where each clock signal ck pi0- ck pi M-1 is a phase-shifted clock signal separated by M steps (e.g., 1xT space between adjacent phases) within a time period MxT (e.g., one period of the first level clock). Accordingly, continuing with the above example, the signals with adjacent phases (e.g., the one or more first level clock signals, the one or more second level clock signals, and / or the one or more interpolated clock signals) are the phase closest signals in the MxT space. In some examples, the falling edge of the second level ADC clock signal φ 2,0,0 may be adjusted based on the phase shift of the corresponding interpolated clock signal ck pi (e.g., ck pi0) such that the falling edge of the second level ADC clock signal φ 2,0,0 may correspond to the entire MxT period of the first level clock signal.

[0039] Each PI slice 205a-205m can include two multiplexers (a first multiplexer 210 and a second multiplexer 215), respectively. In some examples, the first and second multiplexers 210, 215 can be M / 2: 1 multiplexers. Accordingly, the first multiplexer 210 can be coupled to even input clock signals (ck0- ck M-2 ), e.g., even first level clock signals, while the second multiplexer 215 can be coupled to odd input clock signals (ck1- ck M-1 ), e.g., odd first level clock signals. In various examples, the output of the first multiplexer 210 can be denoted as cka, while the output of the second multiplexer 215 can be denoted as ckb. The pair of outputs ckaand ckbmay thus provide any two adjacent phases of the clock signals across the entire MxT range, with a 1xT time interval between adjacent phases. In some examples, the adjacent phases can be set by even-side and odd-side multiplexer selection codes.

[0040] In various examples, the output ckaand ckbmay be weighted via respective DACs (first DAC 220 and second DAC 225). In some embodiments, the first DAC 220 and the second DAC 225 can be s-bit thermometer DACs. The first DAC 220 can weight cka with a first weighting factor wa, and the second DAC 225 can weight ckbwith a second weighting factor wb. Thus, the weighted clock signals wa*ckaand wa*ckbmay be added in vector form by the two output connected s-bit thermometer DACs to produce an interpolated clock signal ck_p1 within a 1xT timing interval. In some further examples, the phase within the 1xT timing space can be selected by the selection of the weighting factors waand wb.

[0041] second level ADC clock signal φ 2,i,j may be moved in accordance with the output of the phase interpolator. Thus, the entire MxT period of the first level clock signal φ 1,i of the T&H can be covered, and the alignment between these two levels can be adjusted, and the desired alignment achieved.

[0042] Figure 3 is a schematic diagram of a 2-bit phase detector 300 (hereinafter "PD 300") for time margin setting in accordance with various embodiments. The 2-bit phase detector 300 can include a first phase detector 305 and a second phase detector 310. It should be noted that various components of the PD 300 are schematically illustrated in Figure 3 , and modifications to the various components of the PD 300 and other arrangements can be possible in accordance with various embodiments.

[0043] In some examples, the first and second phase detectors 305, 310 can include, for example, flip-flops. In one example, the first and second phase detectors 305, 310 can be implemented as D flip-flops. In various embodiments, the input of the first phase detector 305 can be configured to accept a replicated first first level clock signal φ Figure 1 from the TH replication circuit 145 of the 1,0 . Thus, the replicated first level clock signal can serve as a reference for the first phase detector 305 (e.g., D flip-flop). Similarly, the input of the second phase detector 310 can be configured to accept a replicated (M-l-R) first level clock signal φ 1,M-1-R . Each of the reference signals φ 1,0 and φ 1,M-1-R may be clocked by the replicated second level ADC clock φ 2,0,0 (e.g., at the clock input of the D flip-flop). In some examples, the replicated second level ADC clock φ 2,0,0The ADC replica circuit 150 can be obtained from Figure 1 .

[0044] In various embodiments, the left margin of the second level ADC clock can be defined as the time space between the rising edge (hold edge) of the first level track-and-hold clock (e.g., first level clock signal) φ 1,0 and the rising edge (sample edge) of the second level ADC clock φ 2,0,0 . Any timing violations can result in the overlap of the setup time window of the track-hold and ADC. The right margin can be the time space between the falling edge (sample edge) of the first level track-hold clock and the falling edge (hold edge) of the second level ADC clock. Any timing violations can result in incorrect sampled data. Thus, the sample clock can be aligned to ensure proper left and right margins.

[0045] In some examples, the alignment target can be set to adaptively maintain a time space RxT from the falling edge (sample edge) of the second level ADC clock to the falling edge of the first level clock. Thus, in some examples, RxT can be set as (PxT - QxT) / 2. As shown in the example timing diagram, in such examples, the left margin & right margin can be evenly distributed (e.g., set equal to each other).

[0046] Thus, by using the (M-1-R)th first level clock signal, where M-1-R is an integer, the phase relationship between the first level clock signals can be used to generate the correct time margins. In other words, the inherent time difference between different phases of the first level clock signals is used to establish a reference for the time margins. Specifically, the replicated first level clock signal φ 1,0 can be used as a reference for pdl, and the replicated first level clock signal φ 1,M-1-R can be used as a reference for pd2. For the right margin, both reference waveforms can be sampled by the falling edge of the replicated second level ADC clock φ 2,0,0 to create the RxT right margin.

[0047] In some examples, the PD 300 can be placed in a locked state. In the locked state, pd2 can be aligned to the falling edge of the replicated φ 1,M-1-R , while pdl is away from the falling edge of the replicated φ 2,0,0the falling edge of the rising edge of the reference clock signal. Thus, the lock state inherently provides the target time margin as a time difference between the two bits (pd1 and pd2) of the PD 300. In further examples, in addition to the lock edge itself, the 2 bits of the PD 300 can provide 1 bit more time alignment information between the first and second level sample clocks. Thus, it is useful to monitor the state and avoid any false lock near the rising / falling edge region, and furthermore since the reference clock signal is only relative in phase and not affected by PVTE variations. Thus, in various examples, the absolute value of the left / right margin defined by the relative phase allows the timing margin to scale with changes in clock rate, and further supports a wide data rate tuning range.

[0048] Figure 4 is a schematic diagram of an adaptive engine 400 according to various embodiments. The adaptive engine 400 can include a majority voter logic 405, an adaptive finite state machine (FSM) 410, a wait counter 415, and a phase interpolator (PI) controller 420. It should be noted that various components of the adaptive engine 400 are schematically illustrated in Figure 4 and modifications to the various components of the adaptive engine 400 and other arrangements can be possible according to various embodiments.

[0049] In various embodiments, the majority voter logic 405 can be configured to accept the outputs pd1 and pd2 of the PD 300 as bit inputs. The majority voter logic 405 can be coupled to the adaptive FSM 410, which can receive a majority vote of pd1 and pd2 and a ready bit as inputs. The adaptive FSM 410, in turn, can be coupled to the PI controller 420 and the wait counter 415.

[0050] In some examples, the majority voter logic 405 can be a logic circuit configured to determine a majority vote of the inputs pd1 and pd2. Thus, the majority voter logic 405 can average the noise effects of the respective outputs pd1 / pd2 to produce denoised phase detector results pd1_major (e.g., a majority voted pd1) and pd2_major (e.g., a majority voted pd2). The denoised results can then be sent to the adaptive FSM 410. The majority voter logic 405 can further output a ready signal to the adaptive FSM 410 that can indicate that the next results are ready, and receive a next signal from the adaptive FSM 410 that can indicate to the majority voter logic 405 to generate the next denoised results of pd1 and pd2.

[0051] Similarly, the adaptive FSM 410 can be implemented as digital logic and configured to determine a left shift (axLSB) and / or a right shift (bxLSB) of the phase interpolator based on previous and current outputs of the phase detector. Thus, the PI controller 420 can update the PI control code pi-ctrl based on the adaptive FSM 410 determining the left or right shift and the current position of the phase interpolator with respect to the first level clock signal (e.g., as determined based on the true clock path second level ADC clock signal in the respective ADC slice).

[0052] In some examples, the wait counter 415 can be set to wait for a timeout duration corresponding to a time for which the PI rotation stabilizes to act on the analog side before the next result is determined. Thus, once the wait counter 415 asserts a timeout signal indicating that the timeout duration has elapsed, the adaptive FSM 410 can complete the cycle by indicating to the master voter 405 to start the next voting cycle.

[0053] In various examples, a digital offset can be provided after the lock state is detected after the adaptive cycle. The digital offset can include shifting the output of the phase interpolator left or right by an additional preset step. The digital offset allows for an offset of any potential systematic differences between the true clock path (e.g., of the replicated first level clock signal and the replicated second level ADC clock signal) and the replica clock path, and the lock is based on information provided by the replica path. In further examples, the digital offset provided by the adaptive engine 400 can further allow for flexible readjustment of the left / right time margin from the hardwired RxT time space for tunable on-the-fly adjustment of the sampling clock, as will be described in further detail below with respect to Figure 5 FIG. 5.

[0054] Figure 5 is a schematic diagram of an adaptive finite state machine 500 (hereinafter “FSM 500”) in accordance with various embodiments. The FSM 500 can start in a state initialization 505 from which one of four states (state 0 510, state 1 515, state 2 520, and state 3 525) can be entered. In various embodiments, the state can be determined using a first level tracking and hold clock (e.g., the first level clock signal φ 1,0 ) and a second level ADC clock (e.g., the second level ADC clock signal φ 2,0,0 ) based on a 2-bit phase detector output (e.g., the PD 300).

[0055] State 0 510 can correspond to phase detector outputs of pdl = 0 (e.g., logic low) and pd2 = 0 (e.g., logic low). In this state, the FSM 500 can determine that the phase interpolator (e.g., M-phase in / out phase interpolator 200) should be shifted left. State 1 515 can correspond to phase detector outputs of pdl = 1 (e.g., logic high) and pd2 = 1 (e.g., logic high), in which case the phase interpolator should be shifted right. State 2 520 can correspond to phase detector outputs of pdl = 1 (e.g., logic high) and pd2 = 0 (e.g., logic low), in which case the phase interpolator should be shifted left. State 3 525 can correspond to phase detector outputs of pdl = 0 and pd2 = 1, in which case the phase interpolator should be shifted left. In various embodiments, the major voted outputs of the phase detectors, pdl_major and pd2_major, can be used as the pdl and pd2 outputs.

[0056] In various embodiments, a background adaptation procedure can be implemented via the FSM 500. At the initial step of each adaptation loop, the current relative position between the first level tracking and holding clock (e.g., first level clock signal) and the second level ADC clock signal can be obtained at state initialization 505. Based on the current state (State 0 510, State 1 515, State 2 520, and State 3 525) determined by the major voted phase detector outputs (e.g., pdl_major and pd2_major). In particular, the output of the phase interpolator can be shifted left or right, as previously described, until entering State 2 520 or pdl = 1 and pd2 = 0. According to some examples, in State 2, the phase interpolator can be continuously shifted left until reaching the condition pdl = 1 and pd2 = 1 from State 2 520 and entering state lock 530.

[0057] In various examples, the lock state (e.g., state lock 530) can follow the unidirectional consistent lock scheme described above for detection. In other words, once having entered State 2 520, the phase interpolator can be continuously shifted left in one direction to ensure right-to-left lock. In other examples, other lock schemes can be used, such as a left-to-right lock scheme. In various examples, a consistent unidirectional lock scheme is employed, such as a left-to-right lock scheme or a right-to-left lock scheme. In some examples, by utilizing a unidirectional lock scheme, the least significant bit (LSB) error introduced by the last shift of the phase interpolator at lock can be consistent. In particular, in right-to-left lock, the lock state is always detected as a transition from State 2 to State 1, and thus always absorbs the LSB error as a left margin reduction. Conversely, in a left-to-right lock scheme, the lock state is always detected as a transition from State 1 to State 2, and thus always absorbs the LSB error as a right margin reduction. Thus, by employing a unidirectional lock scheme, the impact of the LSB error can be limited to continuously impacting the margin of the respective side.

[0058] Once the lock state 530 has been detected, state offset 535 can be entered. In state offset 535, the adaptive FSM 500 can determine a digital offset based on systematic features and / or settings and add the digital offset to the phase interpolator. As previously described, the digital offset can include a left or right shift of the output of the phase interpolator by an additional preset step. The digital offset can allow for an offset of any potential systematic differences between the true clock path and the replica clock path, and the lock is based on the information provided by the replica path. In further examples, the digital offset can further allow for flexible readjustment of the left / right time margins from the hardwired RxT time space for tunable on-the-fly adjustment of the sampling clock.

[0059] In some examples, at block 540, a timer can be set to a preset value defining an adaptive interval. Within the FSM 500, the timer can be used as a global timer utilized after the lock state has been entered and the digital offset has been determined and / or applied. In some examples, the timer can have a preset value or preset duration, which can be referred to as a global wait duration. In some examples, the global wait duration can be preset according to system requirements or based on performance metrics. For example, the global wait duration can be determined based at least in part on power consumption, environmental conditions (e.g., temperature), or chip-specific variations (e.g., PVTE variations), and / or performance metrics (e.g., throughput, bandwidth, etc.). Thus, once the adaptive FSM 500 has entered the lock state and the digital offset has been determined, the adaptive FSM 500 can wait for the timeout duration to elapse at block 545. When the timer is full, at decision block 550, the adaptive loop can be reinitiated to determine the current state based on the relative positions of the first level clock signal and the second level ADC clock signal, and the adaptive process as previously described is repeated until the next lock state is achieved.

[0060] Figure 6 is a flow diagram of a method 600 for adaptive alignment of a sample clock according to various embodiments. The method 600 begins at block 605 by generating two or more first level clocks. As previously described, in some examples, the first level clocks can be first level clock signals generated by a T&H circuit based on an input clock signal. In some examples, the input clock signal can include I / IB / Q / QB clocks, for example, from a receiver phase-locked loop (PLL). In some further examples, the two or more first level clock signals can be generated by frequency dividing the input clock signal into equal slices (e.g., M ADC slices of a time-interleaved ADC) via a clock divider.

[0061] Method 600 can continue at block 610 by generating an interpolated clock. As previously described, in various embodiments, the interpolated clock can be generated via an M-phase input / M-phase output phase interpolator, such as an M-phase in / out phase interpolator. In some examples, the M-phase in / out phase interpolator can be configured to receive each of two or more first-level clock signals. In some examples, each of the two or more first-level clock signals can be offset from an adjacent phase by a phase offset of lxT. Thus, any two adjacent first-level clock signals can have a phase offset of lxT. Even first-level clock signals can be fed to a first M / 2: 1 multiplexer, while odd first-level clock signals can be fed to a second M / 2: 1 multiplexer. The multiplexers can be configured to select two adjacent first-level clock signals, ckaand ckb. The selected clock signals can then be interpolated. In some examples, the interpolated clock signal can include first weighting each of ckaand ckb, and summing the weighted clock signals in vector form. In some examples, even first-level clock signals can be weighted with a first weighting factor, wa, and odd first-level clock signals can be weighted with a second weighting factor, wb. In this way, the interpolated clock signal can be generated by adding the weighted first-level clock signals, wa*cka+ wb*ckb, in vector form. In some examples, the weighted vector of respective clock signals, ckaand ckb, can be generated by respective s-bit thermometer DACs. In this way, an interpolated clock signal having a phase in the lxT space between adjacent phase clock signals of the first-level clock signals can be generated by selecting adjacent phase clock signals and adjusting the first and second weighting factors. In some examples, the first and second weighting factors can be adjustable, while in other examples, the first and second weighting factors can be hard-coded via respective logic.

[0062] At block 615, method 600 continues by generating two or more second-level clocks based on the interpolated clock. As previously described, the phases of the second-level clock signals, φ 2,i,j , within each ADC slice can follow the output of the M-phase in / out phase interpolator and specifically the interpolated clock signal movement. Thus, the interpolated clock signal, including the interpolated clock signal determined above, can cover the entire MxT period of the respective first-level clock signals, and the two or more second-level clock signals can be generated based on the interpolated clock signal.

[0063] At block 620, method 600 continues by waiting for a timeout duration. In various examples, the timeout duration can be determined based on the time needed for the PI to rotate in to be stable to act on the analog side. In some examples, the timeout duration can be controlled via a counter or other suitable hardware.

[0064] The method 600 continues at block 625 by determining sample clock alignment. As previously described, in some examples, the alignment target can be set to adaptively maintain a falling edge (sample edge) of the second level ADC clock a time space RxT from a falling edge of the first level clock. Thus, in some examples, RxT can be set to (PxT - QxT) / 2, which is half of the margin where the falling edge of the second level ADC clock is as high as the falling edge of the first level clock with phase offset M-1-R. This arrangement can help ensure that the left and right margins are evenly distributed based on the replicated clock signals (e.g., set to be equal to each other).

[0065] Thus, by using the (M-1-R)th first level clock signal, where M-1-R is an integer, the phase relationship between the first level clock signals can be used to produce the correct time margins. In other words, the inherent time difference between the different phases of the first level clock signals is used to establish a reference for the time margins. Specifically, in some examples, the replicated first level clock signal φ 1,0 can be used as a reference for pd1, and the replicated first level clock signal φ 1,M-1-R can be used as a reference for pd2. For the right margin, the two reference waveforms can be sampled by the falling edge of the replicated second level ADC clock φ 2,0,0 to create the RxT right margin.

[0066] Any timing violations can result in an overlap of the track-hold and the settling time window of the ADC. The right margin can be a time space between a falling edge (sample edge) of the first level track-hold clock and a falling edge (hold edge) of the second level ADC clock. Any timing violations can result in incorrect sampled data. Thus, the sample clock can be aligned to ensure proper left and right margins. In some examples, the alignment of the sample clock can be determined using a phase detector, such as the 2-bit phase detector previously described with respect to Figure 3

[0067] In further embodiments, the current state of the adaptive FSM can be determined based on the sample clock alignment (e.g., the output of the phase detector). As previously described, an adaptive engine can be implemented to determine the sample clock alignment, and to shift the phase interpolator until alignment has been achieved. As previously described, the adaptive engine can include a majority voter configured to determine a majority of the outputs pd1 and pd2 of the phase detector. In effect, the majority voter circuit can be configured to produce a denoised output of the phase detector for further adaptation and alignment of the sample clock. Based on the denoised output of the phase detector, the current state can be determined to be one of four states: state 0, state 1, state 2, and state 3. Each state can correspond to different phase detector outputs pd1 and pd2, which can be indicative of the alignment of the sample clock.

[0068] ​The method 600 continues at 630 by determining whether a lock state has been entered. As previously described, the lock state can be determined based on a lock scheme. As previously described, a consistent unidirectional lock scheme can be implemented, such as a left-to-right lock scheme or a right-to-left lock scheme. In some examples, by utilizing a unidirectional lock scheme, LSB errors introduced by the last shift of the phase interpolator at lock can remain consistent. Specifically, in a right-to-left lock, the lock state is always detected as a transition from state 2 to state 1, and thus always absorbs LSB errors as a left margin reduction. Conversely, in a left-to-right lock scheme, the lock state is always detected as a transition from state 1 to state 2, and thus always absorbs LSB errors as a right margin reduction. Thus, by employing a unidirectional lock scheme, the impact of LSB errors can be limited to consistently impacting the margin of the respective side. Accordingly, in some examples, the lock state can be determined based on a particular state transition.

[0069] If it is determined that a lock state has not been entered, the method 600 can continue at block 635 by determining a phase interpolator shift. As previously described, in various embodiments, the phase interpolator shift can include the phase interpolator being shifted left or right based on a previous output and a current output of the phase detector (e.g., a state of the adaptive state machine). Specifically, in some examples, an adaptive engine can be implemented to determine a phase shift and adjust the phase interpolator. As previously described, the adaptive engine can determine a state based on the output of the phase detector, and each state can further correspond to a left shift or a right shift of the phase interpolator. Once a left shift or a right shift has been determined based on the state, the method 600 can continue at block 640 by shifting the phase interpolator and, in turn, shifting the interpolated clock. As previously described, in examples, to shift the interpolated clock signal, the PI controller can update the PI control code pi-ctrl based on the adaptive FSM determining a left shift or a right shift (including a digital offset and / or a left shift or a right shift based on a state) and a current position of the phase interpolator with respect to the first level clock signal (e.g., as determined based on the true clock path second level ADC clock signal in the respective ADC slice). In some examples, pi-ctrl can include code for selecting an adjacent phase first level clock signal in order to achieve a left shift or a right shift. In some further examples, pi-ctrl can include code for adjusting weighting factors to create a left shift and / or a right shift within the lxT space between adjacent phases. Once the interpolated clock has been shifted, the method 600 can generate an updated (e.g., shifted) interpolated clock signal at block 610 from which an updated second level clock can be generated.

[0070] If it is determined at block 630 that the lock state has been entered, the method can continue at block 645 by determining a digital offset. As previously described, once the lock state has been detected, the adaptive FSM can determine a digital offset to be added to the phase interpolator based on the settings. As previously described, the digital offset can include a left or right shifting of the output of the phase interpolator by an additional preset step size. The digital offset can allow for an offset of any potential systematic differences between the true clock path and the replica clock path, and the lock is based on the information provided by the replica path. In further examples, the digital offset can further allow for flexible readjustment of the left / right time margins from the hardwired RxT time space for tunable on-the-fly adjustment of the sampling clock. Once the digital offset has been determined, the digital offset can similarly be provided to the PI controller to implement a corresponding shift to the interpolated clock signal.

[0071] The method 600 can continue at block 650 by waiting for a global timer duration. As previously described, in some examples, the timer can have a preset value or preset duration, which can be referred to as a global wait duration. In some examples, the global wait duration can be preset according to system requirements or based on performance metrics. For example, the global wait duration can be determined based at least in part on power consumption, environmental conditions (e.g., temperature), or chip-specific variations (e.g., PVTE variations), and / or performance metrics (e.g., throughput, bandwidth, etc.). When the timer is up, at block 625, the method can continue by reinitiating the adaptive process by again determining the current sample clock alignment and current state based on the relative positions of the first and second level ADC clock signals.

[0072] The techniques and processes described above with respect to various embodiments can be performed by one or more systems 100 and / or subsystems and components thereof, such as the PI 200, PD 300, adaptive engine 400, and FSM 500 described above with respect to Figures 1 to 5 the various other embodiments as described herein.

[0073] While some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Further, although for ease of description, various methods and processes described herein can be described with respect to particular structural and / or functional components, the methods provided by various embodiments are not limited to any particular structural and / or functional architecture but can be implemented in any suitable hardware configuration. Similarly, although some functionality is ascribed to one or more system components, unless the context demands otherwise, this functionality can be distributed among various other system components in accordance with the several embodiments.

[0074] Furthermore, although the procedures of the methods and processes described herein are described in a particular order, unless the context indicates otherwise, various procedures can be reordered, added, and / or omitted according to various embodiments. Moreover, the procedures described with respect to one method or process can be incorporated into other described methods or processes; likewise, system components described according to a particular structural architecture and / or with respect to one system can be organized in alternative structural architectures and / or incorporated into other described systems. Therefore, although the foregoing describes several embodiments, it is understood that the inventive subject matter is not limited to the embodiments specifically described, unless the context indicates otherwise.

Claims

1. A method for clock alignment, comprising: A first clock generator generates two or more first-level clock signals based on an input clock signal for a tracking and holding circuit, each of the two or more first-level clock signals being separated from the corresponding first-level clock signal of an adjacent phase by a phase offset of 1xT. Generating an interpolated clock signal via a phase interpolator, wherein generating the interpolated clock signal further includes: Select an even-numbered first-level clock signal from the two or more clock signals; Select an odd-numbered first-level clock signal from the two or more clock signals, wherein the odd-numbered first-level clock signal has a phase adjacent to that of the even-numbered first-level clock signal; The interpolated clock signal is generated based on the even-numbered first-level clock signal and the odd-numbered first-level clock signal, wherein the interpolated clock signal has a phase within the 1xT phase offset between the even-numbered and odd-numbered first-level clock signals; and Two or more second-level clock signals are generated via a second clock generator based on the interpolated clock signal, wherein the relative phase of the two or more second-level clock signals to the phase of the corresponding first-level clock signal is at least partially determined by the phase of the interpolated clock signal.

2. The method of claim 1, wherein generating the interpolated clock signal further comprises: The even-numbered first-level clock signal is weighted by a first weighting factor to generate a weighted even-numbered first-level clock signal; The odd-numbered first-level clock signal is weighted by a second weighting factor to generate a weighted odd-numbered first-level clock signal; The weighted even-level clock signal and the weighted odd-level clock signal are added in vector form, wherein the vector addition of the even-level clock signal and the odd-level clock signal is generated by a corresponding digital-to-analog converter.

3. The method according to claim 1, further comprising: Determine the alignment between the first second level clock signal and the first first level clock signal, wherein determining the alignment between the first second level clock signal and the first first level clock signal includes determining the phase offset between the falling edge of the first first level clock signal and the falling edge of the first second level clock signal; and The interpolated clock signal is shifted based on the phase shift.

4. The method of claim 3, wherein determining the alignment between the first second-level clock signal and the first first-level clock signal further comprises: The first phase detector of the 2-bit phase detector receives a copied first-level clock signal at its input. At the input of the second phase detector of the 2-bit phase detector, a second first-level clock signal is received, wherein the second first-level clock signal is phase-shifted from the first first-level clock signal by a time margin. The first and second phase detectors receive the copied first and second level clock signals as clock inputs; A first phase detector output is generated that indicates the value of the first first-level clock signal; and A second phase detector output is generated that indicates the value of the second first level clock signal.

5. The method of claim 4, further comprising: The phase interpolator shift is determined at least in part based on the outputs of the first phase detector and the second phase detector, wherein determining the phase interpolator shift includes determining the state based on the outputs of the first phase detector and the second phase detector; and The phase interpolator is shifted by the phase shift of the interpolated clock signal until it enters a locked state.

6. The method according to claim 5, wherein the state is one of a first state, a second state, a third state, or a fourth state. In the first state, both the outputs of the first and second phase detectors are logic low, and the phase interpolator shift is to the left. In the second state, both the first phase detector output and the second phase detector output are logic high, and the phase interpolator shift is to the right. In the third state, the output of the first phase detector is logic high and the output of the second phase detector is logic low, and the phase interpolator shifts to the left. In the fourth state, the output of the first phase detector is logic low and the output of the second phase detector is logic high, and the phase interpolator shifts to the left.

7. The method of claim 6, wherein entering the locked state according to a locking scheme, wherein the method further comprises: In response to determining that a transition has been made from the second state to the first state, the locked state is entered; In response to entering the locked state, the digital offset is determined at least in part based on the difference between the actual clock path of the first and second level clock signals and the copied clock path of the copied first and second level clock signals.

8. A clock generator comprising: A first clock generator is configured to receive an input clock signal and generate two or more first-level clock signals for a track and hold circuit. A phase interpolator configured to generate an interpolated clock signal, wherein the interpolated clock signal is generated based on the two or more first-level clock signals, wherein the phase interpolator comprises: A first multiplexer is configured to receive an even number of first-level clock signals from the two or more first-level clock signals; A second multiplexer configured to receive an odd number of the two or more first-level clock signals; and A second clock generator is configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the relative phases of the two or more second-level clock signals to the phases of corresponding first-level clock signals are at least partially determined by the phases of the interpolated clock signal.

9. The clock generator of claim 8, wherein the phase interpolator further comprises: A first digital-to-analog converter is configured to generate a first vector weighted by a first weighting factor from a selected even-numbered first-level clock signal from the first multiplexer; and A second digital-to-analog converter is configured to generate a second vector from the second multiplexer, weighted by a second weighting factor, based on a selected odd first-level clock signal. The outputs of the first and second digital-to-analog converters are configured to be added to generate added first and second vectors, wherein the added first and second vectors form the interpolated clock signal, wherein the corresponding interpolated clock signal has a phase within the 1xT phase offset between the even and odd first level clock signals.

10. The clock generator of claim 8, further comprising: A 2-bit phase detector coupled to the first clock generator, the second clock generator, and the phase interpolator, the 2-bit phase detector being configured to determine alignment between a first second-level clock signal and a first first-level clock signal, wherein determining alignment between the first second-level clock signal and the first first-level clock signal includes determining phase offset between the falling edge of the first first-level clock signal and the falling edge of the first second-level clock signal.

11. The clock generator of claim 10, wherein the 2-bit phase detector comprises: A first phase detector is configured to receive a copied first first level clock signal at the input of the first phase detector and a copied first second level clock signal at the clock input of the first phase detector. A second phase detector is configured to receive a replicated second first-level clock signal and the replicated first and second-level clock signals at the clock input of the second phase detector, wherein the second first-level clock signal is phase-shifted from the first first-level clock signal by a time margin. The first phase detector is configured to generate a value indicating the first level clock signal. The output of the first phase detector; and The second phase detector is configured to generate a value indicating the second first-level clock signal. Output of the second phase detector.

12. The clock generator of claim 11, further comprising: An adaptive finite state machine configured to determine a phase interpolator shift based at least in part on the outputs of the first and second phase detectors, wherein determining the phase interpolator shift includes determining a state based on the outputs of the first and second phase detectors.

13. The clock generator of claim 12, wherein the state is one of a first state, a second state, a third state, or a fourth state. In the first state, both the outputs of the first and second phase detectors are logic low, and the phase interpolator shift is to the left. In the second state, both the first phase detector output and the second phase detector output are logic high, and the phase interpolator shift is to the right. In the third state, the output of the first phase detector is logic high and the output of the second phase detector is logic low, and the phase interpolator shifts to the left. In the fourth state, the output of the first phase detector is logic low and the output of the second phase detector is logic high, and the phase interpolator shifts to the left.

14. The clock generator of claim 13, wherein entering a locked state according to a locking scheme, wherein the adaptive finite state machine is configured to enter the locked state in response to determining that a transition from the second state to the first state has occurred, and wherein the adaptive finite state machine is further configured to determine a digital offset in response to entering the locked state based at least in part on the difference between the actual clock path of the first second-level clock signal and the copied clock path of the copied first second-level clock signal.

15. An analog-to-digital converter, comprising: A first clock generator is configured to receive an input clock signal and generate two or more first-level clock signals for a track and hold circuit. A phase interpolator configured to generate two or more corresponding interpolated clock signals, wherein each corresponding interpolated clock signal is generated based on the two or more first-level clock signals, wherein the phase interpolator further comprises two or more phase interpolator slices, each corresponding phase interpolator slice further comprising: A first multiplexer is configured to receive an even number of first-level clock signals from the two or more first-level clock signals; A second multiplexer is configured to receive an odd number of the two or more first-level clock signals; Two or more analog-to-digital converter slices, each of which includes: A second clock generator is configured to generate two or more second-level clock signals based on the corresponding interpolated clock signal, wherein the relative phase of the two or more second-level clock signals to the phase of the corresponding first-level clock signal is determined at least in part by the phase of the corresponding interpolated clock signal.

16. The analog-to-digital converter of claim 15, wherein each phase interpolator slice further comprises: A first digital-to-analog converter is configured to generate a first vector weighted by a first weighting factor from a selected even-numbered first-level clock signal from the first multiplexer; and A second digital-to-analog converter is configured to generate a second vector from the second multiplexer, weighted by a second weighting factor, based on a selected odd first-level clock signal. The outputs of the first and second digital-to-analog converters are configured to be added to generate added first and second vectors, wherein the added first and second vectors form the interpolated clock signal, wherein the corresponding interpolated clock signal has a phase within the 1xT phase offset between the even and odd first level clock signals.

17. The analog-to-digital converter of claim 15, further comprising: A 2-bit phase detector coupled to the first clock generator, the second clock generator, and the phase interpolator, the 2-bit phase detector being configured to determine alignment between a first second-level clock signal and a first first-level clock signal, wherein determining alignment between the first second-level clock signal and the first first-level clock signal includes determining phase offset between the falling edge of the first first-level clock signal and the falling edge of the first second-level clock signal.

18. The analog-to-digital converter of claim 17, wherein the 2-bit phase detector comprises: A first phase detector is configured to receive a copied first first level clock signal at the input of the first phase detector and a copied first second level clock signal at the clock input of the first phase detector. A second phase detector is configured to receive a replicated second first-level clock signal and the replicated first and second-level clock signals at the clock input of the second phase detector, wherein the second first-level clock signal is phase-shifted from the first first-level clock signal by a time margin. The first phase detector is configured to generate a value indicating the first level clock signal. The output of the first phase detector; and The second phase detector is configured to generate a value indicating the second first-level clock signal. Output of the second phase detector.

19. The analog-to-digital converter of claim 18, further comprising: An adaptive finite state machine configured to determine a phase interpolator shift based at least in part on the outputs of the first and second phase detectors, wherein determining the phase interpolator shift includes determining a state based on the outputs of the first and second phase detectors.

20. The analog-to-digital converter of claim 19, wherein the state is one of a first state, a second state, a third state, or a fourth state. In the first state, both the outputs of the first and second phase detectors are logic low, and the phase interpolator shift is to the left. In the second state, both the first phase detector output and the second phase detector output are logic high, and the phase interpolator shift is to the right. In the third state, the output of the first phase detector is logic high and the output of the second phase detector is logic low, and the phase interpolator shifts to the left. In the fourth state, the output of the first phase detector is logic low and the output of the second phase detector is logic high, and the phase interpolator shifts to the left.

21. The analog-to-digital converter of claim 20, wherein entering a locked state according to a locking scheme, wherein the adaptive finite state machine is configured to enter the locked state in response to determining that a transition from the second state to the first state has occurred, and wherein the adaptive finite state machine is further configured to determine a digital offset in response to entering the locked state based at least in part on the difference between the actual clock path of the first second-level clock signal and the replicated clock path of the first second-level clock signal.

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