Method for manufacturing a back-end structure

Abstract

The application discloses a manufacturing method of a back-end structure, which comprises the following steps: forming a second etching stop layer, wherein the second etching stop layer covers the surface of a lower electrode layer, a capacitor dielectric layer, a first etching stop layer and an upper electrode, the upper electrode is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the lower electrode layer, the lower electrode layer is formed on a second dielectric layer, the second dielectric layer is formed on a barrier layer, the barrier layer is formed on a first dielectric layer, a metal wire is formed in the first dielectric layer, and the width of the bottom of the capacitor dielectric layer is greater than the width of the upper electrode; covering photoresist on the second etching stop layer through a photoetching process to expose the area to be etched; etching to remove the second etching stop layer and the lower electrode layer on the side of the photoresist, etching to a predetermined depth in the second dielectric layer, and the remaining lower electrode layer forming a lower electrode of an MIM capacitor, wherein the width of the lower electrode is greater than the width of the bottom of the capacitor dielectric layer; removing the photoresist; and forming a third dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to a method for fabricating a back-end structure. Background Technology

[0002] Semiconductor integrated circuit manufacturing processes include front-end of line (FEOL) processes and back-end of line (BEOL) processes. The back-end of line process involves forming several layers of conductive metal interconnects on a wafer containing transistors. These interconnects are electrically connected through vias, and insulated and isolated from each other through interlayer dielectric (ILD) layers.

[0003] In semiconductor integrated circuits, capacitors are essential components in analog and radio frequency (RF) chips, and the accuracy of capacitors often directly affects the performance of the entire chip. Therefore, integrating metal-insulator-metal (MIM) capacitors in the back-end process of integrated circuits has become a common choice for high-performance analog and RF chips.

[0004] In MIM capacitors, high dielectric constant (dielectric constant K greater than 4) MIM capacitors (hereinafter referred to as "high K MIM capacitors") are widely used due to their larger capacitance per unit area and smaller footprint. (Reference) Figure 1 It shows a cross-sectional view after etching the contact vias during the fabrication process of a high-k MIM capacitor provided by the related technology, for example, as shown below. Figure 1 As shown: A barrier layer 120 is formed on the first dielectric layer 111, and a metal interconnect 130 is formed in the first dielectric layer 111. A second dielectric layer 112 is formed on the barrier layer 120, and a high-K MIM capacitor with a stepped cross-section is formed in the second dielectric layer. The capacitor includes a lower electrode layer 141, a capacitor dielectric layer 143, and an upper electrode layer 142 from bottom to top. An etch stop layer 150 is formed on the upper surface of the high-K MIM capacitor. The capacitor dielectric layer 143 is made of a high-K dielectric and has a stepped cross-section. The lower bottom of the stepped capacitor dielectric layer 143 and the lower electrode layer 141 have the same width in the lateral direction. The upper bottom of the stepped capacitor dielectric layer 143 and the upper electrode layer 142 have the same width in the lateral direction. The width of the upper electrode layer 142 in the lateral direction is smaller than that of the lower electrode layer 143.

[0005] After etching, a first via 101, a second via 102, and a third via 103 are formed in the second dielectric layer 112 and the barrier layer 120. The upper electrode layer 142 at the bottom of the first via 101 is exposed, the lower electrode layer 141 at the bottom of the second via 102 is exposed, and the metal interconnect 130 at the bottom of the third via 103 is exposed. Typically, the upper and lower electrode layers and the metal interconnect are made of different materials. After the contact hole is etched, while the upper and lower electrode layers and the metal interconnect are exposed, the capacitor dielectric layer 143, which is located on the lower electrode layer 141 and has the same width as it, will also be etched and exposed. The high-k material constituting the capacitor dielectric layer 143 will contaminate the upper and lower electrode layers, the metal interconnect, and the device cavity, reducing the reliability and yield of the device product. Summary of the Invention

[0006] This application provides a method for fabricating a back-end structure, which can solve the problem of poor device reliability and yield caused by the need to open the dielectric layer of the MIM capacitor during contact hole etching in the back-end structure with integrated MIM capacitors provided in the related technology. The method includes: A second etch stop layer is formed, which covers the lower electrode layer, the capacitor dielectric layer, the first etch stop layer, and the exposed surface of the upper electrode. The upper electrode is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the lower electrode layer, the lower electrode layer is formed on the second dielectric layer, the second dielectric layer is formed on the barrier layer, the barrier layer is formed on the first dielectric layer, and metal interconnects are formed in the first dielectric layer. The cross-section of the capacitor dielectric layer is a two-step type, the width of the top of the two-step capacitor dielectric layer is the same as the width of the upper electrode, and the width of the bottom of the two-step capacitor dielectric layer is greater than the width of the upper electrode. The first etch stop layer surrounds the periphery of the upper electrode. Photoresist is applied to the second etch stop layer using photolithography to expose the area to be etched. The photoresist covers the upper electrode, capacitor dielectric layer, and first etch stop layer. Etching is performed to remove the second etch stop layer and the lower electrode layer on the periphery of the photoresist, and etching is performed to a predetermined depth in the second dielectric layer. The remaining lower electrode layer constitutes the lower electrode of the MIM capacitor. The width of the lower electrode is greater than the width of the bottom of the two-stage stepped capacitor dielectric layer. Remove light obstruction; A third dielectric layer is formed, which covers the second etch stop layer, the lower electrode, and the exposed surface of the first dielectric layer; In the subsequent etching steps of the first contact hole, the second contact hole, and the third contact hole, the capacitor dielectric layer will not be exposed. The first contact hole is used to contact the upper electrode, the second contact hole is used to contact the lower electrode, and the third contact hole is used to contact the metal interconnect.

[0007] In some embodiments, prior to forming the second etch stop layer, the method further includes: A lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are sequentially formed on the second dielectric layer; Photoresist is covered in a predetermined area on the upper electrode layer by photolithography, exposing the area to be etched; Etching is performed to remove the upper electrode layer in areas other than the predetermined area, and etching is performed to the predetermined depth of the capacitor dielectric layer in areas other than the predetermined area. After etching, the cross-section of the capacitor dielectric layer is a two-step type, and the remaining upper electrode layer constitutes the upper electrode of the MIM capacitor. Remove light obstruction; A first etch stop layer is formed, which covers the area where the upper electrode and capacitor dielectric layer are exposed; Etching is performed, and the first etching stop layer at the top of the upper electrode layer and the periphery of the upper electrode are removed. After etching, the cross-section of the capacitor dielectric layer is a three-step type. The remaining first etching stop layer is located on the second step of the capacitor dielectric layer and surrounds the periphery of the upper electrode. Etching is performed to remove the capacitor dielectric layer around the first etch stop layer. The cross-section of the remaining capacitor dielectric layer is a two-step type, and the bottom width of the two-step capacitor dielectric layer is smaller than the width of the lower electrode layer.

[0008] In some embodiments, after forming the third dielectric layer, the method further includes: A first through-hole and a second through-hole are formed in the third dielectric layer, and a third through-hole is formed in the second dielectric layer, the third dielectric layer and the barrier layer. The upper electrode at the bottom of the first through-hole is exposed, the lower electrode at the bottom of the second through-hole is exposed and the second through-hole does not penetrate the capacitor dielectric layer, and the metal interconnect at the bottom of the third through-hole is exposed. A metal layer is filled in the first through hole, the second through hole and the third through hole, the metal layer in the first through hole forms the first contact hole, the metal layer in the second through hole forms the second contact hole, and the metal layer in the third through hole forms the third contact hole.

[0009] In some embodiments, the capacitor dielectric layer includes an aluminum oxide layer, a hafnium dioxide layer, or a zirconium dioxide layer.

[0010] In some embodiments, the upper electrode or the lower electrode comprises a titanium nitride layer.

[0011] In some embodiments, the barrier layer includes an NDC layer.

[0012] In some embodiments, the first etch stop layer and the second etch stop layer comprise silicon nitride layers.

[0013] The technical solution of this application has at least the following advantages: By integrating MIM capacitors in the dielectric layer of the back-end structure during the fabrication of semiconductor integrated circuits, since the width of the dielectric layer of the MIM capacitor is smaller than the width of the lower electrode, a lead-out area can be set at the part of the lower electrode that extends beyond the dielectric layer to form a corresponding contact hole in the subsequent contact hole etching process. This eliminates the need to open the dielectric layer during etching, reduces contamination of high-k materials, and improves the reliability and yield of the device to a certain extent. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a cross-sectional diagram showing the process of etching contact holes during the fabrication of high-K MIM capacitors provided by related technologies. Figure 2 This is a flowchart of a method for manufacturing a back-end structure provided in an exemplary embodiment of this application; Figures 3 to 13 This is a schematic diagram illustrating the formation of a back-end structure provided in an exemplary embodiment of this application; Figure 14 This is a flowchart of a method for manufacturing a back-end structure provided in an exemplary embodiment of this application; Figure 15 This is a flowchart of a method for creating a backend structure provided in an exemplary embodiment of this application. Detailed Implementation

[0016] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0019] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0020] refer to Figure 2 It illustrates a flowchart of a method for manufacturing a back-end structure provided in an exemplary embodiment of this application, such as... Figure 2 As shown, the method includes: Step S1: A second etch stop layer is formed, which covers the lower electrode layer, the capacitor dielectric layer, the first etch stop layer, and the exposed surface of the upper electrode. The upper electrode is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the lower electrode layer, the lower electrode layer is formed on the second dielectric layer, the second dielectric layer is formed on the barrier layer, the barrier layer is formed on the first dielectric layer, and metal interconnects are formed in the first dielectric layer. The cross-section of the capacitor dielectric layer is a two-step type, the width of the top of the two-step capacitor dielectric layer is the same as the width of the upper electrode, and the width of the bottom of the two-step capacitor dielectric layer is greater than the width of the upper electrode. The first etch stop layer surrounds the periphery of the upper electrode.

[0021] refer to Figure 8 This illustrates a cross-sectional view after the formation of the second etch stop layer. For example, as shown... Figure 8As shown, the second etch stop layer 360 covers the exposed surfaces of the lower electrode layer 341, the capacitor dielectric layer 343, the first etch stop layer 350, and the upper electrode 342. The upper electrode 342 is formed on the capacitor dielectric layer 343, the capacitor dielectric layer 343 is formed on the lower electrode layer 341, the lower electrode layer 341 is formed on the second dielectric layer 3121, the second dielectric layer 3121 is formed on the barrier layer 320, the barrier layer 320 is formed on the first dielectric layer 311, and a metal interconnect 330 is formed in the first dielectric layer 311. The cross-section of the capacitor dielectric layer 343 is a two-step type. The width of the top of the two-step capacitor dielectric layer 343 is the same as the width of the upper electrode 342, and the width of the bottom of the two-step capacitor dielectric layer 343 is greater than the width of the upper electrode 342. The first etch stop layer 350 surrounds the periphery of the upper electrode 342 and is located above the second step.

[0022] The capacitor dielectric layer 343 includes a high-K material layer, such as an aluminum oxide (Al2O3) layer, a hafnium dioxide (HfO2) layer, or a zirconium dioxide (ZrO2) layer; the upper electrode 342 and the lower electrode layer 341 may include titanium nitride (TiN) layers; the first dielectric layer 311 and the second dielectric layer 3121 include silicon dioxide (SiO2) layers; and the metal interconnect 330 includes a copper (Cu) layer. In some embodiments, the barrier layer 320 includes a nitride-doped silicon carbide (NDC) layer, and the thickness of the barrier layer 320 ranges from 200 Å to 1000 Å (e.g., it can be 500 Å). The first etch stop layer 350 and the second etch stop layer 360 include silicon nitride (Si3N4) layers. The second etch stop layer 360 can be formed by depositing the silicon nitride layer using a chemical vapor deposition (CVD) process, and the thickness of the second etch stop layer 360 ranges from 200 Å to 1500 Å (e.g., it can be 800 Å).

[0023] Step S2: Photoresist is applied to the second etch stop layer using photolithography to expose the area to be etched. The photoresist covers the upper electrode, capacitor dielectric layer, and first etch stop layer.

[0024] refer to Figure 9 This illustrates a cross-sectional schematic diagram of photoresist covering a second etch stop layer using a photolithography process. For example, as shown... Figure 9 As shown, photoresist 402 can be covered on the second etch stop layer 360 by photolithography. The area covered by photoresist 402 is the area corresponding to the lower electrode of the MIM capacitor, which encapsulates the upper electrode 342, the capacitor dielectric layer 343 and the first etch stop layer 350.

[0025] Step S3: Etching is performed to remove the second etch stop layer and the lower electrode layer on the periphery of the photoresist, etching to a predetermined depth in the second dielectric layer. The remaining lower electrode layer constitutes the lower electrode of the MIM capacitor, and the width of the lower electrode is greater than the width of the bottom of the two-stage stepped capacitor dielectric layer.

[0026] Step S4: Remove photoresist.

[0027] refer to Figure 10 This illustrates a cross-sectional view after etching to form the lower electrode. For example, as shown... Figure 10 As shown, except for the area covered by photoresist 402 (the area corresponding to the lower electrode), the second etch stop layer 360 and the lower electrode layer 341 in other areas are removed, and the second dielectric layer 3121 in other areas is etched to a predetermined depth. The remaining lower electrode layer 341 constitutes the lower electrode of the MIM capacitor. The width of the lower electrode 341 in the lateral direction is greater than the width of the capacitor dielectric layer 343 in the lateral direction. Forming contact holes for the lower electrode in the area where the lower electrode 341 extends beyond the capacitor dielectric layer 343 can avoid opening the capacitor dielectric layer 343 and causing contamination.

[0028] Step S5: A third dielectric layer is formed, which covers the second etch stop layer, the lower electrode, and the exposed surface of the first dielectric layer.

[0029] In the subsequent etching steps of the first contact hole, the second contact hole, and the third contact hole, the capacitor dielectric layer will not be exposed. The first contact hole is used to contact the upper electrode, the second contact hole is used to contact the lower electrode, and the third contact hole is used to contact the metal interconnect.

[0030] refer to Figure 11 The diagram shows a cross-sectional schematic of the formation of the third dielectric layer. For example, the third dielectric layer 3122 can be formed by depositing a silicon dioxide layer using a CVD process, and then the third dielectric layer 3122 can be planarized (e.g., by a chemical mechanical planarization (CMP) process).

[0031] In summary, in this embodiment of the application, by integrating a MIM capacitor in the dielectric layer of the back-end structure during the fabrication of the semiconductor integrated circuit, since the width of the dielectric layer of the MIM capacitor is smaller than the width of the lower electrode, a lead-out area can be set at the part of the lower electrode that extends beyond the dielectric layer to form a corresponding contact hole in the subsequent contact hole etching process. Thus, it is not necessary to open the dielectric layer during etching, reducing the contamination of high-K material and improving the reliability and yield of the device to a certain extent.

[0032] refer to Figure 14It illustrates a flowchart of a method for manufacturing a back-end structure provided in an exemplary embodiment of this application, the method being... Figure 2 The method performed before step S1 in the embodiment, such as Figure 14 As shown, the method includes: Step S101: A lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are sequentially formed on the second dielectric layer.

[0033] In step S102, photoresist is applied to a predetermined area on the upper electrode layer using photolithography to expose the area to be etched.

[0034] refer to Figure 3 It shows a cross-sectional schematic diagram of a photoresist layer covering the upper electrode layer after a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are formed on the second dielectric layer. For example, as shown... Figure 3 As shown, a titanium nitride layer can be deposited on the second dielectric layer 3121 by CVD process to form a lower electrode layer 341. A high-k material layer can be deposited on the lower electrode layer 341 by CVD process to form a capacitor dielectric layer 343. A titanium nitride layer can be deposited on the capacitor dielectric layer 343 by CVD process to form an upper electrode layer 342. A photoresist 401 can be covered on the upper electrode layer 342 by photolithography process to expose the area to be etched. The predetermined area covered by the photoresist 401 is the area corresponding to the upper electrode.

[0035] The thickness of the lower electrode layer 341 ranges from 300 angstroms to 1000 angstroms (e.g., it can be 500 angstroms), the thickness of the capacitor dielectric layer 343 ranges from 50 angstroms to 300 angstroms (e.g., it can be 190 angstroms), and the thickness of the upper electrode layer 342 ranges from 300 angstroms to 1000 angstroms (e.g., it can be 500 angstroms).

[0036] Step S103: Etching is performed to remove the upper electrode layer in areas other than the predetermined area. The etching is performed to the predetermined depth of the capacitor dielectric layer in areas other than the predetermined area. After etching, the cross-section of the capacitor dielectric layer is a two-step type, and the remaining upper electrode layer constitutes the upper electrode of the MIM capacitor.

[0037] Step S104: Remove photoresist.

[0038] refer to Figure 4 This illustrates a cross-sectional view after etching to form the upper electrode. For example, such as... Figure 4As shown, after etching to remove photoresist 401, the upper electrode layer in other areas outside the predetermined area is removed, and the capacitor dielectric layer 343 in other areas outside the predetermined area is etched to a predetermined depth. The remaining upper electrode layer constitutes the upper electrode 342 of the MIM capacitor. After etching, the cross-section of the capacitor dielectric layer 343 is a two-step type. The etched area of ​​the capacitor dielectric layer 343 is etched to a depth of 30 angstroms to 150 angstroms (for example, it can be etched to 100 angstroms). This depth is the step difference between the first step and the second step.

[0039] Step S105: A first etch stop layer is formed, which covers the area where the upper electrode and capacitor dielectric layer are exposed.

[0040] refer to Figure 5 This illustrates a cross-sectional schematic diagram of the formation of the first etch stop layer. For example, as shown... Figure 5 As shown, a first etch stop layer 350 can be formed by depositing a silicon nitride layer through a CVD process. The thickness of the first etch stop layer 350 ranges from 400 angstroms to 1200 angstroms (for example, it can be 800 angstroms).

[0041] Step S106: Etching is performed, and the first etching stop layer at the top of the upper electrode layer and around the upper electrode is removed. After etching, the cross-section of the capacitor dielectric layer is a three-step type, and the remaining first etching stop layer is located on the second step of the capacitor dielectric layer and surrounds the upper electrode.

[0042] refer to Figure 6 This illustrates a cross-sectional schematic diagram of the three-step capacitor dielectric layer formed after etching. For example, as shown... Figure 6 As shown, etching can be performed using a dry etching process to remove the top of the upper electrode layer 342 and the first etching stop layer 350 around the upper electrode 342. The remaining first etching stop layer 350 is located on the second step of the capacitor dielectric layer 343 and surrounds the upper electrode 342.

[0043] Step S107: Etch to remove the capacitor dielectric layer around the first etch stop layer. The cross-section of the remaining capacitor dielectric layer is a two-step type, and the bottom width of the two-step capacitor dielectric layer is smaller than the width of the lower electrode layer.

[0044] refer to Figure 7 The diagram shows a cross-sectional view of the capacitor dielectric layer surrounding the first etch stop layer 350, which has been etched away. For example, the capacitor dielectric layer surrounding the first etch stop layer 350 can be removed by a wet etching process, leaving a two-step cross-section for the remaining capacitor dielectric layer 343. The bottom width of the two-step capacitor dielectric layer 343 is smaller than the width of the lower electrode layer 341.

[0045] Step S108: A second etch stop layer is formed, which covers the lower electrode layer, the capacitor dielectric layer, the upper electrode, and the surface exposed by the first etch stop layer.

[0046] refer to Figure 15 It illustrates a flowchart of a method for manufacturing a back-end structure provided in an exemplary embodiment of this application, the method being... Figure 2 The method executed after step S5 in the embodiment is as follows: Figure 15 As shown, the method includes: Step 501: A first via and a second via are formed in the third dielectric layer, and a third via is formed in the second dielectric layer, the third dielectric layer and the barrier layer. The upper electrode at the bottom of the first via is exposed, the lower electrode at the bottom of the second via is exposed and the second via does not penetrate the capacitor dielectric layer, and the metal interconnect at the bottom of the third via is exposed.

[0047] refer to Figure 12 It shows a cross-sectional schematic diagram after the formation of the first through hole, the second through hole, and the third through hole. For example... Figure 12 As shown, the first through hole 301, the second through hole 302 and the third through hole 303 can be formed by photolithography and etching processes. The upper electrode 342 at the bottom of the first through hole 301 is exposed, the lower electrode 341 at the bottom of the second through hole 302 is exposed and the second through hole does not penetrate the capacitor dielectric layer 343, and the metal interconnect 330 at the bottom of the third through hole 303 is exposed.

[0048] Step 502: Fill the first through hole, the second through hole and the third through hole with a metal layer. The metal layer in the first through hole forms a first contact hole, the metal layer in the second through hole forms a second contact hole, and the metal layer in the third through hole forms a third contact hole.

[0049] refer to Figure 13 It shows a cross-sectional schematic diagram after the formation of the first contact hole, the second contact hole, and the third contact hole. For example, as shown... Figure 13 As shown, step 502 includes, but is not limited to: forming a metal layer, the metal layer filling the first through hole 301, the second through hole 302 and the third through hole 303; performing planarization (e.g., planarization can be performed by CMP process), removing the metal layer outside the first through hole 301, the second through hole 302 and the third through hole 303, the metal layer in the first through hole 301 forming the first contact hole 371, the metal layer in the second through hole 302 forming the second contact hole 372, and the metal layer in the third through hole 303 forming the third contact hole 373.

[0050] If the metal layer includes a copper layer, it can be formed by electroplating. If the metal layer includes an aluminum (Al) layer, it can be deposited by physical vapor deposition (PVD). If the metal layer includes a tungsten (W) layer, it can be deposited by CVD.

[0051] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for manufacturing a rear-section structure, characterized in that, include: A second etch stop layer is formed, which covers the lower electrode layer, the capacitor dielectric layer, the first etch stop layer, and the exposed surface of the upper electrode. The upper electrode is formed on the capacitor dielectric layer, the capacitor dielectric layer is formed on the lower electrode layer, the lower electrode layer is formed on the second dielectric layer, the second dielectric layer is formed on the barrier layer, the barrier layer is formed on the first dielectric layer, and metal interconnects are formed in the first dielectric layer. The cross-section of the capacitor dielectric layer is a two-step type, the width of the top of the two-step capacitor dielectric layer is the same as the width of the upper electrode, and the width of the bottom of the two-step capacitor dielectric layer is greater than the width of the upper electrode. The first etch stop layer surrounds the periphery of the upper electrode. Photoresist is applied to the second etch stop layer using photolithography to expose the area to be etched. The photoresist covers the upper electrode, capacitor dielectric layer, and first etch stop layer. Etching is performed to remove the second etch stop layer and the lower electrode layer on the periphery of the photoresist, and etching is performed to a predetermined depth in the second dielectric layer. The remaining lower electrode layer constitutes the lower electrode of the MIM capacitor. The width of the lower electrode is greater than the width of the bottom of the two-stage stepped capacitor dielectric layer. Remove light obstruction; A third dielectric layer is formed, which covers the second etch stop layer, the lower electrode, and the exposed surface of the first dielectric layer; In the subsequent etching steps of the first contact hole, the second contact hole, and the third contact hole, the capacitor dielectric layer will not be exposed. The first contact hole is used to contact the upper electrode, the second contact hole is used to contact the lower electrode, and the third contact hole is used to contact the metal interconnect.

2. The method according to claim 1, characterized in that, Before forming the second etch stop layer, the process also includes: A lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are sequentially formed on the second dielectric layer; Photoresist is covered in a predetermined area on the upper electrode layer by photolithography, exposing the area to be etched; Etching is performed to remove the upper electrode layer in areas other than the predetermined area, and etching is performed to the predetermined depth of the capacitor dielectric layer in areas other than the predetermined area. After etching, the cross-section of the capacitor dielectric layer is a two-step type, and the remaining upper electrode layer constitutes the upper electrode of the MIM capacitor. Remove light obstruction; A first etch stop layer is formed, which covers the area where the upper electrode and capacitor dielectric layer are exposed; Etching is performed, and the first etching stop layer at the top of the upper electrode layer and the periphery of the upper electrode are removed. After etching, the cross-section of the capacitor dielectric layer is a three-step type. The remaining first etching stop layer is located on the second step of the capacitor dielectric layer and surrounds the periphery of the upper electrode. Etching is performed to remove the capacitor dielectric layer around the first etch stop layer. The cross-section of the remaining capacitor dielectric layer is a two-step type, and the bottom width of the two-step capacitor dielectric layer is smaller than the width of the lower electrode layer.

3. The method according to claim 2, characterized in that, After forming the third dielectric layer, the method further includes: A first through-hole and a second through-hole are formed in the third dielectric layer, and a third through-hole is formed in the second dielectric layer, the third dielectric layer and the barrier layer. The upper electrode at the bottom of the first through-hole is exposed, the lower electrode at the bottom of the second through-hole is exposed and the second through-hole does not penetrate the capacitor dielectric layer, and the metal interconnect at the bottom of the third through-hole is exposed. A metal layer is filled in the first through hole, the second through hole and the third through hole, the metal layer in the first through hole forms the first contact hole, the metal layer in the second through hole forms the second contact hole, and the metal layer in the third through hole forms the third contact hole.

4. The method according to any one of claims 1 to 3, characterized in that, The capacitor dielectric layer includes an aluminum oxide layer, a hafnium dioxide layer, or a zirconium dioxide layer.

5. The method according to claim 4, characterized in that, The upper electrode or the lower electrode includes a titanium nitride layer.

6. The method according to claim 5, characterized in that, The barrier layer includes an NDC layer.

7. The method according to claim 6, characterized in that, The first etch stop layer and the second etch stop layer comprise silicon nitride layers.

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