A slew rate adaptive amplifier circuit

Abstract

This application relates to a slew rate adaptive amplifier circuit, which includes a differential amplifier module, a current control module, a first current source I1, a mirror module, a first resistor R1, and a second resistor R2. Both the differential amplifier module and the control module are electrically connected to the mirror module. The negative terminal of the first current source I1 is connected to the power supply VDD, and the anode of the first current source I1 is connected to one end of the first resistor R1 and one end of the second resistor R2. The other ends of the first resistor R1 and the second resistor R2 are both electrically connected to the current control module. The current control module controls the current flowing through the first resistor R1 and the second resistor R2 according to the differential signal. The mirror module replicates the output current of the differential amplifier module to the controlled terminal of the differential amplifier module. This application has the effect of conveniently adapting the slew rate to the magnitude of the differential signal input to the differential amplifier circuit.

Description

Technical Field

[0001] This application relates to the field of amplifiers, and more particularly to a slew rate adaptive amplifier circuit. Background Technology

[0002] Differential amplifier circuits have a strong ability to suppress common-mode input signals, but have little effect on differential-mode signals. Therefore, differential amplifier circuits are generally used as input stages and intermediate stages in integrated computing systems. After a differential signal is input to a differential amplifier circuit, the circuit will output an amplified signal. The conversion efficiency of the amplified signal output by a differential amplifier circuit is generally expressed using slew rate.

[0003] The slew rate of a differential amplifier circuit is generally set by adjusting the tail current of the differential amplifier circuit. When adjusting the slew rate of a differential amplifier circuit, a current source is usually installed in the branch through which the tail current of the differential amplifier circuit passes.

[0004] However, when the tail current is controlled by the current source, the tail current becomes a fixed value, thus keeping the slew rate of the differential amplifier circuit constant. As the differential signal input to the differential amplifier circuit increases, the required slew rate also increases. If the slew rate is less than the required slew rate, the amplified signal output by the differential amplifier will be distorted. Conversely, as the differential signal input to the differential amplifier circuit decreases, the required slew rate also decreases. If the slew rate is greater than the required slew rate, the power consumption of the differential amplifier will increase. Summary of the Invention

[0005] To facilitate slew rate adaptation to the differential signal magnitude of the input differential amplifier circuit, this application provides a slew rate adaptive amplifier circuit.

[0006] This application provides a slew rate adaptive amplifier circuit, which adopts the following technical solution:

[0007] An adaptive slew rate amplifier circuit includes a differential amplifier module, a current control module, a first current source I1, a mirror module, a first resistor R1, and a second resistor R2. The differential amplifier module has a first input terminal, a second input terminal, an output terminal, and a controlled terminal. The first and second input terminals are used to input differential signals, and the output terminal is used to output amplified signals. The current control module has a first control terminal, a second control terminal, a first input terminal, a second input terminal, and an output terminal. The negative terminal of the first current source I1 is connected to a power supply VDD, and the anode of the first current source I1 is connected to one end of the first resistor R1 and one end of the second resistor R2. The first control terminal of the current control module... The first input terminal of the current control module is connected to the other end of the first resistor R1, and the second input terminal of the current control module is connected to the other end of the second resistor R2. The first input terminal of the current control module is connected to the first input terminal of the differential amplifier module, and the second input terminal of the current control module is connected to the second input terminal of the differential amplifier module. The current control module is used to control the current flowing through the first resistor R1 and the second resistor R2 according to the differential signal. The mirror module is provided with a first input terminal and a second input terminal. The first input terminal of the mirror module is connected to the output terminal of the current control module, and the second output terminal of the mirror module is connected to the controlled terminal of the differential amplifier module. The mirror module is used to copy the output current of the differential amplifier module to the controlled terminal of the differential amplifier module.

[0008] By adopting the above technical solution, the current flowing through the first power supply VDD is a fixed value, and the current flowing through the first power supply VDD is equal to the sum of the currents flowing through the first resistor R1 and the second resistor R2. When the differential signal is input to the differential amplifier module, the differential signal also enters the current control module.

[0009] If the differential signal increases, the current control module decreases the current flowing through the first resistor R1 and increases the current flowing through the second resistor R2. The current control module then inputs the current flowing through the second resistor R2 into the mirror module. The mirror module replicates the current flowing through the second resistor R2 to the controlled terminal of the differential amplifier module, thereby increasing the tail current of the differential amplifier module.

[0010] If the differential signal decreases, the current control module increases the current flowing through the first resistor R1 and decreases the current flowing through the second resistor R2. Then, the current control module inputs the current flowing through the second resistor R2 into the mirror module. The mirror module replicates the current flowing through the second resistor R2 to the controlled terminal of the differential amplifier module, thereby reducing the tail current of the differential amplifier module.

[0011] By allowing the tail current of the differential amplifier module to change with the differential signal, the slew rate can be easily adapted to the magnitude of the differential signal input to the differential amplifier circuit.

[0012] Optionally, the differential amplifier module includes a first thyristor M1, a second thyristor M2, a third thyristor M3, and a fourth thyristor M4. The first thyristor M1 and the second thyristor M2 are PMOS transistors, and the third thyristor M3 and the fourth thyristor M4 are NMOS transistors. The gate of the first thyristor M1 is connected to the first input terminal of the differential amplifier module, and the gate of the second thyristor M2 is connected to the second input terminal of the differential amplifier module. The sources of the first thyristor M1 and the second thyristor M2 are both connected to the controlled terminal of the differential amplifier module. The drain of the first thyristor M1 is connected to the drain of the third thyristor M3, the gate of the third thyristor M3, and the gate of the fourth thyristor M4. The sources of the third thyristor M3 and the fourth thyristor M4 are both connected to the power supply VDD. The drains of the fourth thyristor M4 and the second thyristor M2 are both connected to the output terminal of the differential amplifier module.

[0013] By employing the above technical solution, the parasitic diodes built into the first thyristor M1 and the second thyristor M2 allow current to flow directly from the drain to the source. The sum of the drain-source currents flowing through the first thyristor M1 and the second thyristor M2 is the tail current at the control terminal of the differential amplifier module. The drain current of the first thyristor M1 is replicated to the drain of the fourth thyristor M4 through the third thyristor M3 and the fourth thyristor M4. The drain current of the fourth thyristor M4 is equal to the sum of the drain current of the second thyristor M2 and the output current of the differential amplifier module. Therefore, the output current of the differential amplifier module is equal to the drain current of the first thyristor M1 minus the drain current of the second thyristor M2, thus facilitating the output of the amplified signal from the differential amplifier module.

[0014] Optionally, the mirror module includes a fifth thyristor M5 and a sixth thyristor M6, both of which are PMOS transistors. The drain and gate of the fifth thyristor M5 and the gate of the sixth thyristor M6 are all connected to the first input terminal of the mirror module, and the drain of the sixth thyristor M6 is connected to the second input terminal of the mirror module.

[0015] By adopting the above technical solution, the output current of the current control module enters the drain and gate of the fifth thyristor M5 and the gate of the sixth thyristor M6. In other words, the output current of the current control module is equal to the sum of the drain and gate currents of the fifth thyristor M5 and the gate current of the sixth thyristor M6. The gates of the fifth thyristor M5 and the sixth thyristor M6 are interconnected, thus making their gate voltages equal. The drain current of the sixth thyristor M6 is equal to the drain current of the fifth thyristor M5 multiplied by the width-to-length ratio between the fifth thyristor M5 and the sixth thyristor M6. The controlled current of the differential amplifier module is equal to the drain current of the sixth thyristor M6, thus facilitating the current control module's control of the controlled current of the differential amplifier module, and consequently facilitating slew rate adaptation to the differential signal magnitude of the input differential amplifier circuit.

[0016] Optionally, a follower module is provided between the first input terminal of the current control module and the first input terminal of the differential amplifier module, and between the second input terminal of the current control module and the second input terminal of the differential amplifier module. Each follower module is provided with an input terminal and an output terminal. The input terminal of one follower module is connected to the first input terminal of the differential amplifier module, and the input terminal of another follower module is connected to the second input terminal of the differential amplifier module. The output terminal of one follower module is connected to the first input terminal of the current control module, and the input terminal of another follower module is connected to the second input terminal of the current control module. The follower module is used to input the differential signal from the differential amplifier module into the current control module.

[0017] By adopting the above technical solution, when the differential signal is input to the differential amplifier module, the differential signal is input to the current control module through two follower modules, thereby facilitating the current control module to control the controlled terminal current of the differential amplifier module according to the differential signal.

[0018] Optionally, the follower module includes a seventh thyristor M7 and a second current source I2. The seventh thyristor M7 is a PMOS transistor. The gate of the seventh thyristor M7 is connected to the input terminal of the follower module, the drain of the seventh thyristor M7 is connected to the power supply VDD, the source of the seventh thyristor M7 and the negative terminal of the second current source I2 are both connected to the output terminal of the follower module, and the positive terminal of the second current source I2 is connected to the power supply ground.

[0019] By adopting the above technical solution, the seventh thyristor M7 and the second current source I2 constitute a source follower, thereby making the output voltage of the follower module equal to the input voltage of the follower module. Furthermore, the high gate impedance of the seventh thyristor M7 reduces the impact on the differential signal when the follower module acquires the differential signal.

[0020] Optionally, the current control module includes a first selection submodule and a current adjustment submodule. The first selection submodule is provided with a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The current adjustment submodule is provided with a first input terminal, a second input terminal, and a control terminal. The first output terminal of the first selection submodule is connected to the first input terminal of the current adjustment submodule, the second output terminal of the first selection submodule is connected to the second input terminal of the current adjustment submodule, the first input terminal of the first selection submodule is connected to the first input terminal of the current control module, the second input terminal of the first selection submodule is connected to the second input terminal of the current control module, and the control terminal of the current adjustment submodule is connected to the first control terminal of the current control module. The first selection submodule is used to control the current adjustment submodule according to the positive voltage in the differential signal, and the current adjustment submodule is used to adjust the current flowing through the first resistor R1.

[0021] By adopting the above technical solution, the current adjustment submodule obtains the signal with the larger voltage in the differential signal through the first selection submodule. When the differential signal increases, the current adjustment submodule decreases the current flowing through the first resistor R1, thereby increasing the current flowing through the second resistor R2. When the differential signal decreases, the current adjustment submodule increases the current flowing through the first resistor R1, thereby decreasing the current flowing through the second resistor R2. By controlling the current flowing through the second resistor R2, the slew rate can be easily matched to the magnitude of the differential signal input to the differential amplifier circuit.

[0022] Optionally, the first selection submodule includes an eighth thyristor M8 and a ninth thyristor M9, wherein the eighth thyristor M8 and the ninth thyristor M9 are PMOS transistors. The source of the eighth thyristor M8 and the source of the ninth thyristor M9 are both connected to the first output terminal of the first selection submodule, the drain of the eighth thyristor M8 and the drain of the ninth thyristor M9 are both connected to the second output terminal of the first selection submodule, the gate of the eighth thyristor M8 is connected to the first input terminal of the first selection submodule, and the gate of the ninth thyristor M9 is connected to the second input terminal of the first selection submodule.

[0023] By employing the above technical solution, the differential signal consists of two voltages of equal magnitude but opposite directions. After the differential signal is input to the eighth thyristor M8 and the ninth thyristor M9, the gate voltages of the eighth thyristor M8 and the ninth thyristor M9 are equal in magnitude but opposite in direction. Furthermore, the source voltages of the eighth thyristor M8 and the ninth thyristor M9 are equal, and their drain voltages are equal. This causes the voltage at the first input terminal of the current adjustment submodule to increase as the positive voltage of the differential signal increases and decrease as it decreases. The current adjustment submodule then controls the current flowing through the first resistor R1 based on the positive voltage of the differential signal. When the differential signal increases, the voltage at the first input terminal of the current adjustment submodule increases, and the current adjustment submodule decreases the current flowing through the first resistor R1, thereby increasing the current flowing through the second resistor R2. When the differential signal decreases, the voltage at the first input terminal of the current adjustment submodule decreases, and the current adjustment submodule increases the current flowing through the first resistor R1, thereby decreasing the current flowing through the second resistor R2.

[0024] Optionally, the current adjustment submodule includes a third current source I3, a tenth thyristor M10, an eleventh thyristor M11, a twelfth thyristor M12, and a thirteenth thyristor M13. The tenth thyristor M10 and the eleventh thyristor M11 are NMOS transistors, and the twelfth thyristor M12 and the thirteenth thyristor M13 are PMOS transistors. The sources of the tenth thyristor M10 and the eleventh thyristor M11 are both connected to the power supply VDD. The drain of the tenth thyristor M10 is connected to the second input terminal and the tenth thyristor... The gate of transistor M10 is connected to the gate of the eleventh thyristor M11. The drain of the eleventh thyristor M11 is connected to the drain of the twelfth thyristor M12, the gate of the twelfth thyristor M12, and the gate of the thirteenth thyristor M13. The source of the twelfth thyristor M12 is connected to the negative terminal of the third current source I3 and the first input terminal of the current adjustment submodule. The positive terminal of the third current source I3 is connected to the power supply ground. The drain of the thirteenth thyristor M13 is connected to the control terminal of the current adjustment submodule. The source of the thirteenth thyristor M13 is connected to the power supply ground.

[0025] By employing the above technical solution, the current flowing through the third current source I3 is equal to the sum of the currents flowing through the first selection submodule and the twelfth thyristor M12. The current flowing through the first selection submodule is replicated to the twelfth thyristor M12 through the tenth thyristor M10 and the eleventh thyristor M11, thus making the current of the first selection submodule equal to the current of the twelfth thyristor M12. When the differential signal increases, the first selection submodule increases the voltage at the first input terminal of the current adjustment submodule, thereby reducing the voltage between the drain and source of the twelfth thyristor M12, and consequently reducing the current. Since the eleventh thyristor M11 and the twelfth thyristor M12 need to maintain equal currents, the voltage between the drain and source of the twelfth thyristor M12 decreases, while the voltage between the drain and source of the eleventh thyristor M11 increases, thereby increasing the gate voltage of the thirteenth thyristor M13. The increased gate voltage of the thirteenth thyristor M13 reduces the current flowing through the first resistor R1. When the differential signal decreases, the first selection submodule reduces the voltage at the first input terminal of the current adjustment submodule, thereby increasing the voltage between the drain and source of the twelfth thyristor M12 and decreasing the current. Meanwhile, the eleventh thyristor M11 and the twelfth thyristor M12 need to maintain equal current, which increases the voltage between the drain and source of the twelfth thyristor M12 and the eleventh thyristor M11, thus decreasing the gate voltage of the thirteenth thyristor M13. The decrease in the gate voltage of the thirteenth thyristor M13 increases the current flowing through the first resistor R1. By adjusting the current flowing through the first resistor R1, the current flowing through the second resistor R2 is adjusted, thus facilitating slew rate adaptation to the differential signal magnitude of the input differential amplifier circuit.

[0026] Optionally, the current control module further includes a second selection submodule. The second selection submodule is provided with a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal of the second selection submodule is connected to the first input terminal of the current control module, the second input terminal of the second selection submodule is connected to the second input terminal of the current control module, the control terminal of the second selection submodule is connected to the second control terminal of the current control module, and the output terminal of the second selection submodule is connected to the output terminal of the current control module. The second selection submodule is used to control the current flowing through the second resistor R2 according to the signal with the smaller voltage in the differential signal.

[0027] By employing the above technical solution, the second selection submodule acquires the signal with the smaller voltage in the differential signal. When the differential signal increases, the second selection submodule increases the current flowing through the second resistor R2. When the differential signal decreases, the current adjustment submodule decreases the current flowing through the second resistor R2. By controlling the current flowing through the second resistor R2, the slew rate can be easily matched to the magnitude of the differential signal input to the differential amplifier circuit.

[0028] Optionally, the second selection submodule includes a fourteenth thyristor M14 and a fifteenth thyristor M15, wherein the fourteenth thyristor M14 and the fifteenth thyristor M15 are NMOS transistors. The gate of the fourteenth thyristor M14 is connected to the first input terminal of the second selection submodule, the gate of the fifteenth thyristor M15 is connected to the second input terminal of the second selection submodule, the source of the fourteenth thyristor M14 is connected to the source of the fifteenth thyristor M15 and the control terminal of the second selection submodule, and the drain of the fourteenth thyristor M14 is connected to the drain of the fifteenth thyristor M15 and the output terminal of the second selection submodule.

[0029] By employing the above technical solution, the differential signal consists of two voltages of equal magnitude but opposite directions. After the differential signal is input to the fourteenth thyristor M14 and the fifteenth thyristor M15, the gate voltages of the fourteenth thyristor M14 and the fifteenth thyristor M15 are equal in magnitude but opposite in direction. Furthermore, the source voltages and drain voltages of the fourteenth thyristor M14 and the fifteenth thyristor M15 are equal. This causes the voltage at the end of the second resistor connected to the first power supply VDD to increase as the absolute value of the negative voltage of the differential signal increases and decrease as it decreases. When the differential signal increases, the voltage across the second resistor R2 increases, and the current flowing through the second resistor R2 increases. When the differential signal decreases, the voltage across the second resistor R2 decreases, and the current flowing through the second resistor R2 also decreases, thus facilitating control of the current flowing through the second resistor R2.

[0030] In summary, this application includes at least one of the following beneficial technical effects:

[0031] 1. When the differential signal increases, the current control module increases the current of the second resistor R2 and decreases the current of the first resistor R1. Then, the current flowing through the second resistor R2 is copied to the controlled terminal of the differential amplifier module through the mirror module. This allows the differential amplifier module to have sufficient slew rate to reduce distortion when the differential signal increases. When the differential signal decreases, the current control module decreases the current of the second resistor R2 and increases the current of the first resistor R1. Then, the current flowing through the second resistor R2 is copied to the controlled terminal of the differential amplifier module through the mirror module. This reduces the current at the controlled terminal of the differential amplifier module, thereby reducing the slew rate of the differential amplifier module. Since the slew rate of the differential amplifier module increases with the increase of the differential signal and decreases with the decrease of the differential signal, it is convenient to adapt the slew rate to the magnitude of the differential signal input to the differential amplifier circuit. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of Embodiment 1 of this application;

[0033] Figure 2 This is a circuit diagram of Embodiment 1 of this application;

[0034] Figure 3 This is a circuit diagram of Embodiment 2 of this application;

[0035] Figure 4 This is a circuit diagram of Embodiment 3 of this application.

[0036] Explanation of reference numerals in the attached diagram: 1. Differential amplifier module; 2. Follower module; 3. Current control module; 31. First selection submodule; 32. Second selection submodule; 33. Current adjustment submodule; 4. Mirror module. Detailed Implementation

[0037] The following is in conjunction with the appendix Figure 1-4 This application will be described in further detail.

[0038] Example 1.

[0039] This application discloses a slew rate adaptive amplifier circuit.

[0040] Reference Figure 1 A slew rate adaptive amplifier circuit includes a follower module 2, a differential amplifier module 1, a current control module 3, a first current source I1, a mirror module 4, a first resistor R1, and a second resistor R2.

[0041] The differential amplifier module 1 is provided with a first input terminal, a second input terminal, an output terminal, and a controlled terminal. The first input terminal and the second input terminal of the differential amplifier module 1 are used to input differential signals, and the output terminal of the differential amplifier module 1 is used to output amplified signals.

[0042] The differential amplifier module 1 includes a first thyristor M1, a second thyristor M2, a third thyristor M3, and a fourth thyristor M4. The first thyristor M1 and the second thyristor M2 are PMOS transistors, while the third thyristor M3 and the fourth thyristor M4 are NMOS transistors. The gate of the first thyristor M1 is connected to the first input terminal of the differential amplifier module 1, and the gate of the second thyristor M2 is connected to the second input terminal of the differential amplifier module 1. The source of the first thyristor M1 is connected to the source of the second thyristor M2 and the controlled terminal of the differential amplifier module 1. The drain of the first thyristor M1 is connected to the drain of the third thyristor M3, the gate of the third thyristor M3, and the gate of the fourth thyristor M4. The sources of the third thyristor M3 and the fourth thyristor M4 are both connected to the power supply VDD, and the drains of the fourth thyristor M4 and the second thyristor M2 are both connected to the output terminal of the differential amplifier module 1.

[0043] The differential signals are two voltages of equal magnitude but opposite direction. These differential signals are input to the gates of the first thyristor M1 and the second thyristor M2, respectively. In this application, the width-to-length ratios of the first thyristor M1 and the second thyristor M2 are the same, as are the width-to-length ratios of the third thyristor M3 and the fourth thyristor M4. The parasitic diodes built into the first thyristor M1 and the second thyristor M2 allow current to flow directly from the drain to the source, thus ensuring that the controlled terminal current of the differential amplifier module 1 is equal to the sum of the currents flowing through the first thyristor M1 and the second thyristor M2.

[0044] Then, the current flowing through the drain-source of the first thyristor M1 is copied to the drain of the fourth thyristor M4 through the third thyristor M3 and the fourth thyristor M4. Therefore, the output current of the differential amplifier module 1 is equal to the drain current of the first thyristor M1 minus the drain current of the second thyristor M2, which facilitates the output of the amplified signal from the output of the differential amplifier module 1.

[0045] The current control module 3 is provided with a first control terminal, a second control terminal, a first input terminal, a second input terminal, and an output terminal. The mirror module 4 is provided with a first input terminal and a second input terminal. The first input terminal of the mirror module 4 is connected to the output terminal of the current control module 3, and the second output terminal of the mirror module 4 is connected to the controlled terminal of the differential amplifier module 1.

[0046] The mirror module 4 includes a fifth thyristor M5 and a sixth thyristor M6, both of which are PMOS transistors. The drain of the fifth thyristor M5 is connected to its gate, and the gate of the sixth thyristor M6 is connected to the first input terminal of the mirror module 4. The drain of the sixth thyristor M6 is connected to the second input terminal of the mirror module 4. The sources of both the fifth thyristor M5 and the sixth thyristor M6 are connected to the power supply ground.

[0047] The output current of current control module 3 enters the first input terminal of mirror module 4. A current mirror is formed by the fifth thyristor M5 and the sixth thyristor M6, ensuring that the drain-source current of the sixth thyristor M6 is equal to the amplified drain-source current of the fifth thyristor M5. The amplification factor of the drain-source current of the sixth thyristor M6 is the width-to-length ratio between the fifth thyristor M5 and the sixth thyristor M6.

[0048] When the differential signal increases, the output current of the current control module 3 is increased, which in turn increases the controlled current of the differential amplifier module 1 through the mirror module 4. The increased controlled current of the differential amplifier module 1 increases the slew rate of the differential amplifier module 1, thereby reducing the distortion of the amplified signal output from the output terminal of the differential amplifier module 1.

[0049] When the differential signal decreases, the output current of the current control module 3 is reduced, and the controlled current of the differential amplifier module 1 is reduced through the mirror module 4. The reduced controlled current of the differential amplifier module 1 reduces the slew rate of the differential amplifier module 1, thus facilitating a reduction in the slew rate when the differential signal is small.

[0050] By adjusting the slew rate of the differential amplifier module 1 to increase as the differential signal increases and decrease as the differential signal decreases, the slew rate can be adapted to the magnitude of the differential signal input to the differential amplifier module 1.

[0051] There are two follower modules 2, each with an input terminal and an output terminal. The input terminal of one follower module 2 is connected to the first input terminal of the differential amplifier module 1, and the input terminal of the other follower module 2 is connected to the second input terminal of the differential amplifier module 1. The output terminal of one follower module 2 is connected to the first input terminal of the current control module 3, and the input terminal of the other follower module 2 is connected to the second input terminal of the current control module 3.

[0052] When the differential signal is input to the first and second input terminals of the differential amplifier module 1, the differential signal is input to the current control module 3 through the two follower modules 2, so that the current control module 3 can adjust the slew rate of the differential amplifier module 1 according to the magnitude of the differential signal.

[0053] The follower module 2 includes a seventh thyristor M7 and a second current source I2. The seventh thyristor M7 is a PMOS transistor. The gate of the seventh thyristor M7 is connected to the input terminal of the follower module 2, the drain of the seventh thyristor M7 is connected to the power supply VDD, and the source of the seventh thyristor M7 is connected to the negative terminal of the second current source I2 and the output terminal of the follower module 2. The positive terminal of the second current source I2 is connected to the power supply ground. The seventh thyristor M7 and the second current source I2 constitute a source follower. Simultaneously, the seventh thyristor M7 has a high input impedance, thereby reducing the impact of the differential signal input to the follower module 2 on the differential amplifier module 1.

[0054] The negative terminal of the first current source I1 is connected to the power supply VDD, and the anode of the first current source I1 is connected to one end of the first resistor R1 and one end of the second resistor R2. The first control terminal of the current control module 3 is connected to the other end of the first resistor R1, and the second control terminal of the current control module 3 is connected to the other end of the second resistor R2.

[0055] The current control module 3 controls the current flowing through the first resistor R1 and the second resistor R2, and then inputs the current flowing through the second resistor R2 into the mirror module 4. The mirror module 4 replicates the current of the second resistor R2 to the controlled terminal of the differential amplifier module 1, thereby changing the slew rate of the differential amplifier module 1.

[0056] The current flowing through the first current source I1 is equal to the sum of the currents flowing through the first resistor R1 and the second resistor R2. When the differential signal increases, the current control module 3 decreases the current flowing through the first resistor R1 and increases the current flowing through the second resistor R2, thereby increasing the slew rate of the differential amplifier module 1. When the differential signal decreases, the current control module 3 increases the current flowing through the first resistor R1 and decreases the current flowing through the second resistor R2, thereby decreasing the slew rate of the differential amplifier module 1.

[0057] The current control module 3 includes a first selection submodule 31, a second selection submodule 32, and a current adjustment submodule 33. The first selection submodule 31 is provided with a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The current adjustment submodule 33 is provided with a first input terminal, a second input terminal, and a control terminal. The second selection submodule 32 is provided with a first input terminal, a second input terminal, an output terminal, and a control terminal.

[0058] The first output terminal of the first selection submodule 31 is connected to the first input terminal of the current adjustment submodule 33, and the second output terminal of the first selection submodule 31 is connected to the second input terminal of the current adjustment submodule 33. The first input terminals of both the first selection submodule 31 and the second selection submodule 32 are connected to the first input terminal of the current control module 3, and the second input terminals of both are connected to the second input terminal of the current control module 3. The control terminal of the current adjustment submodule 33 is connected to the first control terminal of the current control module 3, and the current flowing through the first resistor R1 is adjusted through the current adjustment submodule 33 and the first selection submodule 31.

[0059] The control terminal of the second selection submodule 32 is connected to the second control terminal of the current control module 3, and the output terminal of the second selection submodule 32 is connected to the output terminal of the current control module 3. The current flowing through the second resistor R2 is adjusted through the second selection submodule 32.

[0060] The first selection submodule 31 includes an eighth thyristor M8 and a ninth thyristor M9, both of which are PMOS transistors. The source of both thyristor M8 and the source of both thyristor M9 are connected to the first output terminal of the first selection submodule 31, and the drain of both thyristor M8 and the drain of both thyristor M9 are connected to the second output terminal of the first selection submodule 31. The gate of thyristor M8 is connected to the first input terminal of the first selection submodule 31, and the gate of thyristor M9 is connected to the second input terminal of the first selection submodule 31.

[0061] After the differential signals are input to the eighth thyristor M8 and the ninth thyristor M9 respectively, the gate voltages of the eighth thyristor M8 and the ninth thyristor M9 are equal in magnitude but opposite in direction. Because the sources of the eighth thyristor M8 and the ninth thyristor M9 are connected to each other, and their drains are also connected, the voltages between the drains of the eighth thyristor M8 and the source-drain of the ninth thyristor M9 are equal. The voltage at the first input terminal of the current adjustment submodule 33 is made to increase as the positive voltage of the differential signal increases and decrease as the differential signal decreases.

[0062] The current regulation submodule 33 includes a third current source I3, a tenth thyristor M10, an eleventh thyristor M11, a twelfth thyristor M12, and a thirteenth thyristor M13. The tenth thyristor M10 and the eleventh thyristor M11 are NMOS transistors, while the twelfth thyristor M12 and the thirteenth thyristor M13 are PMOS transistors.

[0063] The sources of the tenth thyristor M10 and the eleventh thyristor M11 are both connected to the power supply VDD. The drain of the tenth thyristor M10 is connected to the second input terminal of the current adjustment submodule 33, the gate of the tenth thyristor M10, and the gate of the eleventh thyristor M11. The drain of the eleventh thyristor M11 is connected to the drain of the twelfth thyristor M12, the gate of the twelfth thyristor M12, and the gate of the thirteenth thyristor M13. The source of the twelfth thyristor M12 is connected to the first input terminal of the current adjustment submodule 33 and the negative terminal of the third current source I3. The drain of the thirteenth thyristor M13 is connected to the control terminal of the current adjustment submodule 33, and the positive terminal of the third current source I3 is connected to the power supply ground.

[0064] The current flowing through the third current source I3 is equal to the sum of the currents flowing through the first selection submodule 31 and the twelfth thyristor M12. The current flowing through the first selection submodule 31 is replicated to the twelfth thyristor M12 through the tenth thyristor M10 and the eleventh thyristor M11, thereby making the current in the first selection submodule 31 equal to the current in the twelfth thyristor M12.

[0065] When the differential signal increases, the first selection submodule 31 increases the voltage at the first input terminal of the current adjustment submodule 33, thereby reducing the voltage between the drain and source of the twelfth thyristor M12, and thus reducing the current. However, the third current source I3 keeps the sum of the currents flowing through the first selection submodule 31 and the twelfth thyristor M12 constant, and the current flowing through the twelfth thyristor M12 increases when the first selection submodule 31 increases and decreases when the first selection submodule 31 decreases. The eleventh thyristor M11 and the twelfth thyristor M12 are connected in series, so that the currents flowing through the eleventh thyristor M11 and the twelfth thyristor M12 need to be kept equal. The eleventh thyristor M11 increases its drain voltage, thereby reducing the situation where the current decreases due to the increase in the voltage at the first input terminal of the current adjustment submodule 33. The increase in the drain voltage of the eleventh thyristor M11 increases the gate voltage of the thirteenth thyristor M13, thereby reducing the current flowing through the first resistor R1.

[0066] When the differential signal decreases, the first selection submodule 31 reduces the voltage at the first input terminal of the current adjustment submodule 33, thereby increasing the voltage between the drain and source of the twelfth thyristor M12, and thus increasing the current. However, the third current source I3 keeps the sum of the currents flowing through the first selection submodule 31 and the twelfth thyristor M12 constant, and the current flowing through the twelfth thyristor M12 increases when the first selection submodule 31 increases and decreases when the first selection submodule 31 decreases. The eleventh thyristor M11 and the twelfth thyristor M12 are connected in series, so that the currents flowing through the eleventh thyristor M11 and the twelfth thyristor M12 need to be kept equal. The eleventh thyristor M11 reduces its drain voltage, thereby reducing the possibility of an increase in current caused by a decrease in the voltage at the first input terminal of the current adjustment submodule 33. The decrease in the drain voltage of the eleventh thyristor M11 reduces the gate voltage of the thirteenth thyristor M13, thereby reducing the current flowing through the first resistor R1.

[0067] The second selection submodule 32 includes a fourteenth thyristor M14 and a fifteenth thyristor M15, both of which are NMOS transistors. The gate of the fourteenth thyristor M14 is connected to the first input terminal of the second selection submodule 32, and the gate of the fifteenth thyristor M15 is connected to the second input terminal of the second selection submodule 32. The source of the fourteenth thyristor M14 is connected to the source of the fifteenth thyristor M15 and the control terminal of the second selection submodule 32, and the drain of the fourteenth thyristor M14 is connected to the drain of the fifteenth thyristor M15 and the output terminal of the second selection submodule 32.

[0068] When differential signals are input to the fourteenth thyristor M14 and the fifteenth thyristor M15 respectively, the gate voltages of the fourteenth thyristor M14 and the fifteenth thyristor M15 are equal in magnitude but opposite in direction. Because the sources of the fourteenth thyristor M14 and the fifteenth thyristor M15 are connected to each other, and the drains of the fourteenth thyristor M14 and the fifteenth thyristor M15 are also connected to each other, the voltages between the drains of the fourteenth thyristor M14 and the source and drain of the fifteenth thyristor M15 are equal.

[0069] The second selection submodule 32 causes the voltage at one end of the second resistor R2 connected to the positive terminal of the first current source I1 to change with the negative voltage of the differential signal. When the differential signal increases, the first selection submodule 31 increases the voltage at one end of the positive terminal of the first current source I1, thereby increasing the current flowing through the second resistor R2. When the differential signal decreases, the first selection submodule 31 decreases the voltage at one end of the positive terminal of the first current source I1, thereby decreasing the current flowing through the second resistor R2.

[0070] The current flowing through the second resistor R2 increases as the differential signal increases and decreases as the differential signal decreases, thus facilitating the slew rate to match the magnitude of the differential signal in the input differential amplifier circuit.

[0071] The implementation principle of the slew rate adaptive amplifier circuit in this application embodiment is as follows: a differential signal is input to a differential amplifier module 1 and two follower modules 2. The differential amplifier module 1 outputs an amplified signal according to the differential signal, and at the same time, the tail current of the differential amplifier module 1 is output from the controlled terminal of the differential amplifier module 1.

[0072] Two follower modules 2 input the differential signal to the current control module 3. When the differential signal increases, the current control module 3 increases the current flowing through the second resistor R2 and decreases the current flowing through the first resistor R1. Then, the mirror module 4 replicates the current flowing through the second resistor R2 to the controlled terminal of the differential amplifier module 1, and the ratio of the current replicated by the mirror module 4 is the width-to-length ratio of the eighth thyristor M8 and the ninth thyristor M9, thereby increasing the slew rate of the differential amplifier module 1 and reducing the distortion caused by the small slew rate and large differential signal in the differential amplifier module 1.

[0073] When the differential signal increases, the current control module 3 reduces the current flowing through the second resistor R2 and increases the current flowing through the first resistor R1. Then, the mirror module 4 copies the current flowing through the second resistor R2 to the controlled terminal of the differential amplifier module 1. The ratio of the current copied by the mirror module 4 is the width-to-length ratio of the eighth thyristor M8 and the ninth thyristor M9, thereby reducing the slew rate of the differential amplifier module 1 and mitigating the increased losses caused by a large slew rate and a small differential signal.

[0074] The differential amplifier module 1 is controlled by the current control module 3, which makes it easy to match the slew rate with the magnitude of the differential signal input to the differential amplifier circuit.

[0075] Example 2.

[0076] This application discloses a slew rate adaptive amplifier circuit.

[0077] Reference Figure 1 The difference between the slew rate adaptive amplifier circuit of this application embodiment and Embodiment 1 is that the differential amplifier module 1 still includes a first thyristor M1, a second thyristor M2, a third thyristor M3, and a fourth thyristor M4. However, the first thyristor M1 and the second thyristor M2 are NMOS transistors, and the third thyristor M3 and the fourth thyristor M4 are PMOS transistors.

[0078] The gate of the first thyristor M1 is connected to the first input terminal of the differential amplifier module 1, and the gate of the second thyristor M2 is connected to the second input terminal of the differential amplifier module 1. The sources of both the first thyristor M1 and the second thyristor M2 are connected to the controlled terminal of the differential amplifier module 1. The drain of the first thyristor M1 is connected to the drain of the third thyristor M3, the gate of the third thyristor M3, and the gate of the fourth thyristor M4. The sources of both the third thyristor M3 and the fourth thyristor M4 are connected to the power supply ground. The drain of both the fourth thyristor M4 and the second thyristor M2 are connected to the output terminal of the differential amplifier module 1.

[0079] The implementation principle of the slew rate adaptive amplifier circuit in this application is as follows: the parasitic diodes built into the first thyristor M1 and the second thyristor M2 allow the current to flow directly from the source to the drain. The sum of the drain-source currents flowing through the first thyristor M1 and the second thyristor M2 is the tail current of the control terminal of the differential amplifier module 1. The drain current of the first thyristor M1 is replicated to the drain of the fourth thyristor M4 through the third thyristor M3 and the fourth thyristor M4. The drain current of the fourth thyristor M4 is equal to the sum of the drain current of the second thyristor M2 and the output current of the differential amplifier module 1. Therefore, the output current of the differential amplifier module 1 is equal to the drain current of the first thyristor M1 minus the drain current of the second thyristor M2, thereby facilitating the output of the amplified signal from the output terminal of the differential amplifier module 1.

[0080] Example 3.

[0081] This application discloses a slew rate adaptive amplifier circuit.

[0082] Reference Figure 1The difference between the slew rate adaptive amplifier circuit in this embodiment and Embodiment 1 is that the follower module 2 also includes a seventh thyristor M7 and a second current source I2. However, the seventh thyristor M7 is an NMOS transistor, the negative terminal of the second current source I2 is connected to the power supply VDD, and the positive terminal of the second current source I2 is connected to the source of the seventh thyristor M7 and the output terminal of the follower module 2. The gate of the seventh thyristor M7 is connected to the input terminal of the follower module 2. The drain of the seventh thyristor M7 is connected to the power supply ground.

[0083] The implementation principle of the slew rate adaptive amplifier circuit in this application embodiment is as follows: the seventh thyristor M7 and the second current source I2 form a source follower, thereby facilitating the input of the differential signal to the current control module 3. At the same time, the gate impedance of the seventh thyristor M7 is large, thereby reducing the impact on the differential signal input to the differential amplifier module 1.

[0084] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A slew rate adaptive amplifier circuit, characterized in that: The system includes a differential amplifier module (1), a current control module (3), a first current source I1, a mirror module (4), a first resistor R1, and a second resistor R2. The differential amplifier module (1) has a first input terminal, a second input terminal, an output terminal, and a controlled terminal. The first and second input terminals of the differential amplifier module (1) are used to input differential signals, and the output terminal of the differential amplifier module (1) is used to output amplified signals. The current control module (3) has a first control terminal, a second control terminal, a first input terminal, a second input terminal, and an output terminal. The negative terminal of the first current source I1 is connected to the power supply VDD, and the anode of the first current source I1 is connected to one end of the first resistor R1 and one end of the second resistor R2. The first control terminal of the current control module (3) is connected to the other end of the first resistor R1. The second control terminal of the current control module (3) is connected to the other end of the second resistor R2. The first input terminal of the current control module (3) is connected to the first input terminal of the differential amplifier module (1). The second input terminal of the current control module (3) is connected to the second input terminal of the differential amplifier module (1). The current control module (3) is used to control the current flowing through the first resistor R1 and the second resistor R2 according to the differential signal. The mirror module (4) is provided with a first input terminal and a second input terminal. The first input terminal of the mirror module (4) is connected to the output terminal of the current control module (3). The second output terminal of the mirror module (4) is connected to the controlled terminal of the differential amplifier module (1). The mirror module (4) is used to copy the output current of the differential amplifier module (1) to the controlled terminal of the differential amplifier module (1).

2. The slew rate adaptive amplifier circuit according to claim 1, characterized in that: The differential amplifier module (1) includes a first thyristor M1, a second thyristor M2, a third thyristor M3, and a fourth thyristor M4. The first thyristor M1 and the second thyristor M2 are PMOS transistors, and the third thyristor M3 and the fourth thyristor M4 are NMOS transistors. The gate of the first thyristor M1 is connected to the first input terminal of the differential amplifier module (1), and the gate of the second thyristor M2 is connected to the second input terminal of the differential amplifier module (1). The source of the first thyristor M1 and the source of the second thyristor M2 are both connected to the controlled terminal of the differential amplifier module (1). The drain of the first thyristor M1 is connected to the drain of the third thyristor M3, the gate of the third thyristor M3, and the gate of the fourth thyristor M4. The source of the third thyristor M3 and the source of the fourth thyristor M4 are both connected to the power supply VDD. The drain of the fourth thyristor M4 and the drain of the second thyristor M2 are both connected to the output terminal of the differential amplifier module (1).

3. The slew rate adaptive amplifier circuit according to claim 1, characterized in that: The mirror module (4) includes a fifth thyristor M5 and a sixth thyristor M6. Both the fifth thyristor M5 and the sixth thyristor M6 are PMOS transistors. The drain of the fifth thyristor M5, the gate of the fifth thyristor M5, and the gate of the sixth thyristor M6 are all connected to the first input terminal of the mirror module (4). The drain of the sixth thyristor M6 is connected to the second input terminal of the mirror module (4). The source of the fifth thyristor M5 and the source of the sixth thyristor M6 are both connected to the power supply ground.

4. The slew rate adaptive amplifier circuit according to claim 1, characterized in that: A follower module (2) is provided between the first input terminal of the current control module (3) and the first input terminal of the differential amplifier module (1), and between the second input terminal of the current control module (3) and the second input terminal of the differential amplifier module (1). Each follower module (2) is provided with an input terminal and an output terminal. The input terminal of one follower module (2) is connected to the first input terminal of the differential amplifier module (1), and the input terminal of the other follower module (2) is connected to the second input terminal of the differential amplifier module (1). The output terminal of one follower module (2) is connected to the first input terminal of the current control module (3), and the input terminal of the other follower module (2) is connected to the second input terminal of the current control module (3). The follower module (2) is used to input the differential signal input to the differential amplifier module (1) into the current control module (3).

5. The slew rate adaptive amplifier circuit according to claim 4, characterized in that: The follower module (2) includes a seventh thyristor M7 and a second current source I2. The seventh thyristor M7 is a PMOS transistor. The gate of the seventh thyristor M7 is connected to the input terminal of the follower module (2). The drain of the seventh thyristor M7 is connected to the power supply VDD. The source of the seventh thyristor M7 and the negative terminal of the second current source I2 are both connected to the output terminal of the follower module (2). The positive terminal of the second current source I2 is connected to the power supply ground.

6. The slew rate adaptive amplifier circuit according to claim 1, characterized in that: The current control module (3) includes a first selection submodule (31) and a current adjustment submodule (33). The first selection submodule (31) is provided with a first input terminal, a second input terminal, a first output terminal and a second output terminal. The current adjustment submodule (33) is provided with a first input terminal, a second input terminal and a control terminal. The first output terminal of the first selection submodule (31) is connected to the first input terminal of the current adjustment submodule (33). The second output terminal of the first selection submodule (31) is connected to the second input terminal of the current adjustment submodule (33). The first input terminal of the first selection submodule (31) is connected to the first input terminal of the current control module (3). The second input terminal of the first selection submodule (31) is connected to the second input terminal of the current control module (3). The control terminal of the current adjustment submodule (33) is connected to the first control terminal of the current control module (3). The first selection submodule (31) is used to control the current adjustment submodule (33) according to the positive voltage in the differential signal. The current adjustment submodule (33) is used to adjust the current flowing through the first resistor R1.

7. The slew rate adaptive amplifier circuit according to claim 6, characterized in that: The first selection submodule (31) includes an eighth thyristor M8 and a ninth thyristor M9. The eighth thyristor M8 and the ninth thyristor M9 are PMOS transistors. The source of the eighth thyristor M8 and the source of the ninth thyristor M9 are both connected to the first output terminal of the first selection submodule (31). The drain of the eighth thyristor M8 and the drain of the ninth thyristor M9 are both connected to the second output terminal of the first selection submodule (31). The gate of the eighth thyristor M8 is connected to the first input terminal of the first selection submodule (31), and the gate of the ninth thyristor M9 is connected to the second input terminal of the first selection submodule (31).

8. The slew rate adaptive amplifier circuit according to claim 7, characterized in that: The current adjustment submodule (33) includes a third current source I3, a tenth thyristor M10, an eleventh thyristor M11, a twelfth thyristor M12, and a thirteenth thyristor M13. The tenth thyristor M10 and the eleventh thyristor M11 are NMOS transistors, and the twelfth thyristor M12 and the thirteenth thyristor M13 are PMOS transistors. The source of the tenth thyristor M10 and the source of the eleventh thyristor M11 are both connected to the power supply VDD. The drain of the tenth thyristor M10 is connected to the second input terminal of the current adjustment submodule (33). The gate of 10 is connected to the gate of the eleventh thyristor M11. The drain of the eleventh thyristor M11 is connected to the drain of the twelfth thyristor M12, the gate of the twelfth thyristor M12, and the gate of the thirteenth thyristor M13. The source of the twelfth thyristor M12 is connected to the negative terminal of the third current source I3 and the first input terminal of the current adjustment submodule (33). The positive terminal of the third current source I3 is connected to the power supply ground. The drain of the thirteenth thyristor M13 is connected to the control terminal of the current adjustment submodule (33). The source of the thirteenth thyristor M13 is connected to the power supply ground.

9. The slew rate adaptive amplifier circuit according to claim 6, characterized in that: The current control module (3) further includes a second selection submodule (32). The second selection submodule (32) is provided with a first input terminal, a second input terminal, an output terminal and a control terminal. The first input terminal of the second selection submodule (32) is connected to the first input terminal of the current control module (3). The second input terminal of the second selection submodule (32) is connected to the second input terminal of the current control module (3). The control terminal of the second selection submodule (32) is connected to the second control terminal of the current control module (3). The output terminal of the second selection submodule (32) is connected to the output terminal of the current control module (3). The second selection submodule (32) is used to control the current flowing through the second resistor R2 according to the signal with the smaller voltage in the differential signal.

10. The slew rate adaptive amplifier circuit according to claim 9, characterized in that: The second selection submodule (32) includes a fourteenth thyristor M14 and a fifteenth thyristor M15. The fourteenth thyristor M14 and the fifteenth thyristor M15 are NMOS transistors. The gate of the fourteenth thyristor M14 is connected to the first input terminal of the second selection submodule (32). The gate of the fifteenth thyristor M15 is connected to the second input terminal of the second selection submodule (32). The source of the fourteenth thyristor M14 is connected to the source of the fifteenth thyristor M15 and the control terminal of the second selection submodule (32). The drain of the fourteenth thyristor M14 is connected to the drain of the fifteenth thyristor M15 and the output terminal of the second selection submodule (32).

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