A short-term warning method for solid-state hard drives

Abstract

A short-term warning method for solid-state drives (SSDs) stores hot data and builds a short-term warning system that periodically predicts the lifespan of SSDs, including predictions of read disturbance (RD) and endurance. By predicting the number of bit errors (Fail Bit Count (FBC)) in flash memory blocks after a certain number of operations, the system adaptively selects a low-density parity check (LDPC) code with appropriate error correction capabilities based on the FBC prediction results. This method saves more storage space for user data in the early stages of the SSD's lifespan and improves the error correction capability of the LDPC code in the later stages of the SSD's lifespan, thereby extending the SSD's lifespan.

Description

Technical Field

[0001] The present invention relates to the field of SSDs, and in particular to a short-term early warning method for solid-state drives. Background Art

[0002] With the advent of the big data era, market demand for large-capacity storage has exploded. With its advantages of fast read and write speeds, low power consumption, high reliability, and high storage density, solid-state drives (SSDs) have replaced hard disk drives (HDDs) and become the mainstream storage device.

[0003] As a data storage device, an SSD has two key components: the SSD controller and the flash memory array. The SSD's memory array is typically NAND flash memory. Since the advent of NAND flash memory, its memory cell size has been shrinking annually, resulting in continuously increasing storage density and increasingly severe crosstalk between cells. In recent years, when 2D NAND flash memory reached a bottleneck in cell size reduction, manufacturers began researching 3D NAND architecture to improve space efficiency and storage density. Based on the charge storage method, 3D NAND flash memory can be divided into two types: floating-gate (FG) and charge-trap (CT). FG NAND flash memory stores charge in an isolated floating gate layer, allowing free charge movement; CT NAND flash memory, on the other hand, stores charge in defects in the nitride layer, preventing free charge movement. 2D NAND flash memory mostly uses FG technology, while 3D NAND flash memory mostly uses CT technology. Due to its stacked architecture and shared storage layer, the failure mechanisms in 3D NAND flash memory are much more complex than those in 2D NAND flash memory. Due to the presence of a common storage layer, charge can migrate from the target memory cell to the spatial region between adjacent word lines (WLs). Furthermore, erase and write operations on NAND flash memory can create shallow energy level defects in the CT layer of the memory cell, increasing the likelihood of lateral charge diffusion and making the bit error rate of the flash block difficult to predict after erase and write wear. Hot data stored in the flash array is subject to frequent read operations, causing read disturb, which makes predicting the lifespan of 3D CT NAND flash memory more challenging.

[0004] Many algorithms in SSD controllers, such as the Flash Translation Layer (FTL), serve the flash array. Therefore, optimizing NAND flash memory is crucial for SSD development. Error bits are inevitable in NAND flash memory. To correct these errors, low-density parsing (LDPC) codes have been introduced. LDPC codes have become the mainstream error-correcting code (ECC) due to their advantages, including error correction performance approaching the Shannon limit, good compatibility, simple decoding algorithms, and ease of industrial implementation. Currently, research is proposing dynamic LDPC code technology, which can save storage space for user data in the early stages of NAND flash memory lifespan and extend its lifespan. However, this technology requires accurate prediction of NAND flash memory reliability degradation trends. Previously established lifespan prediction models are typically based on machine learning techniques, requiring additional on-chip training and significant data overhead. Furthermore, these models require numerous input parameters, such as operating time and threshold voltage (Vth), which increases the overhead of dynamic LDPC codes.

[0005] The era of big data places higher demands on the storage performance of NAND flash-based SSDs. Improving NAND flash storage density is a promising solution. However, higher NAND flash storage density increases bit errors and shortens its lifespan. Therefore, lifespan prediction and LDPC code optimization are crucial for the development of NAND flash-based SSDs. Summary of the Invention

[0006] In order to overcome the deficiencies of the above technologies, the present invention provides a short-term warning method that can periodically predict the lifespan and extend the lifespan of SSDs.

[0007] The technical solution adopted by the present invention to overcome the technical problems is:

[0008] A short-term warning method for a solid-state hard drive, comprising:

[0009] S01. Select a flash memory block in the SSD for wear and record the number of erases and writes i;

[0010] S02. If the number of erase times i is the threshold value X or p1 times, step S03 is executed. If the number of erase times i is not the threshold value or an integer multiple of step, step S01 is returned to, p1 is m times the step, where m is a positive integer;

[0011] S03. Record the number of bit errors after p1 wear

[0012] S04. Through the formula Calculate the predicted number of bit errors after p2 wear times Where a3, a4, b3, b4, c3, c4, d3, d4 are all constants, FBC X is the number of bit errors after the Xth wear, p2>p1≥X;

[0013] S05. Determine the number of bit errors Is it less than C1? If yes, assign LDPC code 1 and execute step S09; if not, execute step S06;

[0014] S06. Determine the number of bit errors FBC p2 Is it less than C2? If yes, assign LDPC code 2 and execute step S09; if not, execute step S07;

[0015] S07. Determine the number of bit errors FBC p2 Is it less than C3? If so, assign LDPC code 3 and execute step S09; if not, execute step S08;

[0016] S08. Determine the number of bit errors FBC p2 Is it less than C4? If so, assign LDPC code 4 and execute step S09; if not, execute step S10;

[0017] S09. Before writing data into the SSD, encode the written data according to the corresponding LDPC and then execute step S01; S10. Execute step S01 after the system issues an early warning.

[0018] Preferably, in step S02, the threshold X is set to 10 and the step is set to 200.

[0019] Preferably, in step S04, a3=0.93, a4=-4090, b3=0.00032, b4=0.00054, c3=0, c4=0, d3=0, d4=0.

[0020] Preferably, the value of C1 in step S05 is 16, the value of C2 in step S06 is 50, the value of C3 in step S07 is 95, and the value of C4 in step S08 is 151.

[0021] A short-term warning method for a solid-state hard drive, comprising:

[0022] S01. Select a flash memory block in the SSD for a read operation and record the number of reads j;

[0023] S02. If the number of reads j is the threshold value Y or r1, then execute step S03. If the number of reads j is not the threshold value or an integer multiple of step, then return to step S01, where r1 is p times step, and p is a positive integer.

[0024] S03. Record the number of bit errors after r1 readings

[0025] S04. Through the formula Calculate the predicted number of bit errors after r2 readings Where a1, a2, b1, b2, c1, c2, d1, d2 are all constants, FBC Y is the number of bit errors after the Yth reading, r2>r1≥Y;

[0026] S05. Determine the number of bit errors Is it greater than C4? If yes, go to step S06; if not, go back to step S01;

[0027] S06. After the system issues an early warning, execute step S01.

[0028] Preferably, in step S02, the threshold Y is set to 100 and the step is set to 100.

[0029] Preferably, in step S04, a1=2.2837, a2=-27700, b1=0.000069, b2=0.0000997, c1=-1.27797, c2=26905, d1=-0.00069, d2=-0.00052.

[0030] Preferably, in step S05, the value of C4 is 151.

[0031] The present invention has the beneficial effect of constructing a short-term warning system for hot data storage in SSDs that can periodically predict the lifespan, including predictions of read disturbance (RD) and endurance. By predicting the number of bit errors (Fail Bit Count, FBC) in flash memory blocks after a certain number of operations, the system can adaptively select a low-density parity check (LDPC) code with corresponding error correction capabilities based on the FBC prediction results. This saves more storage space for user data in the early stages of the SSD's lifespan, improves the error correction capability of the LDPC code in the later stages of the SSD's lifespan, and extends the SSD's lifespan. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a flow chart of system wear prediction of the present invention;

[0033] Figure 2 is a flow chart of system read disturbance prediction of the present invention;

[0034] Figure 3 This is a parameter table of the NAND flash memory chip used in the present invention;

[0035] Figure 4 This is a verification diagram of the short-term life prediction system of the present invention;

[0036] Figure 5 This is a NAND flash memory wear characteristic diagram of the present invention;

[0037] Figure 6 This is a NAND flash memory read interference characteristic diagram of the present invention;

[0038] Figure 7 This is a verification diagram of the wear prediction model of the present invention;

[0039] Figure 8 This is a verification diagram of the read disturbance prediction model of the present invention. DETAILED DESCRIPTION

[0040] The following is combined with Figure 1 To the attached Figure 8 The present invention is further described.

[0041] As attached Figure 1 As shown, a short-term warning method for a solid-state hard disk for predicting wear conditions includes the following steps: S01. Select a flash memory block in the SSD for wear and record the number of erase and write times i.

[0042] S02. If the number of erase / write times i is the threshold value X or p1 times, execute step S03. If the number of erase / write times i is not the threshold value or an integer multiple of step, return to execute step S01, where p1 is m times step, and m is a positive integer.

[0043] S03. Record the number of bit errors after p1 wear

[0044] S04. Through the formula Calculate the predicted number of bit errors after p2 wear times Where a3, a4, b3, b4, c3, c4, d3, d4 are constants related to the working environment and chip type of the solid state drive. X is the number of bit errors after the Xth wear, p2>p1≥X.

[0045] S05. Determine the number of bit errors Is it less than C1? If so, assign LDPC code 1 and execute step S09; if not, execute step S06.

[0046] S06. Determine the number of bit errors Is it less than C2? If so, assign LDPC code 2 and execute step S09; if not, execute step S07.

[0047] S07. Determine the number of bit errors Is it less than C3? If so, assign LDPC code 3 and execute step S09; if not, execute step S08.

[0048] S08. Determine the number of bit errors Is it less than C4? If so, assign LDPC code 4 and execute step S09; if not, execute step S10.

[0049] S09. Before writing the data into the SSD, encode the written data according to the corresponding LDPC and then execute step S01.

[0050] S10. After the system issues an early warning, execute step S01.

[0051] In one embodiment of the present invention, the threshold value X in step S02 is 10 and the step value is 200. Figure 3 As shown, for the BiCS structure 3D TLC CT NAND flash memory used in the test, in step S04, a3 = 0.93, a4 = -4090, b3 = 0.00032, b4 = 0.00054, c3 = 0, c4 = 0, d3 = 0, d4 = 0. In step S05, C1 is 16, in step S06, C2 is 50, in step S07, C3 is 95, and in step S08, C4 is 151.

[0052] In this embodiment, the FBC that has experienced 3000 and 6000 wears is predicted, and the prediction results are as follows: Figure 7 The dashed line in the figure shows that, to validate the model's effectiveness, actual wear tests were conducted, and the test data demonstrates a high degree of prediction accuracy. It should be noted that the LDPC code decoding capacity warning limit C in this example is the highest FBC at which the average number of decoding iterations required does not exceed 20 at the code rate.

[0053] The error bit prediction model is to select the target predicted wear level, and then record the error bit count FBC when the flash memory block is erased and written for the 10th time by establishing a mapping table. Then, the current error bit count FBC is recorded every Step of erase and write wear. When the latest error bit count FBC is recorded, the previous error bit count FBC record will be overwritten to save storage space. 10 and Using the short-term prediction model for durability, we can get the number of bit errors FBC after experiencing p2 wear times. Then enter the adaptive LDPC module and judge The system determines whether the error correction limit of the four set LDPC codes has been exceeded, and allocates the most suitable LDPC code to the data in the next operation phase based on the judgment result. When the LDPC with the maximum error correction capability cannot complete the error correction, the system issues an early warning. In order to compare the decoding capabilities of adaptive LDPC and static LDPC, we compared the average number of iterations required for decoding of the two schemes. The results are shown in the attached figure. Figure 4 As shown in the figure. When FBC reaches 50-100 / KB, which is in the late stage of the SSD life cycle, LDPC code 3 has the same decoding capability as the adaptive LDPC code. However, when FBC exceeds 100 / KB, LDPC code 3 will not be able to correct errors and the block will be marked as a bad block, while the short-term life prediction system can still correct errors until FBC exceeds 150 / KB. As shown in the figure. Figure 2 As shown, the short-term warning method for a solid-state drive for predicting frequent read conditions includes the following steps:

[0054] S01. Select a flash memory block in the SSD for a read operation and record the number of reads j.

[0055] S02. If the number of reads j is the threshold Y or r1 times, execute step S03. If the number of reads j is not the threshold or an integer multiple of step, return to execute step S01, where r1 is p times step and p is a positive integer.

[0056] S03. Record the number of bit errors after r1 readings

[0057] S04. Through the formula Calculate the predicted number of bit errors after r2 readings Where a1, a2, b1, b2, c1, c2, d1, and d2 are constants related to the working environment and chip type of the solid-state drive. Y is the number of bit errors after the Yth reading, r2>r1≥Y.

[0058] S05. Determine the number of bit errors Is it greater than C4? If so, execute step S06; if not, return to execute step S01.

[0059] S06. After the system issues an early warning, execute step S01.

[0060] In one embodiment of the present invention, the threshold value Y in step S02 is 100, and the step value is 100. Figure 3As shown, for the BiCS structure 3D TLC CT NAND flash memory used in the test, in step S04, a1=2.2837, a2=-27700, b1=0.000069, b2=0.0000997, c1=-1.27797, c2=26905, d1=-0.00069, d2=-0.00052. In step S05, the value of C4 is 151. In this embodiment, the FBC after 5000 and 10000 reads is predicted, and the prediction results are as follows. Figure 8 In order to verify the model effect, an actual read disturbance test was conducted, and the test data showed that the prediction results were highly accurate.

[0061] For read-intensive applications (read times exceeding 10,000), when the number of bit errors FBC exceeds the error correction capability of the LDPC code, the data can be migrated to a new memory block or DRAM storage unit.

[0062] Attachment Figure 5 The figure shows how the bit error count (FBC) changes with the increase in the number of reads. It can be observed that the bit error count (FBC) of different flash memory blocks with the same number of reads and endurance is different, but the bit error count (FBC) increases with the increase in the number of wears. At the same time, the trend of the bit error count (FBC) is similar in the figure as the number of reads increases. Figure 6 As shown in the figure, it suggests that there may be a certain potential correlation between the number of bit errors FBC in the early stage of read disturbance and the number of bit errors FBC in the late stage of read disturbance. Unlike read disturbance, erase and write wear causes permanent damage to storage cells, increasing the impact of the final failure mechanism and possibly expanding the characteristic differences of storage cells in the later stage of their life. Figure 6 The FBC curves for different blocks and different read counts are shown. We can observe that, relative to the RD curve, the FBC increases rapidly under high wear conditions.

[0063] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A short-term warning method for a solid-state hard disk, characterized in that: include: S01. Select a flash memory block in the SSD for wear and record the number of erases and writes i; S02. If the number of erase times i is the threshold value X or p1 times, step S03 is executed. If the number of erase times i is not the threshold value or an integer multiple of step, step S01 is returned to, p1 is m times the step, where m is a positive integer; S03. Record the number of bit errors after p1 wear S04. Through the formula Calculate the predicted number of bit errors after p2 wear times Where a3, a4, b3, b4, c3, c4, d3, d4 are all constants, FBC X is the number of bit errors after the Xth wear, p2>p1≥X; S05. Determine the number of bit errors Is it less than C1? If yes, assign LDPC code 1 and execute step S09; if not, execute step S06; S06. Determine the number of bit errors Is it less than C2? If yes, assign LDPC code 2 and execute step S09; if not, execute step S07; S07. Determine the number of bit errors Is it less than C3? If so, assign LDPC code 3 and execute step S09; if not, execute step S08; S08. Determine the number of bit errors Is it less than C4? If so, assign LDPC code 4 and execute step S09; if not, execute step S10; S09 before the data is written to the SSD according to the corresponding LDPC encoding of the written data after executing step S01; S10. After the system issues an early warning, execute step S01.

2. The solid-state hard disk short-term warning method according to claim 1, characterized in that: In step S02, the threshold value X is 10 and the step value is 200.

3. The solid state drive short-term warning method according to claim 1, wherein: In step S04 a3=0.93, a4=-4090, b3=0.00032, b4=0.00054, c3=0, c4=0, d3=0, d4=0.

4. The solid state drive short-term warning method according to claim 1, wherein: In step S05 , the value of C1 is 16; in step S06 , the value of C2 is 50; in step S07 , the value of C3 is 95; and in step S08 , the value of C4 is 151.

5. A short-term warning method for a solid-state hard disk, characterized in that: include: S01. Select a flash memory block in the SSD for a read operation and record the number of reads j; S02. If the number of reads j is the threshold value Y or r1, then execute step S03. If the number of reads j is not the threshold value or an integer multiple of step, then return to step S01, where r1 is p times step, and p is a positive integer; S03. Record the number of bit errors after r1 readings S04. Through the formula Calculate the predicted number of bit errors after r2 readings Where a1, a2, b1, b2, c1, c2, d1, d2 are all constants, FBC Y is the number of bit errors after the Yth reading, r2>r1≥Y; S05. Determine the number of bit errors Is it greater than C4? If yes, go to step S06; if not, go back to step S01; S06. After the system issues an early warning, execute step S01.

6. The solid state drive short-term warning method according to claim 5, characterized in that: In step S02, the threshold Y is set to 100 and the step is set to 100.

7. The solid state drive short-term warning method according to claim 5, characterized in that: In step S04 a1=2.2837, a2=-27700, b1=0.000069, b2=0.0000997, c1=-1.27797, c2=26905, d1=-0.00069, d2=-0.00052.

8. The solid state drive short-term warning method according to claim 5, characterized in that: In step S05, the value of C4 is 151.

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