Analog error detection and correction method, corresponding circuit and storage medium

Abstract

An analog error correction circuit for implementing an analog error correction code is disclosed. The analog circuit includes a crossbar array of memristors or other non-volatile adjustable resistance memory devices. The crossbar array includes a first crossbar array portion programmed with the value of a target calculation matrix and a second crossbar array portion programmed with the value of an encoder matrix, for correcting calculation errors in matrix multiplication of an input vector and a calculation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion programmed with the value of a decoder matrix, thereby implementing single-cycle error detection. Computational errors are detected based on the output of a decoder matrix circuit, and the location of the error is determined via an inverse matrix multiplication operation, thereby feeding back the decoder matrix output to the decoder matrix.

Description

Background Art

[0001] Vector-matrix computations are performed in many applications including data compression, neural networks, encryption, etc. Hardware techniques for optimizing vector-matrix computations include the use of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), graphics processing units (GPUs), and more recently, an analog dot product computation device based on a crossbar array. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] According to one or more different aspects, the present disclosure is described in detail with reference to the following drawings. The drawings are provided for illustration purposes only and merely depict typical or example aspects of the disclosed technology.

[0003] Figure 1 Circuit implementations for analog error detection and correction in accordance with aspects of the disclosed technology are depicted.

[0004] Figure 2 Schematically depicted is obtaining a measured syndrome vector as an output from a decoder matrix in accordance with aspects of the disclosed technique, wherein a value of the measured syndrome vector indicates whether a computational error is present in the matrix multiplication output.

[0005] Figure 3 An inverse matrix multiplication operation between a thresholded syndrome vector and a decoder matrix is ​​schematically depicted in accordance with aspects of the disclosed technique to obtain an inverse matrix multiplication output vector indicating locations of computation errors in the matrix multiplication output.

[0006] Figure 4 is a flow chart of an illustrative method for programming a crossbar-based analog error detection and correction circuit and utilizing the programmed circuit to detect and correct computation errors in matrix multiplication outputs in accordance with aspects of the disclosed technology.

[0007] Figure 5 are example computing components that can be used to implement various features of the disclosed technology.

[0008] The drawings are not exhaustive and do not limit the disclosure to the precise forms disclosed. DETAILED DESCRIPTION

[0009] Analog computing devices based on crossbar arrays have proven to be effective for many applications. A crossbar array, as the term is used herein, refers to an array comprising a set of row lines and a set of column lines that intersect the row lines to form a junction at each intersection, and wherein a corresponding memory device is coupled to each junction and programmed with a matrix value. The memory device coupled to the junction may be a memristor, or may be a device utilizing other non-volatile resistive memory technologies, such as flash memory, spin transfer torque (STT) or magnetic tunnel junction (MTJ) magnetic random access memory (MRAM), phase-change memory, and the like. The input values ​​along each row line of the crossbar array are weighted by the matrix values ​​in each column and accumulated as outputs from each column to form a dot product. As such, an analog memory crossbar array may also be referred to as a dot product engine (DPE).

[0010] Although crossbar arrays are effective for analog computing, inaccuracies when programming memory devices in the crossbar array and noise when reading outputs can affect the accuracy of the computation. In addition, if the junctions in the crossbar array are shorted, unprogrammable, or stuck in an open state, inaccuracies may also occur at the junctions in the crossbar array. Therefore, although memristors or other non-volatile resistive analog memories, crossbar-based matrix multiplication accelerators have shown great promise, their tendency to generate unexpected computational errors may limit their chances of replacing mainstream digital systems. In particular, although various analog computing applications tolerate small errors (e.g., neural networks), significant outliers may cause problems unless detected and corrected.

[0011] A technique for detecting / correcting errors in analog computations is described in co-owned co-pending U.S. Application No. 16 / 429,983. The technique provides error correction codes (ECC) for analog computations that enable detection and correction of computational errors when performing vector-matrix multiplication using a DPE. Various aspects of the technology disclosed herein relate to a circuit implementation for analog ECC described in the co-pending application cited above. According to various aspects of the disclosed technology, a first crossbar array portion is programmed with target computation matrix values, a second crossbar array portion is programmed with encoder matrix values ​​for correcting computational errors in the matrix multiplication result output of the first crossbar array portion, and a third crossbar array portion is programmed with decoder matrix values ​​for detecting computational errors.

[0012] In some aspects, the circuit disclosed herein connects a first crossbar array portion that encodes a target computation matrix and a second crossbar array portion that encodes an encoder matrix to a third crossbar array portion that encodes a decoder matrix, thereby achieving single-cycle analog error detection. The first, second, and third crossbar array portions may form a portion of one or more crossbar arrays. For example, a first crossbar array of memristors may include first and second crossbar array portions, and a second crossbar array connected to the first crossbar array may include a third crossbar array portion. Alternatively, the circuit may include a single crossbar array that includes first, second, and third crossbar array portions.

[0013] Aspects of the disclosed technology also relate to an analog error correction circuit implementation that can implement a reverse DPE operation, such as an inverse matrix multiplication involving a third crossbar array portion that encodes a decoder matrix. The reverse DPE operation enables the location of a computational error in a matrix multiplication output to be determined. More specifically, the third crossbar array portion can receive the matrix multiplication outputs from the first and second crossbar array portions as inputs, and can itself output a syndrome vector that indicates whether there is a computational error in the matrix multiplication output.

[0014] As described in more detail later in the present invention, in some aspects, each column in the decoder matrix may include two non-zero values, and thus, if the syndrome vector includes two outside-threshold values, a computation error may be detected, wherein the outside-threshold value is a value above a first threshold or below a second threshold (the second threshold may be the negative of the first threshold). In addition, in some aspects, the measured syndrome vector may be thresholded (i.e., converted to a binary value) and fed back to the third crossbar array portion to perform an inverse matrix multiplication with the decoder matrix encoded in the third crossbar array portion. In some aspects, the position of a particular expected value in the resulting inverse matrix multiplication output vector may indicate the position of a computation error.

[0015] The circuit implementation disclosed herein provides a technical solution for the technical problem of implementing the analog ECC cited above. The technical solution provides many technical improvements / benefits for analog error detection technology. Among them is the ability to perform single-cycle analog error detection, which improves the efficiency of the analog error detection / correction process, and it is implemented by connecting the first and second cross-switch array portions that encode the encoder matrix and the calculation matrix to the third cross-switch array portion that encodes the decoder matrix. In addition, the encoder and decoder matrices can be selectively disabled, reused and / or rerouted between the cross-switch arrays to dynamically control the use of error detection and save power and / or reduce delay overhead when error detection is not expected or when error detection is only required for part of the data in the computation batch. Further, the analog error correction implementation involving reverse DPE operation according to the exemplary aspects of the disclosed technology provides a technical benefit of eliminating the need for a separate lookup table for error position calculation, which leads to greater chip area and energy savings.

[0016] Figure 1 An example implementation of an analog error detection circuit 100 according to various aspects of the disclosed technology is depicted. Circuit 100 includes various crossbar array portions that form part of one or more analog crossbar arrays. Circuit 100 includes a first crossbar array portion that includes circuitry 102 programmed with analog values ​​that represent values ​​of an actual target computation matrix A' for performing a vector-matrix multiplication. Circuit 100 also includes a second crossbar array portion that includes circuitry 104 programmed with values ​​of an encoder matrix A", which is used to correct errors in a first output of the first crossbar array portion, wherein the first output represents a result of a multiplication of an input vector u with the computation matrix A'.

[0017] More specifically, circuit 100 includes a crossbar array of l row lines and n column lines that intersect to form a crossbar junction, wherein a memory device (e.g., a memristor) is coupled to each crossbar junction and encodes a matrix value. Thus, the crossbar array includes lxn memory locations. The l row of the crossbar array can receive an input signal as a vector of length l. Then, the n columns can output an output signal as a vector of length n, which is the dot product of the matrix value encoded in the lxn storage locations and the input signal.

[0018] In some aspects, an lxn matrix A can be programmed into a crossbar switch array comprising l row lines and n column lines. Matrix A can have the following structure: A=(A'|A"), where A' is a target computation matrix (a lxk matrix including the first k columns of A), and A" is an encoder matrix (a lxm matrix including the remaining m=nk columns of matrix A). More specifically, a group of k columns (where k<n) out of the n columns of the crossbar switch array (i.e., the k columns constituting circuit 102) can be programmed with the values ​​of the target computation matrix A'. In addition, a second group of m (e.g., nk) columns (i.e., circuit 104) can be programmed with continuous analog values ​​corresponding to the values ​​of the encoder matrix A". Each row of the encoder matrix A" can be determined based on the corresponding corresponding row of the computation matrix A', so that computation errors above a threshold error value can be detected and corrected in the output vector y representing the result of the matrix multiplication of the input vector u and the matrix A.

[0019] like Figure 1 As depicted in , each memory device coupled to the row and column lines at a corresponding cross junction within circuit 102 may be a memristor 106 or any other suitable non-volatile resistive memory device. Similarly, each memory device coupled to the row and column lines at a corresponding cross junction within circuit 104 may be a memristor 108 or any other suitable non-volatile resistive memory device. Thus, in example aspects, the conductance value of memristor 106 may be tuned to represent the value of the computation matrix A' and the conductance value of memristor 108 may be tuned to represent the value of the encoder matrix A".

[0020] In operation, a set of digital-to-analog converters (DACs) (not shown) may be provided to convert an input signal representing an input vector containing digital values ​​into a set of corresponding voltages, which are then applied to the set of row lines shared between the first crossbar array portion (i.e., circuit 102) and the second crossbar array portion (i.e., circuit 104). More specifically, each element u of the input vector u is i is fed to the corresponding DAC to generate i The first output signal from the first crossbar switch array portion may represent a first output vector c'=uA', which is the result of the desired matrix multiplication calculation between the input vector u and the computation matrix A'. More specifically, each element of the first output vector c' may be the dot product of the input vector u and a corresponding one of the k columns of the circuit 102 encoding the computation matrix A'.

[0021] Along similar lines, the second output signal from the second cross-switch array portion may represent a second output vector c"=uA", which is the result of a matrix multiplication operation between the input vector u and the encoder matrix A". More specifically, each element of the second output vector c" may be the dot product of the input vector u and a corresponding corresponding one of the nk columns of the circuit 104 that encodes the encoder matrix A". The second output vector c" may include redundant symbols that allow correction of computational errors in c'. The first and second output signals may be determined (i.e., the first and second output vectors may be calculated) by reading the current at the analog current measurement device 110, which may be a grounded column conductor, such as a transimpedance amplifier.

[0022] In an example aspect, the value of the encoder matrix A" depends on the value of the computation matrix A' and not on the value of the input vector u. Further, in an example aspect, the size of the encoder matrix A" having nk columns depends on: the alphabet size q (i.e., the number of levels or information bits programmed into each memristor cell 106 in the first crossbar array portion that encodes the computation matrix A'); the expected number of errors τ that the encoder matrix A" is capable of correcting; and the expected error correction capability (i.e., the threshold error value Δ used to delineate detectable / correctable errors).

[0023] Typically, the actual measured output vector y from the first and second crossbar array portions (i.e., circuit 102 and circuit 104) can be expressed as y=c+ε+e, where c represents an ideal calculation result vector of matrix multiplication of the input vector u with the matrix values ​​of both the calculation matrix A' and the encoder matrix A" (e.g., c can be a cascade of the first output vector c' and the second output vector c"); ε is a tolerable simulation inaccuracy; and e is an undesirable error. More specifically, -δ<ε<δ, and therefore may be a bounded tolerable inaccuracy, while e represents a detectable and correctable error when e>Δ or e<-Δ and Δ>δ. In particular, e can be a vector whose non-zero entries are abnormal errors. In some aspects, abnormal errors can be errors greater than δ or less than -δ. Such errors (i.e., errors greater than δ or less than -δ) may be detectable, but may not be correctable if they do not exceed the threshold error value (i.e., they are within [-Δ, Δ]). On the other hand, abnormal errors that exceed the threshold error value (i.e., errors greater than Δ or less than –Δ) may be intolerable errors to be corrected. In some aspects, both δ and Δ are preset thresholds, and the ratio between them is an adjustable parameter. In some aspects, the ratio of δ to Δ (or vice versa) can be tuned to reduce the difference between δ and Δ. For example, in one example aspect, the ratio can be 1, in which case, if the error is detectable, it is also ensured to be correctable. However, doing so may result in an increase in the number of redundant columns of the encoder matrix A".

[0024] Various types of analog computing errors may occur, including transient errors (i.e., errors that reoccur unpredictably), permanent errors, and intrinsic errors. Examples of transient errors include, but are not limited to, read noise from peripheral circuits, memristor conductance fluctuations, and the like. Although transient errors can be detected and corrected using circuit 100 implementing analog ECC, in some scenarios, as an alternative to correcting the error, the calculation can simply be performed again, since the error is unlikely to reoccur, since it is defined as a transient error. Permanent errors include, but are not limited to, conductance value drift, open / short junctions and / or wires, and the like. In example terms, permanent errors are at least detected and are correctable in some scenarios. However, in other scenarios, a DPE block that experiences a permanent error may instead be reprogrammed or replaced entirely. Intrinsic errors include, but are not limited to, inaccurate programming, wire resistance, device IV nonlinearity, and the like. In example terms, intrinsic errors can be considered part of the "normal" operation of a matrix multiplication accelerator based on an analog crossbar and ignored. In other example aspects where an abnormal intrinsic error is detected, circuit 100 and its implemented analog ECC may be used to correct the error, if possible, to improve the accuracy of the computation and / or to intentionally tune the resulting randomness.

[0025] Still reference Figure 1 , circuit 100 also includes a third crossbar switch array portion that encodes the values ​​of the decoder matrix. More specifically, circuit 114 of the third crossbar switch array portion is programmed with the values ​​of the decoder matrix / parity check matrix. Similar to the first and second crossbar switch array portions, the third crossbar switch array portion (i.e., circuit 114) includes intersecting row lines and column lines, wherein a corresponding memory device (e.g., memristor 118) is coupled to each cross junction between the corresponding row line and column line. The first and second crossbar switch array portions (i.e., circuit 102 and circuit 104) can be connected to the third crossbar switch array portion (i.e., circuit 114) so ​​that single-cycle analog error detection is provided. That is, the current outputs from the first and second crossbar array sections (which represent an output vector c) including c' (the desired calculation result) and c" (redundant symbols for correcting errors in the desired calculation result) can be directly fed into the third crossbar array section (i.e., circuit 114) without undergoing processing such as analog-to-digital conversion. In some aspects, the column lines of circuit 114 can be the same as the column lines of circuits 102 and 104. In this way, circuits 102, 104, and 114 - representing the first, second, and third crossbar array sections, respectively - can constitute a single crossbar array.

[0026] In example aspects, the values ​​of the decoder / parity check matrix can follow various rules specified by analog ECC, depending on the number of detectable and / or correctable errors sought. For example, to detect a single outlier error, given positive integers r and n, such that r≤n, then the decoder / parity check matrix H is an rxn matrix on {0,1} that satisfies the following properties: 1) each column in H is a unit vector, i.e., each column contains exactly one 1, and 2) the number of 1s in each row is the nearest integer below n / r or the nearest integer above n / r. On the other hand, to detect and correct a single outlier error, given positive integers r and n, such that n≤r(r-1), then the decoder / parity check matrix H is an rxn matrix on {-1,0,1} that satisfies the following properties: 1) all columns of H are distinct, 2) each column in H contains exactly two non-zero entries, the first of which is 1, and 3) the non-zero entries in each row of H are the nearest integer less than 2n / r or the nearest integer greater than 2n / r.

[0027] In an example aspect, each value in the decoder / parity check matrix H can be encoded by the conductance values ​​of pairs of adjacent memristors 118 (i.e., adjacent memristors 118 in the same column) in the circuit 114, which follows the above-mentioned properties for correcting single abnormal errors. More specifically, a 1 value in the decoder matrix can be mapped to an adjacent memristor pair 118 with tuned conductance (low resistance state (LRS), high resistance state (HRS)), while a -1 value in the decoder matrix can be mapped to (HRS, LRS), and a 0 value can be mapped to (HRS, LRS).

[0028] In an example aspect, if the computation error in the matrix multiplication result 112 (which represents the result of the matrix multiplication of the input vector u and the computation matrix A') is within a preset tolerance value (e.g., a threshold error value Δ), then all outputs of the circuit 114 programmed with the decoder matrix value will be below the threshold, as detected by the comparator between adjacent outputs. In an example aspect, this is a result of the properties followed by the decoder / parity check matrix. In particular, if Figure 1 As shown in FIG. 1 , a transimpedance amplifier 120 may be provided that virtually grounds adjacent row lines in the decoder matrix circuit 114 and converts current into voltage. In particular, the voltage output of each amplifier 120 may be −I in *R ref , where I in represents the input current to the amplifier 120, and R ref is the reference voltage. Comparator 122 may then compare these converted voltages to determine whether the calculation error is within a threshold error value Δ.

[0029] More specifically, the threshold error value Δ may be implemented as an adjustable parameter or input terminal (not shown) within the comparator 122, depending on the design. Figure 1 1, but it should be understood that a corresponding amplifier 120 and a corresponding comparator 122 may be provided for each pair of adjacent row outputs from the decoder matrix circuit 114. That is, a different set of amplifiers 120 may be provided to convert the current outputs of rows 3 and 4 from the decoder matrix circuit 114 into corresponding voltages, which may then be input to another comparator 122 to determine whether any computational errors present in the matrix multiplication result 112 are within a threshold error value Δ. The same is true for rows 5 and 6 of the decoder matrix circuit 114, rows 7 and 8 of the circuit 114, and so on.

[0030] If the calculation error is within the threshold error value Δ, the comparator 122 may output a low logic signal, which may then be inverted to a high logic signal and provided as an input to the AND gate 124. If the calculation error is outside the threshold error value (i.e., greater than Δ or less than −Δ), the comparator 122 may output a high logic signal, which may be inverted to a low logic signal and fed to the AND gate 124. In some aspects, the matrix multiplication result 112 may be verified if each comparator 122 determines that the difference between the corresponding adjacent outputs of the decoder matrix circuit 114 that it is configured to compare is less than the threshold error value Δ, in which case each comparator 122 outputs a high logic signal to the AND gate 124, and the matrix multiplication result 112 is verified. On the other hand, if one or more comparators 122 output a low logic signal, indicating that the calculation error is a threshold external value (greater than Δ or less than -Δ), then that (those) comparator(s) 122 will output a low logic signal to AND gate 124, and AND gate 124 will then output a low logic signal, which causes the matrix multiplication result 112 to not be verified.

[0031] As previously noted, various types of analog computation errors may occur. In the case of transient errors, the error may be detected and corrected by the circuit implementation 100 disclosed herein and the analog ECC it implements, or alternatively, the computation error may be corrected by simply reading the computation result again based on the output from the decoder matrix circuit 114 after the computation error is detected. In contrast, if a computation error is detected at the first read and then detected again at the second read (or nth read, where n≥2), the device controller (which may be Figure 5 In some aspects, a computational error may be corrected a threshold number of times and may be designated as permanent only if it occurs again a threshold number of times.

[0032] If the goal is to detect permanent errors (i.e., errors that occur every time after the initial onset of the error), then in some example aspects, to reduce power consumption, the decoder matrix circuit 114 can be enabled only for the last vector input in the input batch. This can be achieved by selectively applying the decoder signal 116 to enable the decoder matrix circuit 114. In addition, in some example aspects, when the computation matrix A' is replicated into multiple copies (i.e., encoded into multiple crossbar array portions) - such as in the case of convolution kernels in a pixel-level parallel convolutional neural network (CNN) - the decoder matrix circuit 114 can be shared between the various copies and can be enabled for one copy at a time.

[0033] Figure 2 Schematically depicting obtaining a measured syndrome vector 212 as an output from a decoder matrix A″ according to aspects of the disclosed technology, wherein the value of the measured syndrome vector 212 indicates whether there is a computational error in the matrix multiplication output 202. In an example aspect, the matrix multiplication output 202 can be a matrix multiplication output 202. Figure 1 , which represents a matrix multiplication operation between the input vector u and the matrix A including the calculation matrix A′ and the encoder matrix A″. Figure 2 Depicted is a decoder matrix representation 204 comprising a set of pixels, where each pixel represents a conductance difference between two adjacent memristors 118 of a circuit 114 encoding the decoder matrix. In the decoder matrix representation 204, a pixel 206 may represent a conductance difference G corresponding to a (HRS, LRS) representation of a -1 value in the decoder matrix. HRS -G LRS Pixel 208 may represent a conductance difference G corresponding to the (LRS, HRS) representation of a 1 value in the decoder matrix LRS -G HRS ; and pixel 210 may represent a conductance difference G corresponding to the (HRS, HRS) representation of a 0 value in the decoder matrix HRS -G HRS Because the decoder matrix values ​​are programmed into circuit 114 in the analog domain, it should be appreciated that decoder matrix representation 204 may include a range of conductance differences between adjacent memristors corresponding to real numbers between -1 and 1.

[0034] In example aspects of the disclosed technology where there are no computation errors that are outside the threshold error value Δ, all values ​​of the output of the decoder matrix circuit - the syndrome vector 212 - will be below the threshold. On the other hand, if one of the DPE outputs of the matrix multiplication output 202 is corrupted (i.e., includes a computation error that exceeds the threshold error value Δ), then the corresponding value of the decoder matrix is ​​added to the syndrome vector 212. In example aspects, due to the predefined properties of the decoder / parity check matrix, each column of the decoder matrix is ​​unique and contains exactly two non-zero entries. Thus, in the scenario where a single computation error is outside the threshold error value, there are exactly two values ​​in the syndrome vector 212 that are above the threshold. The absolute value of the computation error added to the syndrome vector 212 can be given by (G LRS -G HRS )*V err Given, where V err is the error to be corrected. The location of the detected computational error may then be determined using an inverse matrix multiplication operation between a thresholded version of the syndrome vector 212 and the decoder matrix.

[0035] Figure 3 Schematically depicting an inverse matrix multiplication operation between a thresholded syndrome vector 302 and a decoder matrix according to aspects of the disclosed technology to obtain an inverse matrix multiplication output vector 306 indicating the location of a computational error in a matrix multiplication output (e.g., matrix multiplication output 202). The measured syndrome vector 212 may be thresholded to obtain the thresholded syndrome vector 302 by converting the values ​​of the syndrome vector 212 to binary values. More specifically, each value in the syndrome vector 212 that is above a first threshold may be converted to 1, and each value in the syndrome vector 212 that is below a second threshold may be converted to -1. In the case of a single error correction, there are two such values. In some aspects, the first and second thresholds may be additive inverse elements. Any value in the syndrome vector 212 that is between the first and second thresholds (which would be a zero value in the case of a single error correction) is set to binary 0.

[0036] In some aspects, the thresholded syndrome vector 302 may be fed back to the third crossbar array portion (i.e., the decoder matrix circuit 114) to perform an inverse matrix multiplication operation. In particular, the values ​​of the thresholded syndrome vector 302 may be mapped to corresponding voltage pairs, and these voltage pairs may be applied to the row lines of the decoder matrix circuit 114 to generate output signals representing the inverse matrix multiplication output vector 306. More specifically, a binary 1 in the thresholded syndrome vector 302 (which corresponds to a value in the syndrome vector 212 that is above the first threshold) may be mapped to (V r , -V r), while the binary -1 in the thresholded syndrome vector 302 (which corresponds to a value in the syndrome vector 212 below the second threshold) can be mapped to (-V r , V r ).

[0037] In an exemplary aspect, based on the properties of the decoder / parity check matrix, when performing an inverse matrix multiplication operation, only one output (corresponding to a particular value of the inverse matrix multiplication output vector 306) will have a value equal to 2V r ·(G LRS -G HRS ) and it is output as a unique matching element multiplication. In particular, (V r ,-V r ) multiplied by (G LRS -G HRS ) and (-V r ,V r ) multiplied by (G LRS -G HRS ) is the only result that results in 1, and based on the properties of the decoder / parity-check matrix, there is only one column in the decoder matrix with two matches to produce this result.

[0038] As pointed out, only one of the inverse matrix multiplication outputs produces a value equal to 2V. r ·(G LRS -G HRS ) current. Therefore, it means 2V r ·(G LRS -G HRS ) corresponds to the location of the computation error. In particular, the location of the particular value in output vector 306 corresponds to a particular column of the decoder matrix, and therefore corresponds to a particular column of decoder matrix circuit 114. Due to the connection between the first and second crossbar array portions (i.e., circuits 102 and 104) and the third crossbar array portion (i.e., circuit 114), the particular column of decoder matrix circuit 114 corresponds to a column in circuit 102 that contains a computation error (e.g., the same column as a column in circuit 102).

[0039] In an example aspect, the measured syndrome vector 212 can be used to determine the actual value of the error for correction. In particular, in an example aspect, the value of the error for correction can be determined by the average absolute value of two threshold external values ​​in the measured syndrome vector 212, which can be approximated as (G LRS -G HRS )*V err Additionally, in example aspects, the same decoder matrix circuit 114 may be used to perform error correction.

[0040] Figure 4 4 is a flow chart of an illustrative method 400 for programming a crossbar-based analog error detection and correction circuit and utilizing the programmed circuit to detect and correct computational errors in matrix multiplication outputs in accordance with aspects of the disclosed technology. In some aspects, the method 400 may be responsive to one or more processing units (e.g., Figure 5 , (multiple) processors 504, controllers, etc.) execute programs stored in, for example, main memory 506, read-only memory (ROM) 512, and / or storage device 514 ( Figure 5 ) or the like. In some aspects, method 400 may be performed at least in part by a crossbar-based matrix multiplication hardware accelerator 508 ( Figure 5 ) is performed by hardwired logic in the method 400. One or more operations of the method 400 may be described below as being performed by, for example, Figure 1 The matrix multiplication may be performed by a crossbar-based matrix multiplication hardware accelerator (eg, hardware accelerator 508 ) of the circuit 100 depicted in FIG.

[0041] At block 402 of method 400, a first crossbar array portion may be programmed with analog values ​​corresponding to values ​​of a target computation matrix A' for performing a desired matrix multiplication with an input vector u. For example, each memristor 106 ( Figure 1 ) can be programmed with tuned conductances representing corresponding values ​​in the computational matrix A'.

[0042] At block 404 of method 400, the second crossbar array portion may be programmed with analog values ​​representing values ​​of an encoder matrix A'' that includes redundant symbols for performing error correction on a computation result of a matrix multiplication of an input vector u and a computation matrix A'. For example, each memristor 108 ( Figure 1 ) can be programmed with tuned conductances representing corresponding values ​​in the encoder matrix A".

[0043] At block 406 of method 400, the third crossbar array portion may be programmed with analog values ​​representing values ​​in a decoder / parity check matrix H. As previously noted, the decoder / parity check matrix H may adhere to various properties, which may include, but are not limited to, uniqueness of each column of the matrix H and each column having exactly two non-zero values, the first of which is 1, in the case of a single error correction. Each memristor 118 ( Figure 1 ) may be programmed with tuned conductances representing corresponding values ​​in the decoder / parity check matrix H. In some embodiments, the first, second and third crossbar array portions may form part of the same crossbar array or multiple crossbar arrays may be connected to each other.

[0044] At block 408 of method 400, the input vector u may be converted to a set of corresponding voltages and the voltages may be applied to the shared row lines of the first and second crossbar array portions. More specifically, each element u of the input vector u i is fed to the corresponding DAC to generate i proportional to the corresponding voltage level.

[0045] At block 410 of method 400, the result of a vector-matrix multiplication between a target computation matrix A' programmed into the first cross-switch array portion and an input vector u may be calculated. More specifically, a first output signal from the first cross-switch array portion may represent a first output vector c'=uA', which is the result of a desired matrix multiplication computation between the input vector u and the computation matrix A'. Along similar lines, a second output signal from the second cross-switch array portion may represent a second output vector c"=uA", which is the result of a matrix multiplication operation between the input vector u and the encoder matrix A". The second output vector c" may include redundant symbols that allow for correction of computational errors in c'. The first and second output signals may be determined, that is, the first and second output vectors representing the matrix multiplication outputs of the first and second cross-switch array portions may be calculated by reading currents collected at the column lines.

[0046] At block 412 of method 400, the current output representing the matrix multiplication result of the calculation and encoder matrix programmed into the first and second crossbar array sections, respectively, and the input vector u can be fed as an input to the third crossbar array section, where the decoder matrix value is programmed. Then, at block 414 of method 400, a measured syndrome vector can be obtained as an output from the third crossbar array section, where the measured syndrome vector represents the output of the decoder matrix based on the matrix multiplication result input it receives.

[0047] At block 416 of method 400, the measured syndrome vector may be thresholded to obtain a thresholded syndrome vector. As previously noted, thresholding the measured syndrome vector may include converting the values ​​of the syndrome vector to binary values. More specifically, thresholding may include converting values ​​of the measured syndrome vector above a first threshold to binary 1 and converting values ​​of the measured syndrome vector below a second threshold to binary -1.

[0048] At block 418 of method 400, assuming that the syndrome vector indicates that there is a computation error that exceeds a threshold error value, the thresholded syndrome vector can be fed back to the third crossbar array portion to perform an inverse matrix multiplication operation to determine the location of the computation error in the matrix multiplication result. The location can be determined in the manner described above. Then at block 420 of method 400, the value of the computation error for correction can be determined based on the threshold outer element of the measured syndrome vector, as described above.

[0049] Figure 5 A block diagram of an example computer system 500 is depicted in which various aspects of the disclosed technology described herein may be implemented. The computer system 500 includes a bus 502 or other communication mechanism for communicating information, and one or more hardware processors 504 coupled to the bus 502 for processing information. The hardware processor 504 may be, for example, one or more general-purpose microprocessors.

[0050] The computer system 500 also includes a main memory 506, such as a random access memory (RAM), cache, and / or other dynamic storage device, coupled to the bus 502 for storing instructions and information to be executed by the processor 504. The main memory 506 may also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor 504. Such instructions, when stored in a storage medium accessible to the processor 504, render the computer system 500 as a special-purpose machine customized to perform the operations specified in the instructions.

[0051] Computer system 500 additionally includes a crossbar-based matrix multiplication hardware accelerator 508, which may include Figure 1 508. In some aspects, the hardware accelerator 508 may be configured to execute instructions (i.e., programming or software code) stored in the main memory 506, ROM 512, and / or storage device 514. In an example implementation, the exemplary hardware accelerator 508 may include multiple integrated circuits, which in turn may include ASICs, FPGAs, or other very large scale integrated circuits (VLSI). The integrated circuits of the exemplary hardware accelerator 508 may be specifically optimized to perform a discrete subset of computer processing operations or to execute a discrete subset of computer executable instructions in an accelerated manner. For example, the hardware accelerator 508 may be configured or manufactured to implement simulated crossbar-based vector-matrix multiplication and simulated error detection and correction.

[0052] The circuit 100 that may be implemented within the accelerator 508 may include non-volatile memory constructed using technologies including, for example, resistive switching memory (i.e., memristors), phase change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device (Re-RAM), or a combination of these technologies. More generally, the circuit 100 may be implemented using technologies that allow the circuit 100 to retain its contents even when it is powered off or otherwise removed. Thus, the data in the circuit 100 "persists" and the circuit 100 may act as so-called "non-volatile memory."

[0053] The computer system 500 also includes a read only memory (ROM) 512 or other static storage device coupled to the bus 502 for storing static information and instructions for the processor 504. A storage device 514, such as a magnetic disk, optical disk, or USB thumb drive (flash drive), etc., is provided and coupled to the bus 502 for storing information and instructions.

[0054] The computer system 500 may be coupled to a display 516, such as a liquid crystal display (LCD) (or touch screen), via the bus 502 for displaying information to a computer user. An input device 518, which may include alphanumeric and other keys, is coupled to the bus 502 for communicating information and providing command selections to the processor 504. Another type of user input device is a cursor control 520, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to the processor 504 and for controlling cursor movement on the display 516. In some aspects, the same direction information and command selections as the cursor control 520 may be implemented without a cursor via receiving touches on a touch screen.

[0055] The computing system 500 may include a user interface module to implement a GUI that may be stored in a mass storage device as executable software code executed by the computing device(s). As examples, this module and other modules may include various components such as software components, object-oriented software components, class components, and task components, including but not limited to processes; functions, properties; programs; subroutines; program code segments; drivers; firmware; microcode; circuits; data; databases; data structures; tables; arrays; and variables.

[0056] In general, as used herein, the terms "component", "engine", "system", "database", "data repository", etc. may refer to logic embodied in hardware or firmware, or to a collection of software instructions written in a programming language such as, for example, Java, C, or C++, which may have entry and exit points. Software components may be compiled and linked into an executable program, installed in a dynamic link library, or may be written in an interpreted programming language such as, for example, BASIC, Perl, or Python. It should be understood that software components may be called from other components or from themselves, and / or may be called in response to detected events or interrupts. Software components configured for execution on a computing device may be provided on a computer-readable medium such as a compressed disk, a digital video disk, a flash drive, a magnetic disk, or any other tangible medium, or as a digital download (and may be initially stored in a compressed or installable format that requires installation, decompression, or decryption prior to execution). Such software code may be stored in part or in whole on a memory device of an executing computing device for execution by the computing device. Software instructions may be embedded in firmware such as an EPROM. It will also be appreciated that hardware components may be composed of connected logic units, such as gates and flip-flops, and / or may be composed of programmable units, such as programmable gate arrays or processors.

[0057] The computer system 500 can implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, makes the computer system 500 a special purpose machine or programs it as a special purpose machine. According to one aspect, the techniques herein are performed by the computer system 500 in response to the processor(s) 504 executing one or more sequences of one or more instructions contained in the main memory 506. Such instructions may be read into the main memory 506 from another storage medium such as the storage device 510. Execution of the sequences of instructions contained in the main memory 506 causes the processor(s) 504 to perform the process steps described herein. In alternative aspects, hardwired circuitry may be used in place of or in combination with software instructions.

[0058] As used herein, the term "non-transitory medium" and similar terms such as machine-readable storage media refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 510. Volatile media include dynamic memory, such as main memory 506. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a pattern of holes, RAM, PROMs and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or cassettes, and networked versions thereof.

[0059] Non-transient media are distinct from transmission media but may be used in conjunction with transmission media. Transmission media participate in the transfer of information between non-transient media. For example, transmission media include coaxial cables, copper wire, and optical fiber, including the wires that make up bus 502. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0060] Computer system 500 also includes a communication interface 522 coupled to bus 502. Communication interface 522 provides bidirectional data communication coupled to one or more network links connected to one or more local area networks. For example, communication interface 522 can be an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem for providing a data communication connection to a telephone line of a corresponding type. As another example, communication interface 522 can be a local area network (LAN) card to provide a data communication connection to a compatible LAN (or a WAN component communicating with a WAN). Wireless links can also be implemented. In any such implementation, communication interface 522 sends and receives electrical, electromagnetic or optical signals carrying digital data streams representing various types of information.

[0061] A network link typically provides data communication to other data devices through one or more networks. For example, a network link may provide a connection to a host or data device operated by an Internet Service Provider (ISP) through a local area network. The ISP, in turn, provides data communication services through the global packet data communication network now commonly referred to as the "Internet." Both local area networks and the Internet use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on the network link and the signals through the communication interface 522 are all example forms of transmission media that carry digital data to and from the computer system 500.

[0062] Computer system 500 may send messages and receive data, including program code, through network(s), network links, and communication interface 522. In the Internet example, a server may transmit the requested code for an application program through the Internet, an ISP, a local area network, and communication interface 522. The received code may be executed by processor 504 as it is received, and / or stored in storage device 510 or other non-volatile storage for later execution.

[0063] Each of the processes, methods, and algorithms described in the foregoing sections can be embodied in a code component executed by one or more computer systems or computer processors including computer hardware, and fully or partially automated by it. One or more computer systems or computer processors may also be operated to support the execution of related operations in a "cloud computing" environment or operate as "software as a service" (SaaS). The processes and algorithms may be implemented in part or in whole in a dedicated circuit. The various features and processes described above may be used independently of each other, or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of the present disclosure, and certain methods or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular order, and the blocks or states associated therewith may be executed in other appropriate orders, or may be executed in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example aspects. The performance of certain operations or processes may be distributed between computer systems or computer processors, which may reside in a single machine or be deployed on several machines.

[0064] As used herein, any form of hardware, software or combination thereof can be utilized to realize circuit.For example, one or more processors, controllers, ASIC, PLA, PAL, CPLD, FPGA, logic components, software routines or other mechanisms can be realized to form circuit.In implementation, various circuits described herein can be implemented as discrete circuits, or described functions and features can be partially or completely shared between one or more circuits.Even if various features or functional elements can be described or claimed separately as separate circuits, these features and functionality can also be shared between one or more common circuits, and such descriptions should not require or imply that separate circuits are needed to realize these features or functionality.In the case where the circuit is implemented in whole or in part using software, such software can be implemented to operate together with a computing or processing system (such as computer system 500) that can perform the functionality described therein.

[0065] As used herein, the term "or" may be interpreted as inclusive or exclusive. In addition, descriptions of resources, operations, or structures in the singular should not be interpreted as excluding the plural. Unless otherwise expressly stated, or otherwise understood in the context of use, conditional language, particularly such as "can," "may," "could," or "might," is generally intended to convey that certain aspects include, while other aspects may not include, certain features, elements, and / or steps.

[0066] Unless expressly stated otherwise, the terms and phrases used in this document and their variations should be interpreted as open-ended and non-restrictive. Adjectives such as "conventional", "traditional", "normal", "standard", "known", and terms of similar meaning should not be interpreted as limiting the items described to a given time period or items available to a given time, but should be interpreted as covering conventional, traditional, normal or standard technologies that may be available or known at any time now or in the future. In some cases, the presence of broad words and phrases such as "one or more", "at least", "but not limited to" or other similar phrases should not be interpreted as meaning that a narrower situation is intended or required where such broad words may not be present.

Claims

1. An analog error correction circuit, comprising: One or more non-volatile resistive analog memory crossbar switch arrays including: a first crossbar array portion programmed with values ​​of the multiplication matrix; a second crossbar array portion programmed with the values ​​of the encoder matrix; and The third crossbar array portion is programmed with the values ​​of the decoder matrix, wherein the first crossbar switch array section and the second crossbar switch array section are configured to output a first output and a second output, respectively, the first output and the second output representing a result of a matrix multiplication operation with an input vector, wherein the first output and the second output are provided as inputs to the third crossbar switch array section, and wherein a third output of the third crossbar array portion indicates whether a computation error is present in the first output of the first crossbar array portion, wherein the third output of the third crossbar array portion represents a measured syndrome vector, and wherein the measured syndrome vector includes two threshold-outside values, the two threshold-outside values ​​indicating the presence of the computation error in the first output of the first crossbar array portion, and wherein the measured syndrome vector is thresholded to obtain a thresholded syndrome vector, and wherein the thresholded syndrome vector is fed back to the third crossbar array portion to determine a location of the computation error, Wherein a fourth output of the third crossbar switch array section represents a result of an inverse matrix multiplication operation between the thresholded syndrome vector and the decoder matrix.

2. The analog error correction circuit of claim 1 , wherein the third output of the third crossbar array section is used in conjunction with the values ​​of the decoder matrix to determine the location of the computational error present in the first output of the first crossbar array section.

3. The analog error correction circuit of claim 1 , wherein the fourth output is an output vector, and wherein particular elements of the output vector have unique values ​​that indicate the location of the computational error in the first output of the first crossbar array portion.

4. The analog error correction circuit of claim 3 , wherein each column of the decoder matrix is ​​unique, and wherein the particular element of the output vector is the result of the inverse matrix multiplication operation between the particular column of the decoder matrix and the thresholded syndrome vector.

5. The analog error correction circuit of claim 4, wherein the location of the calculated error is in a particular column of the first crossbar array portion, the particular column generating a corresponding output, the corresponding output being provided as an input to a particular column of the third crossbar array portion programmed with the value of the particular column of the decoder matrix.

6. The analog error correction circuit of claim 1, wherein the value of the calculated error is an average absolute value of two threshold external values ​​in the measured syndrome vector.

7. The analog error correction circuit of claim 1, wherein the conductance difference between adjacent nonvolatile resistive device elements in the third crossbar switch array portion represents a corresponding value of the decoder matrix.

8. A method for analog error detection and correction implemented in an analog memory crossbar switch, the method comprising: programming a first crossbar array portion of one or more nonvolatile resistive analog memory crossbar arrays with values ​​of the multiplication matrix; programming a second crossbar array portion of the one or more nonvolatile resistive analog memory crossbar arrays with values ​​of an encoder matrix; as well as programming a third crossbar array portion of the one or more nonvolatile resistive analog memory crossbar arrays with values ​​of a decoder matrix, Convert the input vector into a set of corresponding voltages; applying the set of corresponding voltages to the first crossbar array portion and the second crossbar array portion to obtain first and second outputs, respectively, representing results of a matrix multiplication operation with the input vector; providing the first output and the second output as inputs to the third crossbar array portion to obtain a third output of the third crossbar array portion, the third output indicating whether a computational error exists in the first output of the first crossbar array portion, wherein the third output of the third crossbar array portion represents a measured syndrome vector, and wherein the measured syndrome vector includes two threshold-outside values, the two threshold-outside values ​​indicating the computational error exists in the first output of the first crossbar array portion, and wherein the measured syndrome vector is thresholded to obtain a thresholded syndrome vector, and wherein the thresholded syndrome vector is fed back to the third crossbar array portion to determine a location of the computational error; and A fourth output of the third crossbar array portion is obtained, the fourth output representing a result of an inverse matrix multiplication operation between a thresholded syndrome vector and the decoder matrix.

9. The method of claim 8, using the third output of the third crossbar array section in combination with the value of the decoder matrix to determine the location of the computational error present in the first output of the first crossbar array section.

10. The method of claim 8, wherein the fourth output is an output vector, and wherein particular elements of the output vector have unique values ​​that indicate locations of the computational errors in the first output of the first crossbar array portion.

11. The method of claim 10, wherein each column of the decoder matrix is ​​unique, and wherein the particular element of the output vector is a result of the inverse matrix multiplication operation between the particular column of the decoder matrix and the thresholded syndrome vector.

12. The method of claim 11, wherein the location of the computational error is in a particular column of the first crossbar array portion, the particular column generating a corresponding output, the corresponding output being provided as an input to a particular column of the third crossbar array portion programmed with a value of the particular column of the decoder matrix.

13. The method of claim 8, wherein a conductance difference between adjacent nonvolatile resistive device elements in the third crossbar switch array portion represents a corresponding value of the decoder matrix.

14. A non-transitory computer readable medium storing machine executable instructions, the instructions in response to execution by a processor causing a method to be performed, the method comprising: programming a first crossbar array portion of one or more nonvolatile resistive analog memory crossbar arrays with values ​​of the multiplication matrix; programming a second crossbar array portion of the one or more nonvolatile resistive analog memory crossbar arrays with values ​​of an encoder matrix; as well as programming a third crossbar array portion of the one or more nonvolatile resistive analog memory crossbar arrays with values ​​of a decoder matrix, applying a set of voltages representing an input vector to a first crossbar array portion and a second crossbar array portion to obtain a first output and a second output, respectively, representing a result of a matrix multiplication operation with the input vector; providing the first output and the second output as inputs to the third crossbar array portion to obtain a third output of the third crossbar array portion, the third output indicating whether a computational error exists in the first output of the first crossbar array portion, wherein the third output of the third crossbar array portion represents a measured syndrome vector, and wherein the measured syndrome vector includes two threshold-outside values, the two threshold-outside values ​​indicating the computational error exists in the first output of the first crossbar array portion, and wherein the measured syndrome vector is thresholded to obtain a thresholded syndrome vector, and wherein the thresholded syndrome vector is fed back to the third crossbar array portion to determine a location of the computational error; and A fourth output of the third crossbar array portion is obtained, the fourth output representing a result of an inverse matrix multiplication operation between a thresholded syndrome vector and the decoder matrix.

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