Delay prediction method, device, apparatus and storage medium

Abstract

This application discloses a delay prediction method, apparatus, device, and storage medium. The delay prediction method includes: acquiring the unit characteristic information of each unit in a circuit and the characteristic sequence of each unit's interconnection; calculating the equivalent capacitance value of the interconnection path between units based on the capacitance and resistance values ​​of each unit's interconnection, and determining the target interconnection delay characteristics between units based on the equivalent capacitance values; determining the unit delay characteristics of each unit based on the equivalent capacitance values ​​and unit characteristic information; inputting the interconnection delay characteristics and unit delay characteristics into a preset delay prediction model; and performing prediction processing on the interconnection delay characteristics and unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit. This application equates the capacitance and resistance values ​​of each unit's interconnection to equivalent capacitance values, overcoming the deficiency in related technologies where the load capacitance ignores the resistance shielding effect, thereby reducing the error of the load capacitance and improving the accuracy of timing prediction.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, and in particular to a delay prediction method, apparatus, device and storage medium. Background Technology

[0002] For high-performance chip design, timing convergence is the most critical requirement. To obtain a chip design with accurate timing, timing analysis tools need to be used at each stage of physical design to analyze timing margins, thereby guiding the chip design process. Therefore, accurate timing analysis results are crucial for guiding iterative optimization of the chip design and achieving good timing convergence results.

[0003] Traditional algorithms, including the Elmore model and the D2M model, are used in timing estimation methods for digital integrated circuits after routing to calculate interconnect delays. When applying the Elmore and D2M models, it's necessary to calculate the load capacitance downstream of each node. This method uses the sum of the capacitances to ground of downstream circuit nodes as the load capacitance. However, this sum of ground capacitances contains a certain error, and the accumulation of this error during transmission leads to low accuracy in timing prediction. Summary of the Invention

[0004] The main objective of this application is to provide a delay prediction method, apparatus, device, and storage medium, aiming to solve the technical problem of low accuracy in timing prediction in the prior art.

[0005] To achieve the above objectives, this application provides a time delay prediction method, the time delay prediction method comprising:

[0006] Obtain the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value;

[0007] Based on the capacitance and resistance values ​​of each unit interconnect, the equivalent capacitance value of the interconnect path between each unit is calculated, and based on the equivalent capacitance value, the target interconnect delay characteristics between each unit are determined.

[0008] Based on the equivalent capacitance value and the unit feature information, the unit delay characteristics of each unit are determined;

[0009] The interconnect delay characteristics and the cell delay characteristics are input into a preset delay prediction model. Based on the delay prediction model, the interconnect delay characteristics and the cell delay characteristics are predicted to obtain the delay result of the circuit.

[0010] Optionally, the step of calculating the equivalent capacitance value of the interconnect path between each unit based on the capacitance and resistance values ​​of each unit interconnect, and determining the target interconnect delay characteristics between each unit based on the equivalent capacitance value, includes:

[0011] Based on the capacitance and resistance values ​​of the interconnects of each unit, an RC tree model of the interconnection path between each unit is established and the resistance value of each node in the RC tree model is determined.

[0012] All downstream nodes of each node in the RC tree model are equivalent to the π model of each node;

[0013] Based on the π model of each node, the equivalent capacitance value of the interconnection path between each unit is calculated;

[0014] Based on the equivalent capacitance and resistance values ​​of each node, the ECM delay between each unit is calculated.

[0015] The ECM delay is determined as the delay characteristic of the target interconnect.

[0016] Optionally, after the step of calculating the ECM delay between each unit based on the equivalent capacitance value and the resistance value of each node, the method includes:

[0017] Determine the capacitance value of each node in the RC tree model;

[0018] Based on the resistance and capacitance values ​​of each node, the ECM delay is recursively calculated to obtain the second moment of each node.

[0019] Based on the ECM delay and the second moment, the MD2M delay between each unit is calculated;

[0020] The step of determining the ECM delay as the delay characteristic of the target interconnect includes:

[0021] The ECM delay and the MD2M delay are determined as the delay characteristics of the target interconnect.

[0022] Optionally, after the step of calculating the MD2M delay between each unit based on the ECM delay and the second moment, the method includes:

[0023] Based on the capacitance and resistance values ​​of the interconnects of each unit, the Elmore delay and D2M delay between each unit are determined.

[0024] The ECM delay, the MD2M delay, the Elmore delay, and the D2M delay are determined as the target interconnect delay characteristics between each of the units.

[0025] Optionally, before the step of inputting the interconnect delay characteristics and the cell delay characteristics into a preset delay prediction model, and performing prediction processing on the interconnect delay characteristics and the cell delay characteristics based on the delay prediction model to obtain the delay result of the circuit, the method includes:

[0026] Obtain unit feature samples and target delay result labels for the unit feature samples, wherein the unit feature samples include interconnect delay feature samples and unit delay feature samples;

[0027] Based on the interconnect delay feature samples, the unit delay feature samples, and the target delay result labels of the unit feature samples, the preset training model is iteratively trained to obtain a delay prediction model that meets the accuracy requirements.

[0028] Optionally, the step of obtaining the target time delay result label of the unit feature sample includes:

[0029] Obtain the target interconnect delay characteristics, cell delay characteristics, and initial delay result values ​​of the cell feature samples;

[0030] The target interconnect delay feature and the unit delay feature of the unit feature sample are summed to obtain the target delay result value of the unit feature sample. The initial delay result value is then compared with the target delay result value of the unit feature sample to obtain the target delay result label of the unit feature sample.

[0031] Optionally, the step of iteratively training a preset training model based on the interconnect delay feature samples, the cell delay feature samples, and the target delay result labels of the cell feature samples to obtain a delay prediction model that meets the accuracy requirements includes:

[0032] The interconnect delay feature samples and the cell delay feature samples are input into the preset training model to obtain the predicted delay result;

[0033] The difference between the predicted latency result and the target latency result label of the unit feature sample is calculated to obtain the error result;

[0034] Determine whether the error result meets the error standard indicated by the preset error threshold range;

[0035] If the error result does not meet the error standard indicated by the preset error threshold range, the process returns to the step of inputting the interconnect delay feature sample and the cell delay feature sample into the preset training model to obtain the predicted delay result. Training stops when the training error result meets the error standard indicated by the preset error threshold range, and a delay prediction model with the required accuracy is obtained.

[0036] This application also provides a time delay prediction device, characterized in that the time delay prediction device includes:

[0037] The acquisition module is used to acquire the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value;

[0038] The calculation module is used to calculate the equivalent capacitance value of the interconnect path between each unit based on the capacitance and resistance values ​​of each unit interconnect, and to determine the target interconnect delay characteristics between each unit based on the equivalent capacitance value.

[0039] The determining module is used to determine the unit delay characteristics of each unit based on the equivalent capacitance value and the unit characteristic information;

[0040] The prediction module is used to input the interconnect delay characteristics and the unit delay characteristics into a preset delay prediction model, and perform prediction processing on the interconnect delay characteristics and the unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit.

[0041] This application also provides a latency prediction device, which includes: a memory, a processor, and a program stored in the memory for implementing the latency prediction method.

[0042] The memory is used to store the program that implements the delay prediction method;

[0043] The processor is used to execute a program that implements the delay prediction method, so as to implement the steps of the delay prediction method.

[0044] This application also provides a storage medium storing a program for implementing a latency prediction method, wherein the program for implementing the latency prediction method is executed by a processor to implement the steps of the latency prediction method.

[0045] This application provides a time delay prediction method, apparatus, device, and storage medium. Compared to related technologies that use the sum of the capacitances to ground of downstream circuit nodes as the load capacitance, but where this sum of capacitances has a certain error, and the continuous accumulation of this error during transmission leads to low accuracy in timing prediction, this application obtains the unit characteristic information of each unit in the circuit and the characteristic sequence of each unit interconnection, wherein the characteristic sequence includes capacitance and resistance values; based on the capacitance and resistance values ​​of each unit interconnection, the equivalent capacitance value of the interconnection path between each unit is calculated, and based on the equivalent capacitance value, the target interconnection time delay characteristics between each unit are determined; based on the equivalent capacitance value and the unit characteristic information, the unit time delay characteristics of each unit are determined; the interconnection time delay characteristics and the unit time delay characteristics are input into a preset time delay prediction model, and based on the time delay prediction model, the interconnection time delay characteristics and the unit time delay characteristics are predicted to obtain the time delay result of the circuit. In this application, the capacitance and resistance values ​​of each unit interconnect are equivalent to equivalent capacitance values, and these equivalent capacitance values ​​are used as load capacitances. This overcomes the shortcomings of related technologies that use the sum of capacitances to ground as load capacitances while ignoring the resistance shielding effect, thereby reducing load capacitance errors and improving the accuracy of timing predictions. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0047] Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of this application;

[0048] Figure 2 This is a flowchart illustrating the first embodiment of the latency prediction method of this application;

[0049] Figure 3 This is a schematic diagram of the delay prediction device of this application;

[0050] Figure 4 This is a schematic diagram of the RC tree of the first embodiment of the delay prediction method of this application;

[0051] Figure 5 This is a schematic diagram of the π model and equivalent capacitance of the first embodiment of the delay prediction method of this application;

[0052] Figure 6This is a flowchart illustrating the second embodiment of the delay prediction method of this application.

[0053] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0054] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0055] like Figure 1 As shown, Figure 1 This is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiments of this application.

[0056] The terminal in this application embodiment can be a PC, or a smartphone, tablet computer, e-book reader, MP3 (Moving Picture Experts Group Audio Layer III) player, MP4 (Moving Picture Experts Group Audio Layer IV) player, portable computer, or other portable terminal devices with display functions.

[0057] like Figure 1 As shown, the terminal may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a memory 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard. Optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0058] Optionally, the terminal may also include a camera, RF (Radio Frequency) circuitry, sensors, audio circuitry, a WiFi module, and so on. Sensors may include light sensors, motion sensors, and other sensors. Specifically, light sensors may include ambient light sensors and proximity sensors. The ambient light sensor can adjust the display brightness according to the ambient light level, while the proximity sensor can turn off the display and / or backlight when the mobile terminal is moved to the ear. As a type of motion sensor, a gravity accelerometer can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity, and can be used for applications that identify the mobile terminal's posture (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition functions (such as pedometers, taps), etc. Of course, the mobile terminal may also be equipped with other sensors such as gyroscopes, barometers, hygrometers, thermometers, and infrared sensors, which will not be elaborated here.

[0059] Those skilled in the art will understand that Figure 1 The terminal structure shown does not constitute a limitation on the terminal and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0060] like Figure 1 As shown, the memory 1005, which serves as a computer storage medium, may include an operating device, a network communication module, a user interface module, and a latency prediction program.

[0061] exist Figure 1 In the terminal shown, the network interface 1004 is mainly used to connect to the backend server and communicate with the backend server; the user interface 1003 is mainly used to connect to the client (user terminal) and communicate with the client; and the processor 1001 can be used to call the delay prediction program stored in the memory 1005.

[0062] Reference Figure 2 This application provides a latency prediction method, which includes:

[0063] Step S100: Obtain the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value;

[0064] Step S200: Based on the capacitance and resistance values ​​of each unit interconnect, calculate the equivalent capacitance value of the interconnect path between each unit, and based on the equivalent capacitance value, determine the target interconnect delay characteristics between each unit.

[0065] Step S300: Based on the equivalent capacitance value and the cell feature information, determine the cell delay characteristics of each cell;

[0066] Step S400: Input the interconnect delay characteristics and the cell delay characteristics into a preset delay prediction model. Based on the delay prediction model, perform prediction processing on the interconnect delay characteristics and the cell delay characteristics to obtain the delay result of the circuit.

[0067] In this embodiment, the application scenario is:

[0068] As an example, a scenario for delay prediction could be timing analysis performed after digital integrated circuit routing to guide the iterative optimization of high-performance chip design. Related technologies use traditional algorithms, including the Elmore model and the D2M model, to calculate the delay values ​​of interconnects for timing estimation after digital integrated circuit routing. When applying the Elmore and D2M models, it is necessary to calculate the load capacitance value downstream of each node. This method uses the sum of the capacitances to ground of downstream circuit nodes as the load capacitance. However, this sum of ground capacitances has a certain error, and the continuous accumulation of this error during transmission leads to low accuracy in timing prediction. To address this scenario, the delay prediction method in this embodiment equates the capacitance and resistance values ​​of each unit interconnect to equivalent capacitance values ​​and uses these equivalent capacitance values ​​as the load capacitance. This overcomes the shortcomings of related technologies that use the sum of capacitances to ground as the load capacitance while ignoring the resistive shielding effect, thereby reducing the error in load capacitance and improving the accuracy of timing prediction.

[0069] As an example, the application scenarios for delay prediction are not limited to timing analysis after routing of digital integrated circuits for high-performance chips, as mentioned above, but also include various delay prediction scenarios, without specific limitations here.

[0070] This embodiment aims to improve the accuracy of time series forecasting.

[0071] In this embodiment, the delay prediction method is applied to the delay prediction device.

[0072] The specific steps are as follows:

[0073] Step S100: Obtain the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value;

[0074] In this embodiment, the circuit refers to the digital integrated circuit after the chip is wired, or it can be the digital integrated circuit before the wired wiring. Since the accurate parasitic parameter information such as capacitance and resistance of the interconnects is lacking in the early stage of wiring, it is impossible to estimate the relatively accurate unit and interconnect delay information. Therefore, the digital integrated circuit after the wired wiring is preferred.

[0075] In this embodiment, the feature sequence includes capacitance and resistance values. The unit feature information of each unit includes, but is not limited to, unit type, unit port name, load capacitance, input slew rate, output slew rate, and signal polarity, as shown in Table 1 below:

[0076] Table 1

[0077]

[0078] Step S200: Based on the capacitance and resistance values ​​of each unit interconnect, calculate the equivalent capacitance value of the interconnect path between each unit, and based on the equivalent capacitance value, determine the target interconnect delay characteristics between each unit.

[0079] In this embodiment, the equivalent capacitance value is obtained by equivalently converting the capacitance and resistance values ​​of each unit. That is, the equivalent capacitance value includes the resistance, thereby taking into account the resistance shielding effect in the load capacitance, reducing the error of the load capacitance, and improving the accuracy of timing prediction.

[0080] In this embodiment, the interconnection path between each unit refers to the path of the interconnection between units on the circuit, and a corresponding time delay will be generated on this path, that is, the target interconnection time delay characteristic between each unit.

[0081] Specifically, step S200 includes the following steps S210-S250:

[0082] Step S210: Based on the capacitance and resistance values ​​of each unit interconnection line, establish an RC tree model of the interconnection line path between each unit and determine the resistance value of each node in the RC tree model;

[0083] In this embodiment, the RC tree model refers to Figure 4 , Figure 4 An RC tree model is shown, which represents the cell and the interconnection path between cells. The model consists of the capacitance and resistance values ​​of the cells, and all the capacitances in the RC tree are located between the nodes and the power ground.

[0084] Step S220: Convert all downstream nodes of each node in the RC tree model into equivalent π models of each node;

[0085] In this embodiment, the device equates all downstream nodes of each node in the RC tree model to the π model of each node, wherein the π model of each node is referenced. Figure 5 The circuit on the left specifically involves a device that equates the subtree downstream of each node in the RC tree to a π model, and then recursively equates the entire RC tree to a π model from bottom to top.

[0086] Step S230: Based on the π model of each node, calculate the equivalent capacitance value of the interconnection path between each unit;

[0087] In this embodiment, the device calculates the equivalent capacitance value of the interconnect path between the units based on the π model of each node. Specifically, the device first performs a Taylor expansion on the input of the circuit downstream of each node i when s=0, referring to the following formula:

[0088] Y i (s)=y 1，i s+y 2，i s 2 +y 3，i s 3 +…

[0089] Where i represents a node, s represents a coefficient, and y represents the input moment of node i.

[0090] In this embodiment, the three moments (y1, y2, y3) calculated above can be used to represent the circuit downstream of node i as an equivalent π model, as shown in the following formula:

[0091] C ni =y 1，i -C fi

[0092]

[0093]

[0094] Among them, Cni, Rπi, and Cfi are Figure 5 The capacitor and resistor on the left.

[0095] In this embodiment, based on the equivalent π model, the equivalent capacitance can be calculated as follows:

[0096]

[0097] Among them, C eff This represents the equivalent capacitance value.

[0098] Step S240: Based on the equivalent capacitance value and the resistance value of each node, calculate the ECM delay between each unit.

[0099] In this embodiment, the device calculates the ECM delay between each unit based on the equivalent capacitance and resistance values ​​of each node. Specifically, the device expresses the ECM model for calculating interconnect delay as follows:

[0100]

[0101] Among them, Decm This represents the equivalent capacitance value.

[0102] Step S250: The ECM delay is determined as the delay characteristic of the target interconnect.

[0103] In this embodiment, the device determines the ECM delay as the delay characteristic of the target interconnect.

[0104] After step S240, where the ECM delay between each unit is calculated based on the equivalent capacitance and resistance values ​​of each node, the method includes the following steps A100-A400:

[0105] Step A100: Determine the capacitance value of each node in the RC tree model;

[0106] Step A200: Based on the resistance and capacitance values ​​of each node, the ECM delay is recursively calculated to obtain the second moment of each node;

[0107] In this embodiment, the MD2M model is used to calculate the arrival time of each node in the interconnect and the overall delay of the interconnect. The ECM delay is the first moment of the impulse response, while MD2M considers the second moment of the impulse response. For node v i j th A moment can be recursively represented as:

[0108]

[0109] Step A300: Based on the ECM delay and the second moment, calculate the MD2M delay between each of the units;

[0110] Where m1 and m2 are node v i The impulse response of j th For each node, m0 = 1. This formula allows for the recursive calculation of moments of any order at each node. Based on this expression, the MD2M model is defined as follows:

[0111]

[0112] Where m1 and m2 are the first and second moments of the impulse response, respectively. The MD2M model first requires calculating the ECM delay, and then iteratively calculates the second moment. This model is as simple and fast as the ECM model, but its accuracy is higher.

[0113] Step A400: The ECM delay and the MD2M delay are determined as the delay characteristics of the target interconnect.

[0114] In this embodiment, the device determines the ECM delay and the MD2M delay as the target interconnect delay characteristics, providing more and more accurate interconnect delay characteristics, thereby reducing load capacitance errors and improving the accuracy of timing prediction.

[0115] After step A300, where the MD2M delay between each unit is calculated based on the ECM delay and the second-order moment, the method includes the following steps B100-B200:

[0116] Step B100: Based on the capacitance and resistance values ​​of each unit interconnect, determine the Elmore delay and D2M delay between each unit;

[0117] In this embodiment, the device determines the Elmore delay and D2M delay between each unit based on the capacitance and resistance values ​​of each unit interconnect. Specifically, each interconnect is modeled as an RC tree, and the Elmore model is used to calculate the arrival time of each node in the interconnect and the overall delay value of the interconnect based on the capacitance and resistance information. The Elmore model is described as follows:

[0118]

[0119] Where N refers to the number of nodes in the RC tree, and R... i This refers to the resistance value of node i, C. D This refers to the load capacitance downstream of node i.

[0120] In this embodiment, the device uses the D2M model to calculate the arrival time of each node in the interconnect and the overall time delay of the interconnect. The aforementioned Elmore model can be considered as the first moment of the impulse response, while D2M considers the second moment of the impulse response. For node v i j th A moment can be recursively represented as:

[0121]

[0122] Where m1 and m2 are node v i The impulse response of j th For each node, m0 = 1. This formula allows for the recursive calculation of moments of any order at each node. Based on this expression, the D2M model is defined as follows:

[0123]

[0124] Where m1 and m2 are the first and second moments of the impulse response, respectively. As can be seen from the formula, the D2M model first needs to calculate the Elmore time delay, and then iteratively calculate the second moment. This model is as simple and fast as the Elmore model, but its accuracy is higher.

[0125] Step B200: The ECM delay, the MD2M delay, the Elmore delay, and the D2M delay are determined as the target interconnect delay characteristics between each of the units.

[0126] In this embodiment, the device determines the ECM delay, the MD2M delay, the Elmore delay, and the D2M delay as the target interconnect delay characteristics between each of the units, that is, it provides more and more accurate interconnect delay characteristics, thereby reducing the error of load capacitance and improving the accuracy of timing prediction.

[0127] Step S300: Based on the equivalent capacitance value and the cell feature information, determine the cell delay characteristics of each cell;

[0128] In this embodiment, the device determines the unit delay characteristics of each unit based on the equivalent capacitance value and the unit characteristic information.

[0129] Step S400: Input the interconnect delay characteristics and the cell delay characteristics into a preset delay prediction model. Based on the delay prediction model, perform prediction processing on the interconnect delay characteristics and the cell delay characteristics to obtain the delay result of the circuit.

[0130] In this embodiment, the device inputs the interconnect delay features and the unit delay features into a preset delay prediction model. Based on the delay prediction model, the device performs prediction processing on the interconnect delay features and the unit delay features to obtain the delay result of the circuit. The delay prediction model is a machine learning model, including but not limited to Naive Bayes model, decision tree model, KNN algorithm, SVM algorithm, and logistic regression model. In this embodiment, the XGBoost model among decision tree models is preferred. XGBoost (eXtreme Gradient Boosting) is a high-efficiency decision tree algorithm that mainly constructs a strong learner by ensembling weak learners based on decision trees. In the XGBoost algorithm, all decision trees are generated independently and in parallel, making XGBoost training highly efficient.

[0131] This application provides a time delay prediction method that, compared to related technologies that use the sum of the capacitances to ground of downstream circuit nodes as the load capacitance (which has a certain error, and the accumulation of this error during transmission leads to low accuracy in timing prediction), this application obtains the unit characteristic information of each unit in the circuit and the characteristic sequence of each unit interconnect, wherein the characteristic sequence includes capacitance and resistance values; based on the capacitance and resistance values ​​of each unit interconnect, the equivalent capacitance value of the interconnect path between each unit is calculated, and based on the equivalent capacitance value, the target interconnect time delay characteristics between each unit are determined; based on the equivalent capacitance value and the unit characteristic information, the unit time delay characteristics of each unit are determined; the interconnect time delay characteristics and the unit time delay characteristics are input into a preset time delay prediction model, and based on the time delay prediction model, the interconnect time delay characteristics and the unit time delay characteristics are predicted to obtain the time delay result of the circuit. In this application, the capacitance and resistance values ​​of each unit interconnect are equivalent to equivalent capacitance values, and these equivalent capacitance values ​​are used as load capacitances. This overcomes the shortcomings of related technologies that use the sum of capacitances to ground as load capacitances while ignoring the resistance shielding effect, thereby reducing load capacitance errors and improving the accuracy of timing predictions.

[0132] Based on the first embodiment described above, this application also provides another embodiment, referring to... Figure 6 The delay prediction method includes:

[0133] Before step S300, where the interconnect delay characteristics and the cell delay characteristics are input into a preset delay prediction model, and the delay prediction model is used to predict the interconnect delay characteristics and the cell delay characteristics to obtain the delay result of the circuit, the method includes the following steps C100-C200:

[0134] In this embodiment, before the interconnect delay features and delay information are input into the machine learning model, the data needs to be preprocessed. First, the unit type and unit port name need to be numbered, with each unit type and each port name having a unique ID. Second, since the length of each time path is not uniform, the feature sequence length of each path is different, so the feature sequences need to be padded to make all feature sequences the same length. If the maximum length of the time path in the selected training dataset and test dataset is max_length, if the feature sequence length is less than this value, it is padded with "0" to the length max_length. If the length of the time path in the test set is greater than this value, the feature sequence is pruned to make its length max_length.

[0135] Step C100: Obtain the unit feature sample and the target delay result label of the unit feature sample, wherein the unit feature sample includes interconnect delay feature sample and unit delay feature sample;

[0136] Specifically, step C100 includes the following steps C110-C120:

[0137] Step C110: Obtain the target interconnect delay characteristics, cell delay characteristics, and initial delay result values ​​of the cell feature sample;

[0138] In this embodiment, the initial latency result value is the latency value of the corresponding timing path extracted from the commercial timing analysis tool report, which is a relatively accurate latency result value.

[0139] Step C120: Summing the target interconnect delay feature and the unit delay feature of the unit feature sample to obtain the target delay result value of the unit feature sample, and calculating the ratio between the initial delay result value and the target delay result value of the unit feature sample to obtain the target delay result label of the unit feature sample.

[0140] In this embodiment, when selecting a tag, the present invention uses the latency value PD of the corresponding time path extracted from a commercial time series analysis tool report. PT Instead of using labels, the latency value (PD) of the corresponding time series path reported by the business time series analysis tool will be used. PT The mean delay PD of the timing path, calculated by the internally developed timing analysis tool using linear interpolation and the Elmore, ECM, and D2M methods mentioned above, is compared with that of the internally developed timing analysis tool. IM The ratio PD PT / PD IE It is important to note that PD is used as input into the machine learning model. elmore PD ecm PD d2m and PD md2m When used in a feature, it represents the arrival time of the unit pin in each timing path, which is a sequence. When used in a feature, it represents the delay value of each timing path, which is a numerical value.

[0141] PD elmore =D cell +D elmore

[0142] PD ecm =D cell +D ecm

[0143] PD d2m =D cell +Dd2m

[0144] PD md2m =D cell +D md2m

[0145]

[0146]

[0147] Among them, D cell D represents the time delay of a unit. elmore Indicates Elmore delay, D ecm D represents ECM latency. d2M D represents the D2M delay, D md2m Indicates DM2M latency, PD IM The value represents the mean of the target interconnect delay characteristics, and Label represents the ratio of the target interconnect delay characteristics to the initial delay result value.

[0148] In this embodiment, if only ECM delay is considered, it is only necessary to calculate the ratio of the sum of the ECM delay of the unit sample and the unit delay value to the initial delay result value. If two or more delays are used, the ratio of the average delay value to the initial delay result value is taken.

[0149] The feature sequence matrix with dimensions [sample_num, feature_num * max_length] is input into the XGboost machine learning model. Here, sample_num is the number of training sets, feature_num is the number of selected features, and max_length is the length of the padded feature sequence.

[0150] Step C200: Based on the interconnect delay feature samples, the unit delay feature samples, and the target delay result labels of the unit feature samples, the preset training model is iteratively trained to obtain a delay prediction model that meets the accuracy conditions.

[0151] In this embodiment, the device iteratively trains a preset training model based on the interconnect delay feature samples, the cell delay feature samples, and the target delay result labels of the cell feature samples to obtain a delay prediction model that meets the accuracy requirements.

[0152] Specifically, step C200 includes the following steps C210-C240:

[0153] Step C210: Input the interconnect delay feature samples and the cell delay feature samples into the preset training model to obtain the predicted delay result;

[0154] In this embodiment, the device inputs the interconnect delay feature samples and the cell delay feature samples into the preset training model to obtain the predicted delay result. The preset training detection model is an initial model with preliminary delay prediction function. The preset training detection model differs from the delay prediction model only in detection accuracy. The predicted delay result is the prediction information of the preset training detection model.

[0155] Step C220: Calculate the difference between the predicted latency result and the target latency result label of the unit feature sample to obtain the error result;

[0156] In this embodiment, the latency prediction model is preferably XGBoost (eXtreme Gradient Boosting), where XGBoost is a highly efficient decision tree algorithm that primarily constructs a strong learner by ensembling weak learners based on decision trees. In the XGBoost algorithm, all decision trees are generated independently and in parallel, making the XGBoost training process highly efficient. In this algorithm, each decision tree is trained based on the previous decision tree, and in each iteration, only the sub-model in the current step is optimized. In the m-th step:

[0157] F k (x i ) = F k-1 (x i )+f k (x i )

[0158] f k (x i F represents the sub-model of the current step. k-1 (x i This is to train the first k-1 sub-models that have already been fixed.

[0159] One advantage of the XGBoost model is that it allows for missing values ​​in features, typically preceded by data preprocessing including missing value imputation and feature scaling. Borrowing from the Random Forest algorithm, this model supports both column and row sampling, which reduces overfitting risk and computational cost. Furthermore, XGBoost incorporates a regularization term into its objective function, including the number of leaf nodes and the L2 norm of the leaf node outputs. By constraining the tree structure, it reduces model variance and the risk of overfitting. XGBoost employs a level-wise strategy to generate decision trees, simultaneously splitting nodes at the same level. An approximate histogram algorithm is used to select the optimal splitting method, and a loss function measures the gain after splitting. To limit tree growth, a threshold is introduced; when the gain exceeds the threshold, a split occurs. This process is repeated until the decision tree reaches a predetermined depth or no longer yields any benefit from splitting. Finally, XGBoost linearly combines the outputs of all decision trees to obtain the final prediction result.

[0160] During testing, the test set is input into the trained XGBoost machine learning model, and the output is a ratio. This ratio is multiplied by the mean of the interconnect delay, which is composed of the unit delay and the interconnect delay calculated by the Elmore model, ECM model, D2M model and MD2M model respectively, to obtain the final delay of the corresponding timing path.

[0161] Step C230: Determine whether the error result meets the error standard indicated by the preset error threshold range;

[0162] In this embodiment, the device determines whether the error result meets the error standard indicated by the preset error threshold range. The error standard indicated by the error threshold range is set by the developer / user. That is, if the error result meets the error standard, it means that the risk detection model of the current training round has qualified risk detection accuracy for the non-fault sample signal. If the error result does not meet the error standard, it means that the accuracy error of the risk detection model of the current training round for the non-fault sample signal is too large, and then the next round of model training is entered.

[0163] Step C240: If the error result does not meet the error standard indicated by the preset error threshold range, then return to the step of inputting the interconnect delay feature sample and the cell delay feature sample into the preset training model to obtain the predicted delay result, until the training error result meets the error standard indicated by the preset error threshold range and then stop training to obtain a delay prediction model that meets the accuracy conditions.

[0164] In this embodiment, if the error result does not meet the error standard indicated by the preset error threshold range, the process returns to the step of inputting the interconnect delay feature sample and the cell delay feature sample into the preset training model to obtain the predicted delay result. Training stops when the training error result meets the error standard indicated by the preset error threshold range, thus obtaining a delay prediction model that meets the accuracy conditions. That is, the detection model to be trained is iteratively trained so that the accuracy of the delay prediction model meets the accuracy conditions, thereby improving the accuracy of delay prediction.

[0165] In this embodiment, the slew rate of the input pin and the equivalent capacitance of the interconnect connected to the output pin are incorporated as load capacitance into the timing path delay prediction. The timing path delay value, calculated by summing the unit delay, interconnect resistance, and the equivalent capacitance of the downstream circuit of each node using the ECM and MD2M models, is added to the features. The average of the unit delay and the sum of the interconnect delays obtained using the Elmore, ECM, D2M, and MD2M models is calculated. For each path, the ratio of the delay value obtained through commercial tool analysis to the average delay is used as a label, thereby reducing the error of the load capacitance and improving the accuracy of timing prediction.

[0166] This application also provides a time delay prediction device, the time delay prediction device comprising:

[0167] The acquisition module 10 is used to acquire the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value;

[0168] The calculation module 20 is used to calculate the equivalent capacitance value of the interconnect path between each unit based on the capacitance value and resistance value of each unit interconnect, and to determine the target interconnect delay characteristics between each unit based on the equivalent capacitance value.

[0169] The determining module 30 is used to determine the unit delay characteristics of each unit based on the equivalent capacitance value and the unit characteristic information;

[0170] The prediction module 40 is used to input the interconnect delay characteristics and the unit delay characteristics into a preset delay prediction model, and perform prediction processing on the interconnect delay characteristics and the unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit.

[0171] Optionally, the computing module 20 includes:

[0172] A module is established to build an RC tree model of the interconnection path between the units based on the capacitance and resistance values ​​of the interconnection lines of each unit, and to determine the resistance value of each node in the RC tree model.

[0173] An equivalent module is used to convert all downstream nodes of each node in the RC tree model into the π model of each node.

[0174] An equivalent capacitance calculation module is used to calculate the equivalent capacitance value of the interconnection path between each unit based on the π model of each node.

[0175] The ECM delay calculation module is used to calculate the ECM delay between each unit based on the equivalent capacitance value and the resistance value of each node.

[0176] The first determining module is used to determine the ECM delay as the delay characteristic of the target interconnect.

[0177] Optionally, the computing module 20 further includes:

[0178] A capacitance value determination module is used to determine the capacitance value of each node in the RC tree model;

[0179] The recursive calculation module is used to recursively calculate the ECM delay based on the resistance and capacitance values ​​of each node, and obtain the second moment of each node.

[0180] The MD2M delay calculation module is used to calculate the MD2M delay between each unit based on the ECM delay and the second moment.

[0181] The second determining module is used to determine the ECM delay and the MD2M delay as the delay characteristics of the target interconnect.

[0182] Optionally, the computing module 20 further includes:

[0183] The delay determination module is used to determine the Elmore delay and D2M delay between each unit based on the capacitance and resistance values ​​of the interconnects of each unit.

[0184] The third determining module is used to determine the ECM delay, the MD2M delay, the Elmore delay, and the D2M delay as the target interconnect delay characteristics between each of the units.

[0185] Optionally, the delay prediction device further includes:

[0186] The sample acquisition module is used to acquire unit feature samples and target delay result labels of the unit feature samples, wherein the unit feature samples include interconnect delay feature samples and unit delay feature samples;

[0187] The training module is used to iteratively train a preset training model based on the interconnect delay feature samples, the unit delay feature samples, and the target delay result labels of the unit feature samples, to obtain a delay prediction model that meets the accuracy conditions.

[0188] Optionally, the sample acquisition module includes:

[0189] The delay result value acquisition module is used to acquire the target interconnect delay characteristics, unit delay characteristics, and initial delay result values ​​of the unit feature samples;

[0190] The mean calculation module is used to sum the target interconnect delay feature and the unit delay feature of the unit feature sample to obtain the target delay result value of the unit feature sample, and to calculate the ratio between the initial delay result value and the target delay result value of the unit feature sample to obtain the target delay result label of the unit feature sample.

[0191] Optionally, the training module includes:

[0192] The input module is used to input the interconnect delay feature samples and the unit delay feature samples into the preset training model to obtain the predicted delay result;

[0193] The difference calculation module is used to calculate the difference between the predicted time delay result and the target time delay result label of the unit feature sample to obtain the error result;

[0194] The judgment module is used to determine whether the error result meets the error standard indicated by the preset error threshold range;

[0195] The iterative training module is used to return to the step of inputting the interconnect delay feature sample and the cell delay feature sample into the preset training model to obtain the predicted delay result if the error result does not meet the error standard indicated by the preset error threshold range. Training is stopped when the training error result meets the error standard indicated by the preset error threshold range, and a delay prediction model with the accuracy condition is obtained.

[0196] The specific implementation of the delay prediction device in this application is basically the same as the embodiments of the delay prediction method described above, and will not be repeated here.

[0197] Reference Figure 1 , Figure 1 This is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiments of this application.

[0198] like Figure 1As shown, the terminal may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a memory 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard. Optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0199] Optionally, the latency prediction device may also include a rectangular user interface, a network interface, a camera, RF (Radio Frequency) circuitry, sensors, audio circuitry, a WiFi module, etc. The rectangular user interface may include a display screen and an input submodule such as a keyboard. Optionally, the rectangular user interface may also include a standard wired interface or a wireless interface. The network interface may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0200] Those skilled in the art will understand that Figure 1 The delay prediction device structure shown does not constitute a limitation on the delay prediction device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0201] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, and a latency prediction program. The operating system is a program that manages and controls the hardware and software resources of the latency prediction device, supporting the operation of the latency prediction program and other software and / or programs. The network communication module is used to enable communication between the various components within the memory 1005, as well as communication with other hardware and software in the latency prediction system.

[0202] exist Figure 1 In the delay prediction device shown, the processor 1001 is used to execute the delay prediction program stored in the memory 1005 to implement the steps of the delay prediction method described in any of the above claims.

[0203] The specific implementation of the delay prediction device in this application is basically the same as the embodiments of the delay prediction method described above, and will not be repeated here.

[0204] This application also provides a storage medium storing a program implementing a latency prediction method, the program implementing the latency prediction method being executed by a processor to implement the latency prediction method as follows:

[0205] Obtain the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value;

[0206] Based on the capacitance and resistance values ​​of each unit interconnect, the equivalent capacitance value of the interconnect path between each unit is calculated, and based on the equivalent capacitance value, the target interconnect delay characteristics between each unit are determined.

[0207] Based on the equivalent capacitance value and the unit feature information, the unit delay characteristics of each unit are determined;

[0208] The interconnect delay characteristics and the cell delay characteristics are input into a preset delay prediction model. Based on the delay prediction model, the interconnect delay characteristics and the cell delay characteristics are predicted to obtain the delay result of the circuit.

[0209] Optionally, the step of calculating the equivalent capacitance value of the interconnect path between each unit based on the capacitance and resistance values ​​of each unit interconnect, and determining the target interconnect delay characteristics between each unit based on the equivalent capacitance value, includes:

[0210] Based on the capacitance and resistance values ​​of the interconnects of each unit, an RC tree model of the interconnection path between each unit is established and the resistance value of each node in the RC tree model is determined.

[0211] All downstream nodes of each node in the RC tree model are equivalent to the π model of each node;

[0212] Based on the π model of each node, the equivalent capacitance value of the interconnection path between each unit is calculated;

[0213] Based on the equivalent capacitance and resistance values ​​of each node, the ECM delay between each unit is calculated.

[0214] The ECM delay is determined as the delay characteristic of the target interconnect.

[0215] Optionally, after the step of calculating the ECM delay between each unit based on the equivalent capacitance value and the resistance value of each node, the method includes:

[0216] Determine the capacitance value of each node in the RC tree model;

[0217] Based on the resistance and capacitance values ​​of each node, the ECM delay is recursively calculated to obtain the second moment of each node.

[0218] Based on the ECM delay and the second moment, the MD2M delay between each unit is calculated;

[0219] The step of determining the ECM delay as the delay characteristic of the target interconnect includes:

[0220] The ECM delay and the MD2M delay are determined as the delay characteristics of the target interconnect.

[0221] Optionally, after the step of calculating the MD2M delay between each unit based on the ECM delay and the second moment, the method includes:

[0222] Based on the capacitance and resistance values ​​of the interconnects of each unit, the Elmore delay and D2M delay between each unit are determined.

[0223] The ECM delay, the MD2M delay, the Elmore delay, and the D2M delay are determined as the target interconnect delay characteristics between each of the units.

[0224] Optionally, before the step of inputting the interconnect delay characteristics and the cell delay characteristics into a preset delay prediction model, and performing prediction processing on the interconnect delay characteristics and the cell delay characteristics based on the delay prediction model to obtain the delay result of the circuit, the method includes:

[0225] Obtain unit feature samples and target delay result labels for the unit feature samples, wherein the unit feature samples include interconnect delay feature samples and unit delay feature samples;

[0226] Based on the interconnect delay feature samples, the unit delay feature samples, and the target delay result labels of the unit feature samples, the preset training model is iteratively trained to obtain a delay prediction model that meets the accuracy requirements.

[0227] Optionally, the step of obtaining the target time delay result label of the unit feature sample includes:

[0228] Obtain the target interconnect delay characteristics, cell delay characteristics, and initial delay result values ​​of the cell feature samples;

[0229] The target interconnect delay feature and the unit delay feature of the unit feature sample are summed to obtain the target delay result value of the unit feature sample. The initial delay result value is then compared with the target delay result value of the unit feature sample to obtain the target delay result label of the unit feature sample.

[0230] Optionally, the step of iteratively training a preset training model based on the interconnect delay feature samples, the cell delay feature samples, and the target delay result labels of the cell feature samples to obtain a delay prediction model that meets the accuracy requirements includes:

[0231] The interconnect delay feature samples and the cell delay feature samples are input into the preset training model to obtain the predicted delay result;

[0232] The difference between the predicted latency result and the target latency result label of the unit feature sample is calculated to obtain the error result;

[0233] Determine whether the error result meets the error standard indicated by the preset error threshold range;

[0234] If the error result does not meet the error standard indicated by the preset error threshold range, the process returns to the step of inputting the interconnect delay feature sample and the cell delay feature sample into the preset training model to obtain the predicted delay result. Training stops when the training error result meets the error standard indicated by the preset error threshold range, and a delay prediction model with the required accuracy is obtained.

[0235] The specific implementation of the storage medium in this application is basically the same as the embodiments of the latency prediction method described above, and will not be repeated here.

[0236] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described delay prediction method.

[0237] The specific implementation of the computer program product in this application is basically the same as the embodiments of the delay prediction method described above, and will not be repeated here.

[0238] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0239] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0240] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0241] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A time delay prediction method, characterized in that, The time delay prediction method includes: Obtain the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value; Based on the capacitance and resistance values ​​of each unit interconnect, the equivalent capacitance value of the interconnect path between each unit is calculated, and based on the equivalent capacitance value, the target interconnect delay characteristics between each unit are determined. Based on the equivalent capacitance value and the unit feature information, the unit delay characteristics of each unit are determined; The interconnect delay characteristics and the cell delay characteristics are input into a preset delay prediction model. Based on the delay prediction model, the interconnect delay characteristics and the cell delay characteristics are predicted to obtain the delay result of the circuit. The step of calculating the equivalent capacitance value of the interconnect path between each unit based on the capacitance and resistance values ​​of each unit interconnect, and determining the target interconnect delay characteristics between each unit based on the equivalent capacitance value, includes: Based on the capacitance and resistance values ​​of the interconnects of each unit, an RC tree model of the interconnection path between each unit is established and the resistance value of each node in the RC tree model is determined. All downstream nodes of each node in the RC tree model are equivalent to the π model of each node; Based on the π model of each node, the equivalent capacitance value of the interconnection path between each unit is calculated; Based on the equivalent capacitance and resistance values ​​of each node, the ECM delay between each unit is calculated. The ECM delay is determined as the delay characteristic of the target interconnect; After the step of calculating the ECM delay between each unit based on the equivalent capacitance and resistance values ​​of each node, the method includes: Determine the capacitance value of each node in the RC tree model; Based on the resistance and capacitance values ​​of each node, the ECM delay is recursively calculated to obtain the second moment of each node. Based on the ECM delay and the second moment, the MD2M delay between each unit is calculated; The step of determining the ECM delay as the delay characteristic of the target interconnect includes: The ECM delay and the MD2M delay are determined as the delay characteristics of the target interconnect.

2. The time delay prediction method as described in claim 1, characterized in that, After the step of calculating the MD2M delay between each unit based on the ECM delay and the second moment, the method includes: Based on the capacitance and resistance values ​​of the interconnects of each unit, the Elmore delay and D2M delay between each unit are determined. The ECM delay, the MD2M delay, the Elmore delay, and the D2M delay are determined as the target interconnect delay characteristics between each of the units.

3. The time delay prediction method as described in claim 1, characterized in that, Before the step of inputting the interconnect delay characteristics and the cell delay characteristics into a preset delay prediction model, and performing prediction processing on the interconnect delay characteristics and the cell delay characteristics based on the delay prediction model to obtain the delay result of the circuit, the method includes: Obtain unit feature samples and target delay result labels for the unit feature samples, wherein the unit feature samples include interconnect delay feature samples and unit delay feature samples; Based on the interconnect delay feature samples, the unit delay feature samples, and the target delay result labels of the unit feature samples, the preset training model is iteratively trained to obtain a delay prediction model that meets the accuracy requirements.

4. The time delay prediction method as described in claim 3, characterized in that, The step of obtaining the target time delay result label of the unit feature sample includes: Obtain the target interconnect delay characteristics, cell delay characteristics, and initial delay result values ​​of the cell feature samples; The target interconnect delay feature and the unit delay feature of the unit feature sample are summed to obtain the target delay result value of the unit feature sample. The initial delay result value is then compared with the target delay result value of the unit feature sample to obtain the target delay result label of the unit feature sample.

5. The time delay prediction method as described in claim 3, characterized in that, The step of iteratively training a preset training model based on the interconnect delay feature samples, the unit delay feature samples, and the target delay result labels of the unit feature samples to obtain a delay prediction model that meets the accuracy requirements includes: The interconnect delay feature samples and the cell delay feature samples are input into the preset training model to obtain the predicted delay result; The difference between the predicted latency result and the target latency result label of the unit feature sample is calculated to obtain the error result; Determine whether the error result meets the error standard indicated by the preset error threshold range; If the error result does not meet the error standard indicated by the preset error threshold range, the process returns to the step of inputting the interconnect delay feature sample and the cell delay feature sample into the preset training model to obtain the predicted delay result. Training stops when the training error result meets the error standard indicated by the preset error threshold range, and a delay prediction model with the required accuracy is obtained.

6. A time delay prediction device, characterized in that, The delay prediction device includes: The acquisition module is used to acquire the unit feature information of each unit in the circuit and the feature sequence of each unit interconnection line, wherein the feature sequence includes capacitance value and resistance value; The calculation module is used to calculate the equivalent capacitance value of the interconnect path between each unit based on the capacitance and resistance values ​​of each unit interconnect, and to determine the target interconnect delay characteristics between each unit based on the equivalent capacitance value. The determining module is used to determine the unit delay characteristics of each unit based on the equivalent capacitance value and the unit characteristic information; The prediction module is used to input the interconnect delay characteristics and the unit delay characteristics into a preset delay prediction model, and perform prediction processing on the interconnect delay characteristics and the unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit. The calculation module includes: A module is established to build an RC tree model of the interconnection path between the units based on the capacitance and resistance values ​​of the interconnection lines of each unit, and to determine the resistance value of each node in the RC tree model. An equivalent module is used to convert all downstream nodes of each node in the RC tree model into the π model of each node. An equivalent capacitance calculation module is used to calculate the equivalent capacitance value of the interconnection path between each unit based on the π model of each node. The ECM delay calculation module is used to calculate the ECM delay between each unit based on the equivalent capacitance value and the resistance value of each node. The first determining module is used to determine the ECM delay as the delay characteristic of the target interconnect; The computing module also includes: A capacitance value determination module is used to determine the capacitance value of each node in the RC tree model; The recursive calculation module is used to recursively calculate the ECM delay based on the resistance and capacitance values ​​of each node, and obtain the second moment of each node. The MD2M delay calculation module is used to calculate the MD2M delay between each unit based on the ECM delay and the second moment. The second determining module is used to determine the ECM delay and the MD2M delay as the delay characteristics of the target interconnect.

7. A time delay prediction device, characterized in that, The delay prediction device includes: a memory, a processor, and a program stored in the memory for implementing the delay prediction method. The memory is used to store the program that implements the delay prediction method; The processor is configured to execute a program that implements the delay prediction method to carry out the steps of the delay prediction method as described in any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium stores a program for implementing the delay prediction method, which is executed by a processor to implement the steps of the delay prediction method as described in any one of claims 1 to 5.

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