Clock disciplining system and method for a hydroacoustic communication device

Abstract

This invention relates to a clock discipline system and synchronization discipline method for underwater acoustic communication devices, belonging to the fields of underwater acoustic communication and underwater positioning and navigation technology. It solves the problem that existing network clock systems in underwater acoustic communication networks based on underwater acoustic communication devices can only discipline the clock of one timing node at a time, making it impossible to synchronously discipline the clocks of multiple timing nodes; furthermore, it fails to balance the accuracy, power consumption, and size of the timing nodes. This invention includes a discipline unit and N timing nodes. The discipline unit sequentially sends discipline commands to the N timing nodes via chip select. After receiving the discipline command, each timing node begins receiving a calibrated second pulse signal from the discipline unit, achieving synchronous discipline of the N timing nodes. Each disciplined timing node generates a second timestamp and a microsecond timestamp. The discipline unit also displays the discipline completion status of each timing node. It is primarily applied in underwater acoustic communication device synchronous clock networks.

Description

Technical Field

[0001] This invention belongs to the field of underwater acoustic communication and underwater positioning and navigation technology. Background Technology

[0002] Underwater acoustic communication devices are fundamental components of network nodes in an underwater acoustic communication network. Each underwater acoustic communication device acts as a network node, and its clock system serves as a timing node. In practical applications, whether forwarding communication as a network node or performing ranging and detection, the underwater acoustic communication device needs a high-precision local clock as a reference source to accurately locate itself and measure distances to other target nodes. Clock systems used in underwater acoustic communication networks typically combine high-precision timing nodes with high-precision discipline systems to achieve a high-precision, low-power underwater acoustic communication device synchronous clock network. For such systems, the timing nodes must possess high timing accuracy, low power consumption, and small size to achieve long-term high-precision timing operation; the discipline system must have a one-to-many rapid discipline capability to improve the networking efficiency of the synchronous clock network.

[0003] The high-precision time synchronization node provides each underwater acoustic communication device with a high-precision timestamp synchronized with satellite time. Currently, the mainstream approach is to use a chip atomic clock + FPGA or a chip atomic clock + MCU + peripheral circuitry to generate the high-precision timestamp. While these solutions can achieve microsecond-level high-precision time synchronization, they suffer from the following problems:

[0004] 1) For the chip atomic clock + FPGA solution, although FPGA has advantages in high-precision signal processing, FPGA devices consume a lot of power and are not suitable for long-term unmanned underwater operation of underwater acoustic communication devices.

[0005] 2) For the chip atomic clock + MCU + peripheral circuit solution, the chip atomic clock is usually combined with an external frequency divider circuit to replace the external crystal oscillator of the low-power MCU to achieve high-precision time synchronization. However, the space in underwater acoustic communication devices is compact, and this solution is relatively large, making it unsuitable for integration. Specifically, in the chip atomic clock + MCU + peripheral circuit solution, there are two main ways to ensure the timing accuracy of the MCU: 1) Use the microcontroller (i.e., MCU) I / O software interrupt to receive the chip atomic clock clock signal. The disadvantage is that there is a delay error in the I / O software interrupt input and output, and it is affected by interference from other interrupt operations in the software process. In the worst case, missed timing may occur, resulting in low timestamp generation accuracy. 2) Use an externally designed hardware frequency divider circuit to divide the 10MHz frequency standard output signal of the chip atomic clock into 32kHz, which is used as a low-speed external clock for the microcontroller. The disadvantage is that the externally designed frequency divider circuit increases system power consumption and system size.

[0006] The high-precision discipline system achieves synchronized discipline of each node in a high-precision time synchronization node network. The high-precision discipline system obtains satellite synchronization time by receiving GPS signals, and then uses discipline operations to synchronize the clock of each tamed node with the discipline system's clock, ultimately achieving network synchronization for the entire underwater acoustic communication device. However, most discipline systems can only discipline one time synchronization node at a time. Therefore, if each node in the high-precision time synchronization node network is disciplined one by one, the time required to achieve network clock synchronization is too long. Using multiple discipline systems to discipline multiple time synchronization nodes separately would result in a large system size and wasted resources; therefore, these problems urgently need to be solved. Summary of the Invention

[0007] The purpose of this invention is to solve the problems in existing network clock systems for underwater acoustic communication networks based on underwater acoustic communication devices, where a single discipline system can only discipline the clock of one timing node at a time, making it impossible to simultaneously discipline the clocks of multiple timing nodes; at the same time, it cannot simultaneously address the issues of timing node accuracy, power consumption, and size; this invention provides a clock discipline system and synchronous discipline method for underwater acoustic communication devices.

[0008] A clock discipline system for underwater acoustic communication devices includes one discipline unit and N timing nodes; wherein each timing node is the clock system of an underwater acoustic communication device.

[0009] The taming unit is used to send taming commands to N timing nodes sequentially via chip selection. After receiving the taming command, each timing node begins to receive a calibrated second pulse signal from the taming unit, thereby achieving synchronous taming of the N timing nodes. After taming, each timing node generates a second timestamp and a microsecond timestamp. The taming unit is also used to display the taming completion status of each timing node.

[0010] Among them, the second pulse signal after one calibration serves as the reference clock for each timing node;

[0011] Each timing node generates a second timestamp and a microsecond timestamp, which are used to synchronize the time with the devices of the underwater acoustic communication device corresponding to that timing node.

[0012] As a preferred embodiment, the taming unit is implemented based on a GPS taming clock and an FPGA.

[0013] The GPS discipline clock is used to self-calibrate the satellite second pulse signal received through the GPS antenna, generate a calibrated second pulse signal, and send it to the FPGA.

[0014] The FPGA is used to receive the start command and, upon receiving it, to begin receiving a calibrated second pulse signal. Simultaneously, it sends a disciplining command to N timing nodes sequentially via chip select. Each timing node, upon receiving the disciplining command, begins receiving the calibrated second pulse signal forwarded by the FPGA, ensuring that all N timing nodes receive the calibrated second pulse signal sequentially. This calibrated second pulse signal is used to synchronize and discipline the N timing nodes. The FPGA also receives and displays the disciplining completion status from each timing node.

[0015] As a preferred embodiment, each timing node is implemented based on a chip atomic clock, an external crystal oscillator, and a microcontroller.

[0016] The chip atomic clock is used to receive the first-calibrated second pulse signal output by the FPGA after receiving the disciplining command, perform self-calibration, generate a second-calibrated second pulse signal and a disciplining completion status, and send the disciplining completion status and the second-calibrated second pulse signal to the microcontroller.

[0017] The microcontroller is used to forward the taming completion status to the FPGA; it is also used to trigger the generation of second and microsecond timestamps based on the second pulse signal after secondary calibration and the clock signal emitted by the external crystal oscillator.

[0018] Preferably, the FPGA includes a tri-state circuit, a time-division multiplexing state machine selector, a processor, serial port 1, and N disciplined status indicator lights; the N disciplined status indicator lights correspond one-to-one with the N timing nodes;

[0019] The processor generates two enable signals based on the received start-up command to control the start-up of the time-division multiplexing state machine selector and the tri-state circuit, respectively.

[0020] The three-state circuit is used to simultaneously forward the calibrated second pulse signal generated by the GPS discipline clock to N timing nodes;

[0021] The processor is used to send the chip select signal it generates to the time-division multiplexing state machine selector through serial port 1. It is also used to receive the disciplining completion status output by each timing node and display it through the disciplining status indicator light corresponding to that timing node.

[0022] The time-division multiplexing state machine selector selects the corresponding timing node based on the received chip select signal and sends a disciplining command to the selected timing node. At this time, the timing node begins to receive a calibrated second pulse signal.

[0023] Preferably, the communication between the three-state circuit and the GPS discipline clock is achieved through a single I / O port;

[0024] Communication between the three-state circuit and the N timing nodes is achieved through N I / O ports respectively;

[0025] The communication between the time-division multiplexing state machine selector and the N timing nodes is implemented through N I / O ports respectively;

[0026] Communication between the processor and the N discipline status indicator lights is achieved through N I / O ports.

[0027] Preferably, the microcontroller includes a second timer, a microsecond timer, an internal clock, a serial port 2, and two I / O ports;

[0028] Both the second timer and the microsecond timer are used to receive the second pulse signal after secondary calibration;

[0029] The second pulse signal after secondary calibration is used to trigger the second timer to count, so that the second timer generates a second timestamp;

[0030] The second pulse signal after secondary calibration is also used to reset and clear the microsecond timer;

[0031] The internal clock is used to trigger the microsecond timer to count based on the clock signal received from the external crystal oscillator, so that the microsecond timer generates a microsecond timestamp.

[0032] The first I / O port is used to forward the taming completion status generated by the chip's atomic clock to the taming unit;

[0033] The second I / O port is used to receive the disciplining command issued by the FPGA and forward the disciplining command to the chip atomic clock;

[0034] The chip atomic clock, based on the received disciplining command, begins to receive a calibrated second pulse signal.

[0035] As a preferred option, the GPS discipline clock also has a display function to show the self-calibration status.

[0036] As a preferred option, the microcontroller is an STM32L4R9 MCU.

[0037] The synchronization discipline method implemented using the clock discipline system for underwater acoustic communication devices includes the following steps:

[0038] Step 1: Power on the discipline unit. After the GPS discipline clock performs self-calibration on the received satellite second pulse signal, it generates a calibrated second pulse signal and sends it to the FPGA.

[0039] Step 2: After sending the start command to the FPGA, the FPGA begins to receive a calibrated second pulse signal and simultaneously sends the calibrated second pulse signal to N timing nodes. At this time, the FPGA sends a disciplining command to the N timing nodes in sequence using chip select. After each timing node receives the disciplining command, it begins to receive a calibrated second pulse signal, thus achieving synchronous disciplining of the N timing nodes.

[0040] During the process of taming the timing node by the FPGA, the timing node also feeds back the current taming completion status to the FPGA in real time, and the FPGA displays the current taming completion status of the timing node.

[0041] The present invention brings the following benefits:

[0042] 1. The clock discipline system for underwater acoustic communication devices described in this invention utilizes a discipline unit + N timing nodes configuration. It sequentially accesses the N timing nodes, so that each timing node, after receiving the discipline command to invite access, begins to receive a calibrated second pulse signal issued by the discipline unit, thereby achieving synchronous discipline of the N timing nodes and solving the problem of difficult networking of synchronous clock networks for underwater acoustic communication devices.

[0043] When applied, this invention eliminates the need to wait for the previous timing node to complete its training before proceeding to the next. Through chip selection, this invention can simultaneously train N timing nodes, resulting in faster and more convenient training and networking speeds.

[0044] 2. This invention also improves the structure of the timing node by using a chip atomic clock + microcontroller configuration. This configuration is simple and avoids the shortcomings of the existing chip atomic clock + MCU + peripheral circuit scheme, which suffers from poor timing accuracy and system complexity due to the microcontroller (i.e., MCU) scheme. Specifically, this invention uses the hardware timer of the microcontroller for counting, namely, a second timer and a microsecond timer for clock counting. Its advantage is that it overcomes the problem of poor timing accuracy of the microcontroller through software system in the existing technology. This invention uses a direct connection between the chip atomic clock and the microcontroller, instead of adding an additional hardware clock divider module for pre-clock signal processing, overcoming the problem of large system power consumption and size in the existing technology. Thus, the timing node of this invention simultaneously considers accuracy, power consumption, and system size, further enabling this invention to be used in the clock discipline system of underwater acoustic communication devices.

[0045] 3. The discipline unit adopts a high-precision GPS discipline clock and an FPGA to form a high-precision discipline unit. It utilizes the high-performance parallel processing architecture of the FPGA to realize the synchronous discipline of multiple high-precision time synchronization nodes in the clock network.

[0046] 4. A high-precision time synchronization node is formed by using a low-power chip atomic clock and a low-power microcontroller, and the high-performance timer peripheral of the microcontroller is used to achieve high-precision time synchronization. Attached Figure Description

[0047] Figure 1 A schematic diagram illustrating the principle of a taming unit taming multiple timing nodes;

[0048] Figure 2 This is a structural diagram of a tamed unit;

[0049] Figure 3 This is a schematic diagram of the time synchronization node. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0052] Detailed Implementation Method 1, see [link / reference] Figure 1 and Figure 2 This embodiment describes a clock discipline system for an underwater acoustic communication device, comprising a discipline unit and N timing nodes; wherein each timing node is a clock system for an underwater acoustic communication device.

[0053] The taming unit is used to send taming commands to N timing nodes sequentially via chip selection. After receiving the taming command, each timing node begins to receive a calibrated second pulse signal from the taming unit, thereby achieving synchronous taming of the N timing nodes. After taming, each timing node generates a second timestamp and a microsecond timestamp. The taming unit is also used to display the taming completion status of each timing node.

[0054] Among them, the second pulse signal after one calibration serves as the reference clock for each timing node;

[0055] Each timing node generates a second timestamp and a microsecond timestamp, which are used to synchronize the time with the devices of the underwater acoustic communication device corresponding to that timing node.

[0056] In this embodiment, the present invention is constructed by using a discipline unit and N timing nodes. The N timing nodes are accessed sequentially, and each timing node, after receiving the discipline command to invite access, begins to receive a calibrated second pulse signal issued by the discipline unit, thereby realizing the synchronous discipline of the N timing nodes and solving the problem of difficult networking of synchronous clock networks for underwater acoustic communication devices.

[0057] The second pulse signal after one calibration is used as the reference clock for each timing node to calibrate the clock of its timing node, thereby achieving clock synchronization and discipline of N timing nodes. This enables each timing node to generate high-precision second and microsecond timestamps. The second and microsecond timestamps generated by each timing node are the clocks of the clock system of the underwater acoustic communication device corresponding to that timing node.

[0058] See Figure 2 Furthermore, the taming unit is implemented based on a GPS taming clock and FPGA1;

[0059] The GPS discipline clock is used to self-calibrate the satellite second pulse signal received through the GPS antenna, generate a calibrated second pulse signal, and send it to FPGA1.

[0060] FPGA1 is used to receive the start command and, upon receiving the start command, begin receiving a calibrated second pulse signal. Simultaneously, it sequentially sends a discipline command to N timing nodes via chip select. After receiving the discipline command, each timing node begins receiving the calibrated second pulse signal forwarded by FPGA1, enabling the N timing nodes to sequentially receive the calibrated second pulse signal. This calibrated second pulse signal is used to synchronize and discipline the N timing nodes. FPGA1 is also used to receive and display the discipline completion status feedback from each timing node.

[0061] In this preferred embodiment, the taming unit is composed of a GPS high-precision taming clock and an FPGA1 to form a high-precision taming unit. By utilizing the high-performance parallel processing architecture of the FPGA1, the synchronous taming of multiple high-precision time synchronization nodes in the clock network can be achieved.

[0062] Furthermore, a high-precision GPS disciplined clock can employ a self-made GPS temperature-controlled crystal oscillator discipline box. By receiving GPS signals (i.e., satellite second pulse signals), it achieves synchronization between the local disciplined clock and satellite time. Then, through an internal constant-temperature control algorithm, it controls the clock signal output of the crystal oscillator, ultimately enabling it to provide a single high-precision, high-stability second pulse signal synchronized with the satellite signal. The GPS disciplined clock can also have a display function to show the self-calibration status. As an example, an LCD-GPS disciplined clock is used. Because the self-calibration time of a high-precision GPS disciplined clock is relatively long, an LCD display showing the lock status is used to determine the GPS disciplined clock's calibration status.

[0063] See Figure 2 Furthermore, FPGA1 includes a tri-state circuit 1-1, a time-division multiplexing state machine selector 1-2, a processor 1-3, serial port 1-4, and N disciplined status indicator lights; the N disciplined status indicator lights correspond one-to-one with the N timing nodes.

[0064] Processor 1-3 generates two enable signals based on the received start-up command to control the start-up of time-division multiplexing state machine selector 1-2 and tri-state circuit 1-1 respectively;

[0065] The three-state circuit 1-1 is used to simultaneously forward the calibrated second pulse signal generated by the GPS discipline clock to N timing nodes;

[0066] Processor 1-3 is used to send the chip select signal it generates to time division multiplexing state machine selector 1-2 through serial port 1-4. It is also used to receive the disciplining completion status output by each timing node and display it through the disciplining status indicator light corresponding to the timing node.

[0067] The time-division multiplexing state machine selector 1-2 selects the corresponding timing node according to the received chip select signal and sends a disciplining command to the selected timing node. At this time, the timing node begins to receive a calibrated second pulse signal.

[0068] As an example, the status of taming can be displayed by controlling the on / off state of the taming indicator light or by using different colors. Specifically, the indicator light can be on to indicate that taming is complete, and off to indicate that taming is not complete. Alternatively, the indicator light can be green to indicate that taming is complete, and red to indicate that taming is not complete, and so on.

[0069] See Figure 2 In practical applications, the communication between the tri-state circuit 1-1 and the GPS discipline clock is achieved through one I / O port; the communication between the tri-state circuit 1-1 and N timing nodes is achieved through N I / O ports respectively; and the communication between the time-division multiplexing state machine selector 1-2 and the N timing nodes is achieved through N I / O ports respectively.

[0070] Communication between processors 1-3 and the N disciplined status indicator lights is achieved through N I / O ports.

[0071] Furthermore, see Figure 3 Each timing node is implemented based on a chip atomic clock, an external crystal oscillator, and a microcontroller.

[0072] The chip atomic clock is used to receive the first-calibrated second pulse signal output by FPGA1 after receiving the disciplining command, perform self-calibration, generate a second-calibrated second pulse signal and disciplining completion status, and send the disciplining completion status and the second-calibrated second pulse signal to the microcontroller 2.

[0073] Microcontroller 2 is used to forward the taming completion status to FPGA1; it is also used to trigger the generation of second timestamps and microsecond timestamps based on the second pulse signal after secondary calibration and the clock signal emitted by the external crystal oscillator.

[0074] In this preferred embodiment, a high-precision timing node is formed by using a low-power chip atomic clock and a low-power microcontroller. This overcomes the shortcomings of the existing chip atomic clock + MCU + peripheral circuit scheme, which has poor timing accuracy and complex system. The present invention uses a direct connection between the chip atomic clock and the microcontroller, instead of adding an additional hardware clock divider module for pre-clock signal processing as in the existing technology, thus overcoming the shortcomings of large system power consumption and size in the existing technology.

[0075] The chip atomic clock can be implemented using existing technology, as long as it can achieve the signal generation function of this invention. Figure 3 The example shown is a specific configuration of the internal structure of a chip atomic clock, and is for reference only.

[0076] For details, see Figure 3 The microcontroller 2 includes a second timer 2-1, a microsecond timer 2-2, an internal clock 2-3, serial port 2-4, and two I / O ports;

[0077] Both the second timer 2-1 and the microsecond timer 2-2 are used to receive the second pulse signal after secondary calibration;

[0078] The second pulse signal after secondary calibration is used to trigger the second timer 2-1 to count, so that the second timer 2-1 generates a second timestamp;

[0079] The second pulse signal after secondary calibration is also used to reset and clear the microsecond timer 2-2;

[0080] Internal clock 2-3 is used to trigger microsecond timer 2-2 to count based on the clock signal received from the external crystal oscillator, so that microsecond timer 2-2 generates a microsecond timestamp;

[0081] The first I / O port is used to forward the taming completion status generated by the chip's atomic clock to the taming unit;

[0082] The second I / O port is used to receive the disciplining command issued by FPGA1 and forward the disciplining command to the chip atomic clock;

[0083] The chip atomic clock, based on the received disciplining command, begins to receive a calibrated second pulse signal.

[0084] In this preferred embodiment, the microcontroller 2 has a simple structure, consisting only of a second timer 2-1, a microsecond timer 2-2, an internal clock 2-3, a serial port 2-4, and two I / O ports. The microcontroller 2 has low power consumption and a small size. To ensure the accuracy of the timestamp generated by the microcontroller 2, hardware timers are used for clock counting, specifically the second timer 2-1 and the microsecond timer 2-2. The advantage of using hardware is that the microcontroller's timing function is not affected by any software process operations or system clock drift errors; its accuracy relies entirely on the high-performance on-chip and off-chip hardware circuitry of the microcontroller. Existing technologies mainly guarantee the timing accuracy of the microcontroller through two methods: 1) using I / O software interrupts to receive the chip's atomic clock signal. The disadvantage is that I / O software interrupts introduce delay errors and are subject to interference from other interrupt operations in the software process. In the worst case, missed timing may occur, resulting in low timestamp generation accuracy. 2) Using an externally designed hardware frequency divider circuit to divide the 10MHz frequency standard output signal of the chip atomic clock to 32kHz for use as a low-speed external clock for the microcontroller has the disadvantage that the externally designed frequency divider circuit increases system power consumption and system size. The advantage of this invention is that it uses a hardware timer within the microcontroller to count clock signals to achieve high-precision timing. Structurally, it uses a chip atomic clock + microcontroller combination, reducing system power consumption and size.

[0085] As an example, see Figure 3 The high-precision timing node consists of a low-power atomic clock chip SA.45 and a low-power MCU STM32L4R9, achieving timing accuracy down to the microsecond. The total system power consumption is <200mW, resulting in a compact size. The atomic clock chip and the MCU are connected only by a serial port and a second pulse signal line. The serial port forwards disciplining commands from the disciplining unit, while the second pulse signal line provides the MCU with a second-cycle trigger signal. For second-level timing, the high-performance timer peripheral of the MCU is periodically triggered by the second pulse signal to achieve second counting. For microsecond-level timing, microsecond signal counting also relies on a hardware timer peripheral. Through hardware configuration of the timer, the microsecond signal source can be triggered by the MCU's internal system clock signal for counting, while the second pulse signal input from the external atomic clock is cleared, thus achieving microsecond-level timing. Because the timer counting and clearing operations are entirely implemented by independent hardware peripherals and are not affected by the MCU software process, high timing accuracy is achieved.

[0086] Detailed implementation method two, see below. Figures 1 to 3 This embodiment describes a synchronization discipline method implemented using the clock discipline system for underwater acoustic communication devices as described in Specific Embodiment 1. This method includes the following steps:

[0087] Step 1: Power on the discipline unit. After the GPS discipline clock performs self-calibration on the received satellite second pulse signal, it generates a calibrated second pulse signal and sends it to FPGA1.

[0088] Step 2: After sending the start command to FPGA1, FPGA1 begins to receive a calibrated second pulse signal and simultaneously sends the calibrated second pulse signal to N timing nodes. At this time, FPGA1 sends a disciplining command to the N timing nodes in sequence using chip select. After each timing node receives the disciplining command, it begins to receive a calibrated second pulse signal, thus achieving synchronous disciplining of the N timing nodes.

[0089] During the process of taming the timing node, the timing node also feeds back the current taming completion status to the FPGA1 in real time, and the FPGA1 displays the current taming completion status of the timing node.

[0090] In this embodiment, the control module of the high-precision discipline unit uses an EP4CE6E22C8 FPGA as the main controller and a high-precision discipline clock (i.e., a second pulse signal after one calibration) as the clock input source for the FPGA. It is also connected to an external device being disciplined, thereby achieving synchronous discipline of multiple time synchronization nodes. After the discipline clock completes self-calibration locking, pressing the user button on the discipline system sends a start command, which in turn sends a high-precision second pulse signal after one calibration and a discipline command to all time synchronization nodes. FPGA1 sequentially sends discipline commands to N time synchronization nodes using a chip select method. Each time synchronization node, upon receiving the discipline command, begins receiving the second pulse signal after one calibration, achieving synchronous discipline of the N time synchronization nodes. The discipline completion status of each time synchronization node is determined by the messages returned by each node.

[0091] When applied, this invention eliminates the need to wait for the previous timing node to complete its training before proceeding to the next. Through chip selection, this invention can simultaneously train N timing nodes, resulting in faster and more convenient training and networking speeds.

[0092] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A clock disciplining system for an underwater acoustic communication set, characterized by, It includes one disciplined unit and N timing nodes; where each timing node is the clock system of an underwater acoustic communication device; The taming unit is used to send taming commands to N timing nodes sequentially via chip selection. After receiving the taming command, each timing node begins to receive a calibrated second pulse signal from the taming unit, thereby achieving synchronous taming of the N timing nodes. After taming, each timing node generates a second timestamp and a microsecond timestamp. The taming unit is also used to display the taming completion status of each timing node. Among them, the second pulse signal after one calibration serves as the reference clock for each timing node; Each timing node generates a second timestamp and a microsecond timestamp, which are used to synchronize the time of each device in the underwater acoustic communication device corresponding to that timing node; The taming unit is implemented based on a GPS taming clock and an FPGA (1); The GPS discipline clock is used to self-calibrate the satellite second pulse signal received through the GPS antenna, generate a calibrated second pulse signal, and send it to the FPGA (1). FPGA (1) is used to receive the start-up command and, after receiving the start-up command, to start receiving the calibrated second pulse signal. At the same time, it sends a disciplining command to N timing nodes in sequence through chip select. After receiving the disciplining command, each timing node starts receiving the calibrated second pulse signal forwarded by FPGA (1), so that the N timing nodes receive the calibrated second pulse signal in sequence. The calibrated second pulse signal is used to synchronously discipline the N timing nodes. It is also used to receive and display the disciplining completion status fed back by each timing node. Each timing node is implemented based on a chip atomic clock, an external crystal oscillator, and a microcontroller (2); The chip atomic clock is used to receive the taming command, start receiving the second pulse signal after the first calibration output by the FPGA (1), perform self-calibration, generate the second pulse signal after the second calibration and the taming completion status, and send the taming completion status and the second pulse signal after the second calibration to the microcontroller (2). The microcontroller (2) is used to forward the taming completion status to the FPGA (1); it is also used to trigger the generation of second timestamp and microsecond timestamp based on the second pulse signal after secondary calibration and the clock signal emitted by the external crystal oscillator.

2. The clock disciplining system for an underwater acoustic communication device according to claim 1, wherein The FPGA (1) includes a tri-state circuit (1-1), a time-division multiplexing state machine selector (1-2), a processor (1-3), serial port 1 (1-4), and N disciplined status indicator lights; the N disciplined status indicator lights correspond one-to-one with the N timing nodes; The processor (1-3) generates two enable signals based on the received start-up command to control the start-up of the time-division multiplexing state machine selector (1-2) and the tri-state circuit (1-1) respectively; The three-state circuit (1-1) is used to simultaneously forward the calibrated second pulse signal generated by the GPS discipline clock to N timing nodes; The processor (1-3) is used to send the chip select signal it generates to the time-division multiplexing state machine selector (1-2) through serial port 1 (1-4), and is also used to receive the disciplining completion status output by each timing node and display it through the disciplining status indicator light corresponding to the timing node; The time-division multiplexing state machine selector (1-2) selects the corresponding timing node according to the received chip select signal and sends a disciplining command to the selected timing node. At this time, the timing node begins to receive a calibrated second pulse signal.

3. The clock disciplining system for an underwater acoustic communication set according to claim 2, wherein, Communication between the three-state circuit (1-1) and the GPS discipline clock is achieved through an I / O port; Communication between the three-state circuit (1-1) and the N timing nodes is implemented through N I / O ports respectively; The communication between the time-division multiplexing state machine selector (1-2) and the N time synchronization nodes is implemented through N I / O ports respectively; Communication between the processor (1-3) and the N disciplined status indicator lights is achieved through N I / O ports.

4. The clock disciplining system for an underwater acoustic communication set according to claim 1, wherein, The microcontroller (2) includes a second timer (2-1), a microsecond timer (2-2), an internal clock (2-3), serial port 2 (2-4), and two I / O ports; Both the second timer (2-1) and the microsecond timer (2-2) are used to receive the second pulse signal after secondary calibration; The second pulse signal after secondary calibration is used to trigger the second timer (2-1) to count, so that the second timer (2-1) generates a second timestamp; The second pulse signal after secondary calibration is also used to reset and clear the microsecond timer (2-2); The internal clock (2-3) is used to trigger the microsecond timer (2-2) to count based on the clock signal received from the external crystal oscillator, so that the microsecond timer (2-2) generates a microsecond timestamp. The first I / O port is used to forward the taming completion status generated by the chip's atomic clock to the taming unit; The second IO port is used to receive the disciplining command issued by the FPGA (1) and forward the disciplining command to the chip atomic clock; The chip atomic clock, based on the received disciplining command, begins to receive a calibrated second pulse signal.

5. The clock discipline system for an underwater acoustic communication device according to claim 1, characterized in that, The GPS discipline clock also has a display function to show the self-calibration status.

6. The clock discipline system for an underwater acoustic communication device according to claim 1, characterized in that, The microcontroller (2) is implemented using an STM32L4R9 MCU.

7. A synchronization discipline method implemented using the clock discipline system for underwater acoustic communication devices as described in claim 1, characterized in that, The method includes the following steps: Step 1: Power on the discipline unit. After the GPS discipline clock performs self-calibration on the received satellite second pulse signal, it generates a calibrated second pulse signal and sends it to the FPGA (1). Step 2: After sending the start command to FPGA (1), FPGA (1) begins to receive a calibrated second pulse signal and simultaneously sends the calibrated second pulse signal to N timing nodes. At this time, FPGA (1) sends a disciplining command to N timing nodes in sequence using chip select. After each timing node receives the disciplining command, it begins to receive a calibrated second pulse signal, thereby achieving synchronous disciplining of N timing nodes. During the process of taming the timing node by the FPGA (1), the timing node also feeds back the current taming completion status to the FPGA (1) in real time, and the FPGA (1) displays the current taming completion status of the timing node.

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