Queue Configuration for Host Interface

Abstract

This application relates to queue configuration for a host interface. A device may include a host system that includes a first circular queue having a first entry that indicates a location of a first command for a memory system and data associated with the first command. The device may include a controller that can access the first entry of the first circular queue and generate a second command for the memory system based on the data associated with the first command and the first entry. The controller may then transmit the second command to the memory system based on generating the command. The controller may also receive a response from the memory system based on transmitting the command. The controller may remove the first entry from the first circular queue based on receiving the response from the memory system.

Description

[0001] Cross-reference

[0002] This patent application is a national stage application of International Patent Application No. PCT / US2021 / 072596, filed on Dec. 24, 2021 by GYLLENSKOG, entitled "QUEUE CONFIGURATION FOR HOST INTERFACE", which claims priority to U.S. Patent Application No. 17 / 524,470, filed on Nov. 11, 2021 by GYLLENSKOG, entitled "Queue Configuration for Host Interface", and U.S. Provisional Patent Application No. 63 / 120,028, filed on Dec. 1, 2020 by GYLLENSKOG, entitled "Queue Configuration for Host Interface", each of which is assigned to the present assignee and each of which is incorporated herein by reference in its entirety. Technical Field

[0003] The following generally relates to one or more systems for memory, and more particularly, to queue configurations for a host interface. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to a logic 1 or a logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into the corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3D cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time even in the absence of an external power source. Summary of the Invention

[0006] A device is described. The device can include: a host system including a first circular queue having a first entry that indicates a first command for a memory system and a location of data associated with the first command; and a controller coupled to the host system and configured to: access the first entry of the first circular queue; generate a second command for the memory system at least in part based on the data associated with the first command stored in the first circular queue and the first entry of the first circular queue; transmit the second command to the memory system at least in part based on generating the second command; receive a response indicating completion of the second command from the memory system at least in part based on transmitting the second command; and remove the first entry from the first circular queue at least in part based on receiving the response from the memory system.

[0007] A method is described. The method can include: accessing a first entry of a first circular queue at a host system, the first entry indicating a first command for a memory system and a location of data associated with the first command; generating a second command for the memory system at least in part based on the data associated with the first command stored in the first circular queue and the first entry of the first circular queue; transmitting the second command to the memory system at least in part based on generating the second command; receiving a response indicating completion of the second command from the memory system at least in part based on transmitting the second command; and removing the first entry from the first circular queue at least in part based on receiving the response indicating completion of the second command from the memory system.

[0008] Describes a non-transitory computer-readable medium. The non-transitory computer-readable medium can store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: access a first entry of a first circular queue at a host system, the first entry indicating a first command for a memory system and a location of data associated with the first command; generate a second command for the memory system at least in part based on the data associated with the first command stored in the first circular queue and the first entry of the first circular queue; transmit the second command to the memory system at least in part based on generating the second command; receive a response indicating completion of the second command from the memory system at least in part based on transmitting the second command; and remove the first entry from the first circular queue at least in part based on receiving the response indicating completion of the second command from the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Illustrates an example of a system supporting a queue configuration for a host interface according to an example disclosed herein.

[0010] Figure 2 Illustrates an example of a host system supporting a queue configuration for a host interface according to an example disclosed herein.

[0011] Figure 3 Illustrates an example of a process flow supporting a queue configuration for a host interface according to an example disclosed herein.

[0012] Figure 4 Illustrates a block diagram of a host system controller supporting a queue configuration for a host interface according to an example disclosed herein.

[0013] Figure 5 Illustrates a flowchart depicting one or more methods supporting a queue configuration for a host interface according to an example disclosed herein. DETAILED DESCRIPTION

[0014] A host system can transfer commands to a memory system coupled to the host system to perform various operations, applications, and processing tasks. Some host systems may implement registers in host software for commands that direct a host controller to communicate with the memory system. For example, a host system may use registers into which a processing core of the host system can input commands. The host controller can then read the commands from the registers, encapsulate the commands, and transfer the commands to the memory system. In such instances, the number of commands that the host controller can transfer may be limited by the number of entries that can be stored in the registers, e.g., for some registers, 32 commands can be transferred. Additionally or alternatively, in such instances, the cores of the host system may not be able to input commands into the registers simultaneously. That is, if the host system has two (2) cores, the first core can input commands while the second core will wait. When the first core finishes inputting commands, the second core can then input a second command. Thus, the host system processing time may be extended due to processing bottlenecks around the registers, e.g., while the second core is waiting, the host system may experience latency that degrades the overall performance of the host system.

[0015] Systems, apparatuses, and techniques are described for a host system to transfer commands and responses to a memory system using multiple circular queues, where the memory system is coupled to the host system. For example, a host system can dynamically configure multiple queues across multiple cores of the host system, e.g., the host system can utilize one or more circular queues in a first core and one or more circular queues in a second core based on various parameters. Such a configuration can allow each core of the host system to input commands into corresponding queues simultaneously, e.g., the first core can input a first command into a first queue while the second core can input a second command into a second queue simultaneously. Additionally, the host system can utilize a first set of circular queues to track commands transferred to the memory system and a second set of circular queues to track responses from the memory system. By utilizing multiple circular queues, the host system can increase the number of commands that it can transfer to the memory system simultaneously at a given time and can thereby reduce processing time.

[0016] First, the features of the present disclosure are described in the context of the systems, apparatuses, and circuits described in Figure 1 The features of the present disclosure are described in the context of the host systems and process flowcharts described in Figure 2 and 3 The features of the present disclosure are described in the context of the host systems and process flowcharts described in Figure 4 and 5 These and other features of the present disclosure are further illustrated and described by reference to the device diagrams and flowcharts related to queue configurations for host interfaces described in

[0017] Figure 1An example of a system 100 that supports queue configurations for a host interface in accordance with the examples disclosed herein. The system 100 includes a host system 105 coupled to a memory system 110.

[0018] The memory system 110 may be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded MultiMediaCard (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0019] The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0020] The system 100 may include a host system 105 that may be coupled to the memory system 110. In some examples, this coupling may include interfacing with a host system controller 125, which may be an example of a control component configured to cause the host system 105 to perform various operations in accordance with the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 may use the memory system 110 to, for example, write data to and read data from the memory system 110. Although one memory system 110 is shown Figure 1 in, the host system 105 may be coupled to any number of memory systems 110.

[0021] In some instances, the host system 105 may include a host system controller 125 (e.g., a host controller interface). The host system controller 125 may be configured to communicate between the host system 105 and the memory system 110. For example, the host system controller 125 may transmit commands to the memory system 110 and receive responses from the memory system 110. In such instances, the host system controller 125 may receive a first command from the host system 105 software and translate or convert the first command into a second command that is transmitted to the memory system 110. Similarly, the host system controller 125 may receive a response from the memory system 110 and translate or convert the response into a message that can be read by the host system 105 software.

[0022] In some instances, the host system controller 125 may receive commands from the host system 105 software via registers, such as a 32-entry register or a 32-bit register. In such instances, the host system controller 125 may read the register for the command, access data associated with the command, generate a second command for the memory system 110, and then transmit the second command to the memory system 110. In such instances, the host system controller 125 may be limited in terms of the number of commands that the host system controller 125 can simultaneously transmit to the memory system 110. For example, the commands that the host system controller 125 simultaneously transmits may not be able to be more than the number of bits in the register. Additionally, the cores of the host system 105 may not be able to simultaneously input commands into the register. For example, if the first core of the host system 105 is inputting a command into the register for the host system controller 125 to read, then the second core of the host system 105 may not be able to input a second command until the first core is finished. In some cases, this may limit the time it takes for some programs to complete and may thus increase the processing time of the host system 105.

[0023] As described herein, the host system controller 125 may receive commands from the host system 105 software via multiple circular queues. The multiple circular queues may be dynamically configured by the host system 105. For example, the host system 105 software may configure two (2) circular queues for the first core and three (3) circular queues for the second core. Utilizing multiple circular queues may enable the cores of the host system 105 to simultaneously input commands into their respective queues. The host system controller 125 may also write responses from the memory system into different sets of the multiple circular queues. That is, the host system 105 software may also be able to simultaneously process multiple responses from the memory system 110 across its respective circular queues. This may enable the host system 105 to increase the processing time and increase the number of commands that the host system controller 125 can simultaneously transmit to the memory system 110.

[0024] The host system 105 may be coupled to the memory system 110 via at least one physical host interface (e.g., a host controller interface). In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Universal Flash Storage (UFS) interfaces, Embedded MultiMediaCard (eMMC) interfaces, Peripheral Component Interconnect Express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM socket interfaces that support DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be included or otherwise supported between the host system controller 125 of the host system 105 and the memory system controller 115 of the memory system 110. In some instances, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 125 may be coupled to the memory system controller 115).

[0025] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices 130-a and 130-b are shown in the Figure 1 example, the memory system 110 may include any number of memory devices 130. Additionally, in cases where the memory system 110 includes more than one memory device 130, the different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0026] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and can be an instance of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or updating data, and other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effect the desired access to the memory device 130. And in some cases, the memory system controller 115 can exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert a response (e.g., a data packet or other signal) associated with the memory device 130 into a corresponding signal for the host system 105.

[0027] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between a logical address (e.g., a logical block address (LBA)) associated with a command from the host system 105 and a physical address (e.g., a physical block address) associated with memory cells within the memory device 130.

[0028] The memory system controller 115 can include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware can include circuitry with dedicated (e.g., hard-wired) logic to perform the operations ascribed to the memory system controller 115 herein. The memory system controller 115 can be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that can store operation codes (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, e.g., internal storage or operations related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, when reading from or writing to the memory device 130, data may be stored in the local memory 120, and the data may be used within the local memory 120 for subsequent retrieval or manipulation (e.g., update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0030] Although Figure 1 the example of the memory system 110 in [description] has been shown as including the memory system controller 115, in some cases the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 (e.g., local controller 135-a and local controller 135-b) within the memory device 130 to perform the functions attributed to the memory system controller 115 herein, respectively. Generally, one or more of the functions attributed to the memory system controller 115 may, in some cases, be performed instead by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select-in memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include random access memory (RAM) memory cells such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some instances, memory device 130 may include local controller 135 (e.g., on the same die or within the same package), which may perform operations on one or more memory cells of memory device 130. Local controller 135 may operate in conjunction with memory system controller 115 or may perform one or more functions ascribed herein to memory system controller 115.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include memory die 160. For example, in some cases, memory device 130 may be a package including one or more die 160. In some instances, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if configured to each store two bits of information, triple-level cells (TLCs) if configured to each store three bits of information, quad-level cells (QLCs) if configured to each store four bits of information, or more generally multi-level memory cells. The multi-level memory cells may provide a greater storage density relative to the SLC memory cells, but in some cases, may involve a narrower read or write margin or greater complexity for the supporting circuitry.

[0035] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may be performed within different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., with respect to command decoding, page address decoding circuitry, or other circuitry shared across the planes 165).

[0036] In some cases, a block 170 may include memory cells organized in rows (pages 175) and columns (e.g., strings, not shown). For example, the memory cells within the same page 175 may share a common word line (e.g., coupled thereto), and the memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, the memory cells may be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but erased at a second granularity level (e.g., at the block granularity level). That is, a page 175 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or read operation), and a block 170 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Additionally, in some cases, the NAND memory cells may be erased before they can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0038] Figure 2An example of a host system 200 that supports a queue configuration for a host interface according to the examples disclosed herein is shown. The host system 200 may be an example of the host system 105 described in reference Figure 1 The host system 200 may include four (4) cores 205-a through 205-d. Figure 2 Four cores 205 are shown for illustrative purposes only in Figure 1 In other examples, the host system 200 may include any number of cores 205, including one, two, three, four, five, six, seven, eight, nine, ten, eleven, twelve, thirteen, fourteen, fifteen, sixteen, seventeen, or more cores 205. The host system 200 may also include a first set of circular queues 210, e.g., circular queue 210-a through circular queue 210-f. In some examples, the first set of circular queues 210 may be referred to as submission queues. The host system may include a second set of circular queues 230, e.g., circular queue 230-a through circular queue 230-c. In some examples, the second set of circular queues 230 may be referred to as completion queues. The cores 205 may be coupled to a host system controller 225. The host system controller 225 may be an example of the host system controller 125 described in reference

[0039] The host system 200 may be configured to dynamically configure the number of the first set of circular queues 210 and the second set of circular queues 230. That is, each core 205 may be configured to operate independently of each other, e.g., independently perform the computing tasks of the host system 200. Thus, the host system 200 may use software to determine the number of the first set of circular queues 210 and the second set of circular queues 230. For example, the host system 200 may configure the number of circular queues 210 in each core 205 based on the maximum size of the commands transferred between the host system 200 and the memory system. In other examples, the host system 200 may configure the number of circular queues 210 based on the number of entries 250 that the circular queues 210 can store.

[0040] In addition, the host system 200 may consider other parameters or factors when determining the number of circular queues 210. For example, the host system 200 may determine that the fourth core 205-d processes a relatively large number of tasks and data migrations, and may thus configure the fourth core 205-d to have three (3) circular queues 210. In some examples, the host system 200 may configure the second core 205-b to process commands and the third core 205-c to process from the memory system (e.g., reference​Figure 1 Response of the described memory system 110). In such instances, the host system 200 may configure the second core 205-b to include two (2) circular queues 210 and configure the third core 205-c to include one (1) circular queue 230. In some instances, each core 205 may be configured to also dynamically configure the number of the first set of circular queues 210 and the second set of circular queues 230. That is, the third core 205-c may determine that it receives more responses and may thus configure the circular queue 230-b. In some instances, the number of circular queues 210 may be limited by the number of commands that the memory system can execute simultaneously. For example, the host system 200 may prevent the number of circular queues 210 from exceeding the number of commands that the memory system can receive at a given time. In some instances, the host system 200 may determine the number of commands that the memory system can receive by transmitting an initial request for information. In other instances, the number of commands that the memory system can receive may be based on industry standards. Additionally, the core 205 may be configured to communicate internally (intra-core messaging) via the routing lines 235 (e.g., routing lines 235-a, 235-b, and 235-c). In other instances, the core 205 may be configured to communicate with other cores via the routing lines 255 (intra-core messaging).

[0041] The first set of circular queues 210 can be configured to transfer commands and messages between the host system 200 and the memory system. For example, the circular queue 210 can store commands issued by the core 205 and the host system 200. That is, the core 205 can input commands as entries 250 into the circular queue 210. The circular queue 210 can store multiple entries 250 and act as a queue of commands and messages for transmission from the host system 200 to the memory system. For example, the shaded portion in the circular queue 210 can be an instance of the number of entries 250 and commands that the circular queue 210 is storing. The number of entries 250 that the circular queue 210 can have can be based on the processing capabilities of the host system 200 and the core 205 and other circular queues 210 in the core. Although each circular queue 210 is shown as having eight (8) entries 250, in other instances, the circular queue 210 can have more or fewer than eight (8) entries 250. The core 205 can configure the size of each entry 250 based on the size of the largest command or message being transferred from the host system 200 to the memory system. Each circular queue 210 can operate independently of another circular queue 210. For example, circular queue 210-a can operate independently of circular queue 210-b and circular queue 210-d. In such instances, each core 205 can perform tasks simultaneously (or in parallel) with another core 205. For example, the first core 205-a can input commands into circular queue 210-a while core 205-d inputs commands into circular queue 210-d. Thus, the host system 200 can perform multiple tasks simultaneously and increase the overall processing speed of the host system 200.

[0042] Additionally, each circular queue 210 may have a head pointer 215 and a tail pointer 220 (e.g., doorbell). The head pointer 215 may be configured to indicate an entry 250 in the circular queue 210-a that is available for storing a command or message. In some instances, the head pointer 215 may be configured to increment from the first entry 250 to the second entry 250 when a command is stored at the first entry 250. For example, when the entry indicated by the head pointer 215 is written by the first core 205-s, the head pointer 215 may increment to the entry 250-a. The tail pointer 220 may be configured to indicate an entry 250 in the circular queue 210-a that is available for removal (e.g., erasure). In some instances, when the command stored at the first entry 250 is executed (e.g., consumed), the tail pointer 220 may increment from the first entry 250 to the second entry 250. For example, after the current entry 250 pointed to by the tail pointer 220 is removed, the tail pointer 220 may shift left. When the head pointer 215 and the tail pointer 220 are in the same position, the core 205-a may determine that the circular queue 210-a is empty (e.g., contains no entries). When the head pointer 215 exceeds the number of entries 250, the head pointer 215 may wrap back to the start of the position of the circular queue 210-a. For example, a wrap condition may occur when the head pointer 215 exceeds the number of entries 250 and may then be reset and indicate the first entry 250 (e.g., starting point) of the circular queue 210-a. In some instances, the circular queue 210 is a first-in, first-out circular queue. For example, the first entry 250 written to the circular queue 210-a may be the first entry accessed by the host system controller 225, the second entry 250 written to the circular queue 210-a may be the second entry accessed by the host system controller 225, and so on.

[0043] The second set of circular queues 230 can be configured to act as a mechanism for receiving responses and messages between the host system 200 and the memory system. For example, the circular queue 230 can store responses received from the memory system. That is, the host system controller 225 can write a response from the memory system to the circular queue 230-a, where the response is based on a command sent from the circular queue 210-a. The circular queue 230 can store multiple responses. For example, the shaded portion can represent the stored responses. The size of each entry in the circular queue 230 can be based on the maximum size of the responses that can be received from the memory system. Each circular queue 230 can have more or fewer than eight (8) queues. For example, although each circular queue 230 is shown with eight (8) entries, in other instances, the circular queue 230 can have more or fewer than eight (8) entries. The circular queues 230 can also operate independently of each other. For example, the circular queue 230-a can receive a first response, and the circular queue 230-b can simultaneously receive a second response. In some instances, a single circular queue 230 can receive responses associated with multiple circular queues 210. For example, the circular queue 230-b can receive a response associated with a command from the circular queue 210-b and a response associated with a command from the circular queue 210-c, even when the circular queue 230-b is on a different core.

[0044] Additionally, each circular queue 230 can have a head pointer 260 and a tail pointer 265. The head pointer 260 can indicate the entry in the circular queue 230-a that is available to write a response into. In some instances, the head pointer 260 can increment from the first entry to the second entry based on a response being written to the first entry and the second entry being available to write a second response. The tail pointer 265 can indicate the entry in the circular queue 230-a that can be removed. In such instances, the core 205-a can remove the entry to process the response from the memory system, for example, to determine that the memory system has properly executed the command associated with the response. The tail pointer 265 can increment from the first entry to the second entry, where the second entry will be removed based on the first entry being removed from the circular queue 230-a. In some instances, the circular queue 230 is a first-in-first-out circular queue. For example, the first entry 250 written to the circular queue 230-a can be the first command received from the memory system, the second entry 250 written to the circular queue 230-a can be the second command sent to the memory system, and so on.

[0045] The host system controller 225 (e.g., host controller interface) can be configured to transfer commands and responses between the host system 200 and the memory system. For example, the host system controller 225 can be configured to read entries from the first set of circular queues 210. The host system controller 225 can then package commands suitable for transmission to the memory system, e.g., commands that the host system controller 225 can translate between the host system 200 software and the memory system. For example, the host system controller 225 can extract the data indicated in the entry and generate a second command to be transmitted to the memory system containing the information. Using the host system controller 225 (e.g., as part of the host controller interface) with the ability to translate between commands from the host and commands for the memory system can allow host systems to work together even if the host systems may use different command protocols. The host system controller 225 can be configured to communicate between the host system 200 software and the memory system, which is coupled to the host system 200. The host system controller 225 can also be configured to receive responses from the memory system after the memory system executes a command. In some instances, the host system controller 225 can be configured to write the responses to the second set of circular queues 230.

[0046] The host system controller 225 can also include a first set of registers 240 and a second set of registers 245. In some instances, each register 240 in the first set of registers 240 can correspond to one of the circular queues 210 in the first set of circular queues 210. For example, register 240-a can correspond to circular queue 210-a. In some instances, register 240-a can identify an entry 250 in circular queue 210-a from which the host system controller 225 can read. In other instances, each register 245 in the second set of registers 245 can correspond to one of the circular queues 230 in the second set of circular queues 230. For example, register 245-a can correspond to circular queue 230-a. In some instances, register 245-a can identify an entry in circular queue 210-a that can be used for removal. That is, the host system controller 225 can use the first set of registers 240 to determine when to read from the first set of circular queues 210, and can use the second set of registers 245 to determine when to remove entries from the second set of circular queues 230.

[0047] Figure 3 An example of a process flow 300 that supports queue configurations for a host interface according to examples disclosed herein is shown. The process flow 300 can be executed by processing logic, which can include hardware (e.g., a processing system, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some instances, the process flow 300 can be performed by reference toFigure 1 The described system (e.g., system 100) performs. For example, process flow 300 may be performed by host system 305 (e.g., refer to Figure 1 the host system 105 described) and memory system 310 (e.g., refer to Figure 2 the memory system 110 described). In some instances, memory system 310 may execute a set of code to control the functional elements of the memory system to perform the functions described below. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments are used as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various instances. Thus, not all processes are required in every instance. Other process flows are possible. Figure 3 System 100 may be shown to utilize multiple circular queues (e.g., a first set of circular queues 210 and a second set of circular queues 230) to transfer commands and responses between host system 305 and memory system 310.

[0048] At 315, the circular queues may be configured. For example, host system 305 may configure multiple circular queues across multiple cores (e.g., refer to Figure 2 the cores 205 described). The circular queues may be configured by a host system controller (e.g., refer to Figure 2 the host system controller 225 described). In some instances, host system 305 may configure the circular queues dynamically. That is, host system 305 may configure the circular queues based on the needs of host system 305 or one of the multiple cores. In some instances, host system 305 may configure the circular queues based on the number of entries (e.g., refer to Figure 2 the entries 250 described) contained in a single circular queue or based on the size of the entries. That is, host system 305 may configure the circular queues based on the maximum size of the commands or responses stored in the circular queues. In some instances, host system 305 may also configure the circular queues based on the number of commands that memory system 310 can receive simultaneously.

[0049] At 320, a first entry may be added to the first circular queue. For example, the host system 305 adds the first entry at the first circular queue among a plurality of circular queues. The first entry may be added by the core of the host system 305. In some instances, the host software of the host system 305 may determine a command to be transmitted to the memory system 310. In such instances, the host system 305 or the core may add the command as the first entry of the first circular queue, such as writing the command to the first entry. In some cases, the host system 305 may also add the first entry at the second circular queue (e.g., storing the command). That is, the host system 305 may store commands at multiple circular queues simultaneously, thereby shortening the processing time. In some instances, the first circular queue may be in the first core, and the second circular queue may be in the second core. In some instances, the command stored at the first entry may include a command pointer (command PTR), a response offset, a response size, a total size, an identification code (ID), and an overall status. Additionally, the command may include the location of data associated with the command and the location to write the response to the command. That is, the command may indicate a PRDT, for example, where the data is stored in a scatter list in the host system 305. In some instances, the command may indicate a data buffer in the host system 305 that stores data associated with the command. The command may also indicate a response UFS protocol information unit (UPIU), for example, the location to store the response received from the memory system 310. The UPIU may also indicate the nature of the response, such as the type of response that the host system 305 expects to receive from the memory system 310. In some instances, the host system 305 may store the command at the first entry based on a first indicator (e.g., the head pointer 215 described with reference to Figure 2 indicating that the entry is available for storing the command. After the host system 305 stores the first command at the first entry, the indicator may be incremented to the second entry. For example, the first indicator may then indicate that the second entry is available for storing a second command from the host system 305.

[0050] At 325, the first entry can be accessed. For example, the host system 305 can access the first entry of the first circular queue. The host system controller can access the first entry based on a register (e.g., the first set of registers 240) indicating that the first entry is accessible. In some instances, the host system controller can access the first entry and generate a second command for the memory system 310. That is, the host system controller can convert the command stored by the host system 305 software at the first entry into a second command that can be received by the memory system 310. For example, the host system controller can access data at the location indicated by the command stored at the first entry, e.g., the data that the host system controller can use to generate the second command. For example, the host system controller can access the first data buffer in the host system 305 to extract data associated with the command based on the data location. The host system controller can also record the location where the response from the memory system 310 will be stored after the memory system 310 executes the second command. After obtaining the data and recording the location to store the response, the host system controller can package the command to generate a second command for the memory system 310.

[0051] At 330, the second command can be sent. For example, the host system 305 can transmit the second command to the memory system 310. In some instances, the second command is sent by the host system controller. In some instances, the host system controller can also transmit other commands (e.g., a third command) to the memory system in parallel with the second command from the second circular queue.

[0052] At 335, the second command can be executed. For example, the memory system 310 can execute the second command received from the memory system controller. In some instances, the second command can be a read, write, or refresh command (e.g., an access command). After executing the second command, the memory system 310 can generate a response to transmit to the host system 305.

[0053] At 340, the response can be received. For example, the host system 305 can receive the response from the memory system 310. In some instances, the response can be received at the host system controller.

[0054] At 345, the response can be written to the third circular queue. For example, the host system 305 can write the first entry to the third circular queue (e.g., one of the second set of circular queues 230). The host system controller can write the response to the third circular queue. In some instances, the host system 305 can include a completion circular queue, e.g., a queue that keeps track of each response received from the memory system 310. The third circular queue can be an instance of the completion circular queue. The host system controller can write the information associated with the response to the first entry of the third queue after receiving the response from the memory system 310. In some instances, the host system controller can write the response to the first entry of the third circular queue based on a second indicator (e.g., the head pointer 260 described with reference to Figure 2 After writing the first entry, the host system controller can increment the indicator to the second entry to indicate that the second entry is available for storing the second response from the memory system 310. In other instances, the host system controller can write the information to the first entry of the third circular queue based on the location indicated by the command (e.g., the response UPIU).

[0055] At 350, the first entry can be removed. For example, the host system 305 can remove the first entry from the first circular queue. In some instances, after the response is written to the third circular queue, the host system controller can remove the first entry (e.g., erase the first entry). That is, the host system controller can remove the first entry after the command in the first entry has been executed by the memory system 310. In some instances, the host system controller can remove the first entry based on a second indicator (e.g., the tail pointer 220 described with reference to Figure 2 After removing the first entry, the host system controller can increment the second indicator to the second entry, e.g., the host system controller can indicate that the second entry containing the second command has been sent and is waiting for a response before being removed from the queue. In some instances, the host system controller can also determine that the first queue is empty (e.g., contains no entries) based on both the first indicator and the second indicator indicating the same location.

[0056] At 355, the response at the third circular queue can be removed. For example, the host system 305 can remove the response from the memory system 310 from the third circular queue. In some instances, the host system 305 or the core of the host system 305 can remove the response after processing the response from the memory system 310. That is, the host system 305 can extract the information associated with the response written to the third queue, determine that the memory system 310 has properly executed the response, and accordingly remove the response from the third circular queue. In some instances, the host system 305 can be based on the second indicator at the third circular queue (e.g., the reference to Figure 2The described tail pointer 265) removes the response. After removing the response, the host system 305 may increment the second indicator from the first entry storing the response to the second entry storing the second response. In some instances, the host system 305 may continue to transmit other commands and receive other responses using the processes described herein. For example, the host system 305 may write a second command to the second entry of the first circular queue based on the second entry being indicated by the first indicator. The host system 305 may then increment the first indicator to the third entry at the first circular queue. The host system controller may access the second entry, package the third command stored in the second entry to generate a fourth command to be transmitted to the memory system 310. The host system controller may then receive the second response and store the second response at the second entry of the third circular queue based on the first indicator of the third circular queue. The host system controller may then increment the first indicator to the third entry of the third circular queue. The host system controller may then remove the second entry from the first circular queue and increment the second indicator of the first circular queue to the third entry. The host system 305 may process the second response and remove the second response from the third circular queue and then increment the second indicator of the third circular queue to the third entry of the third circular queue, etc. In some instances, the host system may perform the processes described for simultaneously utilizing the second and fourth circular queues at the second core.

[0057] Figure 4 FIG. 400 is a block diagram showing a host system controller 420 supporting a queue configuration for a host interface according to an example disclosed herein. The host system controller 420 may be an example of an aspect of the host system controller described with reference Figures 1 to 3 The host system controller 420 or its various components may be examples of components for performing various aspects of the queue configuration for the host interface described herein. For example, the host system controller 420 may include an access component 425, a generator component 430, a transmission component 435, a receiving component 440, a queue component 445, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0058] The access component 425 can be configured to or otherwise support components for: accessing the first entry of the first circular queue at the host system, where the first entry indicates a first command for the memory system and the location of data associated with the first command. In some instances, the access component 425 can be configured to or otherwise support components for: accessing the first entry of the first circular queue at the host system to issue a third command at least in part based on incrementing from the first entry to a second entry based on an indicator. In some cases, the access component 425 can be configured to or otherwise support components for: accessing the location of data associated with the first command, where generating a second command is at least in part based on accessing the location of data associated with the first command.

[0059] The generator component 430 can be configured to or otherwise support components for: generating a second command for the memory system at least in part based on data associated with the first command stored in the first circular queue and the first entry of the first circular queue.

[0060] The transmission component 435 can be configured to or otherwise support components for: transmitting the second command to the memory system at least in part based on generating the second command.

[0061] The receiving component 440 can be configured to or otherwise support components for: receiving, from the memory system, a response indicating completion of the second command at least in part based on transmitting the second command.

[0062] The queue component 445 can be configured to or otherwise support components for: removing the first entry from the first circular queue at least in part based on receiving, from the memory system, a response indicating completion of the second command.

[0063] In some instances, the queue component 445 can be configured to or otherwise support components for: writing information to the second entry of a second circular queue in the host system at least in part based on receiving a response from the memory system, where removing the first entry from the first circular queue is at least in part based on writing to the second entry of the second circular queue. In some instances, the queue component 445 can determine that the second location will store the response based on the first circular queue indicating that the second location will store the response from the memory system. In some cases, the queue component 445 can be configured to or otherwise support components for: incrementing an indicator from the first entry to a second entry in the first circular queue at least in part based on receiving a response from the memory system, where the indicator is configured to indicate an entry in the first circular queue to be removed by the host system, and where removing the first entry from the first circular queue is at least in part based on incrementing the indicator.

[0064] In some cases, the queue component 445 may be configured or otherwise support components for: identifying a second entry of a first circular queue for writing a second command to a memory system at least in part based on an indicator associated with the first circular queue, the indicator configured to indicate an entry in the first circular queue configured to receive information from a host system. In some cases, the queue component 445 may be configured or otherwise support components for: writing second data associated with the second command to the second entry of the first circular queue at the host system at least in part based on identifying the second entry using the indicator. In some instances, the queue component 445 may be configured or otherwise support components for: incrementing the indicator from the second entry of the first circular queue to a third entry to indicate that the third entry is available for the host system to write, at least in part based on writing the second data to the second entry.

[0065] In some instances, the queue component 445 may be configured or otherwise support components for: configuring a first circular queue of a first processor at least in part based on a quantity parameter and an entry size parameter associated with an entry of the first circular queue, wherein accessing the first circular queue is at least in part based on configuring the first circular queue. In some cases, the queue component 445 may be configured or otherwise support components for: determining that the first circular queue is empty of data at least in part based on a first indicator associated with the first circular queue and a second indicator associated with the first circular queue pointing to the same location, the first indicator configured to indicate an entry in the first circular queue available for the host system to write, and the second indicator configured to indicate an entry in the first circular queue to be removed by the host system.

[0066] In some instances, the queue component 445 may configure a first circular queue to store commands issued by a first processor core of a host system. In some cases, the queue component 445 may configure a second circular queue to store commands issued by a second processor core of the host system. In some instances, the queue component 445 is configured to store a command in the second circular queue while the host system is configured to store a first command in the first circular queue. In some cases, the queue component 445 may configure the first circular queue to indicate an order sequence for accessing multiple entries of the first circular queue, the multiple entries including a first entry.

[0067] Figure 5 A flowchart illustrating a method 500 for supporting queue configuration for a host interface according to an example disclosed herein is shown. Operations of method 500 may be implemented by the host system controller or its components described herein. For example, operations of method 500 may be implemented by referring to Figures 1 - 4The described host system controller performs. In some instances, the host system controller may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the host system controller may use dedicated hardware to perform aspects of the described functions.

[0068] At 505, the method may include accessing, at a host system, a first entry of a first circular queue, the first entry indicating a first command for a memory system and a location of data associated with the first command. The operation of 505 may be performed in accordance with the examples disclosed herein. In some instances, aspects of the operation of 505 may be performed by the access component 425 described with reference to Figure 4 the access component 425 described with reference to

[0069] At 510, the method may include generating, at least in part based on data associated with the first command stored in the first circular queue and the first entry of the first circular queue, a second command for the memory system. The operation of 510 may be performed in accordance with the examples disclosed herein. In some instances, aspects of the operation of 510 may be performed by the generator component 430 described with reference to Figure 4 the generator component 430 described with reference to

[0070] At 515, the method may include transmitting, at least in part based on generating the second command, the second command to the memory system. The operation of 515 may be performed in accordance with the examples disclosed herein. In some instances, aspects of the operation of 515 may be performed by the transmission component 435 described with reference to Figure 4 the transmission component 435 described with reference to

[0071] At 520, the method may include receiving, at least in part based on transmitting the second command, a response from the memory system indicating completion of the second command. The operation of 520 may be performed in accordance with the examples disclosed herein. In some instances, aspects of the operation of 520 may be performed by the receiving component 440 described with reference to Figure 4 the receiving component 440 described with reference to

[0072] At 525, the method may include removing, at least in part based on receiving from the memory system a response indicating completion of the second command, the first entry from the first circular queue. The operation of 525 may be performed in accordance with the examples disclosed herein. In some instances, aspects of the operation of 525 may be performed by the queue component 445 described with reference to Figure 4 the queue component 445 described with reference to

[0073] In some instances, the devices described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: accessing a first entry of a first circular queue at a host system, the first entry indicating a first command for a memory system and a location of data associated with the first command; generating a second command for the memory system at least in part based on the data associated with the first command stored in the first circular queue and the first entry of the first circular queue; transmitting the second command to the memory system at least in part based on generating the second command; receiving, from the memory system, a response indicating completion of the second command at least in part based on transmitting the second command; and removing the first entry from the first circular queue at least in part based on receiving, from the memory system, the response indicating completion of the second command.

[0074] Some cases of method 500 and the device described herein may further include operations, features, circuitry, logic, components, or instructions for: writing information to a second entry of a second circular queue in the host system at least in part based on receiving the response from the memory system, wherein removing the first entry from the first circular queue may be at least in part based on writing to the second entry of the second circular queue.

[0075] In some cases of method 500 and the device described herein, the first circular queue indicates that a second location will store a response from the memory system.

[0076] Some instances of method 500 and the device described herein may further include operations, features, circuitry, logic, components, or instructions for: incrementing an indicator from the first entry to a second entry in the first circular queue at least in part based on receiving the response from the memory system, the indicator configured to indicate an entry in the first circular queue to be removed by the host system, wherein removing the first entry from the first circular queue may be at least in part based on incrementing the indicator.

[0077] In some cases of method 500 and the device described herein, accessing a first entry of the first circular queue at the host system to issue a third command at least in part based on the indicator incrementing from the first entry to the second entry.

[0078] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: identifying, at least in part based on an indicator associated with a first circular queue, a second entry in the first circular queue into which a second command for a memory system is to be written, the indicator being configured to indicate an entry in the first circular queue configured to receive information from a host system; and writing, at least in part based on the identification of the second entry using the indicator, second data associated with the second command to the second entry of the first circular queue at the host system.

[0079] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: incrementing the indicator from the second entry of the first circular queue to a third entry at least in part based on writing the second data to the second entry, to indicate that the third entry is available for the host system to write.

[0080] Some cases of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: accessing a location of data associated with a first command, wherein generating the second command may be at least in part based on accessing the location of data associated with the first command.

[0081] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: configuring a first circular queue for a first processor at least in part based on a quantity parameter and an entry size parameter associated with an entry of the first circular queue, wherein accessing the first circular queue may be at least in part based on configuring the first circular queue.

[0082] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: determining that the first circular queue may be data - free at least in part based on a first indicator associated with the first circular queue and a second indicator associated with the first circular queue pointing to the same location, the first indicator being configured to indicate an entry in the first circular queue available for the host system to write, and the second indicator being configured to indicate an entry in the first circular queue to be removed by the host system.

[0083] In some cases of the method 500 and apparatus described herein, the first circular queue may be configured to store commands issued by a first processor core of a host system, and the second circular queue may be configured to store commands issued by a second processor core of the host system.

[0084] In some examples of the method 500 and apparatus described herein, the host system may be configured to store commands in a second circular queue while the host system may be configured to store a first command in a first circular queue.

[0085] In some examples of the method 500 and apparatus described herein, the first circular queue indicates an order sequence for accessing a plurality of entries of the first circular queue, the plurality of entries including a first entry.

[0086] Note that the above method describes possible implementations, and operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, two or more portions from the method may be combined.

[0087] An apparatus is described. The apparatus may include: a host system including a first circular queue having a first entry, the first entry indicating a location of a first command for a memory system and data associated with the first command; and a controller coupled to the host system and configured to: access the first entry of the first circular queue; generate, at least in part based on the data associated with the first command stored in the first circular queue and the first entry of the first circular queue, a second command for the memory system; transmit the second command to the memory system at least in part based on generating the second command; receive a response indicating completion of the second command from the memory system at least in part based on transmitting the second command; and remove the first entry from the first circular queue at least in part based on receiving the response from the memory system.

[0088] In some examples of the apparatus, the controller may further be configured to write information to a second entry of a second circular queue in the host system at least in part based on receiving the response from the memory system, wherein the controller may be configured to remove the first entry from the first circular queue at least in part based on writing to the second entry of the second circular queue.

[0089] In some examples of the apparatus, the controller may further be configured to increment an indicator from the first entry to a second entry in the first circular queue at least in part based on receiving the response from the memory system, the indicator configured to indicate an entry in the first circular queue to be removed by the host system, wherein removing the first entry from the first circular queue may be at least in part based on incrementing the indicator.

[0090] In some examples of the apparatus, the controller may further be configured to access the first entry of the first circular queue to issue a third command at least in part based on incrementing the indicator from the first entry to the second entry.

[0091] In some instances of the device, the controller may be further configured to identify, at least in part, a second entry in the first circular queue into which a second command for the memory system is to be written, based on an indicator associated with the first circular queue, the indicator being configured to indicate an entry in the first circular queue that is configured to receive information from the host system; and write second data associated with the second command to the second entry of the first circular queue at the host system, at least in part, based on identifying the second entry using the indicator.

[0092] In some cases of the device, the controller may be further configured to increment the indicator from the second entry of the first circular queue to a third entry, at least in part, based on writing the second data to the second entry, to indicate that the third entry is available for the host system to write to.

[0093] In some examples of the device, the controller may be further configured to access a location of data associated with a first command, wherein the controller may be configured to generate a second command, at least in part, based on accessing the location of data associated with the first command.

[0094] In some instances of the device, the controller may be further configured to determine that the first circular queue may be data - free, at least in part, based on a first indicator associated with the first circular queue and a second indicator associated with the first circular queue pointing to the same location, the first indicator being configured to indicate an entry in the first circular queue that is available for the host system to write to, and the second indicator being configured to indicate an entry in the first circular queue that is to be removed by the host system.

[0095] In some cases of the device, the controller may be further configured to configure a first circular queue of a first processor, at least in part, based on a quantity parameter and an entry - size parameter associated with an entry of the first circular queue, wherein accessing the first circular queue may be at least in part based on configuring the first circular queue.

[0096] In some cases of the device, the first circular queue may be configured to store commands issued by a first processor core of the host system, and the second circular queue may be configured to store commands issued by a second processor core of the host system.

[0097] In some instances of the device, the host system may be configured to store a command in the second circular queue while the host system may be configured to store a first command in the first circular queue.

[0098] In some cases of the device, the first circular queue may be configured to indicate an order sequence for accessing a plurality of entries of the first circular queue, the plurality of entries including the first entry.

[0099] Any one of a variety of different technologies and techniques can be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, a signal can represent a bus of signals, where the bus can have various bit widths.

[0100] The terms "electronically communicate", "electrically contact", "connect", and "couple" can refer to the relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating with each other (or in electrical contact with each other or connected to each other or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between components that are electronically communicating with each other (or in electrical contact with each other or connected to each other or coupled to each other) can be an open circuit or a closed circuit. The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components such as switches or transistors can be used, for example, to interrupt the flow of signals between the connected components for a period of time.

[0101] The term "couple" refers to the condition of changing from an open-circuit relationship between components, in which a signal cannot currently be transmitted between the components through a conductive path, to a closed-circuit relationship between the components, in which a signal can be transmitted between the components through the conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components through a conductive path that previously did not allow the signal to flow.

[0102] The term "isolate" refers to the relationship between components in which a signal cannot currently flow between the components. Components are isolated from each other if there is an open circuit between them. For example, when a switch is open, the components separated by the switch located between two components are isolated from each other. When a controller isolates two components, the controller implements a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0103] The devices (including memory arrays) discussed in this document can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemicals including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

[0104] The switching components or transistors discussed in this document can represent field-effect transistors (FETs), and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components by a conductive material such as metal. The source and the drain can be conductive and can include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and the drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET respectively can make the channel conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned off" or "deactivated".

[0105] The example configurations are described in the specific embodiments presented in conjunction with the accompanying drawings and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "preferred over" or "superior to" other instances. The specific embodiments include specific details to provide an understanding of the described technologies. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0106] In the drawings, like components or features can have the same reference numeral. Additionally, various components of the same type can be distinguished by adding a dash followed by a second numeral that differentiates among the like components after the reference numeral. If only the first reference numeral is used in the specification, the description applies to any one of the like components having the same first reference numeral, regardless of the second reference numeral.

[0107] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted through a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the above functions can be implemented using software, hardware, firmware, hardwiring, or any combination of these executed by a processor. The features implementing the functions can also be physically located in various positions, including being distributed such that parts of the functions are implemented at different physical locations.

[0108] For example, the various illustrative blocks and modules described in connection with the present disclosure can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor; however, in the alternative, the processor can be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0109] As used herein, including in the claims, the "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed to refer to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" can be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0110] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium including any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, the non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0111] The description provided herein enables a person of ordinary skill in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device, which comprises: A host system, which includes a first circular queue configured to store commands issued by a first processor core of the host system and a second circular queue configured to store commands issued by a second processor core of the host system. The first circular queue has a first entry, and the first entry indicates the position of a first command for the memory system and data associated with the first command, where the first command is associated with a first protocol of the host system; and A host system controller, which is coupled to the host system and configured to: Access the first entry of the first circular queue; Generate a second command associated with a second protocol of the memory system, where the second command includes the data associated with the first command stored in the first circular queue and the first entry of the first circular queue; Transmit the second command to the memory system at least partially based on generating the second command for execution of the second command at the memory system; Receive a response indicating completion of the second command from the memory system at least partially based on execution of the second command at the memory system; and Remove the first entry from the first circular queue at least partially based on receiving the response from the memory system.

2. The device according to claim 1, where the host system controller is further configured to: Write information to a second entry of a third circular queue in the host system at least partially based on receiving the response from the memory system, where the host system controller is configured to remove the first entry from the first circular queue at least partially based on writing the second entry to the third circular queue.

3. The device according to claim 1, where the host system controller is further configured to: Increment an indicator from the first entry to a second entry in the first circular queue at least partially based on receiving the response from the memory system. The indicator is configured to indicate an entry in the first circular queue to be removed by the host system, and removing the first entry from the first circular queue is at least partially based on incrementing the indicator.

4. The device according to claim 3, where the host system controller is further configured to: Access the first entry of the first circular queue to issue a third command at least partially based on the indicator incrementing from the first entry to the second entry.

5. The device according to claim 1, where the host system controller is further configured to: Identify a second entry in the first circular queue to which the second command for the memory system will be written at least partially based on an indicator associated with the first circular queue. The indicator is configured to indicate an entry in the first circular queue configured to receive information from the host system; and Writing second data associated with the second command to the second entry of the first circular queue at the host system, at least in part based on identifying the second entry using the indicator.

6. The apparatus according to claim 5, wherein the host system controller is further configured to: Increment the indicator from the second entry of the first circular queue to a third entry, at least in part based on writing the second data to the second entry, to indicate that the third entry is available for writing by the host system.

7. The apparatus according to claim 1, wherein the host system controller is further configured to: Access the location of the data associated with the first command, wherein the host system controller is configured to generate the second command at least in part based on accessing the location of the data associated with the first command.

8. The apparatus according to claim 1, wherein the host system controller is further configured to: Determine that the first circular queue is data-free, at least in part based on a first indicator associated with the first circular queue and a second indicator associated with the first circular queue pointing to the same location, the first indicator configured to indicate that an entry in the first circular queue is available for writing by the host system, and the second indicator configured to indicate an entry in the first circular queue to be removed by the host system.

9. The apparatus according to claim 1, wherein the host system controller is further configured to: Configure the first circular queue for the first processor core, at least in part based on a quantity parameter and an entry size parameter associated with an entry of the first circular queue, wherein accessing the first circular queue is at least in part based on configuring the first circular queue.

10. The apparatus according to claim 1, wherein while the host system is configured to store the first command in the first circular queue, the host system is configured to store commands in the second circular queue.

11. The apparatus according to claim 1, wherein the first circular queue is configured to: Indicate an order sequence for accessing a plurality of entries of the first circular queue, the plurality of entries including the first entry.

12. A method performed by a host system, the method comprising: Accessing a first entry of a first circular queue at the host system, the first entry indicating a first command for a memory system and a location of data associated with the first command, wherein the first command is associated with a first protocol of the host system, wherein the first circular queue is configured to store commands issued by a first processor core of the host system, and wherein a second circular queue is configured to store commands issued by a second processor core of the host system; Generating a second command associated with a second protocol of the memory system, the second command including the data associated with the first command stored in the first circular queue and the first entry of the first circular queue; Transmit the second command to the memory system, at least in part based on generating the second command, for execution of the second command at the memory system; Receive, from the memory system, a response indicating completion of the second command, at least in part based on execution of the second command at the memory system; and Remove the first entry from the first circular queue, at least in part based on receiving, from the memory system, the response indicating completion of the second command.

13. The method of claim 12, further comprising: Write information to a second entry of a third circular queue in the host system, at least in part based on receiving the response from the memory system, wherein removing the first entry from the first circular queue is at least in part based on writing the second entry to the third circular queue.

14. The method of claim 12, wherein the first circular queue indicates a second location for storing the response from the memory system.

15. The method of claim 12, further comprising: Increment an indicator from the first entry to a second entry in the first circular queue, at least in part based on receiving the response from the memory system, the indicator configured to indicate an entry in the first circular queue to be removed by the host system, wherein removing the first entry from the first circular queue is at least in part based on incrementing the indicator.

16. The method of claim 15, further comprising: Access the first entry of the first circular queue at the host system to issue a third command, at least in part based on the indicator incrementing from the first entry to the second entry.

17. The method of claim 12, further comprising: Identify a second entry of the first circular queue to write the second command for the memory system, at least in part based on an indicator associated with the first circular queue, the indicator configured to indicate an entry in the first circular queue configured to receive information from the host system; and Write second data associated with the second command to the second entry of the first circular queue at the host system, at least in part based on identifying the second entry using the indicator.

18. The method of claim 17, further comprising: Increment the indicator from the second entry to a third entry of the first circular queue, at least in part based on writing the second data to the second entry, to indicate that the third entry is available for writing by the host system.

19. The method of claim 12, further comprising: Access the location of the data associated with the first command, wherein generating the second command is at least in part based on accessing the location of the data associated with the first command.

20. The method of claim 12, further comprising: Configure the first circular queue for the first processor core at least in part based on a quantity parameter and an entry size parameter associated with an entry of the first circular queue, wherein accessing the first circular queue is at least in part based on configuring the first circular queue.

21. The method according to claim 12, further comprising: Determine that the first circular queue is data-free at least in part based on a first indicator associated with the first circular queue and a second indicator associated with the first circular queue pointing to the same location, the first indicator configured to indicate an entry in the first circular queue that can be used for writing by the host system, and the second indicator configured to indicate an entry in the first circular queue to be removed by the host system.

22. The method according to claim 12, wherein the first circular queue indicates an order sequence of a plurality of entries accessing the first circular queue, the plurality of entries including the first entry.

23. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of a host system controller of a host system, cause the host system controller to: Access a first entry of a first circular queue at the host system, the first entry indicating a location of a first command for a memory system and data associated with the first command, wherein the first command is associated with a first protocol of the host system, wherein the first circular queue is configured to store commands issued by a first processor core of the host system, and wherein a second circular queue is configured to store commands issued by a second processor core of the host system; Generate a second command associated with a second protocol of the memory system, the second command including the data associated with the first command stored in the first circular queue and the first entry of the first circular queue; Transmit the second command to the memory system at least in part based on generating the second command for execution of the second command at the memory system; Receive, at least in part based on execution of the second command at the memory system, a response indicating completion of the second command from the memory system; and Remove the first entry from the first circular queue at least in part based on receiving the response indicating completion of the second command from the memory system.

24. The non-transitory computer-readable medium according to claim 23, wherein the instructions, when executed by the processor of the host system controller of the host system, further cause the host system controller to write information to a second entry of a third circular queue in the host system at least in part based on receiving the response from the memory system, wherein the processor of the host system controller of the host system is configured to remove the first entry from the first circular queue at least in part based on writing the second entry to the third circular queue.

Images