Pixel driving circuit and pixel driving method, display panel

Abstract

A pixel driving circuit, a pixel driving method, and a display panel that simplify pixel driving methods are disclosed. The pixel driving circuit includes: a driving transistor (M3); a storage capacitor (Cst) connected to a first node (N1) and a second node (N2); a data writing unit (110) for outputting a data voltage (Vdata) to the second node (N2) in response to a first scan signal (Gate_P); a light emission control unit (130) for electrically connecting a third node (N3) and a fourth node (N4) in response to a light emission control signal (EM); a first reset unit (140) for outputting a reference voltage (Vref) to the second node (N2) in response to the light emission control signal (EM) or a first reset signal (Re_P); and a second reset unit (150) for outputting an initialization voltage (Vinit) to the first node (N1) in response to a second reset signal (Re_N).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a pixel driving circuit and pixel driving method, and a display panel. Background Technology

[0002] Electroluminescent devices, such as organic light-emitting diodes (OLEDs), are widely used in the display field. Display devices can incorporate pixel driving circuits that drive the electroluminescent devices to emit light. These pixel driving circuits typically include driving transistors to generate driving current. To improve display quality, some pixel driving circuits can compensate for the threshold voltage of the driving transistors, overcoming display differences caused by variations in the threshold voltages of different driving transistors.

[0003] However, in the prior art, the pixel driving circuit usually first compensates the threshold voltage of the driving transistor and then writes the data voltage to the pixel driving circuit; this makes the driving process of the pixel driving circuit more complicated. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a pixel driving circuit, a pixel driving method, and a display panel, thereby simplifying the pixel driving method.

[0005] According to one aspect of this disclosure, a pixel driving circuit is provided, comprising:

[0006] Drive the transistor to connect the first node and the third node;

[0007] A storage capacitor is connected to the first node and the second node;

[0008] A data writing unit, connected to the second node, is used to output a data voltage to the second node in response to a first scan signal;

[0009] A light-emitting control unit, connected to the third node and the fourth node, is used to electrically connect the third node and the fourth node in response to a light-emitting control signal;

[0010] A first reset unit, connected to the second node, is used to output a reference voltage to the second node in response to the light emission control signal or the first reset signal;

[0011] The second reset unit is connected to the first node and is used to output an initialization voltage to the first node in response to the second reset signal.

[0012] According to one embodiment of this disclosure, the pixel driving circuit further includes:

[0013] The third reset unit, connected to the fourth node, is used to output the initialization voltage to the fourth node in response to the first reset signal.

[0014] According to one embodiment of this disclosure, the pixel driving circuit further includes a threshold compensation unit connected to the first node and the third node, configured to electrically connect the first node and the third node in response to a second scanning signal, wherein the threshold compensation unit includes:

[0015] The second transistor includes a first electrode, a second electrode, and a gate. The first electrode is connected to the third node, the second electrode is connected to the first node, and the gate is used to load the second scan signal.

[0016] The second reset unit includes:

[0017] The fourth transistor includes a first electrode, a second electrode, and a gate. The first electrode is used to apply the initialization voltage, the second electrode is connected to the first node, and the gate is used to apply the second reset signal.

[0018] The active layers of both the second transistor and the fourth transistor are made of metal oxide semiconductor material.

[0019] According to one embodiment of the present disclosure, the gate of the second transistor includes a first gate and a second gate, both used for loading the second scan signal, and the active layer of the second transistor includes a channel region; the first gate, the channel region and the second gate of the second transistor are stacked sequentially.

[0020] The gate of the fourth transistor includes a first gate and a second gate, both used for loading the second scan signal, and the active layer of the fourth transistor includes a channel region; the first gate, the channel region and the second gate of the fourth transistor are stacked sequentially.

[0021] According to one embodiment of this disclosure, the pixel driving circuit is disposed on one side of the substrate.

[0022] The first gate of the second transistor is located on the side of the channel region of the second transistor closer to the substrate; the orthographic projection of the second gate of the second transistor on the substrate is located within the orthographic projection of the first gate of the second transistor on the substrate.

[0023] The first gate of the fourth transistor is located on the side of the channel region of the fourth transistor close to the substrate; the orthographic projection of the second gate of the fourth transistor on the substrate is located within the orthographic projection of the first gate of the fourth transistor on the substrate.

[0024] According to one embodiment of this disclosure, the pixel driving circuit is disposed on one side of the substrate.

[0025] The storage capacitor includes a first electrode plate, a second electrode plate, a third electrode plate, and a fourth electrode plate stacked sequentially on one side of the substrate, with an insulating medium sandwiched between any two adjacent electrode plates; the first electrode plate and the third electrode plate are both electrically connected to the first node; the second electrode plate and the fourth electrode plate are both connected to the second node.

[0026] According to one embodiment of the present disclosure, the pixel driving circuit is applied to a display panel, the display panel including the substrate.

[0027] The display panel further includes a first passivation layer and a first planarization layer stacked sequentially on the side of the third electrode plate away from the substrate, and the fourth electrode plate is disposed on the side of the first planarization layer away from the substrate.

[0028] The first planarization layer includes at least a first portion and a second portion. The first portion of the first planarization layer is sandwiched between the third electrode plate and the fourth electrode plate. The second portion of the first planarization layer does not overlap with the third electrode plate and the fourth electrode plate. The thickness of the first portion is less than the thickness of the second portion.

[0029] According to one embodiment of the present disclosure, the display panel further includes a first passivation layer and a first planarization layer sequentially stacked on the side of the third electrode plate away from the substrate, and the fourth electrode plate is disposed on the side of the first planarization layer away from the substrate.

[0030] The thickness of a first portion of the first planarization layer is 0, so as to expose the first passivation layer.

[0031] According to one embodiment of the present disclosure, the driving transistor includes a first electrode, a second electrode, and a gate, wherein the first electrode is used to apply a first power supply voltage, the second electrode is connected to the third node, and the gate is connected to the first node;

[0032] The data writing unit includes:

[0033] The first transistor includes a first electrode, a second electrode, and a gate. The first electrode is used to load the data voltage, the second electrode is connected to the second node, and the gate is used to load the first scan signal.

[0034] The light-emitting control unit includes:

[0035] The seventh transistor includes a first electrode, a second electrode, and a gate. The first electrode is connected to the third node, the second electrode is connected to the fourth node, and the gate is used to load the light-emitting control signal.

[0036] The first reset unit includes:

[0037] The fifth transistor includes a first electrode, a second electrode, and a gate. The first electrode is used to apply the reference voltage, the gate is used to apply the first reset signal, and the second electrode is connected to the second node.

[0038] The sixth transistor includes a first electrode, a second electrode, and a gate. The first electrode is used to apply the reference voltage, the gate is used to apply the light emission control signal, and the second electrode is connected to the second node.

[0039] The third reset unit includes:

[0040] The eighth transistor includes a first electrode, a second electrode, and a gate. The first electrode is used to apply the initialization voltage, the gate is used to apply the first reset signal, and the second electrode is connected to the fourth node.

[0041] According to one embodiment of this disclosure, the active layer of the first transistor, the driving transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor includes a channel region, a first electrode, and a second electrode located on both sides of the channel region, and the material of the active layer is polycrystalline silicon semiconductor material.

[0042] According to one embodiment of the present disclosure, the pixel driving circuit is disposed on one side of the substrate of the display panel;

[0043] The display panel includes data leads and a first power supply voltage lead extending along the column direction. The data leads are connected to the first electrode of the first transistor, and the first power supply voltage lead is electrically connected to the first electrode of the driving transistor.

[0044] The pixel driving circuit includes a first metal wiring structure, which is electrically connected to the first power supply voltage lead and insulated from the data lead; the orthographic projection of the data lead on the substrate at least partially overlaps with the orthographic projection of the first metal wiring structure on the substrate.

[0045] According to one embodiment of the present disclosure, the pixel driving circuit further includes a second metal wiring structure, the second metal wiring structure connecting the second electrode of the fifth transistor and the second electrode of the sixth transistor;

[0046] The orthographic projection of the second metal wiring structure on the substrate overlaps with the orthographic projection of the data lead on the substrate.

[0047] According to one embodiment of the present disclosure, the display panel further includes a second gate layer, a first metal wiring layer and a second metal wiring layer sequentially disposed on one side of the substrate.

[0048] The first metal wiring structure is located in the second gate layer and extends along the column direction; the second metal wiring structure is located in the first metal wiring layer, and the first metal wiring layer further includes a third metal wiring structure; the first power supply voltage lead and the data lead are located in the second metal wiring layer;

[0049] Wherein, the orthographic projection of the third metal wiring structure on the substrate coincides with the orthographic projection of the data lead on the substrate; the third metal wiring structure is electrically connected to the first metal wiring structure through a via, and is also connected to the first power supply voltage lead through a via.

[0050] According to one embodiment of the present disclosure, the display panel further includes a polysilicon semiconductor layer located between the substrate and the second gate layer;

[0051] The polycrystalline silicon semiconductor layer includes the active layer of the first transistor, the active layer of the sixth transistor, and a first conductive lead; the first conductive lead connects the second electrode of the first transistor and the second electrode of the sixth transistor, and extends along the column direction;

[0052] The first metal wiring layer includes a fourth metal wiring structure, which is connected to the first electrode of the first transistor through a via and to the data lead through a via.

[0053] The orthographic projection of the first metal wiring structure on the substrate overlaps at least partially with the orthographic projection of the first conductive lead on the substrate.

[0054] According to one embodiment of the present disclosure, the display panel further includes a first gate layer located between the polysilicon semiconductor layer and the second gate layer;

[0055] The storage capacitor includes a first electrode plate located in the first gate layer, a second electrode plate located in the second gate layer, a third electrode plate located in the first metal wiring layer, and a fourth electrode plate located in the second metal wiring layer; the third electrode plate is electrically connected to the first electrode plate through a via, the fourth electrode plate is electrically connected to the second metal wiring structure through a via, and the second metal wiring structure is electrically connected to the second electrode plate through a via.

[0056] The polysilicon semiconductor layer also includes the active layer of the fifth transistor, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are connected to the second metal wiring structure through vias.

[0057] According to one embodiment of the present disclosure, the first metal wiring layer further includes an initial voltage lead extending in the row direction, the initial voltage lead having a first protrusion extending in the column direction; the orthographic projection of the first protrusion on the substrate overlaps with the orthographic projection of the data lead on the substrate.

[0058] The first electrode of the fifth transistor is reused as the first electrode of the sixth transistor, and is electrically connected to the first protrusion through a via.

[0059] According to one embodiment of this disclosure, the channel region of the fifth transistor includes a first sub-channel region and a second sub-channel region, and the polysilicon semiconductor layer further includes a second conductive lead that connects the first sub-channel region and the second sub-channel region in series; the first sub-channel region and the second sub-channel region both extend along the column direction and are arranged along the row direction.

[0060] The first gate layer further includes a first reset lead extending along the first direction; the orthographic projections of the first subchannel region and the second subchannel region on the substrate are located within the orthographic projection of the first reset lead on the substrate.

[0061] According to one embodiment of this disclosure, the polycrystalline silicon semiconductor layer further includes an active layer for driving transistors, a third conductive lead, and a fourth conductive lead, wherein a first electrode of the driving transistor is connected to the third conductive lead, and a second electrode of the driving transistor is connected to the fourth conductive lead.

[0062] The first electrode plate covers the channel region of the driving transistor;

[0063] The third conductive lead is electrically connected to the third metal wiring structure through a via.

[0064] According to one embodiment of the present disclosure, the display panel further includes a metal oxide semiconductor layer located between the first gate layer and the second gate layer, the metal oxide semiconductor layer including an active layer of a second transistor and an active layer of a fourth transistor;

[0065] The first gate layer includes a second scan lead and a second reset lead extending along the row direction;

[0066] The second scan lead includes a first lead segment and a second lead segment that are alternately arranged and connected in sequence. The size of the first lead segment in the column direction is larger than the size of the second lead segment in the column direction. The orthogonal projection of the channel region of the second transistor onto the first gate layer is located within the first lead segment.

[0067] The second reset lead includes a third lead segment and a fourth lead segment that are alternately arranged and connected in sequence. The dimension of the third lead segment in the column direction is larger than the dimension of the fourth lead segment in the column direction. The orthogonal projection of the channel region of the fourth transistor on the first gate layer is located within the third lead segment.

[0068] According to one embodiment of the present disclosure, the second gate layer includes a third scan lead and a third reset lead extending along the row direction;

[0069] The orthogonal projection of the third scanning lead on the substrate covers the orthogonal projection of the channel region of the second transistor on the substrate.

[0070] The orthogonal projection of the third reset lead on the substrate covers the orthogonal projection of the channel region of the fourth transistor on the substrate.

[0071] According to one embodiment of the present disclosure, the first metal wiring layer further includes a fifth metal wiring structure and a sixth metal wiring structure;

[0072] The fifth metal wiring structure is electrically connected to the third electrode plate, and is connected to the second electrode of the second transistor through a via, and is also connected to the second electrode of the fourth transistor through a via.

[0073] The sixth metal wiring structure is connected to the fourth conductive lead through a via, and is also connected to the first electrode of the second transistor through a via.

[0074] According to one embodiment of the present disclosure, the first gate layer further includes a first scan lead extending along the said direction;

[0075] The orthographic projection of the channel region of the first transistor onto the substrate is located within the orthographic projection of the first scan lead onto the substrate.

[0076] The orthographic projection of the first scanning lead on the substrate at least partially overlaps with the orthographic projection of the fifth metal wiring structure on the substrate.

[0077] According to one embodiment of the present disclosure, the first scanning lead has a second protrusion; the orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projection of the fifth metal wiring structure on the substrate.

[0078] According to one embodiment of the present disclosure, the second gate layer further includes a power distribution lead extending along the row direction, the power distribution lead being connected to the first metal wiring structure.

[0079] According to one embodiment of the present disclosure, the first power supply voltage lead further includes a third protrusion, the orthographic projection of the third protrusion on the substrate covering the orthographic projection of the channel region of the second transistor on the substrate and the orthographic projection of the channel region of the fourth transistor on the substrate.

[0080] According to one embodiment of this disclosure, the polysilicon semiconductor layer further includes an active layer of a seventh transistor and an active layer of an eighth transistor. The first electrode of the seventh transistor is connected to the fourth conductive lead, and the second electrode of the seventh transistor and the second electrode of the eighth transistor overlap. The first electrode of the eighth transistor is connected to the initialization signal lead through a via.

[0081] The first gate layer further includes a light-emitting control lead extending along the row direction; the orthographic projection of the channel region of the sixth transistor on the substrate and the orthographic projection of the channel region of the seventh transistor on the substrate are located within the orthographic projection of the light-emitting control lead on the substrate.

[0082] The orthographic projection of the channel region of the eighth transistor onto the substrate lies within the orthographic projection of the first reset lead onto the substrate.

[0083] According to a second aspect of this disclosure, a display panel is provided, including the pixel driving circuit described above.

[0084] According to a third aspect of this disclosure, a pixel driving method is provided, applied to the aforementioned pixel driving circuit; wherein the driving method of the pixel driving circuit includes:

[0085] During the reset phase, the first reset signal is applied to the first reset unit to apply the reference voltage to the second node; the second reset signal is applied to the second reset unit to apply the initialization voltage to the first node.

[0086] During the data writing phase, the first scan signal is applied to the data writing unit to apply the data voltage to the second node; the second scan signal is applied to the threshold compensation unit to connect the first node and the third node until the current between the first node and the third node is zero.

[0087] During the light emission phase, the light emission control signal is applied to the light emission control unit and the first reset unit to connect the third node and the fourth node, and to apply the reference voltage to the second node.

[0088] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0089] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0090] Figure 1 This is a schematic diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0091] Figure 2 This is a schematic diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0092] Figure 3 This is a schematic diagram of the driving timing of a pixel driving circuit in one embodiment of the present disclosure.

[0093] Figure 4 This is a schematic diagram of the structure of the polysilicon semiconductor layer of the display panel in one embodiment of this disclosure.

[0094] Figure 5 This is a schematic diagram of the structure of the first gate layer of a display panel in one embodiment of the present disclosure.

[0095] Figure 6 This is a schematic diagram of the structure of a display panel with a polycrystalline silicon semiconductor layer and a first gate layer stacked in one embodiment of the present disclosure.

[0096] Figure 7 This is a schematic diagram of the structure of the metal oxide semiconductor layer of the display panel in one embodiment of this disclosure.

[0097] Figure 8 This is a schematic diagram of the structure of the second gate layer of the display panel in one embodiment of the present disclosure.

[0098] Figure 9 This is a schematic diagram of the stacked structure of the metal oxide semiconductor layer and the second gate layer of the display panel in one embodiment of the present disclosure.

[0099] Figure 10This is a schematic diagram of the stacked structure of a polycrystalline silicon semiconductor layer, a first gate layer, and a second gate layer in a display panel according to one embodiment of the present disclosure.

[0100] Figure 11 This is a partial structural diagram of a display panel in one embodiment of the present disclosure, showing the stacked polysilicon semiconductor layer, the first gate layer, and the second gate layer.

[0101] Figure 12 This is a schematic diagram of the structure of the first metal wiring layer of the display panel in one embodiment of this disclosure.

[0102] Figure 13 This is a schematic diagram of the stacked structure of a display panel comprising a polysilicon semiconductor layer, a first gate layer, a metal oxide semiconductor layer, a second gate layer, and a first metal wiring layer, according to one embodiment of this disclosure.

[0103] Figure 14 This is a partial structural diagram of the first scanning lead, the third scanning lead, and the fifth metal wiring structure of the display panel in one embodiment of the present disclosure.

[0104] Figure 15 This is a partial structural diagram of the first scanning lead, the third scanning lead, and the fifth metal wiring structure of the display panel in one embodiment of the present disclosure.

[0105] Figure 16 This is a schematic diagram of the structure of the second metal wiring layer of the display panel in one embodiment of the present disclosure.

[0106] Figure 17 This is a schematic diagram of the stacked structure of the first metal wiring layer and the second metal wiring layer of the display panel in one embodiment of this disclosure.

[0107] Figure 18 This is a schematic diagram of the stacked structure of the second gate layer and the second metal wiring layer of the display panel in one embodiment of the present disclosure.

[0108] Figure 19 This is a schematic diagram of the stacked structure of the third and fourth electrode plates of the pixel driving circuit in one embodiment of the present disclosure.

[0109] Figure 20 This is a schematic diagram of the stacked structure of a display panel comprising a polysilicon semiconductor layer, a first gate layer, a metal oxide semiconductor layer, a second gate layer, a first metal wiring layer, and a second metal wiring layer, according to one embodiment of this disclosure.

[0110] Figure 21 This is a schematic diagram of the structure of the pixel electrode layer of the display panel in one embodiment of the present disclosure.

[0111] Figure 22This is a schematic diagram of the stacked structure of a display panel comprising a polysilicon semiconductor layer, a first gate layer, a metal oxide semiconductor layer, a second gate layer, a first metal wiring layer, a second metal wiring layer, and a pixel electrode layer, according to one embodiment of this disclosure.

[0112] Figure 23 In one embodiment of this disclosure, the display panel is in Figure 12 The cross-sectional structure diagram at the position indicated by the dashed line PQ is shown.

[0113] Figure 24 This is a flowchart illustrating a pixel driving method in one embodiment of the present disclosure.

[0114] Explanation of reference numerals in the attached figures:

[0115] 110. Data writing unit; 120. Threshold compensation unit; 130. Light-emitting control unit; 140. First reset unit; 150. Second reset unit; 160. Third reset unit; 170. Light-emitting element; M1. First transistor; M2. Second transistor; M3. Driving transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; Cst. Storage capacitor; Gate_P. First scan signal; Gate_N. Second scan signal; Re_P. First reset signal; Re_N. Second reset signal; EM. Light-emitting control signal; Vref. Reference voltage; Vdata. Data voltage; Vinit. Initialization voltage VDD, First power supply voltage; VSS, Second power supply voltage; GL1, First scan lead; GL2, Second scan lead; GL21, First lead segment; GL22, Second lead segment; GL3, Third scan lead; RL1, First reset lead; RL2, Second reset lead; RL21, Third lead segment; RL22, Fourth lead segment; RL3, Third reset lead; EML, Light emission control lead; ViL, Initialization signal lead; VRL, Reference voltage lead; DataL, Data lead; VDDL, First power supply voltage lead; N1, First node; N2, Second node; N3, Third node; N4, Fourth node; H1, Row direction; H2, Column direction; F100, Substrate; F2 00, Driving circuit layer; Buffer1, First buffer layer; Poly, Polysilicon semiconductor layer; GI1, First gate insulating layer; Gate1, First gate layer; Buffer2, Second buffer layer; Oxide, Metal-oxide-semiconductor layer; GI2, Second gate insulating layer; Gate2, Second gate layer; ILD, Interlayer dielectric layer; SD1, First metal wiring layer; PVX1, First passivation layer; PLN1, First planarization layer; SD2, Second metal wiring layer; PVX2, Second passivation layer; PLN2, Second planarization layer; F300, Pixel layer; F310, Pixel electrode layer; F400, Thin film encapsulation layer; F500, Touch function layer; M1Act, First transistor trench Channel regions; M2Act, channel region of the second transistor; M3Act, channel region of the third transistor; M4Act, channel region of the fourth transistor; M5Act, channel region of the fifth transistor; M6Act, channel region of the sixth transistor; M7Act, channel region of the seventh transistor; M8Act, channel region of the eighth transistor; PL1, first conductive lead; PL2, second conductive lead; PL3, third conductive lead; PL4, fourth conductive lead; ML1, first metal wiring structure; ML2, second metal wiring structure; ML3, third metal wiring structure; ML4, fourth metal wiring structure; ML5, fifth metal wiring structure; ML6, sixth metal wiring structure; ML7, seventh metal wiring structure;ML8, Eighth metal wiring structure; VDDGL, Power distribution lead; Hump1, First protrusion; Hump2, Second protrusion; Hump3, Third protrusion; Hump4, Fourth protrusion; CP1, First electrode plate; CP2, Second electrode plate; CP3, Third electrode plate; CP4, Fourth electrode plate; PR, Pixel electrode of red light-emitting element; PG, Pixel electrode of green light-emitting element; PB, Pixel electrode of blue light-emitting element; HA1, First bottom via area; HA2, Second bottom via area; HA3, Third bottom via area; HA4, Fourth bottom via area; HA5, Fifth bottom via area; HA6, Sixth bottom via area; HA7, Seventh bottom via area; HA8, Eighth bottom via area; HA9, Ninth bottom via area; HA10, Tenth bottom via area; HA11, Eleventh bottom via area; HA12, Twelfth bottom via area; HA13, Thirteenth bottom via area; HA14, Fourteenth bottom via area. Via zones; HA15, 15th bottom via zone; HA16, 16th bottom via zone; HA17, 17th bottom via zone; HA18, 18th bottom via zone; HA19, 19th bottom via zone; HB1, 1st top via zone; HB2, 2nd top via zone; HB3, 3rd top via zone; HB4, 4th top via zone; HB5, 5th top via zone; HB6, 6th top via zone; HB7, 7th top via zone; HB8, 8th top via zone; HB 9. Ninth top via area; HB10. Tenth top via area; HB11. Eleventh top via area; HB12. Twelfth top via area; HB13. Thirteenth top via area; HB14. Fourteenth top via area; HB15. Fifteenth top via area; HB16. Sixteenth top via area; HB17. Seventeenth top via area; HB18. Eighteenth top via area; HB19. Nineteenth top via area; HAP, Adapter via area; SubA, Pixel driving area. Detailed Implementation

[0116] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0117] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0118] In the display panel or pixel driving circuit disclosed herein, the overlapping of two structures refers to the two structures being stacked and intersecting; that is, the two structures are located in different film layers of the display panel, and the orthographic projections of the two structures on the substrate have overlapping areas.

[0119] In this disclosure, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the area through which current primarily flows.

[0120] In this disclosure, one of the drain and source of a transistor is used as the first electrode of the transistor, and the other is used as the second electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this disclosure, in some cases the first electrode can serve as the source and the second electrode can serve as the drain, while in other cases the first electrode can serve as the drain and the second electrode can serve as the source.

[0121] In this disclosure, unless otherwise specified, vias are vias in the conventional sense, and it is not limited to the insulating film layer penetrated by each via or the conductive structure connected to the same via.

[0122] This disclosure provides a pixel driving circuit and a display panel using the pixel driving circuit. See also Figure 1 The pixel driving circuit provided in this disclosure includes:

[0123] Drive transistor M3, connected to the first node N1 and the third node N3, is used to output drive current to the third node N3 under the control of the first node N1;

[0124] The storage capacitor Cst is connected to the first node N1 and the second node N2;

[0125] The data writing unit 110 is connected to the second node N2 and is used to output the data voltage Vdata to the second node N2 in response to the first scan signal Gate_P.

[0126] The light-emitting control unit 130 is connected to the third node N3 and the fourth node N4, and is used to make the third node N3 and the fourth node N4 electrically connected in response to the light-emitting control signal EM;

[0127] The first reset unit 140 is connected to the second node N2 and is used to output a reference voltage Vref to the second node N2 in response to the light emission control signal EM or the first reset signal Re_P.

[0128] The second reset unit 150 is connected to the first node N1 and is used to output the initialization voltage Vinit to the first node N1 in response to the second reset signal Re_N.

[0129] In one embodiment of this disclosure, the pixel driving circuit may further include a threshold compensation unit 120. The threshold compensation unit 120 is connected to the first node N1 and the third node N3, and is used to electrically connect the first node N1 and the third node N3 in response to the second scan signal Gate_N.

[0130] The pixel driving circuit disclosed herein can be found in [reference]. Figure 1 , Figure 3 and Figure 24 The following pixel driving method can be used for driving:

[0131] In step S110, during the reset phase T1, a first reset signal Re_P is loaded into the first reset unit 140 so that the reference voltage Vref is loaded into the second node N2; a second reset signal Re_N is loaded into the second reset unit 150 so that the initialization voltage Vinit is loaded into the first node N1.

[0132] In step S120, during the data writing stage T2, a first scan signal Gate_P is loaded into the data writing unit 110 to load the data voltage Vdata to the second node N2; a second scan signal Gate_N is loaded into the threshold compensation unit 120 to connect the first node N1 and the third node N3 until the current between the first node N1 and the third node N3 is zero. In this way, the threshold voltage of the driving transistor is written into the first node N1 to achieve compensation for the threshold voltage of the driving transistor.

[0133] In step S130, during the light emission stage T3, a light emission control signal EM is loaded onto the light emission control unit 130 and the first reset unit 140 to connect the third node N3 and the fourth node N4, and to load the reference voltage Vref onto the second node N2.

[0134] Understandably, in Figure 3In the timing diagram shown, the first reset signal Re_P, the first scan signal Gate_P, and the light emission control signal EM are valid signals when low and invalid base value signals when high. Similarly, the second reset signal Re_N and the second scan signal Gate_N are valid signals when high and invalid base value signals when low. It can be understood that the high and low levels of these valid signals can be reversed to achieve control of the corresponding units.

[0135] In the pixel driving circuit and driving method disclosed herein, during the reset phase, different reset signals can be used to control the first reset unit 140 and the second reset unit 150 respectively, thereby resetting the second node N2 using the reference voltage Vref and resetting the first node N1 using the initialization voltage Vinit. The reference voltage Vref is a positive voltage, which can be 3V, and the initialization voltage Vinit is a negative voltage, which can be -3V to -5V. During the data writing phase, the data voltage and the threshold voltage of the driving transistor can be written to the two ends of the storage capacitor respectively. The first node N1 is charged to a voltage of VDD+Vth, and the second node N2 is written with the data voltage Data. This allows the data writing and threshold voltage compensation of the driving transistor to be completed in the same phase, simplifying the driving method of the pixel driving circuit. During the light-emitting stage, the first reset unit 140 can be controlled by the light-emitting control signal EM to reset the second node N2. The voltage of the second node N2 changes from Data to Vref. The capacitor follows the principle of charge conservation. The voltage of the first node N1 jumps to VDD+Vth+Vref-Data, realizing the pull-down (or pull-up) of the voltage of the first node N1, so that the driving transistor M3 can generate driving current and drive the light-emitting element 170 to emit light.

[0136] The structure, principle, and effects of the pixel driving circuit provided in this disclosure will be further explained and illustrated below with reference to the accompanying drawings.

[0137] See Figure 23 The display panel provided in this disclosure may include a substrate F100, a driving circuit layer F200, and a pixel layer F300 stacked sequentially. The pixel driving circuit provided in this disclosure may be disposed in the driving circuit layer F200, and the pixel layer F300 may contain a light-emitting element 170 corresponding to the pixel driving circuit. One end of the light-emitting element 170 may be loaded with a second power supply voltage VSS, and the other end may be electrically connected to the fourth node of the pixel driving circuit. Thus, the pixel driving circuit can drive the corresponding light-emitting element 170 to emit light.

[0138] See Figure 1In one embodiment of this disclosure, the pixel driving circuit further includes a third reset unit 160, which is connected to a fourth node N4 and is used to output an initialization voltage Vinit to the fourth node N4 in response to a first reset signal Re_P. Thus, during the reset phase, the pixel driving circuit can simultaneously reset the first node N1, the second node N2, and the fourth node N4. This can quickly eliminate the voltage difference between the cathode and anode of the light-emitting element 170, avoiding motion blur caused by the light-emitting element 170 failing to stop emitting light in time.

[0139] Optionally, see Figure 2 The threshold compensation unit 120 includes a second transistor M2, which includes a first electrode, a second electrode, and a gate. The first electrode is connected to a third node N3, the second electrode is connected to a first node N1, and the gate is used to load the second scan signal Gate_N. The active layer of the second transistor M2 is made of metal-oxide-semiconductor (MODS) material. Thus, the second transistor M2 is an Oxide-TFT, which has low leakage current in the off state, thereby reducing the leakage current of the first node N1. This facilitates the potential maintenance of the storage capacitor Cst during the light-emitting phase, thereby reducing the flicker risk of the light-emitting element 170 during low-frequency driving. In one embodiment of this disclosure, the second transistor M2 is an N-type thin-film transistor.

[0140] Optionally, the gate of the second transistor M2 includes a first gate and a second gate, both used for loading the second scan signal Gate_N, and the active layer of the second transistor M2 includes a channel region. The first gate, the channel region, and the second gate of the second transistor M2 are stacked sequentially. In this way, the channel region of the second transistor M2 is sandwiched between its first gate and second gate, which can reduce the influence of the floating body effect on the second transistor M2 and further reduce the leakage current of the second transistor M2 in the off state.

[0141] In one embodiment of this disclosure, a pixel driving circuit is disposed on one side of a substrate F100. The first gate of the second transistor M2 is located on the side of the channel region of the second transistor M2 near the substrate F100; the orthographic projection of the second gate of the second transistor M2 on the substrate F100 is located within the orthographic projection of the first gate of the second transistor M2 on the substrate F100. In other words, the first gate, the channel region of the second transistor M2, and the second gate of the second transistor M2 are sequentially stacked on one side of the substrate F100; the portion where the active layer of the second transistor M2 overlaps with the second gate of the second transistor M2 serves as the channel region of the second transistor M2, and the channel region of the second transistor M2 is completely shielded by the first gate of the second transistor M2. In this way, the first gate of the second transistor M2 can shield the influence of external light on the channel region of the second transistor M2, avoiding the generation of photocurrent in the channel region of the second transistor M2, which would lead to an increase in the leakage current of the second transistor M2 in the off state.

[0142] Optionally, see Figure 3 The second reset unit 150 includes a fourth transistor M4, which includes a first electrode, a second electrode, and a gate. The first electrode is used to apply an initialization voltage Vinit, the second electrode is connected to the first node N1, and the gate is used to apply a second reset signal Re_N. The active layer of the fourth transistor M4 is made of metal-oxide-semiconductor (MODS). Thus, the fourth transistor M4 is a MODS, which has low leakage current in the off state, thereby reducing the leakage current of the first node N1. This facilitates the potential maintenance of the storage capacitor Cst during the light-emitting phase, thereby reducing the flicker risk of the light-emitting element 170 during low-frequency driving. In one embodiment of this disclosure, the fourth transistor M4 is an N-type thin-film transistor.

[0143] Optionally, the gate of the fourth transistor M4 includes a first gate and a second gate, both used for loading the second reset signal Re_N, and the active layer of the fourth transistor M4 includes a channel region; the first gate, the channel region, and the second gate of the fourth transistor M4 are stacked sequentially. Thus, the channel region of the fourth transistor M4 is sandwiched between its first and second gates, which can reduce the influence of the floating body effect on the fourth transistor M4 and further reduce the leakage current of the fourth transistor M4 in the off state.

[0144] In one embodiment of this disclosure, a pixel driving circuit is disposed on one side of a substrate F100. The first gate of the fourth transistor M4 is located on the side of the channel region of the fourth transistor M4 near the substrate F100; the orthographic projection of the second gate of the fourth transistor M4 on the substrate F100 is completely within the orthographic projection of the first gate of the fourth transistor M4 on the substrate F100.

[0145] In other words, the first gate, the channel region, and the second gate of the fourth transistor M4 are sequentially stacked on one side of the substrate F100; the portion where the active layer of the fourth transistor M4 overlaps with the second gate of the fourth transistor M4 serves as the channel region of the fourth transistor M4, which is completely shielded by the first gate. Thus, the first gate of the fourth transistor M4 can shield the channel region from external light, preventing the generation of photocurrent in the channel region and thus avoiding an increase in leakage current in the off-state of the fourth transistor M4.

[0146] Optionally, the pixel driving circuit is disposed on one side of the substrate F100; the storage capacitor Cst includes at least two overlapping and mutually insulated electrode plates, with an insulating medium filling the space between the two electrode plates. At least one electrode plate can be electrically connected to the first node N1, and at least one electrode plate can be electrically connected to the second node N2.

[0147] Further optional, see Figure 23 The storage capacitor Cst includes a first electrode plate CP1, a second electrode plate CP2, a third electrode plate CP3, and a fourth electrode plate CP4 sequentially stacked on one side of the substrate F100, with an insulating medium sandwiched between any two adjacent electrode plates. The first electrode plate CP1 and the third electrode plate CP3 are both electrically connected to the first node N1; the second electrode plate CP2 and the fourth electrode plate CP4 are both electrically connected to the second node N2. In this embodiment, by increasing the number of electrode plates in the storage capacitor Cst, the capacitance value of the storage capacitor Cst can be increased, thereby reducing the influence of leakage current at the first node N1 on the electromotive force at the first node N1, weakening or eliminating the flickering problem of the pixel driving circuit under low-frequency driving, and improving the display quality of the display panel using this pixel driving circuit.

[0148] Optionally, see Figure 23 The display panel using this pixel driving circuit also includes a first passivation layer PVX1 and a first planarization layer PLN1 stacked sequentially on the side of the third electrode plate CP3 away from the substrate F100, and a fourth electrode plate CP4 disposed on the side of the first planarization layer PLN1 away from the substrate F100.

[0149] See Figure 19The first planarization layer PLN1 includes at least a first portion SA1 and a second portion SA2. The first portion SA1 of the first planarization layer PLN1 is sandwiched between the third electrode plate CP3 and the fourth electrode plate CP4. The second portion SA2 of the first planarization layer PLN1 does not overlap with the third electrode plate CP3 and the fourth electrode plate CP4. The thickness of the first portion SA1 is less than the thickness of the second portion SA2. In other words, the display panel can increase the capacitance of the storage capacitor Cst by thinning the first portion SA1 of the first planarization layer PLN1, thereby reducing the distance between the third electrode plate CP3 and the fourth electrode plate CP4 at the first portion SA1 of the first planarization layer PLN1.

[0150] Optionally, the first planarization layer PLN1 may further include a third portion SA3 sandwiched between the first portion SA1 and the second portion SA2. The inner edge SAE1 of the third portion SA3 may be completely located within the overlapping area of ​​the third electrode plate CP3 and the fourth electrode plate CP4, and the outer edge SAE2 of the third portion SA3 may not overlap with either the third electrode plate CP3 or the fourth electrode plate CP4. The thickness of the third portion SA3 of the first planarization layer PLN1 may be uniform, for example, the same as the thickness of the first portion SA1 or the second portion SA2, or it may be non-uniform, for example, partly the same as the first portion SA1 and the rest the same as the second portion SA2. It is understood that the thickness of the third portion SA3 of the first planarization layer PLN1 may also be in other states, for example, it may be in a gradual state, or in a step-like multiple abrupt state, or in other regular or irregular states.

[0151] In one embodiment of this disclosure, the thickness of the third portion SA3 of the first planarization layer PLN1 can be the same as the thickness of the first portion SA1. Thus, both the first portion SA1 and the third portion SA3 of the first planarization layer PLN1 are thinned (both are thinned regions), reducing the distance between the third electrode plate CP3 and the fourth electrode plate CP4 at any point in their overlapping region, thereby maximizing the capacitance value of the storage capacitor Cst. Furthermore, since the unthinned second part SA2 does not overlap with the third electrode plate CP3 and the fourth electrode plate CP4, that is, the boundary of the thinned area of ​​the first planarization layer PLN1 (i.e., the outer edge SAE2 of the third part SA3) is outside the overlapping area of ​​the third electrode plate CP3 and the fourth electrode plate CP4, this can avoid the boundary of the thinned area of ​​the first planarization layer PLN1 being in the overlapping area of ​​the third electrode plate CP3 and the fourth electrode plate CP4. This avoids the deviation in the overlapping area between the overlapping area and the thinned area of ​​the third electrode plate CP3 and the fourth electrode plate CP4 caused by process errors, and thus avoids the change in the capacitance value of the storage capacitor Cst caused by such deviation. This ensures the uniformity of the storage capacitance value of the storage capacitor Cst of different driving circuits.

[0152] In another embodiment of this disclosure, the thickness of the third portion SA3 of the first planarization layer PLN1 can be the same as the thickness of the second portion SA2. Thus, neither the second portion SA2 nor the third portion SA3 of the first planarization layer PLN1 is thinned, while the first portion SA1 of the first planarization layer PLN1 is thinned (a thinned region). Since the thinned first portion SA1 overlaps with both the third electrode plate CP3 and the fourth electrode plate CP4, the boundary of the thinned region of the first planarization layer PLN1 (i.e., the inner edge SAE1 of the third portion SA3) is completely within the overlapping area of ​​the third electrode plate CP3 and the fourth electrode plate CP4. This avoids the boundary of the thinned region of the first planarization layer PLN1 being only partially within the overlapping area of ​​the third electrode plate CP3 and the fourth electrode plate CP4, thereby avoiding process errors that cause a deviation in the overlapping area between the overlapping area of ​​the third electrode plate CP3 and the fourth electrode plate CP4 and the thinned region. This deviation also prevents changes in the capacitance value of the storage capacitor Cst, ensuring the uniformity of the storage capacitance value of the storage capacitor Cst for different driving circuits.

[0153] In one embodiment of this disclosure, the thickness of the first portion SA1 of the first planarization layer PLN1 can be zero to expose the first passivation layer PVX1. Thus, the first planarization layer PLN1 can be hollowed out at the location of the first portion SA1, exposing the first passivation layer PVX1, with the third electrode plate CP3 and the fourth electrode plate CP4 isolated at this hollowed-out area by the first passivation layer PVX1. In other words, the first passivation layer PVX1 has a first portion SA1 sandwiched between the third electrode plate CP3 and the fourth electrode plate CP4, and the first planarization layer PLN1 has a hollowed-out area exposing the first passivation layer PVX1; the hollowed-out area of ​​the first planarization layer PLN1 exposes at least a portion of the first portion SA1 of the first passivation layer PVX1. The hollowed-out area is the thinned area of ​​the first planarization layer PLN1. It is understood that the third portion SA3 of the first planarization layer PLN1 can be completely hollowed out, partially hollowed out, or completely hollowed out. Therefore, the first part SA1 of the passivation layer PVX1 can be located either partially in the cutout area of ​​the first planarization layer PLN1 or completely in the cutout area of ​​the first planarization layer PLN1.

[0154] Optionally, see Figure 2 The driving transistor M3 includes a first electrode, a second electrode, and a gate. The first electrode is used to apply a first power supply voltage VDD, the second electrode is connected to a third node N3, and the gate is connected to the first node N1.

[0155] Optionally, see Figure 2 The data writing unit 110 may include:

[0156] The first transistor M1 includes a first electrode, a second electrode, and a gate. The first electrode is used to load the data voltage Vdata, the second electrode is connected to the second node N2, and the gate is used to load the first scan signal Gate_P.

[0157] Optionally, see Figure 2 The light-emitting control unit 130 includes:

[0158] The seventh transistor M7 includes a first electrode, a second electrode, and a gate. The first electrode is connected to the third node N3, the second electrode is connected to the fourth node N4, and the gate is used to load the light emission control signal EM.

[0159] Optionally, see Figure 2 The first reset unit 140 includes a fifth transistor M5 and a sixth transistor M6.

[0160] The fifth transistor M5 includes a first electrode, a second electrode, and a gate. The first electrode is used to apply a reference voltage Vref, the gate is used to apply a first reset signal Re_P, and the second electrode is connected to the second node N2.

[0161] The sixth transistor M6 includes a first electrode, a second electrode, and a gate. The first electrode is used to apply a reference voltage Vref, the gate is used to apply a light emission control signal EM, and the second electrode is connected to the second node N2.

[0162] Optionally, see Figure 2 The third reset unit 160 includes:

[0163] The eighth transistor M8 includes a first electrode, a second electrode, and a gate. The first electrode is used to apply the initialization voltage Vinit, the gate is used to apply the first reset signal Re_P, and the second electrode is connected to the fourth node N4.

[0164] Optionally, the active layer of the first transistor M1, driving transistor M3, fifth transistor M5, sixth transistor M6, seventh transistor M7, and eighth transistor M8 is made of polycrystalline silicon semiconductor material, such as low-temperature polycrystalline silicon semiconductor material. Further, the first transistor M1, driving transistor M3, fifth transistor M5, sixth transistor M6, seventh transistor M7, and eighth transistor M8 are P-type thin-film transistors.

[0165] Optionally, see Figure 18 The display panel includes a data lead DataL and a first power supply voltage lead VDDL extending along the column direction H2. The data lead DataL is electrically connected to the first electrode of the first transistor M1, and the first power supply voltage lead VDDL is electrically connected to the first electrode of the driving transistor M3.

[0166] See Figure 18The pixel driving circuit includes a first metal wiring structure ML1, which is electrically connected to a first power supply voltage lead VDDL and insulated from a data lead DataL. Therefore, when the pixel driving circuit is operating, a constant first power supply voltage VDD is applied to the first metal wiring structure ML1. The orthographic projection of the data lead DataL onto the substrate F100 at least partially overlaps with the orthographic projection of the first metal wiring structure ML1 onto the substrate F100. Thus, a parasitic capacitance can be formed between the first metal wiring structure ML1 and the data lead DataL, thereby increasing the capacitance value of the parasitic capacitance of the data lead DataL. When the display panel is configured with a DEMUX (DE-Multiplexer) to drive multiple columns of pixel driving circuits, the data voltage Vdata of each column of pixel driving circuits is pre-stored in the parasitic capacitance of the data lead DataL and written into the storage capacitor Cst after the first transistor M1 is turned on. In this disclosure, because the parasitic capacitance of the data lead DataL is increased, the charge capacity of the data lead DataL is large, the proportion of charge lost when storing the charge that forms the data voltage Vdata is smaller, and the storage capacitor Cst has a stronger charging capability during the data writing stage, which can improve the charging rate of the storage capacitor Cst.

[0167] Optionally, see Figure 17 The pixel driving circuit further includes a second metal wiring structure ML2. The second metal wiring structure ML2 connects the second electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6. Therefore, when the pixel driving circuit is operating, a reference voltage Vref, serving as a constant voltage, is applied to the second metal wiring structure ML2. The orthographic projection of the second metal wiring structure ML2 onto the substrate F100 partially overlaps with the orthographic projection of the data lead DataL onto the substrate F100. Thus, a parasitic capacitance can be formed between the second metal wiring structure ML2 and the data lead DataL, thereby increasing the capacitance value of the parasitic capacitance of the data lead DataL. This is beneficial for improving the charging rate of the storage capacitor Cst.

[0168] See also in this disclosure Figure 4The row direction H1 has opposite first row directions H11 and second row directions H12. In the same pixel driving circuit, along the row direction H1, the channel region M3Act of the driving transistor M3 is located on the first row direction H11 side of the channel region M1Act of the first transistor M1; the channel region M1Act of the first transistor M1 is located on the second row direction H12 side of the channel region M3Act of the driving transistor M3. The column direction H2 has opposite first column directions H21 and second column directions H22. Along the column direction H2, the channel region M3Act of the driving transistor M3 is located on the first column direction H21 side of the channel region M1Act of the first transistor M1; the channel region M1Act of the first transistor M1 is located on the second column direction H22 side of the channel region M3Act of the driving transistor M3.

[0169] In one embodiment of this disclosure, in the same pixel driving circuit, the first transistor M1 and the sixth transistor M6 are arranged in a straight line along the first column direction H21, the seventh transistor M7 and the eighth transistor M8 are arranged in a straight line along the first column direction H21, and the sixth transistor M6 and the seventh transistor M7 are arranged in a straight line along the first row direction H11. Optionally, when the pixel driving circuit has the eighth transistor M8, the fifth transistor M5 and the eighth transistor M8 are arranged in a straight line along the first row direction H11.

[0170] Figure 4 and Figure 7 The location of the channel regions of each transistor is shown in one embodiment. See also Figure 4 and Figure 7In one embodiment of this disclosure, in the same pixel driving circuit, on the orthogonal projection of the column direction H2, the channel regions M4Act of the fourth transistor M4, M2Act of the second transistor M2, M1Act of the first transistor M1, M3Act of the driving transistor M3, M6Act of the sixth transistor M6, and M5Act of the fifth transistor M5 are sequentially arranged along the first column direction H21; it can be understood that the channel regions M4Act of the fourth transistor M4, M2Act of the second transistor M2, M1Act of the first transistor M1, M3Act of the driving transistor M3, M6Act of the sixth transistor M6, and M5Act of the fifth transistor M5 may not be arranged in a straight line along the first column direction H21. In the same pixel driving circuit, on the orthogonal projection of the row direction H1, the channel region M1Act of the first transistor M1, the channel region M4Act of the fourth transistor M4, the channel region M3Act of the driving transistor M3, and the channel region M7Act of the seventh transistor M7 are sequentially arranged along the first row direction H11.

[0171] See Figure 23 In terms of film structure, the display panel includes a substrate F100, a driving circuit layer F200 and a pixel layer F300 stacked in sequence.

[0172] Optionally, the substrate F100 can be an inorganic material substrate F100 or an organic material substrate F100. For example, in one embodiment of this disclosure, the material of the substrate F100 can be a glass material such as soda-lime glass, quartz glass, or sapphire glass, or a metal material such as stainless steel, aluminum, or nickel. In another embodiment of this disclosure, the substrate F100 may be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of this disclosure, the substrate F100 may also be a flexible substrate F100, for example, the material of the substrate F100 may be polyimide (PI). The substrate F100 can also be a composite of multiple materials. For example, in one embodiment of this disclosure, the substrate F100 may include a bottom film, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked sequentially.

[0173] Optionally, see Figure 23 The driving circuit layer F200 may include, sequentially stacked on one side of the substrate F100, a first buffer layer Buffer1, a polysilicon semiconductor layer Poly, a first gate insulating layer GI1, a first gate layer Gate1, an interlayer dielectric layer ILD, a first metal wiring layer SD1, a first planarization layer PLN1, a second metal wiring layer SD2, and a second planarization layer PLN2. In one embodiment of this disclosure, the driving circuit layer F200 may further include a first passivation layer PVX1 located between the first metal wiring layer SD1 and the first planarization layer PLN1. Further, in one embodiment of this disclosure, the driving circuit layer F200 may further include a second passivation layer PVX2 located between the second metal wiring layer SD2 and the second planarization layer PLN2.

[0174] In one embodiment of this disclosure, the pixel driving circuit may include a metal-oxide-semiconductor (MOD) transistor. The driving circuit layer F200 may further include a second buffer layer Buffer2 and a MOD semiconductor layer sequentially stacked on the side of the first gate layer Gate1 away from the substrate, with an interlayer dielectric layer ILD located on the side of the MOD semiconductor layer Oxide away from the substrate. Furthermore, the driving circuit layer may also include a second gate insulating layer GI2 and a second gate layer Gate2 sequentially stacked on the side of the MOD semiconductor layer Oxide away from the substrate, with the interlayer dielectric layer ILD located on the side of the second gate layer Gate2 away from the substrate.

[0175] Optionally, the polysilicon semiconductor layer Poly may be provided with an active layer for the first transistor M1, an active layer for the driving transistor M3, an active layer for the fifth transistor M5, an active layer for the sixth transistor M6, and an active layer for the seventh transistor M7. Further optionally, the polysilicon semiconductor layer Poly may also be provided with an active layer for the eighth transistor M8 to form the eighth transistor M8 as the third reset unit 160. It is understood that the active layer of any one of the first transistor M1, driving transistor M3, fifth transistor M5, sixth transistor M6, seventh transistor M7, and eighth transistor M8 may include a first electrode, a channel region, and a second electrode connected in sequence. The channel region of the transistor can maintain semiconductor characteristics, and the first and second electrodes can be made conductive through methods such as doping. Figure 4 The image shows the location of the channel region for each transistor.

[0176] Optionally, see Figure 4 The polysilicon semiconductor layer (Poly) can also be provided with a conductive first conductive lead PL1, through which the channel region M1Act of the first transistor M1 and the channel region M6Act of the sixth transistor M6 are connected. Thus, the first conductive lead PL1 can be reused as the second electrode of both the first transistor M1 and the sixth transistor M6. Furthermore, in a pixel driving circuit, the first conductive lead PL1 extends along the column direction H2.

[0177] In one embodiment of this disclosure, see Figure 4 The first electrode of the first transistor M1 is located on the side of the channel region M1Act of the first transistor M1 away from the channel region M6Act of the sixth transistor M6, and may have a first bottom via region HA1. The first bottom via region HA1 is electrically connected to the data lead DataL through the via, so that the data loaded on the data lead DataL can be loaded to the first electrode of the first transistor M1.

[0178] In one embodiment of this disclosure, see Figure 4 The first conductive lead PL1 can be part of the second node N2, and its end near the channel region M6Act of the sixth transistor M6 can have a second bottom via region HA2. The second bottom via region HA2 is used to electrically connect to the second electrode plate CP2 and the fourth electrode plate CP4 of the storage capacitor Cst through the via.

[0179] In one embodiment of this disclosure, see Figure 4 The first electrode of the sixth transistor M6 and the first electrode of the fifth transistor M5 can be reused, located on the side of the channel region M6Act of the sixth transistor M6 away from the channel region M1Act of the first transistor M1. The first electrode of the sixth transistor M6 may have a third bottom via region HA3, which is used to electrically connect to the reference voltage lead VrL through the via, so that the reference voltage Vref applied on the reference voltage lead VrL can be applied to the first electrodes of the sixth transistor M6 and the fifth transistor M5.

[0180] In one embodiment of this disclosure, see Figure 4 The second electrode of the fifth transistor M5 may have a fourth bottom via region HA4. The fourth bottom via region HA4 can be electrically connected to the first conductive lead PL1 through vias and other conductive structures, so that the second electrode of the fifth transistor M5 can be electrically connected to the second node N2.

[0181] Optionally, the channel region M5Act of the fifth transistor M5 includes a first sub-channel region and a second sub-channel region. The polysilicon semiconductor layer Poly further includes a conductive second conductive lead PL2 that connects the first sub-channel region and the second sub-channel region in series. Both the first and second sub-channel regions extend along the column direction H2 and are arranged along the row direction H1. The second conductive lead PL2 connects one end of the first column direction H21 of the first sub-channel region and one end of the first column direction H21 of the second sub-channel region. See details... Figure 4 The polysilicon semiconductor layer Poly has a U-shaped bend structure between the first electrode and the second electrode of the fifth transistor M5. It includes a first subchannel region, a second conductive lead PL2, and a second subchannel region connected sequentially. The first and second subchannel regions are located on the two arms of the U-shaped bend structure, respectively. This allows for increasing the length of the channel region M5Act of the fifth transistor M5 while reducing the size of the pixel driving region SubA in the column direction H2.

[0182] In one embodiment of this disclosure, see Figure 4The polysilicon semiconductor layer Poly can also be provided with a conductive third conductive lead PL3. The third conductive lead PL3 can be reused as the first electrode of the driving transistor M3 and is located on the side of the channel region M3Act of the driving transistor M3 near the first conductive lead PL1. At the end of the third conductive lead PL3 away from the channel region M3Act of the driving transistor M3, a fifth bottom via region HA5 can be provided. The fifth bottom via region HA5 is used to electrically connect to the first power supply voltage lead VDDL through the via, so that the first power supply voltage VDD applied on the first power supply voltage lead VDDL can be applied to the first electrode of the driving transistor M3.

[0183] In one embodiment of this disclosure, see Figure 4 The polysilicon semiconductor layer (Poly) may also be provided with a conductive fourth conductive lead (PL4). The fourth conductive lead (PL4) can be connected to the channel region M3Act of the driving transistor M3 to be reused as the second electrode of the driving transistor M3, and serves as part of the third node N3 of the pixel driving circuit. Optionally, the fourth conductive lead (PL4) may extend along the column direction H2, and its end located in the first column direction H21 may be connected to the channel region M7Act of the seventh transistor M7, so that the fourth conductive lead (PL4) can be reused as the first electrode of the seventh transistor M7. The end of the fourth conductive lead (PL4) located in the second column direction H22 may have a sixth bottom via region (HA6), which is used to connect to the second electrode of the second transistor M2 through a via.

[0184] In one embodiment of this disclosure, see Figure 4 The second electrode of the seventh transistor M7 is located on the side of the channel region M7Act of the seventh transistor M7 away from the fourth conductive lead PL4, and has a seventh bottom via region HA7. The seventh bottom via region HA7 is used for electrical connection with the light-emitting element 170 through the via. The second electrode of the seventh transistor M7 can be part of the fourth node N4 node of the pixel driving circuit.

[0185] In one embodiment of this disclosure, see Figure 4 The pixel driving circuit includes an eighth transistor M8. The channel region M8Act of the eighth transistor M8 is located on the first column direction H21 side of the channel region M7Act of the seventh transistor M7, and the second electrode of the seventh transistor M7 is multiplexed as the second electrode of the eighth transistor M8. The first electrode of the eighth transistor M8 is located on the side of the channel region M8Act of the eighth transistor M8 away from the channel region M7Act of the seventh transistor M7, and has an eighth bottom via region HA8. The eighth bottom via region HA8 is used to electrically connect to the initialization signal lead ViL through the via, so that the initialization voltage Vinit applied on the initialization signal lead ViL is applied to the first electrode of the eighth transistor M8.

[0186] See Figure 5 The first gate layer Gate1 may be provided with a first scan lead GL1 for loading the first scan signal Gate_P, a first electrode plate CP1, a light emission control lead EML for loading the light emission control signal EM, and a first reset lead RL1 for loading the first reset signal Re_P. Optionally, the first scan lead GL1, the light emission control lead EML, and the first reset lead RL1 extend along the row direction H1, and multiple pixel driving circuits arranged along the row direction H1 may share the same first scan lead GL1, the light emission control lead EML, and the first reset lead RL1.

[0187] The first gate layer Gate1 may be provided with the gate of the first transistor M1, and the gate of the first transistor M1 is connected to the first scan lead GL1, so that the first transistor M1 can be turned on in response to the first scan signal Gate_P. In one embodiment of this disclosure, see... Figure 6 The orthographic projection of the channel region Act of the first transistor M1 onto the substrate F100 lies within the orthographic projection of the first scan lead GL1 onto the substrate F100. In other words, the first scan lead GL1 can overlap with the channel region M1Act of the first transistor M1, so that the overlapping portion can be reused as the gate of the first transistor M1.

[0188] The first gate layer Gate1 may be provided with the gate of the sixth transistor M6, and the gate of the sixth transistor M6 is connected to the light-emitting control lead EML, so that the sixth transistor M6 can be turned on in response to the light-emitting control signal EM. In one embodiment of this disclosure, see... Figure 6 The orthographic projection of the channel region of the sixth transistor M6 onto the substrate F100 lies within the orthographic projection of the light-emitting control lead EML onto the substrate F100. In other words, the light-emitting control lead EML can overlap with the channel region M6Act of the sixth transistor M6, so that the overlapping portion can be reused as the gate of the sixth transistor M6.

[0189] The first gate layer Gate1 may be provided with the gate of the seventh transistor M7, and the gate of the seventh transistor M7 is connected to the light-emitting control lead EML, so that the seventh transistor M7 can be turned on in response to the light-emitting control signal EM. In one embodiment of this disclosure, see... Figure 6 The orthographic projection of the channel region of the seventh transistor M7 onto the substrate F100 lies within the orthographic projection of the light-emitting control lead EML onto the substrate F100. In other words, the light-emitting control lead EML can overlap with the channel region M7Act of the seventh transistor M7, so that the overlapping portion can be reused as the gate of the seventh transistor M7.

[0190] The first gate layer Gate1 may be provided with the gate of the fifth transistor M5, and the gate of the fifth transistor M5 is connected to the first reset lead RL1, so that the fifth transistor M5 can be turned on in response to the first reset signal Re_P. In one embodiment of this disclosure, see... Figure 6 The first reset lead RL1 can overlap with the channel region M5Act of the fifth transistor M5, so that the overlapping portion is reused as the gate of the fifth transistor M5. Exemplarily, the orthographic projections of the first subchannel region and the second subchannel region on the substrate are located within the orthographic projection of the first reset lead RL1 on the substrate.

[0191] The first gate layer Gate1 may be provided with the gate of the eighth transistor M8, and the gate of the eighth transistor M8 is connected to the first reset lead RL1, so that the eighth transistor M8 can be turned on in response to the first reset signal Re_P. In one embodiment of this disclosure, see... Figure 6 The orthographic projection of the channel region Act of the eighth transistor M8 onto the substrate F100 lies within the orthographic projection of the first reset lead RL1 onto the substrate F100. In other words, the first reset lead RL1 can overlap with the channel region M8Act of the eighth transistor M8, so that the overlapping portion can be reused as the gate of the eighth transistor M8.

[0192] The first electrode plate CP1 can cover the channel region M3Act of the driving transistor M3, so as to be reused as the gate of the driving transistor M3. Thus, the first electrode plate CP1 can serve as part of the first node N1. In one embodiment of this disclosure, see [link to relevant documentation]. Figure 6 The first electrode plate CP1 is located near the fourth conductive lead PL4 on the first row direction H11 side. It extends in the column direction H2 towards the first column direction H21 and the second column direction H22. This can maximize the area of ​​the first electrode plate CP1, thereby increasing the capacitance value of the storage capacitor Cst.

[0193] In one embodiment of this disclosure, see Figure 5 The first electrode plate CP1 may have a thirteenth bottom via region HA13, which is used for electrical connection with the third electrode plate CP3 through the via. Further, the first electrode plate CP1 may have a protrusion on the side near L1, which is located on the side of the first column direction H21 of the third conductive lead PL3; the thirteenth bottom via region HA13 is located on this protrusion.

[0194] Optionally, in the pixel driving region SubA, the first scan lead GL1, the first electrode plate CP1, the light emission control lead EML, and the first reset lead RL1 are arranged sequentially along the first column direction H21.

[0195] Optionally, the gate of the fourth transistor M4 includes the first gate of the fourth transistor M4 located in the first gate layer Gate1. See also Figure 5 The first gate layer Gate1 may also be provided with a second reset lead RL2 for loading the second reset signal Re_N. The second reset lead RL2 is electrically connected to the first gate of the fourth transistor M4, so that the second reset signal Re_N can be loaded onto the first gate of the fourth transistor M4, enabling the fourth transistor M4 to turn on in response to the second reset signal Re_N. Furthermore, the second reset lead RL2 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same second reset lead RL2.

[0196] In one embodiment of this disclosure, the fourth transistor M4 may be a metal-oxide-semiconductor transistor. See also Figure 7 The channel region M4Act of the fourth transistor M4 is located in the metal-oxide-semiconductor layer Oxide; the orthogonal projection of the channel region M4Act onto the first gate layer Gate1 can lie entirely within the first gate of the fourth transistor M4. Thus, the first gate of the fourth transistor M4 can block light from the substrate side from illuminating the channel region M4Act, preventing this light from increasing the leakage current of the fourth transistor M4 in the off state.

[0197] In one embodiment of this disclosure, see Figure 11 The second reset lead RL2 can overlap with the channel region M4Act of the fourth transistor M4 located in the metal-oxide-semiconductor layer Oxide, so as to be reused as the first gate of the fourth transistor M4. For example, see [link to example]. Figure 5 Along the row direction H1, the second reset lead RL2 may include an alternately arranged and sequentially connected third lead segment RL21 and fourth lead segment RL22. The dimension of the third lead segment RL21 in the column direction H2 is larger than the dimension of the fourth lead segment RL22 in the column direction H2. The orthogonal projection of the channel region M4Act of the fourth transistor M4 onto the first gate layer Gate1 can lie entirely within the third lead segment RL21, such that a portion of the third lead segment RL21 can serve as the first gate of the fourth transistor M4.

[0198] Optionally, the gate of the second transistor M2 includes the first gate of the second transistor M2 located in the first gate layer Gate1. See also Figure 5The first gate layer Gate1 may also be provided with a second scan lead GL2 for loading the second scan signal Gate_N. The second scan lead GL2 is electrically connected to the first gate of the second transistor M2, so that the second scan signal Gate_N can be loaded onto the first gate of the second transistor M2, enabling the second transistor M2 to conduct in response to the second scan signal Gate_N. Furthermore, the second scan lead GL2 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same second scan lead GL2.

[0199] In one embodiment of this disclosure, the second transistor M2 may be a metal-oxide-semiconductor transistor. See also Figure 7 The channel region M2Act of the second transistor M2 is located in the metal-oxide-semiconductor layer Oxide. The orthogonal projection of the channel region M2Act of the second transistor M2 onto the first gate layer Gate1 can lie entirely within the first gate of the second transistor M2. In this way, the first gate of the second transistor M2 can block light from the substrate side from illuminating the channel region M2Act of the second transistor M2, preventing the leakage current of the second transistor M2 from increasing in the off state due to such illumination.

[0200] In one embodiment of this disclosure, see Figure 11 The second scan lead GL2 can overlap with the channel region M2Act of the second transistor M2 located in the metal-oxide-semiconductor layer Oxide, so as to be multiplexed as the first gate of the second transistor M2. For example, see [link to example]. Figure 5 Along the row direction H1, the second scan lead GL2 may include an alternately arranged and sequentially connected first lead segment GL21 and second lead segment GL22, wherein the dimension of the first lead segment GL21 in the column direction H2 is larger than the dimension of the second lead segment GL22 in the column direction H2. See also... Figure 11 The orthogonal projection of the channel region M2Act of the second transistor M2 onto the first gate layer Gate1 can be completely located within the first lead segment GL21, so that a portion of the first lead segment GL21 can serve as the first gate of the second transistor M2.

[0201] In one embodiment of this disclosure, in the pixel driving region SubA, the second reset lead RL2, the second scan lead GL2, the first scan lead GL1, the first electrode plate CP1, the light emission control lead EML, and the first reset lead RL1 are arranged sequentially along the first column direction H21.

[0202] In some embodiments of this disclosure, see Figure 23The driving circuit layer F200 may include a second buffer layer Buffer2 and a metal-oxide-semiconductor layer Oxide, which are sequentially stacked on the side of the first gate layer Gate1 away from the substrate F100. Thus, the pixel driving circuit of this disclosure can be configured with a metal-oxide transistor, and the channel region of the transistor is located in the metal-oxide-semiconductor layer Oxide.

[0203] Optionally, the fourth transistor M4 can be a metal-oxide-semiconductor (MOD) transistor. The active layer of the fourth transistor M4 is located on the MOD semiconductor layer and includes a first electrode, a channel region M4Act, and a second electrode connected in sequence. That is, the second electrode and the first electrode of the fourth transistor M4 are located on both sides of the channel region M4Act of the fourth transistor M4, and the second electrode and the first electrode of the fourth transistor M4 can be conductive metal oxides, while the channel region M4Act of the fourth transistor M4 retains semiconductor characteristics.

[0204] Optionally, see Figure 7 The first electrode, the channel region M4Act, and the second electrode of the fourth transistor M4 are arranged along the first column direction H21. The first electrode of the fourth transistor M4 has a ninth bottom via region HA9, which is used to electrically connect to the initialization signal lead ViL through the via, so that the initialization voltage Vinit can be applied to the first electrode of the fourth transistor M4. The second electrode of the fourth transistor M4 has a tenth bottom via region HA10, which is used to electrically connect to the third electrode plate CP3 through the via.

[0205] In one embodiment of this disclosure, two initialization signal leads ViL extending along the row direction H1 pass through a pixel driving region SubA. One initialization signal lead ViL is located at one end of the pixel driving region in the first column direction H21, and the other is located at one end of the pixel driving region in the second column direction H22. Within a pixel driving region SubA, the ninth bottom via region HA9 of the pixel driving circuit in SubA can be electrically connected to the initialization signal lead ViL located at the second column direction H22 via a via, and the eighth bottom via region HA8 of the pixel driving circuit in SubA can be electrically connected to the initialization signal lead ViL located at the first column direction H21 via a via. Correspondingly, two adjacent pixel driving regions SubA along column direction H2 have an overlapping area, and an initialization signal lead ViL is provided in the overlapping area. The initialization signal lead ViL is shared by the pixel driving circuits in the two adjacent pixel driving regions SubA; that is, the initialization signal lead ViL is the initialization signal lead ViL located at one end of the first column direction H21 in the previous pixel driving region SubA, and is the initialization signal lead ViL located at one end of the second column direction H22 in the next pixel driving region SubA.

[0206] Optionally, the second transistor M2 can be a metal-oxide-semiconductor transistor. The active layer of the second transistor M2 is located on the metal-oxide-semiconductor layer Oxide, and includes a first electrode, a channel region M2Act, and a second electrode connected in sequence. That is, the second electrode of the second transistor M2 and the first electrode of the second transistor M2 are located on both sides of the channel region M2Act of the second transistor M2. The second electrode of the second transistor M2 and the first electrode of the second transistor M2 can be conductive metal oxide, and the channel region M2Act of the second transistor M2 maintains semiconductor characteristics.

[0207] Optionally, see Figure 7 The first electrode of the second transistor M2, the channel region M2Act of the second transistor M2, and the second electrode of the second transistor M2 are arranged along the second column direction H22. The second electrode of the second transistor M2 has an eleventh bottom via region HA11, which is used for electrical connection to the third electrode plate CP3 through the via. The first electrode of the second transistor M2 has a twelfth bottom via region HA12, which is used for electrical connection to the fourth conductive lead PL4 through the via.

[0208] In one embodiment of this disclosure, in the pixel driving region SubA, the channel region M4Act of the fourth transistor M4 and the channel region M2Act of the second transistor M2 are located on the side of the second column direction H22 of the first scan lead GL1, and the channel region M4Act of the fourth transistor M4 is located on the side of the second column direction H22 of the channel region M2Act of the second transistor M2.

[0209] In some embodiments of this disclosure, see Figure 23 The driving circuit layer F200 may also be provided with a second gate insulating layer GI2 and a second gate layer Gate2 stacked sequentially on the side of the metal oxide semiconductor layer Oxide away from the substrate F100, and the interlayer dielectric layer ILD is located on the side of the second gate layer Gate2 away from the substrate.

[0210] See Figure 8 The second gate layer Gate2 may be provided with a second electrode plate CP2, which partially overlaps with the first electrode plate CP1. In one embodiment of this disclosure, see... Figure 10 The second electrode plate CP2 has a notch that exposes the thirteenth bottom via region HA13, such that the orthogonal projection of the second electrode plate CP2 onto the first gate layer Gate1 does not coincide with the thirteenth bottom via region HA13. Thus, the thirteenth bottom via region HA13 can be connected to the third electrode plate CP3 via this notch. Furthermore, this notch is located on the second row direction H12 side of the second electrode plate CP2.

[0211] See Figure 8 The second electrode plate CP2 may have a seventeenth bottom via region HA17, which is used to electrically connect to the fourth electrode plate CP4 through the via. Thus, the storage capacitor Cst includes a first electrode plate CP1, a second electrode plate CP2, a third electrode plate CP3, and a fourth electrode plate CP4 stacked sequentially. The first electrode plate CP1 and the third electrode plate CP3 are electrically connected through a via, and the second electrode plate CP2 and the fourth electrode plate CP4 are electrically connected through a via. In one embodiment of this disclosure, see... Figure 8 The second electrode plate CP2 has a fourth protrusion Hump4, and a seventeenth bottom via region HA17 is disposed on the fourth protrusion Hump4. Further, the fourth protrusion Hump4 does not overlap with the first electrode plate CP1. For example, the fourth protrusion Hump4 is disposed on the first column direction H21 side of the second electrode plate CP2 and on the second row direction H12 side, and it can extend to overlap with the channel region M6Act of the sixth transistor M6.

[0212] Optionally, the gate of the fourth transistor M4 includes the second gate of the fourth transistor M4 located in the second gate layer Gate2. See also Figure 8The second gate layer (Gate2) may also be provided with a third reset lead RL3 for loading the second reset signal Re_N. The third reset lead RL3 is electrically connected to the second gate of the fourth transistor M4, so that the second reset signal Re_N can be loaded onto the second gate of the fourth transistor M4, enabling the fourth transistor M4 to turn on in response to the second reset signal Re_N. Furthermore, the third reset lead RL3 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same third reset lead RL3.

[0213] In one embodiment of this disclosure, the fourth transistor M4 can be a metal-oxide-semiconductor (MOD) transistor. The channel region M4Act of the fourth transistor M4 is located in the MOD layer, and the orthogonal projection of the channel region M4Act onto the second gate layer Gate2 can coincide with the second gate of the fourth transistor M4. Further, the third reset lead RL3 can overlap with the channel region M4Act of the fourth transistor M4 located in the MOD layer, thereby multiplexing it as the second gate of the fourth transistor M4. For example, see [link to example]. Figure 9 and Figure 11 The third reset lead RL3 extends along the row direction H1 and overlaps with the active layer of the fourth transistor M4; the portion of the third reset lead RL3 overlapping with the active layer of the fourth transistor M4 can be reused as the second gate of the fourth transistor M4; the portion of the active layer of the fourth transistor M4 overlapping with the third reset lead RL3 can be used as the channel region M4Act of the fourth transistor M4.

[0214] In one embodiment of this disclosure, the gate of the fourth transistor M4 includes a first gate of the fourth transistor M4 located in the first gate layer Gate1 and a second gate of the fourth transistor M4 located in the second gate layer Gate2. Thus, the fourth transistor M4 presents a dual-gate structure, which can eliminate the influence of the floating body effect and reduce the leakage current in the off state.

[0215] Optionally, the gate of the second transistor M2 includes a second gate located in the second gate layer Gate2. See also Figure 8 The second gate layer Gate2 may also be provided with a third scan lead GL3 for loading the second scan signal Gate_N. The third scan lead GL3 is electrically connected to the second gate of the second transistor M2, so that the second scan signal Gate_N can be loaded onto the second gate of the second transistor M2, enabling the second transistor M2 to conduct in response to the second scan signal Gate_N. Furthermore, the third scan lead GL3 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same third scan lead GL3.

[0216] In one embodiment of this disclosure, the second transistor M2 can be a metal-oxide-semiconductor (MOD) transistor, the channel region M2Act of the second transistor M2 is located in the MOD semiconductor layer Oxide, and the orthogonal projection of the channel region M2Act onto the second gate layer Gate2 can coincide with the second gate of the second transistor M2. Further, see... Figure 11 The third scan lead GL3 can overlap with the channel region M2Act of the second transistor M2 disposed on the metal-oxide-semiconductor layer Oxide, so as to be reused as the second gate of the second transistor M2. For example, the third scan lead GL3 extends along the row direction H1 and overlaps with the active layer of the second transistor M2; the portion of the third scan lead GL3 overlapping with the active layer of the second transistor M2 can be reused as the second gate of the second transistor M2; the portion of the active layer of the second transistor M2 overlapping with the third scan lead GL3 can serve as the channel region M2Act of the second transistor M2.

[0217] In one embodiment of this disclosure, the gate of the second transistor M2 includes a first gate of the second transistor M2 located in the first gate layer Gate1 and a second gate of the second transistor M2 located in the second gate layer Gate2. Thus, the second transistor M2 presents a dual-gate structure, which can eliminate the influence of the floating body effect and reduce the leakage current in the off state.

[0218] Optionally, see Figure 8 The second gate layer (Gate2) may also be provided with power distribution leads (VDDGL) extending along the row direction (H1). These power distribution leads (VDDGL) can be electrically connected to one or more first power supply voltage leads (VDDL) of the display panel. This allows the traces conducting the first power supply voltage (VDD) to be meshed, reducing the voltage drop during VDD transmission and improving the uniformity of the first power supply voltage (VDD) at different locations.

[0219] In one embodiment of this disclosure, in the pixel driving region SubA, the power distribution lead VDDGL is disposed between the third scan lead GL3 and the second electrode plate CP2.

[0220] In one embodiment of this disclosure, the power distribution lead VDDGL extends along the row direction H1 and is electrically connected to each of the first power supply voltage leads VDDL extending along the column direction H2.

[0221] Optionally, in the pixel-driving region SubA, see Figure 8 and Figure 10The second gate layer (Gate2) may also have a first metal wiring structure (ML1) extending along the column direction (H2) and at least partially overlapping the first conductive lead (PL1). The first metal wiring structure (ML1) can be electrically connected to the first power supply voltage lead (VDDL), allowing the first power supply voltage (VDD) to be applied to it. This allows a constant voltage signal to be applied to the first metal wiring structure (ML1), stabilizing the voltage on the first conductive lead (PL1) and preventing interference from other signals, particularly shielding the voltage on the data lead (DataL), thus reducing longitudinal (column direction H2) crosstalk in the display panel. Furthermore, a parasitic capacitance can be formed between the first metal wiring structure (ML1) and the data lead (DataL), increasing the parasitic capacitance of DataL. This helps DataL retain its charge and improves its charging capability for the storage capacitor (Cst), thereby improving the accuracy of writing data into the storage capacitor (Cst) and making the display panel more suitable for De-Mux driving.

[0222] In one embodiment of this disclosure, both the first metallic wiring structure ML1 and the first conductive lead PL1 extend along the column direction H2; the orthographic projection of the first conductive lead PL1 in the row direction H1 lies within the orthographic projection of the first metallic wiring structure ML1 in the row direction H1. Thus, the width of the first metallic wiring structure ML1 is greater than the width of the first conductive lead PL1, which better conceals the first conductive lead PL1. Furthermore, in the column direction H2, the first metallic wiring structure ML1 exposes the second bottom via region HA2 and covers the remaining portion of the first conductive lead PL1.

[0223] In one embodiment of this disclosure, see Figure 8 The first metal wiring structure ML1 has a fourteenth bottom via region HA14, which is used to electrically connect to the first power supply voltage lead VDDL through the via. Further, one end of the second column direction H22 of the first metal wiring structure ML1 is connected to the power distribution lead VDDGL, so that the power distribution lead VDDGL is electrically connected to the first power supply voltage lead VDDL via the first metal wiring structure ML1.

[0224] See Figure 12The first metal wiring layer SD1 may include a third electrode plate CP3, an initialization signal lead ViL, and a reference voltage lead VrL. The initialization signal lead ViL extends along the row direction H1 and is used to apply an initialization voltage Vinit. The reference voltage lead VrL extends along the row direction H1 and is used to apply a reference voltage Vref. The third electrode plate CP3 may at least partially overlap with the second electrode plate CP2 and is electrically connected to the first electrode plate CP1 through a via.

[0225] Optionally, see Figure 12 and Figure 13 The initialization signal lead ViL has an eighth top via region HB8 and a ninth top via region HB9. The eighth top via region HB8 and the eighth bottom via region HA8 can be directly connected through vias, so that the first electrode of the eighth transistor M8 is connected to the initialization signal lead ViL through vias; the ninth top via region HB9 and the ninth bottom via region HA9 can be directly connected through vias, so that the first electrode of the fourth transistor M4 is connected to the initialization signal lead ViL through vias.

[0226] Optionally, see Figure 12 and Figure 13 The reference voltage lead VrL has a third top via region HB3, and the third top via region HB3 and the third bottom via region HA3 can be directly connected through a via. Further, see... Figure 12 and Figure 17 The reference voltage lead VrL has a first protrusion Hump1, which extends along the column direction H2 and can overlap with the data lead DataL located in the second metal wiring layer SD2. This creates a larger parasitic capacitance between the data lead DataL and the reference voltage lead VrL, which is beneficial for driving the display panel using the De-Mux method.

[0227] In one embodiment of this disclosure, the reference voltage lead VrL partially overlaps with the first reset lead RL1, and the first protrusion Hump1 extends along the second column direction H22 to overlap with the third bottom via region HA3; the third top via region HB3 is located at one end of the first protrusion Hump1 in the second column direction H22.

[0228] Optionally, see Figure 12 and Figure 13 The third electrode plate CP3 may have a thirteenth top via region HB13, which can be directly connected to the thirteenth bottom via region HA13 via a via, thus connecting the third electrode plate CP3 and the first electrode plate CP1 through a via. In one embodiment of this disclosure, the third electrode plate CP3 may be provided with a protrusion extending toward the second row direction H12, and the thirteenth top via region HB13 is disposed on the protrusion.

[0229] Optionally, see Figure 12 The first metal wiring layer SD1 may also have a second metal wiring structure ML2, which is disposed between the third electrode plate CP3 and the reference voltage lead VrL. The second metal wiring structure ML2 may have a second top via region HB2, a fourth top via region HB4, and a seventeenth top via region HB17. See also... Figure 13 The second top via region HB2 and the second bottom via region HA2 are directly connected vias, the fourth top via region HB4 and the fourth bottom via region HA4 are directly connected vias, and the seventeenth top via region HB17 and the seventeenth bottom via region HA17 are directly connected vias. Thus, the second metal wiring structure ML2 electrically connects the second electrodes of the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the second electrode plate CP2, forming part of the second node N2 of the pixel driving circuit.

[0230] Further, see Figure 12 The second metal wiring structure ML2 may also have an eighteenth bottom via region HA18. The eighteenth bottom via region HA18 is used for electrical connection with the fourth electrode plate CP4 through the via. In this way, the second electrode plate CP2 and the fourth electrode plate CP4 can be electrically connected through the second metal wiring structure ML2, so that the second electrode plate CP2 and the fourth electrode plate CP4 are connected to the second node N2 of the pixel driving circuit.

[0231] Optionally, see Figure 12 The first metal wiring layer SD1 may also be provided with a third metal wiring structure ML3. The orthographic projection of the third metal wiring structure ML3 onto the substrate partially coincides with the orthographic projection of the data lead DataL onto the substrate and the orthographic projection of the third conductive lead PL3 onto the substrate; in other words, the third metal wiring structure ML3 overlaps with the third conductive lead PL3 and the first metal wiring structure ML1. See also... Figure 12 The third metal wiring structure ML3 has a fifth top via region HB5, a fourteenth top via region HB14, and a sixteenth bottom via region HA16. See [link to relevant documentation]. Figure 13The fifth top via region HB5 and the fifth bottom via region HA5 are directly connected via a via, allowing the third metal wiring structure ML3 to connect to the first electrode of the driving transistor M3 via a via. The fourteenth top via region HB14 and the fourteenth bottom via region HA14 are directly connected via a via, allowing the third metal wiring structure ML3 to connect to the first metal wiring structure ML1 via a via. The sixteenth bottom via region HA16 is used to electrically connect to the first power supply voltage lead VDDL via a via, so that the first power supply voltage VDD applied on the first power supply voltage lead VDDL is applied to the first metal wiring structure ML1, the power distribution lead VDDGL, and the first electrode of the driving transistor M3 through the third metal wiring structure ML3.

[0232] Optionally, see Figure 12 The first metal wiring layer SD1 may also be provided with a fourth metal wiring structure ML4, which has a first top via area HB1 and a fifteenth bottom via area HA15. See also Figure 13 The first top via region HB1 and the first bottom via region HA1 are directly connected via a via. The fifteenth bottom via region HA15 is used to electrically connect to the data lead DataL via a via, so that the Data loaded on the data lead DataL is loaded to the first electrode of the first transistor M1 through the fourth metal wiring structure ML4. Further, the fourth metal wiring structure ML4 is located on the second column direction H22 side of the third metal wiring structure ML3.

[0233] Optionally, see Figure 12 The first metal wiring layer SD1 may also have a fifth metal wiring structure ML5. The fifth metal wiring structure ML5 overlaps with the tenth bottom via region HA10 and the eleventh bottom via region HA11, and is connected to the third electrode plate CP3. The fifth metal wiring structure ML5 has a tenth top via region HB10 and an eleventh top via region HB11. See also... Figure 13The tenth top via region HB10 and the tenth bottom via region HA10 are directly connected via a via, which allows the fifth metal wiring structure ML5 to connect to the second electrode of the fourth transistor M4 via a via. Similarly, the eleventh top via region HB11 and the eleventh bottom via region HA11 are directly connected via a via, which allows the fifth metal wiring structure ML5 to connect to the second electrode of the second transistor M2 via a via. Thus, the second electrodes of the fourth transistor M4 and the second electrodes of the second transistor M2 are electrically connected to the third electrode plate CP3 and the first electrode plate CP1 through the fifth metal wiring structure ML5, thereby connecting the second electrodes of the fourth transistor M4 and the second electrodes of the second transistor M2 to the first node N1 of the pixel driving circuit through the fifth metal wiring structure ML5. Furthermore, the fifth metal wiring structure ML5 extends generally along the column direction H2, and the third metal wiring structure ML3 and the fourth metal wiring structure ML4 are located on the second row direction H12 side of the fifth metal wiring structure ML5.

[0234] Optionally, see Figure 14 The first scanning lead GL1 overlaps with the fifth metal wiring structure ML5, meaning that the orthographic projection of the first scanning lead GL1 on the substrate F100 at least partially coincides with the orthographic projection of the fifth metal wiring structure ML5 on the substrate F100. Thus, although the second scanning signal Gate_N affects the electromotive force of the third electrode plate CP3 (first node N1) through coupling with the fifth metal wiring structure ML5, the first scanning signal Gate_P loaded on the first scanning lead GL1 can exert an opposite coupling effect on the fifth metal wiring structure ML5. This causes the effects of the second scanning signal Gate_N and the first scanning signal Gate_P on the electromotive force of the first node N1 to cancel each other out, improving the accuracy of the electromotive force at the first node N1, especially improving the display accuracy of the pixel driving circuit for low grayscale images. For example, the display panel may be provided with a second scan lead GL2 or a third scan lead GL3 for loading the second scan signal Gate_N, and the second scan lead GL2 or the third scan lead GL3 overlaps with the fifth metal wiring structure ML5, and the first scan lead GL1 for loading the first scan signal Gate_P overlaps with the fifth metal wiring structure ML5.

[0235] It is understood that the magnitude of the coupling capacitance formed by the overlap of the first scan lead GL1 and the fifth metal wiring structure ML5 is such that it can offset or minimize the coupling effect of the second scan signal Gate_N on the fifth metal wiring structure ML5. In one embodiment of this disclosure, see... Figure 15The first scan lead GL1 may be provided with a second protrusion Hump2; the orthographic projection of the second protrusion Hump2 on the substrate F100 at least partially coincides with the orthographic projection of the fifth metal wiring structure ML5 on the substrate F100. In other words, part or all of the second protrusion Hump2 may overlap with the fifth metal wiring structure ML5 to increase the overlap area between the first scan lead GL1 and the fifth metal wiring structure ML5, thereby improving the coupling effect of the first scan lead GL1 to the fifth metal wiring structure ML5. Furthermore, the second protrusion Hump2 may be located on the second column direction H22 side of the first scan lead GL1.

[0236] In one embodiment of this disclosure, at least a portion of the area where the first scanning lead GL1 overlaps with the fifth metal wiring structure ML5 may not overlap with the power distribution lead VDDGL, thereby overcoming the shielding effect of the power distribution lead VDDGL on the first scanning lead GL1.

[0237] In one embodiment of this disclosure, the fifth metal wiring structure ML5 may be partially bent to avoid the twelfth bottom via area HA12.

[0238] Optionally, see Figure 12 The first metal wiring layer SD1 may also include a sixth metal wiring structure ML6. The sixth metal wiring structure ML6 overlaps with the fourth conductive lead PL4 and the twelfth bottom via region HA12, and has a sixth top via region HB6 and a twelfth top via region HB12. See also... Figure 13 The sixth top via region HB6 and the sixth bottom via region HA6 are directly connected vias, allowing the sixth metal wiring structure ML6 to connect to the fourth conductive lead PL4 vias. Similarly, the twelfth top via region HB12 and the twelfth bottom via region HA12 are directly connected vias, allowing the sixth metal wiring structure ML6 to connect to the first electrode of the second transistor M2 vias. Thus, the first electrode of the second transistor M2 is connected to the second electrode of the driving transistor M3 via the sixth metal wiring structure ML6, enabling the sixth metal wiring structure ML6 to function as part of the third node N3 of the pixel driving circuit. Furthermore, the sixth metal wiring structure ML6 is located on the first row direction H11 side of the fifth metal wiring structure ML5.

[0239] Optionally, see Figure 12 The first metal wiring layer SD1 may also have a seventh metal wiring structure ML7, which overlaps with the seventh bottom via area HA7 and has a seventh top via area HB7 and a nineteenth bottom via area HA19. See also Figure 13The seventh top via region HB7 and the seventh bottom via region HA7 are directly connected vias to electrically connect the seventh metal wiring structure ML7 to the second electrode of the seventh transistor M7. The nineteenth bottom via region HA19 is used to connect to the light-emitting element 170 vias. Further, the seventh metal wiring structure ML7 is located between the third electrode plate CP3 and the reference voltage lead VrL, and extends along the row direction H1.

[0240] See Figure 16 The second metal wiring layer SD2 may be provided with data leads DataL and a first power supply voltage lead VDDL extending along the column direction H2, and a fourth electrode plate CP4. In one embodiment of this disclosure, the data leads DataL, the first power supply voltage lead VDDL, and the fourth electrode plate CP4 are arranged sequentially along the first row direction H11.

[0241] Optionally, see Figure 16 The data lead DataL has a fifteenth top via region HB15; see [link / reference] Figure 17 The fifteenth top via region HB15 and the fifteenth bottom via region HA15 are directly connected via a via. Thus, the data lead DataL is electrically connected to the first electrode of the first transistor M1 through the fourth metal wiring structure ML4.

[0242] Optionally, see Figure 16 The first power supply voltage lead VDDL has a sixteenth top via region HB16; see also Figure 17 The sixteenth top via region HB16 and the sixteenth bottom via region HA16 are directly connected through vias. In this way, the first power supply voltage lead VDDL distributes the first power supply voltage VDD to the first metal wiring structure ML1 and the power distribution lead VDDGL through the third metal wiring structure ML3.

[0243] Optionally, see Figure 16 The first power supply voltage lead VDDL has a third protrusion Hump3. The orthographic projection of the third protrusion Hump3 onto the substrate F100 covers the orthographic projections of the channel region M2Act of the second transistor M2 and the channel region M4Act of the fourth transistor M4 onto the substrate F100. In other words, the third protrusion Hump3 covers the channel regions M2Act of the second transistor M2 and M4Act of the fourth transistor M4 to shield the second transistor M2 and the fourth transistor M4 from interference by external light and electromagnetic signals, especially to prevent light from shining on the second transistor M2 and the fourth transistor M4, which would increase the leakage current of the second transistor M2 and the fourth transistor M4 in the off state.

[0244] Optionally, see Figure 16The fourth electrode plate CP4 has an eighteenth top via region HB18. See also... Figure 17 The eighteenth top via region HB18 and the eighteenth bottom via region HA18 are directly connected vias. Thus, the fourth electrode plate CP4 is electrically connected to the second electrode plate CP2 through the second metal wiring structure ML2. Further, see... Figure 16 Along the row direction H1, the eighteenth top via area HB18 is located on the side of the second row direction H12 of the fourth electrode plate CP4; along the column direction H2, the eighteenth top via area HB18 is located on the side of the first column direction H21 of CP.

[0245] Optionally, see Figure 16 The second metal wiring layer SD2 may also include an eighth metal wiring structure ML8. The eighth metal wiring structure ML8 at least partially overlaps with the seventh metal wiring structure ML7, wherein the eighth metal wiring structure ML8 has a nineteenth top via area HB19 and a transition via area HAP. See also Figure 17 and Figure 20 The nineteenth top via region HB19 and the nineteenth bottom via region HA19 are directly connected vias, so that the eighth metal wiring structure ML8 is electrically connected to the second electrode of the seventh transistor M7 through the seventh metal wiring structure ML7. The transition via region HAP is used to electrically connect to the pixel electrode of the light-emitting element 170 vias. Further, the eighth metal wiring structure ML8 is located on the first row direction H11 side of the first power supply voltage lead VDDL and on the first column direction H21 side of the fourth electrode plate CP4. It can be understood that the shape of the eighth metal wiring structure ML8 of each pixel driving circuit can be the same or different.

[0246] Optionally, the pixel layer F300 can be disposed on the side of the driving circuit layer F200 away from the substrate F100, and it may include a pixel electrode layer F310. The pixel electrode layer F310 may form pixel electrodes with light-emitting elements, and each light-emitting element can serve as a sub-pixel of the display panel of this disclosure. The pixel electrodes of the light-emitting elements can be connected to the transition via area HAP through vias, so that the second electrode of the seventh transistor M7 is electrically connected to the light-emitting element 170. The light-emitting element can be an OLED (organic light-emitting diode), LED (light-emitting diode), Mini LED (mini light-emitting diode), Micro LED (micro light-emitting diode), OLED-QD (organic light-emitting diode-quantum dot), or other types of electroluminescent devices.

[0247] In one embodiment of this disclosure, the pixel layer includes a red light-emitting element, a green light-emitting element, and a blue light-emitting element. See also Figure 21 and Figure 22The pixel electrodes in the pixel electrode layer F310 may include the pixel electrode PR of the red light-emitting element, the pixel electrode PG of the green light-emitting element, and the pixel electrode PB of the blue light-emitting element; each pixel electrode is connected to the corresponding pixel driving circuit's via area HAP.

[0248] The following description uses an OLED as an example to illustrate the structure of the pixel layer F300. It is understood that the structure of the pixel layer F300 can also be other structures, as long as they provide the light-emitting element 170.

[0249] In this exemplary pixel layer F300, the pixel layer F300 includes a pixel electrode layer, a pixel definition layer, a support pillar layer, an organic light-emitting functional layer, and a common electrode layer stacked sequentially. The pixel electrode layer has multiple pixel electrodes in the display area of ​​the display panel; the pixel definition layer has multiple through-holes in the display area, each corresponding to one of the multiple pixel electrodes, with each pixel opening exposing at least a portion of the corresponding pixel electrode. The support pillar layer includes multiple support pillars in the display area, and the support pillars are located on the surface of the pixel definition layer away from the substrate, so as to support a fine metal mask (FMM) during the evaporation process. The organic light-emitting functional layer at least covers the pixel electrodes exposed by the pixel definition layer. The organic light-emitting functional layer may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. The various films of the organic light-emitting functional layer can be prepared by an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation. The common electrode layer can cover the organic light-emitting functional layer in the display area. In this way, the pixel electrode, the common electrode layer, and the organic light-emitting functional layer located between the pixel electrode and the common electrode layer form an organic light-emitting diode (OLED), and any one of the OLEDs can serve as a sub-pixel of the display panel.

[0250] In some embodiments, the pixel layer may further include a light extraction layer located on the side of the common electrode layer away from the substrate to enhance the light extraction efficiency of the organic light-emitting diode.

[0251] Optionally, see Figure 23The display panel may further include a thin-film encapsulation layer F400. The thin-film encapsulation layer is disposed on the surface of the pixel layer away from the substrate and may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer away from the substrate.

[0252] Optionally, see Figure 23 The display panel may also include a touch function layer F500, which is located on the side of the thin film encapsulation layer away from the substrate and is used to realize touch operation of the display panel.

[0253] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A pixel driving circuit, comprising: a driving transistor connected to a first node and a third node; a storage capacitor connected to the first node and a second node; a data writing unit connected to the second node, configured to output a data voltage to the second node in response to a first scan signal; a light emitting control unit connected to the third node and a fourth node, configured to enable electrical communication between the third node and the fourth node in response to a light emitting control signal; a first reset unit connected to the second node, configured to output a reference voltage to the second node in response to the light emitting control signal or a first reset signal; a second reset unit connected to the first node, configured to output an initialization voltage to the first node in response to a second reset signal; wherein the driving transistor comprises a first electrode for loading a first power voltage, a second electrode connected to the third node, and a gate electrode connected to the first node; the data writing unit comprises a first transistor comprising a first electrode for loading the data voltage, a second electrode connected to the second node, and a gate electrode for loading the first scan signal; the pixel driving circuit is arranged on one side of a substrate of a display panel; the display panel comprises a second gate layer, a first metal wiring layer, and a second metal wiring layer arranged on the one side of the substrate in sequence; the display panel comprises a data lead line and a first power voltage lead line extending along a column direction; the data lead line is connected to the first electrode of the first transistor; the first power voltage lead line is electrically connected to the first electrode of the driving transistor; the pixel driving circuit comprises a first metal wiring structure which is electrically connected to the first power voltage lead line and is arranged in an insulating manner with the data lead line; a normal projection of the data lead line on the substrate at least partially overlaps a normal projection of the first metal wiring structure on the substrate; the display panel further comprises a power distribution lead line extending along a row direction; the power distribution lead line and the first metal wiring structure are both arranged on the second gate layer and are directly connected.

2. The pixel driving circuit according to claim 1, wherein the pixel driving circuit further comprises: a third reset unit connected to the fourth node, configured to output the initialization voltage to the fourth node in response to the first reset signal.

3. The pixel driving circuit of claim 1, wherein, the pixel driving circuit further comprises a threshold compensation unit connected to the first node and the third node, configured to enable electrical communication between the first node and the third node in response to a second scan signal; the threshold compensation unit comprises: a second transistor comprising a first electrode connected to the third node, a second electrode connected to the first node, and a gate electrode for loading the second scan signal; the second reset unit comprises: a fourth transistor comprising a first electrode for loading the initialization voltage, a second electrode connected to the first node, and a gate electrode for loading the second reset signal. Materials of active layers of the second transistor and the fourth transistor are metal oxide semiconductor materials.

4. The pixel driving circuit of claim 3, wherein, The gate of the second transistor includes a first gate and a second gate both for loading the second scanning signal, and the active layer of the second transistor includes a channel region; the first gate, the channel region and the second gate of the second transistor are sequentially stacked. The gate of the fourth transistor includes a first gate and a second gate both for loading the second reset signal, and the active layer of the fourth transistor includes a channel region; the first gate, the channel region and the second gate of the fourth transistor are sequentially stacked.

5. The pixel driving circuit of claim 4, wherein, The pixel driving circuit is arranged on one side of the substrate. The first gate of the second transistor is located on the side of the channel region of the second transistor close to the substrate; the orthographic projection of the second gate of the second transistor on the substrate is located within the orthographic projection of the first gate of the second transistor on the substrate. The first gate of the fourth transistor is located on the side of the channel region of the fourth transistor close to the substrate; the orthographic projection of the second gate of the fourth transistor on the substrate is located within the orthographic projection of the first gate of the fourth transistor on the substrate.

6. The pixel driving circuit of claim 1, wherein, The pixel driving circuit is arranged on one side of the substrate. The storage capacitor includes a first electrode plate, a second electrode plate, a third electrode plate and a fourth electrode plate sequentially stacked on one side of the substrate, and an insulating medium is arranged between any two adjacent electrode plates; the first electrode plate and the third electrode plate are electrically connected with the first node; and the second electrode plate and the fourth electrode plate are electrically connected with the second node.

7. The pixel driving circuit of claim 6, wherein, The pixel driving circuit is applied to a display panel, and the display panel includes the substrate. The display panel further includes a first passivation layer and a first planarization layer sequentially stacked on the side of the third electrode plate away from the substrate, and the fourth electrode plate is arranged on the side of the first planarization layer away from the substrate. The first planarization layer includes at least a first part and a second part, the first part of the first planarization layer is arranged between the third electrode plate and the fourth electrode plate, the second part of the first planarization layer does not overlap with the third electrode plate and the fourth electrode plate, and the thickness of the first part is less than the thickness of the second part.

8. The pixel driving circuit of claim 7, wherein, The thickness of the first part of the first planarization layer is 0, so as to expose the first passivation layer.

9. The pixel driving circuit according to any one of claims 3 to 8, wherein The light emitting control unit includes: The seventh transistor includes a first electrode, a second electrode and a gate, the first electrode is connected with the third node, the second electrode is connected with the fourth node, and the gate is used for loading the light emitting control signal. The first reset unit includes: The fifth transistor includes a first electrode, a second electrode and a gate, the first electrode is used for loading the reference voltage, the gate is used for loading the first reset signal, and the second electrode is connected with the second node. A sixth transistor comprises a first electrode, a second electrode and a gate electrode, the first electrode is used for loading the reference voltage, the gate electrode is used for loading the light-emitting control signal, and the second electrode is connected to the second node; The pixel driving circuit further comprises a third reset unit, and the third reset unit comprises: An eighth transistor comprises a first electrode, a second electrode and a gate electrode, the first electrode is used for loading the initialization voltage, the gate electrode is used for loading the first reset signal, and the second electrode is connected to the fourth node.

10. The pixel driving circuit of claim 9, wherein, The active layers of the first transistor, the driving transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor comprise a channel region, a first electrode and a second electrode located on both sides of the channel region, and the materials of the active layers are all polycrystalline silicon semiconductor materials.

11. The pixel driving circuit of claim 9, wherein, The pixel driving circuit further comprises a second metal wiring structure, and the second metal wiring structure is connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor; The orthogonal projection of the second metal wiring structure on the substrate substrate partially overlaps with the orthogonal projection of the data lead on the substrate substrate.

12. The pixel driving circuit of claim 11, wherein, The first metal wiring structure is located in the second gate layer and extends along the column direction; the second metal wiring structure is located in the first metal wiring layer, and the first metal wiring layer further comprises a third metal wiring structure; the first power voltage lead and the data lead are located in the second metal wiring layer; The orthogonal projection of the third metal wiring structure on the substrate substrate partially overlaps with the orthogonal projection of the data lead on the substrate substrate; the third metal wiring structure is electrically connected to the first metal wiring structure through a via, and is connected to the first power voltage lead through a via.

13. The pixel driving circuit of claim 12, wherein, The display panel further comprises a polycrystalline silicon semiconductor layer located between the substrate substrate and the second gate layer; The polycrystalline silicon semiconductor layer comprises the active layer of the first transistor, the active layer of the sixth transistor and a first conductive lead; the first conductive lead is connected to the second electrode of the first transistor and the second electrode of the sixth transistor and extends along the column direction; The first metal wiring layer comprises a fourth metal wiring structure, and the fourth metal wiring structure is connected to the first electrode of the first transistor through a via and is connected to the data lead through a via; The orthogonal projection of the first metal wiring structure on the substrate substrate at least partially overlaps with the orthogonal projection of the first conductive lead on the substrate substrate.

14. The pixel driving circuit of claim 13, wherein, The display panel further comprises a first gate layer located between the polycrystalline silicon semiconductor layer and the second gate layer; The storage capacitor comprises a first electrode plate located in the first gate layer, a second electrode plate located in the second gate layer, a third electrode plate located in the first metal wiring layer and a fourth electrode plate located in the second metal wiring; The third electrode plate is electrically connected to the first electrode plate through a via, the fourth electrode plate is electrically connected to the second metal wiring structure through a via, and the second metal wiring structure is electrically connected to the second electrode plate through a via; The polycrystalline silicon semiconductor layer further comprises an active layer of the fifth transistor, and a second electrode of the fifth transistor and a second electrode of the sixth transistor are connected with the second metal wiring structure through a via hole.

15. The pixel driving circuit of claim 14, wherein, The first metal wiring layer further comprises an initial voltage lead wire extending along the row direction, the initial voltage lead wire having a first protruding portion extending along the column direction; a projection of the first protruding portion on the substrate substrate partially overlaps with a projection of the data lead wire on the substrate substrate; A first electrode of the fifth transistor is multiplexed as a first electrode of the sixth transistor, and is electrically connected with the first protruding portion through a via hole.

16. The pixel driving circuit of claim 15, wherein, The channel region of the fifth transistor comprises a first sub-channel region and a second sub-channel region, and the polycrystalline silicon semiconductor layer further comprises a second conductive lead wire connecting the first sub-channel region and the second sub-channel region in series; the first sub-channel region and the second sub-channel region both extend along the column direction and are arranged along the row direction; The first gate layer further comprises a first reset lead wire extending along a first direction; a projection of the first sub-channel region and the second sub-channel region on the substrate substrate is located within a projection of the first reset lead wire on the substrate substrate.

17. The pixel driving circuit of claim 14, wherein, The polycrystalline silicon semiconductor layer further comprises an active layer of a driving transistor, a third conductive lead wire and a fourth conductive lead wire, a first electrode of the driving transistor is connected with the third conductive lead wire, and a second electrode of the driving transistor is connected with the fourth conductive lead wire; The first electrode plate covers a channel region of the driving transistor; The third conductive lead wire is electrically connected with the third metal wiring structure through a via hole.

18. The pixel driving circuit of claim 17, wherein, The display panel further comprises a metal oxide semiconductor layer between the first gate layer and the second gate layer, and the metal oxide semiconductor layer comprises an active layer of a second transistor and an active layer of a fourth transistor; The first gate layer comprises a second scan lead wire and a second reset lead wire extending along the row direction; The second scan lead wire comprises first lead wire segments and second lead wire segments arranged alternately and connected sequentially, a size of the first lead wire segments in the column direction is greater than a size of the second lead wire segments in the column direction; a projection of a channel region of the second transistor on the first gate layer is located within the first lead wire segments; The second reset lead wire comprises third lead wire segments and fourth lead wire segments arranged alternately and connected sequentially, a size of the third lead wire segments in the column direction is greater than a size of the fourth lead wire segments in the column direction; a projection of a channel region of the fourth transistor on the first gate layer is located within the third lead wire segments.

19. The pixel driving circuit of claim 18, wherein, The second gate layer comprises a third scan lead wire and a third reset lead wire extending along the row direction; A projection of the third scan lead wire on the substrate substrate covers a projection of the channel region of the second transistor on the substrate substrate; A projection of the third reset lead wire on the substrate substrate covers a projection of the channel region of the fourth transistor on the substrate substrate.

20. The pixel driving circuit of claim 18, wherein, The first metal wiring layer further comprises a fifth metal wiring structure and a sixth metal wiring structure; The fifth metal wiring structure is electrically connected with the third electrode plate, and is connected with the second electrode of the second transistor through a via hole, and is connected with the second electrode of the fourth transistor through a via hole; The sixth metal wiring structure is connected with the fourth conductive lead through a via hole, and is connected with the first electrode of the second transistor through a via hole.

21. The pixel driving circuit of claim 20, wherein, The first gate layer further includes a first scan lead extending along the row direction; A normal projection of the channel region of the first transistor on the substrate substrate is located within a normal projection of the first scan lead on the substrate substrate. A normal projection of the first scan lead on the substrate substrate at least partially overlaps with a normal projection of the fifth metal wiring structure on the substrate substrate.

22. The pixel driving circuit of claim 21, wherein, The first scan lead has a second protruding portion; a normal projection of the second protruding portion on the substrate substrate at least partially overlaps with a normal projection of the fifth metal wiring structure on the substrate substrate.

23. The pixel driving circuit of claim 13, wherein, The second gate layer is provided with the power distribution lead.

24. The pixel driving circuit of claim 18, wherein, The first power voltage lead further includes a third protruding portion; a normal projection of the third protruding portion on the substrate substrate covers a normal projection of the channel region of the second transistor on the substrate substrate and a normal projection of the channel region of the fourth transistor on the substrate substrate.

25. The pixel driving circuit of claim 16, wherein, The polysilicon semiconductor layer further includes an active layer of a seventh transistor and an active layer of an eighth transistor; a first electrode of the seventh transistor is connected with the fourth conductive lead, and a second electrode of the seventh transistor and a second electrode of the eighth transistor overlap; a first electrode of the eighth transistor is connected with an initialization signal lead through a via hole; The first gate layer further includes a light emission control lead extending along the row direction; a normal projection of the channel region of the sixth transistor on the substrate substrate and a normal projection of the channel region of the seventh transistor on the substrate substrate are located within a normal projection of the light emission control lead on the substrate substrate; A normal projection of the channel region of the eighth transistor on the substrate substrate is located within a normal projection of the first reset lead on the substrate substrate.

26. A display panel, comprising the pixel driving circuit according to any one of claims 1-25.

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