Chip package and method for preparing chip package

Abstract

The embodiment of the present application provides a chip package and a method for preparing the chip package, which is conducive to improving the performance of the chip. The chip package includes a substrate, a bare chip, a first protective structure and a barrier structure; the bare chip, the first protective structure and the barrier structure are all arranged on the first surface of the substrate; the first protective structure wraps the side of the bare chip, the barrier structure wraps the surface of the first protective structure away from the bare chip, and the first surface of the bare chip, the first surface of the first protective structure and the first surface of the barrier structure are flush, wherein the first surface of the bare chip is the surface of the bare chip away from the substrate, the first surface of the first protective structure is the surface of the first protective structure away from the substrate, and the first surface of the barrier structure is the surface of the barrier structure away from the substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip package and a method for preparing the chip package in the field of semiconductor technology. Background Art

[0002] In semiconductor packaging technology, flip chip technology is a common packaging technology. Flip chip technology is a technology that deposits tin-lead balls on the input / output (I / O) pads of a bare chip, then flips the bare chip and heats it, and uses the molten tin-lead balls to combine with the packaging substrate.

[0003] In order to further improve the heat dissipation capacity of the bare chip (die), the bare chip soldered on the package substrate can be exposed. Patent application number US 2002 / 0060084A1 protects a flip chip package for stress control and discloses Figure 1 The flip chip package 1 shown in FIG. Figure 1 As shown, the chip package 1 includes a bare chip 2, the bare chip 2 has a contact 3, the contact 3 is connected to a conductive trace (not shown) on a substrate 4, and the conductive trace connects the contact 3 to an external terminal (solder ball) 5 of the substrate 4. The chip package 1 also includes a dam 7 surrounding the bare chip 2 and controlling the shape of the edge of the bottom filler 6. The bottom filler 6 is formed by filling the bottom filler under the bare chip 2 and within the limited volume range of the dam 7, and curing the bottom filler.

[0004] However, since the bottom filler is liquid and the bare chip 2 is solid, there will be an angle (i.e., wetting angle) between the tangent line m of the solid interface and the tangent line n of the liquid interface at the contact point between the bare chip 2 and the bottom filler, so there will also be such an angle for the bottom filler 6 formed after the bottom filler is cured. In this way, the edges and corners of the bare chip 2 will be exposed outside the bottom filler 6, that is, the edges and corners of the bare chip 2 will not be protected.

[0005] therefore, Figure 1 In the flip chip package shown in the figure, when a heat sink is installed on the bare chip or the package of the whole device is vibrated or dropped, the bare chip is very easy to be damaged, thereby affecting the performance of the bare chip. Summary of the invention

[0006] The embodiments of the present application provide a chip package and a method for preparing the chip package, which can provide protection for the bare chip and further improve the performance of the bare chip.

[0007] In a first aspect, an embodiment of the present application provides a chip package, comprising a substrate, a bare chip, a first protective structure and a barrier structure; the bare chip, the first protective structure and the barrier structure are all arranged on the first surface of the substrate; the first protective structure wraps the side of the bare chip, the barrier structure wraps the surface of the first protective structure facing away from the bare chip, and the first surface of the bare chip, the first surface of the first protective structure and the first surface of the barrier structure are flush, wherein the first surface of the bare chip is the surface of the bare chip facing away from the substrate, the first surface of the first protective structure is the surface of the first protective structure facing away from the substrate, and the first surface of the barrier structure is the surface of the barrier structure facing away from the substrate.

[0008] In the chip package provided in the embodiment of the present application, the first protective structure wraps the side of the bare chip, which can protect the bare chip. The first surface of the bare chip is flush with the first surface of the first protective structure, so that the edges and corners of the bare chip are wrapped by the first protective structure, which can play a more comprehensive protective role. In addition, in the scenario where a radiator is installed for the bare chip or in the scenario where the packaging of the whole machine vibrates or falls, the chip package provided in the embodiment of the present application can avoid the cracking of the bare chip caused by the uneven stress caused by the collision of the packaging or other devices (such as the radiator set above the first surface of the bare chip) with the bare chip 120. Therefore, the chip package 100 provided in the embodiment of the present application can improve the reliability and safety of the bare chip.

[0009] In addition, the first surface of the bare chip is flush with the first surface of the first protective structure, which can ensure that the surface of the bare chip is not covered by the surface of the first protective structure. Since the material of the first protective structure is a high thermal conductivity material, the surface can be equivalent to an extension and expansion of the surface, thereby increasing the heat dissipation area of ​​the bare chip and improving the heat dissipation capacity of the bare chip.

[0010] In summary, the chip package provided in the embodiments of the present application can improve the performance of the bare chip.

[0011] It should be noted that the first protection structure described in the embodiment of the present application wraps the side of the bare chip, which can be understood as the surface of the first protection structure close to the bare chip and the surface of the bare chip close to the first protection structure are in contact with each other.

[0012] In a possible implementation manner, a second protection structure is filled between the substrate and the bare chip.

[0013] In the chip package provided in the embodiment of the present application, a second protective structure is filled between the substrate and the bare chip, which can avoid the cracking of the bare chip caused by uneven stress due to the material difference between the substrate and the bare chip. In addition, it can also prevent the pads of the substrate and the bare chip, and the solder balls used for electrically connecting the pads from being contaminated by moisture or other impurities, thereby improving the reliability and safety of the chip package.

[0014] In a possible implementation manner, a material of the first protection structure is different from a material of the second protection structure.

[0015] In a possible implementation manner, the viscosity of the material of the first protection structure is greater than the viscosity of the material of the second protection structure.

[0016] It should be noted that since the main function of the first protective structure is to fix and protect the bare chip, and the main function of the second protective structure is to fill the gap between the substrate and the bare chip and reduce the impact of stress on the bare chip caused by the different materials of the bare chip and the substrate, the viscosity of the material of the first protective structure can be larger, and the viscosity of the material of the second protective structure can be smaller, that is, the viscosity of the material of the first protective structure can be greater than the viscosity of the material of the second protective structure.

[0017] In a possible implementation, there are multiple bare chips, and the orthographic projections of the multiple bare chips on the first surface of the substrate do not overlap with each other.

[0018] In the chip package provided in the embodiment of the present application, a first protection structure and a barrier structure can protect multiple bare chips, thereby reducing the complexity of the manufacturing process and the manufacturing cost.

[0019] In a possible implementation, there are multiple first protection structures, each of the multiple first protection structures wraps at least one bare chip among the multiple bare chips, and the bare chips wrapped by different first protection structures are different.

[0020] In a possible implementation, there are multiple barrier structures, the number of the multiple barrier structures is equal to the number of the multiple first protective structures, and the multiple barrier structures respectively wrap the multiple first protective structures.

[0021] It should be noted that, when the first surfaces of some or all of the multiple bare chips are not flush, an independent first protective structure and a barrier structure are set for at least one bare chip whose first surface is flush among the multiple bare chips, which can ensure that each bare chip and the edge of the first protective structure wrapping each bare chip are completely covered, thereby ensuring the heat dissipation performance and stability of each bare chip and improving the reliability of chip packaging.

[0022] In a second aspect, an embodiment of the present application further provides an integrated circuit, including a printed circuit board PCB, and a chip package as described in the above-mentioned first aspect or any possible implementation thereof, which is arranged on the PCB.

[0023] In a third aspect, an embodiment of the present application further provides a method for preparing a chip package, comprising: arranging a bare chip on a first surface of a substrate; arranging a first barrier structure around the side of the bare chip on the first surface of the substrate, and there is a gap between the first barrier structure and the bare chip, wherein the distance between the first surface of the first barrier structure and the first surface of the substrate is greater than the distance between the first surface of the bare chip and the first surface of the substrate, the first surface of the first barrier structure is the surface of the first barrier structure facing away from the substrate, and the first surface of the bare chip is the surface of the bare chip facing away from the substrate; filling a first filling material in the gap between the first barrier structure and the bare chip until the first surface of the first filling material is flush with the first surface of the first barrier structure, and the first surface of the first filling material is the surface of the first filling material facing away from the substrate; heating and curing the first filling material to form a third protective structure; and grinding the first surface of the third protective structure and the first surface of the first barrier structure until the first surface of the bare chip is exposed.

[0024] In a possible implementation, before filling the first filling material in the space between the first barrier structure and the bare chip, the preparation method further includes: filling the second filling material between the bare chip and the substrate; and heating and curing the second filling material to form a second protective structure.

[0025] In a possible implementation manner, a material of the third protection structure is different from a material of the second protection structure.

[0026] In a possible implementation manner, the viscosity of the material of the third protection structure is greater than the viscosity of the material of the second protection structure.

[0027] In a possible implementation, there are multiple bare chips, and arranging the bare chips on the first surface of the substrate includes: arranging multiple bare chips on the first surface of the substrate, and the orthographic projections of the multiple bare chips on the first surface of the substrate do not overlap with each other.

[0028] In one possible implementation, there are multiple first barrier structures, and the first barrier structures are arranged around the side of the bare chip on the first surface of the substrate, including: multiple first barrier structures are arranged on the first surface of the substrate, each of the multiple first barrier structures surrounds the side of at least one bare chip among the multiple bare chips, and different first barrier structures surround at least one different bare chip.

[0029] In a possible implementation, filling the first filling material in the space between the first barrier structure and the bare chip includes: filling the first filling material in the space between each first barrier structure and at least one bare chip surrounded by each first barrier structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of a flip chip package 1 provided in the prior art;

[0031] Figure 2 is a schematic structural diagram of a chip package 100 provided in an embodiment of the present application;

[0032] Figure 3 is another schematic structural diagram of a chip package 100 provided in an embodiment of the present application;

[0033] Figure 4 is another schematic structural diagram of a chip package 100 provided in an embodiment of the present application;

[0034] Figure 5 is a schematic structural diagram of a chip package 200 provided in an embodiment of the present application;

[0035] Figure 6 is a schematic diagram of electrical connection between a substrate and a bare chip provided in an embodiment of the present application;

[0036] Figure 7 is another electrical connection diagram between the substrate and the bare chip provided in an embodiment of the present application;

[0037] Figure 8 is a schematic structural diagram of a chip package 300 provided in an embodiment of the present application;

[0038] Fig. 9 is another schematic structural diagram of a chip package 300 provided in an embodiment of the present application;

[0039] Fig.10 is another schematic structural diagram of a chip package 300 provided in an embodiment of the present application;

[0040] Fig.11 is another schematic structural diagram of a chip package 300 provided in an embodiment of the present application;

[0041] Fig.12 is another schematic structural diagram of a chip package 300 provided in an embodiment of the present application;

[0042] Fig.13 is another schematic structural diagram of a chip package 300 provided in an embodiment of the present application;

[0043] Fig.14is a schematic flow chart of a preparation method 400 provided in an embodiment of the present application;

[0044] Fig.15 is another schematic flow chart of the preparation method 400 provided in an embodiment of the present application;

[0045] Fig.16 is a schematic flow chart of a preparation method 600 provided in an embodiment of the present application;

[0046] Fig.17 It is a schematic structural diagram of an integrated circuit 800 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solution of the present application will be described below in conjunction with the accompanying drawings.

[0048] In order to solve the problem of poor performance of bare chips in the prior art, an embodiment of the present application provides a chip package that can provide protection for the bare chip and further improve the performance of the bare chip.

[0049] Figure 2 and Figure 3 1 shows a schematic structural diagram of a chip package 100 provided in an embodiment of the present application, wherein: Figure 2 is a top view, Figure 3 It is a front view.

[0050] exist Figure 2 and Figure 3 In the embodiment, the chip package 100 may include: a substrate 110, a bare chip 120 and a first protective structure 130. The bare chip 120 and the first protective structure 130 are both arranged on the surface 110a of the substrate 110 (i.e., the first surface of the substrate). The first protective structure 130 wraps the side of the bare chip 120, and the surface 120a of the bare chip 120 (i.e., the first surface of the bare chip) is flush with the surface 130a of the first protective structure 130 (i.e., the first surface of the first protective structure). The surface 120a is the surface of the bare chip 120 facing away from the substrate 110, and the surface 130a is the surface of the first protective structure 130 facing away from the substrate 110.

[0051] It should be noted that the bare chip 120 refers to a unit that has not been packaged after the wafer has been cut and tested.

[0052] Optionally, the orthographic projection of the bare chip 120 on the surface 110 a may be in various shapes, which is not limited in the embodiment of the present application.

[0053] In one possible implementation, Figure 2 As shown in FIG. 1 , the orthographic projection of the bare chip 120 on the surface 110 a may be a quadrilateral.

[0054] It should be noted that the side surface of the bare chip 120 described in the embodiment of the present application may include the side surface of the bare chip 120. Figure 2 or Figure 3 The surface extends in the z-axis direction.

[0055] For example: Figure 2 As shown in FIG, the side surface of the bare chip 120 may include a surface 120c1, a surface 120c2, a surface 120c3, and a surface 120c4.

[0056] It should also be noted that the first protection structure 130 described in the embodiment of the present application wraps the side of the bare chip 120, which can be understood as the surface of the first protection structure 130 close to the bare chip 120 and the surface of the bare chip 120 close to the first protection structure 130 are in contact with each other.

[0057] Optionally, the orthographic projection of the first protection structure 130 on the surface 110 may be in various shapes, which is not limited in the embodiment of the present application.

[0058] In one possible implementation, Figure 2 As shown in FIG. 1 , the orthographic projection of the first protection structure 130 on the surface 110 a may be in the shape of a square ring.

[0059] That is, the orthographic projection of the surface of the first protection structure 130 facing away from the bare chip 120 on the surface 110 a is a quadrilateral.

[0060] In another possible implementation, Figure 4 As shown, the orthographic projection of the first protection structure 130 on the surface 110 a may be in the shape of a ring with a circle outside and a square inside.

[0061] That is, the orthographic projection of the surface of the first protection structure 130 facing away from the bare chip 120 on the surface 110 a is a circle.

[0062] In one possible implementation, Figure 3 As shown, the surface 120a of the bare chip 120 is flush with the surface 130a of the first protection structure 130, which can be understood as: the distance h1 between the surface 120a of the bare chip 120 and the surface 110a of the substrate 110, and the distance h2 between the surface 130a of the first protection structure 130 and the surface 110a of the substrate 110 are equal.

[0063] In a possible implementation, the material of the first protection structure 130 may be a high thermal conductivity material.

[0064] In the chip package 100 provided in the embodiment of the present application, the first protective structure 130 wraps the side of the bare chip 120, which can protect the bare chip 120. The surface 120a of the bare chip 120 is flush with the surface 130a of the first protective structure 130, so that the edges and corners of the bare chip 120 are wrapped by the first protective structure 130, which can play a more comprehensive protective role. In addition, in the scenario where a radiator is equipped for the bare chip or in the scenario where the packaging of the whole machine vibrates or falls, the chip package 100 can avoid the cracking of the bare chip 120 caused by the uneven stress caused by the collision of the packaging or other devices (such as the radiator set above the surface 120a of the bare chip 120) with the bare chip 120. Therefore, the chip package 100 provided in the embodiment of the present application can improve the reliability and safety of the bare chip 120.

[0065] In addition, the surface 120a of the bare chip 120 is flush with the surface 130a of the first protective structure 130, which can ensure that the surface 120a of the bare chip 120 is not covered by the surface 130a of the first protective structure 130, and because the material of the first protective structure 130 is a high thermal conductivity material, the surface 130 can be equivalent to an extension and expansion of the surface 120, thereby increasing the heat dissipation area of ​​the bare chip 120, thereby improving the heat dissipation capacity of the bare chip 120.

[0066] In summary, the chip package provided in the embodiments of the present application can improve the performance of the bare chip.

[0067] Optionally, the bare chip 120 may be disposed on the substrate 110 in a variety of ways, which is not limited in the embodiment of the present application.

[0068] In one possible implementation, Figure 5 2 shows a schematic structural diagram of a chip package 200 provided in an embodiment of the present application, such as Figure 5 As shown, the chip package 200 may include: a substrate 210, a bare chip 220 and a first protection structure 230. The bare chip 220 and the first protection structure 230 are both disposed on a surface 210a of the substrate 210 (ie, the first surface of the substrate).

[0069] The first protection structure 230 wraps the side of the bare chip 220, and the surface 220a of the bare chip 220 (i.e., the first surface of the bare chip) is flush with the surface 230a of the first protection structure 230 (i.e., the first surface of the first protection structure), and the surface 220a is the surface of the bare chip 220 away from the substrate 210, and the surface 230a is the surface of the first protection structure 230 away from the substrate 210. The surface 220b of the bare chip 220 has a solder ball 240, and the bare chip 220 is soldered to the substrate 210 through the solder ball 240, and the surface 220b of the bare chip 220 is the surface of the bare chip 220 close to the substrate 210.

[0070] For example: Figure 6 and Figure 7 FIG. 2 shows a schematic diagram of a bare chip 220 being soldered to a substrate 210 via solder balls 240. Figure 6 and Figure 7 As shown, a pad 211 is disposed on the surface 210 a of the substrate 210 , and a pad 221 is disposed on the surface 220 b of the bare chip 220 . The pads 211 and 221 are soldered together via solder balls 240 .

[0071] It should be noted that Figure 6 and Figure 7 In the figure, only four solder pads 211, four solder balls 240 and four solder balls 221 are taken as examples for introduction, and the embodiment of the present application does not limit the number of solder pads and solder balls.

[0072] In a possible implementation, in the chip package 200 , a second protection structure 250 may be further filled between the substrate 210 and the bare chip 220 .

[0073] For example: Figure 5 As shown, the second protection structure 250 fills the space between the substrate 210 and the bare chip 220 except for the solder balls 240 .

[0074] In the chip package 200 provided in the embodiment of the present application, a second protective structure 250 is filled between the substrate 210 and the bare chip 220, which can avoid the cracking of the bare chip caused by uneven stress due to the material difference between the substrate and the bare chip. In addition, it can also prevent the pads of the substrate 210 and the bare chip 220, and the solder balls used for electrically connecting the pads from being contaminated by moisture or other impurities, thereby improving the reliability and safety of the chip package.

[0075] In a possible implementation, the material of the first protection structure 230 is different from the material of the second protection structure 250 .

[0076] For example, the viscosity of the material of the first protection structure 230 is different from the viscosity of the material of the second protection structure 250 .

[0077] Further, the viscosity of the material of the first protective structure 230 may be greater than the viscosity of the material of the second protective structure 250 .

[0078] It should be noted that since the main function of the first protective structure 230 is to fix and protect the bare chip 220, and the main function of the second protective structure 250 is to fill the gap between the substrate 210 and the bare chip 220 and reduce the impact of the stress caused by the different materials of the bare chip and the substrate on the bare chip, the viscosity of the material of the first protective structure 230 can be relatively large, and the viscosity of the material of the second protective structure 250 can be relatively small, that is, the viscosity of the material of the first protective structure 230 can be greater than the viscosity of the material of the second protective structure 250.

[0079] It should be noted that Figure 5 For parts not introduced in the Figures 2 to 4 To avoid repetition, the corresponding parts of the introduction will not be repeated here.

[0080] In one possible implementation, Figure 8 and Fig. 9 : shows a schematic structural diagram of a chip package 300 provided in an embodiment of the present application, wherein: Figure 8 is a top view, Fig. 9 is a front view. Figure 8 and Fig. 9 As shown, the chip package 300 may include: a substrate 310, a bare chip 320, a first protection structure 330, and a second protection structure 350 (such as Fig. 9 As shown, Figure 8 The bare chip 320, the first protection structure 330, the second protection structure 350 and the barrier structure 360 ​​are all disposed on the surface 310a of the substrate 310 (ie, the first surface of the substrate).

[0081] The first protection structure 330 wraps around the side of the bare chip 320, the barrier structure 360 ​​wraps around the surface of the first protection structure 330 away from the bare chip 320, and the second protection structure 350 fills between the substrate 310 and the bare chip 320 except for the solder balls 340 (such as Fig. 9 As shown, Figure 8 The surface 320a of the bare chip 320 (i.e., the first surface of the bare chip), the surface 330a of the first protective structure 330 (i.e., the first surface of the first protective structure), and the surface 360a of the barrier structure 360 ​​(i.e., the first surface of the barrier structure) are flush, wherein the surface 320a is the surface of the bare chip 320 facing away from the substrate 310, the surface 330a is the surface of the first protective structure 330 facing away from the substrate 310, and the surface 360a is the surface of the barrier structure 360 ​​facing away from the substrate 310.

[0082] In one possible implementation, Fig. 9As shown, the surface 320a of the bare chip 320, the surface 330a of the first protective structure 330 and the surface 360a of the barrier structure 360 ​​are flush, which can be understood as: the distance h1 between the surface 320a of the bare chip 320 and the surface 110a of the substrate 110, the distance h2 between the surface 130a of the first protective structure 130 and the surface 110a of the substrate 110, and the distance h3 between the surface 360a of the barrier structure 360 ​​and the surface 110a of the substrate 110 are equal.

[0083] Optionally, the number of bare chips in the chip package 100, the chip package 200 and the chip package 300 may be multiple, and the orthographic projections of the multiple bare chips on the substrate do not overlap with each other, which is not limited in the embodiment of the present application.

[0084] Optionally, when there are multiple bare chips in the chip package 200 and the chip package 300 , correspondingly, there may also be multiple second protection structures, which is not limited in the embodiment of the present application.

[0085] In a possible implementation, taking chip 300 as an example, Fig.10 and Fig.11 Another schematic structural diagram of a chip package 300 provided in an embodiment of the present application is shown, wherein: Fig.10 is a top view, Fig.11 is a front view. Fig.10 and Fig.11 As shown, the chip package 300 may include a plurality of bare chips 320 and a plurality of second protection structures 350 (eg, Fig.11 As shown, Fig.10 The first protection structure 330 wraps the side of each bare chip 320 in the plurality of bare chips 320, and the barrier structure 360 ​​wraps the surface of the first protection structure 330 away from the plurality of bare chips 320. There is no solder ball 340 (such as Fig.11 As shown, Fig.10 The second protective structure 350 is filled in the space outside the bare chip 320 (not shown). The surface 320a of each bare chip 320 (i.e., the first surface of the bare chip), the surface 330a of the first protective structure 330 (i.e., the first surface of the first protective structure) and the surface 360a of the barrier structure 360 ​​(i.e., the first surface of the barrier structure) are flush. Among them, the surface 320a is the surface of the bare chip 320 facing away from the substrate 310, the surface 330a is the surface of the first protective structure 330 facing away from the substrate 310, and the surface 360a is the surface of the barrier structure 360 ​​facing away from the substrate 310.

[0086] It should be noted that Fig.10 and Fig.11 For parts not introduced in the Figures 2 to 9To avoid repetition, the corresponding parts of the introduction will not be repeated here.

[0087] It should also be noted that Fig.10 and Fig.11 In the description, two bare chips are used as an example for illustration, and the embodiment of the present application does not limit the specific number of the multiple bare chips.

[0088] By using the chip package 300 provided in the embodiment of the present application, a first protection structure 330 and a barrier structure 360 ​​can protect a plurality of bare chips 320 , thereby reducing the complexity of the manufacturing process and the manufacturing cost.

[0089] Optionally, when there are multiple bare chips in the chip package 100 , the chip package 200 , and the chip package 300 , correspondingly, there may also be multiple first protection structures and barrier structures, which is not limited in the embodiments of the present application.

[0090] In a possible implementation, there may be multiple first protection structures, each of the multiple first protection structures wraps at least one bare chip among the multiple bare chips, and the bare chips wrapped by different first protection structures are different from each other.

[0091] That is, each of the multiple first protection structures can wrap one bare chip or multiple bare chips, and different first protection structures wrap different bare chips.

[0092] In another possible implementation, there may be multiple barrier structures, and the number of the multiple barrier structures is equal to the number of the multiple first protective structures, and each barrier structure in the multiple barrier structures wraps the first protective structure corresponding to each barrier structure.

[0093] That is to say, different barrier structures wrap different first protection structures.

[0094] For example, taking chip 300 as an example, Fig.12 and Fig.13 is another schematic structural diagram of a chip package 300 provided in an embodiment of the present application, wherein: Fig.12 is a top view, Fig.13 is a front view. Fig.12 and Fig.13 As shown, the chip package 500 includes a substrate 310, a plurality of bare chips 320, a plurality of first protection structures 330, a plurality of second protection structures 350 (such as Fig.13 As shown, Fig.12The plurality of bare chips 320, the plurality of first protection structures 330, the plurality of second protection structures 350 and the plurality of barrier structures 360 are all disposed on the surface 310a of the substrate 310 (ie, the first surface of the substrate).

[0095] Different first protection structures 330 wrap different bare chips 320, different barrier structures 360 wrap different first protection structures 330, and different second protection structures 350 are filled between the substrate 310 and different bare chips 320 except for the solder balls 340 (such as Fig.13 As shown, Fig.12 In the interval outside the substrate 310 (not shown), the surface 320a of each bare chip 320 (i.e., the first surface of the bare chip), the surface 330a of each first protective structure 330 (i.e., the first surface of the first protective structure), and the surface 360a of each barrier structure 360 ​​(i.e., the first surface of the barrier structure) are flush. Surface 320a is the surface of the bare chip 320 facing away from the substrate 310, surface 330a is the surface of the first protective structure 330 facing away from the substrate 310, and surface 360a is the surface of the barrier structure 360 ​​facing away from the substrate 310.

[0096] It should be noted that, when the surfaces 320a of some or all of the bare chips 320 are not flush, Fig.12 and Fig.13 The method shown in, i.e., setting an independent first protective structure 350 and a barrier structure 360 ​​for at least one bare chip 320 whose surface 320a is flush with the multiple bare chips 320, can ensure that each bare chip 320 and the edge of the first protective structure 350 wrapping each bare chip are completely covered, thereby ensuring the heat dissipation performance and stability of each bare chip 320 and improving the reliability of chip packaging.

[0097] It should be noted that Fig.12 and Fig.13 In the description, two bare chips, two first protection structures and two barrier structures are used as examples for illustration. The embodiments of the present application do not limit the specific number of the multiple bare chips, the multiple first protection structures and the multiple barrier structures.

[0098] Combined with the above Figures 2 to 13 The chip package provided by the embodiment of the present application is introduced. Figures 14 to 16 The present invention introduces a method for preparing a chip package provided in an embodiment of the present application.

[0099] Fig.14 and Fig.15 A schematic flow chart of a preparation method 400 provided in an embodiment of the present application is shown, wherein: Fig.14 is a top view, Fig.15 is a front view. Fig.14 and Fig.15 As shown, the preparation method 400 includes the following steps.

[0100] S410 , a bare chip 520 is disposed on a surface 510 a of a substrate 510 (ie, a first surface of the substrate).

[0101] S420, a first barrier structure 561 is disposed on the surface 510a around the side surface 520c1, the surface 520c2, the surface 520c3 and the surface 520c4 of the bare chip 520, and there is a gap between the first barrier structure 561 and the side surface 520c1, the surface 520c2, the surface 520c3 and the surface 520c4 of the bare chip 520, wherein a distance k1 between a surface 561a of the first barrier structure 561 (i.e., the first surface of the first barrier structure 561) and the surface 510a is greater than a distance k2 between a surface 520a of the bare chip (i.e., the first surface of the bare chip) and the surface 510a, the surface 561a is the surface of the first barrier structure 561 facing away from the substrate 510, and the surface 520a is the surface of the bare chip 520 facing away from the substrate 510.

[0102] It should be noted that there is a gap between the first barrier structure 561 and the side of the bare chip 520 , which can be understood as the surface of the first barrier structure 561 close to the bare chip 520 and the surface of the bare chip 520 close to the first barrier structure 561 are not in direct contact.

[0103] It should also be noted that the above k1 can be understood as the distance between the lowest point of the surface 561a and the surface 510a; or the distance between the lowest point of the surface 561a close to the bare chip and the surface 510a.

[0104] S430, filling the first filling material 531 within the surrounding range of the first barrier structure 561 until the surface 531a of the first filling material 531 (i.e., the first surface of the filling material) is flush with the surface 561a of the first barrier structure 561, and the surface 531a is the surface of the first filling material 531 facing away from the substrate 510.

[0105] In a possible implementation, in S430 , the first filling material 531 may be filled in the surrounding area of ​​the first barrier structure 561 by dispensing.

[0106] S440 , heating and curing the first filling material 531 to form a third protection structure 532 .

[0107] S450, grinding the surface 532a of the third protective structure 532 (i.e., the first surface of the third protective structure) and the surface 561a of the first barrier structure 561 until the surface 520a of the bare chip 520 is exposed, the third protective structure 532 forms the first protective structure 530, the first barrier structure 561 forms the barrier structure 560, and the surface 520a of the bare chip 520, the surface 530a of the first protective structure 530 and the surface 560a of the barrier structure 560 are flush.

[0108] Furthermore, after the surface 520a of the bare chip 520 is exposed, the surface 532a of the third protection structure 532, the surface 561a of the first barrier structure 561 and the surface 520a of the bare chip 520 can be further ground to a certain extent to ensure that the surface 532a, the surface 561a and the surface 520a are flush.

[0109] It should be noted that S410 to S450 only schematically illustrate the method for preparing chip packaging when the number of bare chips, the first protective structure and the barrier structure are all one. When the number of bare chips is multiple, or the number of bare chips, the first protective structure and the barrier structure are all multiple, the method for preparing chip packaging can refer to the above S410 to S450. To avoid repetition, it will not be repeated here.

[0110] In a possible implementation, when there are multiple bare chips 520 , S410 may include: arranging multiple bare chips 520 on the surface 510 a , wherein the orthographic projections of the multiple bare chips 520 on the surface 510 a do not overlap with each other.

[0111] Accordingly, the number of the first barrier structures 561 is multiple, and S420 may include: setting multiple first barrier structures 561 on the first surface 510a, each of the multiple first barrier structures 561 surrounds at least one bare chip 520 among the multiple bare chips 520, and different first barrier structures 561 surround at least one different bare chip 520.

[0112] Accordingly, S430 may include: filling a first filling material 531 in a space between each first barrier structure 561 and at least one bare chip 520 surrounded by each first barrier structure 561 .

[0113] Fig.16 A schematic flow chart of a preparation method 600 provided in an embodiment of the present application is shown, as Fig.16 As shown, the preparation method 600 includes the following steps.

[0114] S610 , soldering the bare chip 720 on the surface 710 a (ie, the first surface of the substrate) of the substrate 710 through the solder balls 740 .

[0115] S620, a first barrier structure 761 is disposed on the surface 710a around the side surfaces of the bare chip 720 (including the surface 720c1, the surface 720c2, the surface 720c3 and the surface 720c4), and there are gaps between the first barrier structure 761 and the surfaces 720c1, the surface 720c2, the surface 720c3 and the surface 720c4 of the bare chip 720, wherein a distance k1 between a surface 761a of the first barrier structure 761 (i.e., the first surface of the first barrier structure 761) and the surface 710a is greater than a distance k2 between a surface 720a of the bare chip (i.e., the first surface of the bare chip) and the surface 710a, the surface 761a is the surface of the first barrier structure 761 facing away from the substrate 710, and the surface 720a is the surface of the bare chip 720 facing away from the substrate 710.

[0116] It should be noted that there is a gap between the first barrier structure 761 and the side of the bare chip 720 , which can be understood as the surface of the first barrier structure 761 close to the bare chip 720 and the surface of the bare chip 720 close to the first barrier structure 761 are not in direct contact.

[0117] It should also be noted that the above k1 can be understood as the distance between the lowest point of the surface 761a and the surface 710a; or the distance between the lowest point of the surface 761a close to the bare chip and the surface 710a.

[0118] S630 , filling a second filling material 751 in the space between the substrate 710 and the bare chip 720 except for the solder balls 740 .

[0119] In a possible implementation, in S630 , the second filling material 751 may be filled in the space between the substrate 710 and the bare chip 720 except for the solder balls 740 by dispensing.

[0120] S640 , heating and curing the second filling material 751 to form a second protection structure 750 .

[0121] S650, filling the first filling material 731 within the surrounding range of the first barrier structure 761 until the surface 731a of the first filling material 731 (i.e., the first surface of the first filling material) is flush with the surface 761a of the first barrier structure 761, and the surface 731a is the surface of the first filling material 731 facing away from the substrate 710.

[0122] In a possible implementation, in S650 , the first filling material 731 may be filled in the surrounding area of ​​the first barrier structure 761 by dispensing.

[0123] S660 , heating and curing the first filling material 731 to form a third protection structure 732 .

[0124] S670, the surface 732a of the third protective structure 732 (i.e., the first surface of the third protective structure) and the surface 761a of the first barrier structure 761 are ground until the surface 720a of the bare chip 720 is exposed, the third protective structure 732 forms the first protective structure 730, the first barrier structure 761 forms the barrier structure 760, and the surface 720a of the bare chip 720, the surface 730a of the first protective structure 730 and the surface 760a of the barrier structure 760 are flush.

[0125] Furthermore, after the surface 720a of the bare chip 720 is exposed, the surface 732a of the third protection structure 732, the surface 761a of the first barrier structure 761 and the surface 720a of the bare chip 720 may be further ground to ensure that the surfaces 732a, 761a and 720a are flush.

[0126] It should be noted that S610 to S670 only schematically illustrate the method for preparing chip packaging when the number of bare chips, the first protective structure and the barrier structure are all one. When the number of bare chips is multiple, or the number of bare chips, the first protective structure and the barrier structure are all multiple, the method for preparing chip packaging can refer to the above S610 to S670. To avoid repetition, it will not be repeated here.

[0127] In a possible implementation, when there are multiple bare chips 720, 6410 may include: soldering multiple bare chips 720 on the surface 710a of the substrate 710 through solder balls 740, and the orthographic projections of the multiple bare chips 720 on the surface 710a do not overlap each other.

[0128] Accordingly, the number of the first barrier structures 761 is multiple, and S620 may include: setting multiple first barrier structures 761 on the first surface 710a, each of the multiple first barrier structures 761 surrounds at least one bare chip 720 among the multiple bare chips 720, and different first barrier structures 761 surround at least one different bare chip 720.

[0129] Accordingly, S630 may include: filling a second filling material 751 in a space between the substrate 710 and the plurality of bare chips 720 except for the solder balls 740 .

[0130] Accordingly, S650 may include: filling a first filling material 731 in a space between each first barrier structure 761 and at least one bare chip 720 surrounded by each first barrier structure 761 .

[0131] Combined with the above Figures 14 to 16A method for preparing a chip package provided in an embodiment of the present application is introduced, and an integrated circuit integrated with the chip package provided in an embodiment of the present application is introduced below.

[0132] Fig.17 800 according to an embodiment of the present application, as shown in FIG. Fig.17 As shown, the integrated circuit 800 includes a PCB 810 and a chip package 820 , and the chip package 820 is integrated on the PCB 810 .

[0133] It should be noted that the structure of the chip package 820 can refer to the chip package introduced in any embodiment of the present application, and will not be described again here to avoid repetition.

[0134] The words "first", "second" and similar terms mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the words "a" or "an" and similar terms do not indicate a quantity limitation, but indicate the existence of at least one. The words "connected" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0135] In the embodiments of the present application, the words "in one possible implementation" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "in one possible implementation" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the words "in one possible implementation" or "for example" is intended to present the related concepts in a specific way.

[0136] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to a number of two or more. For example, multiple bare chips refers to two or more bare chips.

[0137] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip package, characterized in that: It includes a substrate, a bare chip, a first protection structure and a barrier structure; The bare chip, the first protection structure and the barrier structure are all disposed on the first surface of the substrate; The first protection structure wraps the side of the bare chip, the barrier structure wraps the surface of the first protection structure facing away from the bare chip, and the first surface of the bare chip, the first surface of the first protection structure and the first surface of the barrier structure are flush, wherein the first surface of the bare chip is the surface of the bare chip facing away from the substrate, the first surface of the first protection structure is the surface of the first protection structure facing away from the substrate, and the first surface of the barrier structure is the surface of the barrier structure facing away from the substrate; A second protection structure is filled between the substrate and the bare chip; The material of the first protective structure is different from the material of the second protective structure; The viscosity of the material of the first protective structure is greater than the viscosity of the material of the second protective structure.

2. The chip package according to claim 1, characterized in that: There are multiple bare chips, and the orthographic projections of the multiple bare chips on the first surface of the substrate do not overlap with each other.

3. The chip package according to claim 2, characterized in that: There are multiple first protection structures, each of the multiple first protection structures wraps at least one bare chip among the multiple bare chips, and the bare chips wrapped by different first protection structures are different from each other.

4. The chip package according to claim 3, characterized in that: There are multiple barrier structures, the number of which is equal to the number of the first protective structures, and the barrier structures respectively wrap the first protective structures.

5. An integrated circuit, characterized in that: The invention comprises a printed circuit board PCB, and a chip package as claimed in any one of claims 1 to 4 arranged on the PCB.

6. A method for preparing a chip package, characterized in that: include: Disposing a bare chip on the first surface of the substrate; A first barrier structure is disposed on the first surface of the substrate around the side of the bare chip, and there is a gap between the first barrier structure and the bare chip, wherein the distance between the first surface of the first barrier structure and the first surface of the substrate is greater than the distance between the first surface of the bare chip and the first surface of the substrate, the first surface of the first barrier structure is the surface of the first barrier structure facing away from the substrate, and the first surface of the bare chip is the surface of the bare chip facing away from the substrate; Filling a second filling material between the bare chip and the substrate; heating and curing the second filling material to form a second protective structure; Filling a first filling material in the space between the first barrier structure and the bare chip until a first surface of the first filling material is flush with a first surface of the first barrier structure, wherein the first surface of the first filling material is a surface of the first filling material facing away from the substrate; heating and curing the first filling material to form a third protective structure; Grinding the first surface of the third protection structure and the first surface of the first barrier structure until the first surface of the bare chip is exposed; The material of the third protective structure is different from the material of the second protective structure, and the viscosity of the material of the third protective structure is greater than the viscosity of the material of the second protective structure.

7. The preparation method according to claim 6, characterized in that: The number of the bare chips is multiple, and the bare chips are arranged on the first surface of the substrate, including: A plurality of bare chips are arranged on the first surface of the substrate, and the orthographic projections of the plurality of bare chips on the first surface of the substrate do not overlap with each other.

8. The preparation method according to claim 7, characterized in that: The number of the first barrier structures is plural, and the first barrier structures are arranged on the first surface of the substrate around the side of the bare chip, including: A plurality of first barrier structures are disposed on the first surface of the substrate, each of the plurality of first barrier structures surrounds a side surface of at least one bare chip among the plurality of bare chips, and different first barrier structures surround different at least one bare chip.

9. The preparation method according to claim 8, characterized in that: The step of filling a first filling material in the space between the first barrier structure and the bare chip comprises: The first filling material is filled in a space between each of the first barrier structures and at least one bare chip surrounded by each of the first barrier structures.

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