Configurable parallel test circuit and method for three-dimensional stacked package chips

Abstract

This invention discloses a configurable parallel test circuit and method for a three-dimensional stacked packaged chip. The test circuit includes configurable boundary scan unit pairs. The three-dimensional stacked packaged chip has multiple layers of small dies. Each configurable boundary scan unit pair includes a first configurable boundary scan unit for connecting to the input port of the small die and a second configurable boundary scan unit for connecting to the output port of the small die. The first and second configurable boundary scan units are configured into different modes through different control signals. Multiple configurable boundary scan unit pairs are set on each layer of small dies, and the multiple configurable boundary scan unit pairs on each layer of small dies are connected in series according to different modes. The configurable boundary scan unit pairs on adjacent layers of small dies are cascaded. The advantages of this invention are: flexible configuration of the number of scan chains, which is beneficial to practical applications, and low manufacturing cost.

Description

Technical Field

[0001] This invention relates to integrated circuit testing technology, and more specifically to a configurable parallel test circuit and method for a three-dimensional stacked packaged chip. Background Technology

[0002] Advances in advanced chip packaging technology have led to the emergence of a new generation of packaging: 3D-stacked chips. Unlike traditional single bare die packaging, 3D-stacked chips contain multiple chiplets, each of which is an independent unit. These chiplets are connected to each other via silicon vias (TSVs) and assembled into a whole.

[0003] The key advantages of 3D stacked packaging are: (1) It breaks down a large-area bare die into multiple small chips, each with a smaller area, resulting in a higher yield and lower cost per chip. (2) Each chip can be manufactured using different processes, offering greater flexibility; for example, advanced processes can be used for chips used in high-speed digital signal processing, while less demanding processes can be used for modules, reducing costs and manufacturing difficulty without affecting the overall chip performance.

[0004] Currently, IEEE has proposed the P1838 standard protocol for testing 3D stacked chips. Under this protocol, the test circuit comprises three main components: master-slave controllers (P-TAP and S-TAP), boundary scan register (DWR), and parallel test interface (FPP). The TAP follows and is compatible with the earlier IEEE-1149.1 protocol, only introducing a new 3D test configuration register. The DWR can reuse the circuit structures proposed in earlier IEEE-1149.1, IEEE-1500, and IEEE-1686 protocols; these two components are mandatory requirements of the protocol. The parallel test interface (FPP) is a new feature of the 1838 protocol, defining a flexibly configurable design template for high-throughput parallel test data transmission.

[0005] In the 1838 protocol, although the number of parallel data channels in the parallel test interface (FPP) is adjustable, this adjustment is only possible during the layout design phase. Once the layout is finalized, the number of parallel channels is fixed and cannot be changed during testing. Given the different processes and requirements of various packaging manufacturers, the inflexible configuration of the number of scan chains can sometimes hinder test scheme optimization. Furthermore, the parallel test interface (FPP) requires additional dedicated registers and data lanes, increasing chip manufacturing costs. Chinese patent announcement number CN215867001U discloses a boundary scan circuit, including: a test access port controller that provides test data to the boundary scan chain and receives the test results output by the boundary scan chain; and a user-defined register that provides selection control signals for multiple multiplexers. It can support various packaging test scenarios, improve test coverage, and reduce test costs. However, its number of scan chains is not flexibly configurable, requires additional registers, and has high manufacturing costs. Summary of the Invention

[0006] The technical problem to be solved by this invention is that the existing testing schemes for three-dimensional stacked chips cannot flexibly configure the number of scan chains according to the testing machine resources of different testing manufacturers, which is not conducive to practical application and increases testing costs.

[0007] This invention solves the above-mentioned technical problems through the following technical means: a configurable parallel test circuit for a three-dimensional stacked packaged chip, including configurable boundary scan unit pairs. The three-dimensional stacked packaged chip has multiple layers of small chips. The configurable boundary scan unit pairs include a first configurable boundary scan unit that can be connected to the I / O ports of the small chips and a second configurable boundary scan unit that can be connected to the I / O ports of the small chips. The I / O ports of the small chips include small chip input ports and small chip output ports. The two configurable boundary scan units in the configurable boundary scan unit pairs are configured into different modes through different control signals. Multiple configurable boundary scan unit pairs are set on each layer of small chips. The multiple configurable boundary scan unit pairs on each layer of small chips are connected in series according to different modes. The configurable boundary scan unit pairs on adjacent layers of small chips are directly cascaded through the small chip I / O ports.

[0008] Beneficial effects: In this invention, multiple configurable boundary scan unit pairs on each layer of small core are connected in series according to different modes, and configurable boundary scan unit pairs on adjacent layers of small core are cascaded. By setting the mode of the configurable boundary scan unit pairs, different circuit conduction conditions are formed. The number of scan chains is different under different circuit conduction conditions. By switching the mode of each configurable boundary scan unit pair, the number of scan chains can be flexibly configured. Thus, the number of scan chains can be flexibly configured according to the test machine resources of different test manufacturers. Moreover, the structure is simple, no additional components are required during the test process, and it is lightweight and has low manufacturing cost based on three-dimensional stacked packaging technology.

[0009] Further, the first configurable boundary scan unit includes a first DWR register, a UR register, a first scan path gating module, and a first scan chain segment. The first scan path gating module includes a first controlled buffer gate to a fourth controlled buffer gate, a first selector, and a second selector. The first scan chain segment includes a first boundary scan chain segment, a first internal scan chain segment, a first NOT gate, and a fifth to a seventh controlled buffer gate. The clk terminal of the first DWR register receives the Control clock signal, and the clk terminal of the UR register receives the updateDWR signal. The D terminal of the first DWR register is connected to the output terminal of the first selector, and the Q terminal of the first DWR register is connected to the D terminal of the UR register, the input terminals of the fifth controlled buffer gate, and the sixth controlled buffer gate, respectively. The first terminal of the first selector serves as the input terminal CTI of the first configurable boundary scan unit and is connected to the CVO2 port of the second configurable boundary scan unit.

[0010] The second terminal of the first selector receives the PAD signal and is connected to the first terminal of the second selector. The second terminal of the second selector is connected to the Q terminal of the UR register. The CFO output port of the second selector is connected to the small chip input port. The input terminals of the first NOT gate, the controlled terminals of the fifth controlled buffer gate, and the seventh controlled buffer gate all receive the enISC signal. The output terminal of the first NOT gate is connected to the controlled terminal of the sixth controlled buffer gate. The output terminal of the sixth controlled buffer gate is connected to the output terminal of the seventh controlled buffer gate and the input terminal of the first boundary scan chain segment. The output terminal of the fifth controlled buffer gate is connected to the input terminal of the seventh controlled buffer gate through the first internal scan chain segment. The output terminal of the first boundary scan chain segment is connected to... The input terminals of the first controlled buffer gate to the third controlled buffer gate are connected. The output terminal CVO of the first controlled buffer gate is connected to the CVI2 port of the second configurable boundary scan unit. The output terminal of the second controlled buffer gate serves as the output terminal CTO of the first configurable boundary scan unit. The input terminal of the fourth controlled buffer gate is connected to the output terminal of the third controlled buffer gate and receives the PAD signal. The output terminal of the fourth controlled buffer gate is connected to the first terminal of the first selector. The first controlled buffer gate to the fourth controlled buffer gate receive the enP signal, the enS signal, the enO signal, and the enI signal, respectively. The control terminals of the first selector and the second selector receive the captureDWR signal and the enTest signal, respectively.

[0011] Further, the second configurable boundary scan unit includes a second DWR register, a second scan path gating module, and a second scan chain segment. The second scan path gating module includes an eighth to eleventh controlled buffer gate, a third selector, and a fifth selector. The second scan chain segment includes a second boundary scan chain segment, a second internal scan chain segment, a second NOT gate, and twelfth to fourteenth controlled buffer gates. The clk terminal of the second DWR register receives the Control clock2 signal. The D terminal of the second DWR register is connected to the output terminal of the third selector. The Q terminal of the first DWR register is connected to the second terminal of the fourth selector, the input terminals of the twelfth and thirteenth controlled buffer gates, respectively. The second terminal of the third selector is connected to the first terminal of the fifth selector and to the small chip output port. The first terminal of the third selector serves as the input terminal CTI2 of the second configurable boundary scan unit.

[0012] The inputs of the second NOT gate, the controlled terminals of the twelfth and thirteenth controlled buffer gates all receive the enISC signal. The output of the second NOT gate is connected to the controlled terminal of the thirteenth controlled buffer gate. The output of the thirteenth controlled buffer gate is connected to the output of the fourteenth controlled buffer gate and the input of the second boundary scan chain segment. The output of the twelfth controlled buffer gate is connected to the input of the fourteenth controlled buffer gate through the second internal scan chain segment. The output of the second boundary scan chain segment is connected to the inputs of the eighth to tenth controlled buffer gates. The output CVO2 of the eighth controlled buffer gate is connected to the CVI port of the first configurable boundary scan unit. The output of the ninth controlled buffer gate serves as the second configurable boundary scan... The unit's output terminal CTO2, the output terminal of the tenth controlled buffer gate is connected to the first terminal of the fourth selector, the output terminal of the fourth selector is connected to the second terminal of the fifth selector, the output terminal of the fifth selector is connected to the input terminal of the eleventh controlled buffer gate and receives the PAD2 signal, and the output terminal of the eleventh controlled buffer gate is connected to the first terminal of the third selector; the eighth to eleventh controlled buffer gates receive the enP2 signal, the enS2 signal, the enO2 signal, and the enI2 signal respectively; the control terminals of the third and fourth selectors receive the captureDWR signal, the AND signal of the captureDWR signal and the extest signal respectively; and the control terminal of the fifth selector receives the enTest signal.

[0013] Furthermore, the first configurable boundary scan unit and the second configurable boundary scan unit are configured into different modes via different control signals, including:

[0014] The signals enI, enO, enS, enP, enI2, enO2, enS2, and enP2 are configured with binary signals of 0 or 1 respectively, forming 7 configuration modes M1 to M7. Among them, M1 is 01001001, M2 is 10100100, M3 is 10010100, M4 is 00100010, M5 is 01000001, M6 is 10100010, and M7 is 00010010.

[0015] Furthermore, the three-dimensional stacked packaged chip has three layers of small chips, each layer of small chips is provided with 12 configurable boundary scan unit pairs. The 12 configurable boundary scan unit pairs on each layer of small chips are physically connected in series with each other through input ports and output ports. By setting the mode of the configurable boundary scan unit pairs, different circuit conduction conditions are formed. The number of scan chains is different under different circuit conduction conditions. Thus, the number of scan chains can be configured by switching the mode of each configurable boundary scan unit pair.

[0016] Furthermore, the configuration scheme for the number of scan chains is as follows:

[0017] The three-dimensional stacked packaged chip has three layers of small chips, namely a top layer, a middle layer, and a bottom layer. Each layer has 12 configurable boundary scan units divided into two equal parts. The circuit mode configurations of the two equal parts are exactly the same. The configuration of the configurable boundary scan units of the bottom layer chips is M1, M2, M4, M4, M4, M7, respectively; the configuration of the configurable boundary scan units of the middle layer chips is M1, M2, M4, M4, M4, M7, respectively; and the configuration of the configurable boundary scan units of the top layer chips is M5, M6, M4, M4, M4, M7.

[0018] Furthermore, the configuration scheme for the number of scan chains is as follows:

[0019] The three-dimensional stacked packaged chip has three layers of small chips, which are divided into a top layer, a middle layer, and a bottom layer. The 12 configurable boundary scan units of each layer are divided into three equal parts. The circuit mode configuration of the three equal parts is exactly the same. The configuration of the bottom layer small chip is M1, M2, M4, M7, the configuration of the top layer small chip is M5, M6, M4, M7, and the configuration of the middle layer small chip is M1, M3, X, X, where X represents any value.

[0020] Furthermore, the configuration scheme for the number of scan chains is as follows:

[0021] The three-dimensional stacked packaged chip has three layers of small chips, which are divided into a top layer, a middle layer, and a bottom layer. The 12 configurable boundary scan units of each layer are divided into four equal parts. The circuit mode configuration of the four equal parts is exactly the same. The configuration of the configurable boundary scan units of the bottom chip is M1, M2, and M7, the configuration of the configurable boundary scan units of the middle chip is M1, M2, and M7, and the configuration of the configurable boundary scan units of the top chip is M5, M6, and M7.

[0022] This invention also provides a testing method for a configurable parallel test circuit of a three-dimensional stacked packaged chip. The parallel input and output ports of the test circuit are connected to the input and output ports of a TAP module used to implement the IEEE-1149.1 protocol, respectively. The host computer controls the test vectors to be reordered and segmented according to the order of the scan chain in the configured mode by the configurable boundary scan unit. Each segment is simultaneously sent to the entry of the parallel scan chain corresponding to the test circuit. The response of the test vector will be obtained from the exit of the parallel scan chain when the next test vector moves into the parallel scan chain corresponding to the test circuit. When the scan chain in the configured mode is a single scan chain by the configurable boundary unit, the host computer controls the serial injection of test vectors into the single scan chain. The response of the test vector will be obtained from the exit of the scan chain when the next test vector moves into the scan chain.

[0023] The advantages of this invention are:

[0024] (1) In this invention, multiple configurable boundary scanning unit pairs on each layer of small core are connected in series according to different modes. The cascading of configurable boundary scanning unit pairs on adjacent layers of small cores forms different circuit conduction conditions by setting the mode of the configurable boundary scanning unit pairs. The number of scanning chains is different under different circuit conduction conditions. By switching the mode of each configurable boundary scanning unit pair, the number of scanning chains can be flexibly configured. Thus, the number of scanning chains can be flexibly configured according to the test machine resources of different test manufacturers. Moreover, the structure is simple, no additional components are required during the test, and the lightweight is achieved based on three-dimensional stacked packaging technology, resulting in low manufacturing cost.

[0025] (2) By setting up configurable boundary scanning unit pairs, the port connections between adjacent small core particles and the test modules inside the specified small core particles can be tested independently, thus realizing modular testing.

[0026] (3) The present invention does not require all adjacent configurable boundary scan units to be connected in pairs to the scan chain segments. Each unit under test can be mounted to the configurable boundary scan unit in the configurable boundary scan unit pair according to the test requirements, which facilitates the design of the layout and routing.

[0027] (4) If the internal scan registers are evenly distributed to each configurable boundary scan unit, that is, the lengths of each internal scan chain segment are close, then in all cases, the lengths of each scan chain are approximately the same. Therefore, the scan chain of this scheme is balanced and this balance is ensured at the hardware level. No software optimization algorithm is required, and it is easy to implement.

[0028] (5) The test circuit of the present invention is compatible with IEEE-1149.1 and IEEE-1838 protocols, can use existing test equipment, has strong compatibility, and is easy to put into mass production. Attached Figure Description

[0029] Figure 1 The schematic diagrams are of the first and second configurable boundary scan units in a configurable parallel test circuit for a three-dimensional stacked packaged chip disclosed in an embodiment of the present invention. Figure 1 (a) is a schematic diagram of the first configurable boundary scan unit. Figure 1 (b) is a schematic diagram of the second configurable boundary scan unit;

[0030] Figure 2 This is a schematic diagram showing the connection of configurable boundary scan unit pairs in a configurable parallel test circuit for a three-dimensional stacked packaged chip disclosed in an embodiment of the present invention.

[0031] Figure 3 This invention discloses a configurable parallel test circuit for a three-dimensional stacked packaged chip with seven scan path configuration modes.

[0032] Figure 4 This is a schematic diagram of a scan chain configuration scheme in a configurable parallel test circuit for a three-dimensional stacked packaged chip disclosed in an embodiment of the present invention, wherein... Figure 4 (a) Figure 4 (b) Figure 4 (c) These are three different configuration schemes;

[0033] Figure 5 This is a test wiring diagram of a configurable parallel test circuit for a three-dimensional stacked packaged chip disclosed in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Example 1

[0036] like Figure 1 As shown, a configurable parallel test circuit for a three-dimensional stacked packaged chip is disclosed. The three-dimensional stacked packaged chip has multiple layers of small dies. The test circuit includes a pair of configurable boundary scan units. The pair of configurable boundary scan units includes a first configurable boundary scan unit 100 that can be connected to the I / O ports of the small dies (e.g., ...). Figure 1 (a) shown) and a second configurable boundary scan unit 200 (as shown) that can be connected to the small chip IO port. Figure 1(b) shows the small chip I / O port, which includes a small chip input port and a small chip output port. Both the first configurable boundary scan unit 100 and the second configurable boundary scan unit 200 can be connected to the function input pins or function output pins of the small chip. For example, the first method is that the first configurable boundary scan unit 100 is connected to the small core input port, and another first configurable boundary scan unit 100 is connected to the small core output port, thus forming a configurable boundary scan unit pair; the second method is that the first configurable boundary scan unit 100 is connected to the small core input port, and the second configurable boundary scan unit 200 is connected to the small core output port, thus forming a configurable boundary scan unit pair; the third method is that the second configurable boundary scan unit 200 is connected to the small core input port, and the first configurable boundary scan unit 100 is connected to the small core output port, thus forming a configurable boundary scan unit pair; the fourth method is that the second configurable boundary scan unit 200 is connected to the small core input port, and the second configurable boundary scan unit 200 is connected to the small core output port, thus forming a configurable boundary scan unit pair; if the two configurable boundary scan units forming the configurable boundary scan unit pair have the lower core port being the input terminal and the upper core port being the output terminal, then... Figure 2 This demonstrates the second method described above. The following details the specific structure of the configurable boundary scan unit pair configured in the second method. The first, third, and fourth methods are similar, differing only in their combination. The specific methods for configuring different modes using different control signals, the scan path configuration method, and the scan chain configuration scheme are all the same as in the first method, and will not be elaborated upon here.

[0037] like Figure 1 As shown in (a), the first configurable boundary scan unit 100 includes a first DWR register 1, a UR register 2, a first scan path gating module, and a first scan chain segment. The first scan path gating module includes a first controlled buffer gate 3 to a fourth controlled buffer gate 6, a first selector 7, and a second selector 8. The first scan chain segment includes a first boundary scan chain segment, a first internal scan chain segment 9, a first NOT gate 10, and a fifth controlled buffer gate 11 to a seventh controlled buffer gate 13. The first boundary scan chain segment (BSR in the figure) is formed by cascading several unpaired configurable boundary scan unit pairs of boundary scan registers. The boundary scan registers refer to the DWR register and UR register 2 in the figure. The first internal scan chain segment 9 can be a series connection of a group of internal scan registers, a test unit built into the IP core, or other testable modules with TDI-TDO interfaces. Whether the first internal scan chain segment 9 is mounted on the entire scan chain is controlled by the enISC signal in the figure.

[0038] The clk terminal of the first DWR register 1 receives the Control clock signal, and the clk terminal of the UR register 2 receives the updateDWR signal. The D terminal of the first DWR register 1 is connected to the output terminal of the first selector 7, and the Q terminal of the first DWR register 1 is connected to the D terminal of the UR register 2, the input terminal of the fifth controlled buffer gate 11, and the input terminal of the sixth controlled buffer gate 12, respectively. The first terminal of the first selector 7 serves as the input terminal CTI of the first configurable boundary scan unit 100 and is connected to the CVO2 port of the second configurable boundary scan unit 200. The second terminal of the first selector 7 receives the PAD signal and is connected to the first terminal of the second selector 8. The second terminal of the second selector 8 is connected to the Q terminal of the UR register 2, and the output terminal CFO port of the second selector 8 is connected to the small chip input port. The input terminal of the first NOT gate 10, the controlled terminal of the fifth controlled buffer gate 11, and the controlled terminal of the seventh controlled buffer gate 13 all receive the enISC signal. The output terminal of the first NOT gate 10 is connected to the controlled terminal of the sixth controlled buffer gate 12, and the output terminal of the sixth controlled buffer gate 12 is connected to the control terminal of the sixth controlled buffer gate 12. The output of the seventh controlled buffer gate 13 and the input of the first boundary scan chain segment are connected. The output of the fifth controlled buffer gate 11 is connected to the input of the seventh controlled buffer gate 13 through the first internal scan chain segment 9. The output of the first boundary scan chain segment is connected to the input of the first controlled buffer gate 3 to the third controlled buffer gate 5. The output of the first controlled buffer gate 3, CVO, is connected to the CVI2 port of the second configurable boundary scan unit 200. The output of the second controlled buffer gate 4 serves as the output of the first configurable boundary scan unit 100, CTO. The input of the fourth controlled buffer gate 6 is connected to the output of the third controlled buffer gate 5 and receives the PAD signal. The output of the fourth controlled buffer gate 6 is connected to the first terminal of the first selector 7. The first controlled buffer gate 3 to the fourth controlled buffer gate 6 receive the enP signal, the enS signal, the enO signal, and the enI signal, respectively. The control terminals of the first selector 7 and the second selector 8 receive the captureDWR signal and the enTest signal, respectively.

[0039] like Figure 1 As shown in (b), the second configurable boundary scan unit 200 includes a second DWR register 14, a second scan path gating module, and a second scan chain segment. The second scan path gating module includes an eighth controlled buffer gate 15 to an eleventh controlled buffer gate 18, a third selector 19, and a fifth selector 21. The second scan chain segment includes a second boundary scan chain segment (BSR2 in the figure), a second internal scan chain segment 22, a second NOT gate 23, and twelfth controlled buffer gates 24 to fourteenth controlled buffer gates 26. The second boundary scan chain segment and the second internal scan chain segment 22 have the same structure and function as the first boundary scan chain segment and the first internal scan chain segment 9 described above.

[0040] The clk terminal of the second DWR register 14 receives the Control clock 2 signal. The D terminal of the second DWR register 14 is connected to the output terminal of the third selector 19. The Q terminal of the first DWR register 1 is connected to the second terminal of the fourth selector 20, the input terminals of the twelfth controlled buffer gate 24 and the thirteenth controlled buffer gate 25, respectively. The second terminal of the third selector 19 is connected to the first terminal of the fifth selector 21 and to the small chip output port. The first terminal of the third selector 19 serves as the input terminal CTI2 of the second configurable boundary scan unit 200. The input terminal of the second NOT gate 23... The controlled terminals of the twelfth controlled buffer gate 24 and the thirteenth controlled buffer gate 25 both receive the enISC signal. The output terminal of the second NOT gate 23 is connected to the controlled terminal of the thirteenth controlled buffer gate 25. The output terminal of the thirteenth controlled buffer gate 25 is connected to the output terminal of the fourteenth controlled buffer gate 26 and the input terminal of the second boundary scan chain segment. The output terminal of the twelfth controlled buffer gate 24 is connected to the input terminal of the fourteenth controlled buffer gate 26 through the second internal scan chain segment 22. The output terminal of the second boundary scan chain segment is connected to the eighth controlled buffer gate 25. The input terminals of gates 15 to 17 are connected. The output terminal CVO2 of the eighth controlled buffer gate 15 is connected to the CVI port of the first configurable boundary scan unit 100. The output terminal of the ninth controlled buffer gate 16 serves as the output terminal CTO2 of the second configurable boundary scan unit 200. The output terminal of the tenth controlled buffer gate 17 is connected to the first terminal of the fourth selector 20. The output terminal of the fourth selector 20 is connected to the second terminal of the fifth selector 21. The output terminal of the fifth selector 21 is connected to the input terminal of the eleventh controlled buffer gate 18 and receives the PAD2 signal. The output terminal of the eleventh controlled buffer gate 18 is connected to the first terminal of the third selector 19. The eighth controlled buffer gates 15 to eleventh controlled buffer gates 18 receive the enP2 signal, enS2 signal, enO2 signal, and enI2 signal, respectively. The control terminals of the third selector 19 and the fourth selector 20 receive the captureDWR signal, the AND signal of the captureDWR signal and the extest signal, respectively. The control terminal of the fifth selector 21 receives the enTest signal. It should be noted that the boundary scan register of this invention is compatible with IEEE-149.1 / 1838 and is driven by the shiftCK, captureDWR, and updateDWR signals of the TAP state machine (hereinafter referred to as TAP-FSM). These signals are generated by the TAP-FSM in the shiftDR, captureDR, and updateDR states. Specifically, captureDR controls the DWR register, and updateDR controls UR register 2. The first terminal of the selector is... Figure 1 The symbol in the diagram has one end marked with 0, and the second end is the one marked with 1.

[0041] like Figure 2As shown, the two paired CBCs, namely the first configurable boundary scan unit 100 and the second configurable boundary scan unit 200, are connected, one to an I / O port on the front of the small core, and the other to an I / O port on the back of the small core via a TSV; hereinafter referred to as the bottom CBC and the top CBC, respectively. Since there are two types of CBCs, CBC-I and CBC-O, there are four combinations of configurable boundary scan unit pairs (CBC-pairs). Figure 2 The diagram shows one example, with the bottom CBC designated CBC-I and the top CBC designated CBC-O. Each CBC-pair contains eight control signals, with the four control signals of the top CBC distinguished by a suffix of 2. Based on the CBC-pair, efficient configuration of the scan path can be achieved. To simplify configuration, the combinations of the eight control signals are categorized into seven modes, denoted as M1~M7 (binary codes 000~111). This reduces the required configuration register size for each CBC-pair to only 3 bits. Specifically, the first configurable boundary scan unit 100 and the second configurable boundary scan unit 200 are configured into different modes through different control signals, including configuring the enI, enO, enS, enP, enI2, enO2, enS2, and enP2 signals as binary signals of 0 or 1 respectively, forming seven configuration modes M1 to M7, where M1 is 01001001, M2 is 10100100, M3 is 10010100, M4 is 00100010, M5 is 01000001, M6 is 10100010, and M7 is 00010010. The values ​​of the eight control signals in each mode are shown in Table 1. Correspondingly, the scan path configuration for each mode is shown in Table 1. Figure 3 .

[0042] Table 1 Control signals for 7 modes of CBC-pair

[0043]

[0044] The number of scan chains and whether each small core has been bypassed can both be configured using these modes. Specifically, for example... Figure 4 As shown, the three-dimensional stacked packaged chip has three layers of small chips. Each layer of small chips has 12 configurable boundary scan unit pairs. The 12 configurable boundary scan unit pairs on each layer of small chips are physically connected in series with each other through input ports and output ports. By setting the mode of the configurable boundary scan unit pairs, different circuit conduction conditions are formed. The number of scan chains is different under different circuit conduction conditions. Thus, the number of scan chains can be configured by switching the mode of each configurable boundary scan unit pair.

[0045] It should be noted that the above three-dimensional stacked packaged chip has 3 layers of small chips, and each layer of small chips is provided with 12 configurable boundary scan unit pairs. This is just an example for easy understanding. In actual applications, the present invention can be configured with any number of small chips. The number of configurable boundary scan unit pairs on each layer of small chips can be designed according to the test needs, provided that the number of IO pins on the small chip layer is sufficient, and there is no special limitation.

[0046] Example 2

[0047] Based on Embodiment 1, the present invention also provides a scan chain configuration scheme, such as... Figure 4 (a) Figure 4 (b) and Figure 4 (c) One configuration scheme is given respectively. Figure 4 (a) and Figure 4 In (c), all small core particles must be tested; while Figure 4 In (b), the small core in the middle is bypassed. The hollow dots in the figure represent the internal scan chain segments and boundary scan chain segments mounted in each CBC. The following details the three configuration schemes.

[0048] like Figure 4 As shown in (a), the three-layer stacked packaged chip consists of three small chips: a top layer, a middle layer, and a bottom layer. Each layer has 12 configurable boundary scan units divided into two equal parts. The circuit configurations of the two parts are identical. In one part, the configurable boundary scan units of the bottom layer chips are configured as M1, M2, M4, M4, M4, M7; the middle layer chips are configured as M1, M2, M4, M4, M4, M7; and the top layer chips are configured as M5, M6, M4, M4, M4, M7. Two parallel test vectors are serially input from TDIA and TDIB, respectively, and the responses of the two test vectors are serially output from TDOA and TDOB.

[0049] like Figure 4As shown in (b), the three-layer stacked packaged chip consists of three small chips: a top layer, a middle layer, and a bottom layer. Each layer has 12 configurable boundary scan units divided into three equal parts. The circuit configurations for each of the three equal parts are identical. In one equal part, the configurable boundary scan units for the bottom chip are configured as M1, M2, M4, and M7; for the top chip, M5, M6, M4, and M7; and for the middle chip, M1, M3, X, and X, where X represents any value. Three parallel test vectors are serially input from TDIA, TDIB, and TDIC, respectively, and the responses from these three test vectors are serially output from TDOA, TDOB, and TDOC.

[0050] like Figure 4 As shown in (c), the three-layer stacked packaged chip consists of three small chips: a top layer, a middle layer, and a bottom layer. Each layer has 12 configurable boundary scan units, which are divided into four equal parts. The circuit configurations for each of the four parts are identical. In one part, the configurable boundary scan units for the bottom chip are configured as M1, M2, and M7; for the middle chip, they are M1, M2, and M7; and for the top chip, they are M5, M6, and M7. Four parallel test vectors are serially input from TDIA, TDIB, TDIC, and TDID, respectively. The responses to these four test vectors are serially output from TDOA, TDOB, TDOC, and TDOD.

[0051] Depend on Figure 4 The three examples provided demonstrate that if the internal scan registers are evenly distributed across the configuration boundary units (CBCs), meaning the lengths of each internal scan chain segment are similar, then in all cases, the lengths of each scan chain are approximately the same. Therefore, the scan chains in this scheme are balanced, and this balance is guaranteed at the hardware level, requiring no software-level optimization algorithms.

[0052] It should be noted that the above examples of specific scan chain configuration schemes are provided only to clearly demonstrate the technical solution of the present invention. In actual applications, the above configuration schemes are not limited to these few schemes.

[0053] Through the above technical solutions, the present invention connects multiple configurable boundary scanning unit pairs on each layer of small core particles in series according to different modes, and configurable boundary scanning unit pairs on adjacent layers of small core particles are cascaded. By setting the mode of the configurable boundary scanning unit pairs, different circuit conduction conditions are formed. The number of scanning chains is different under different circuit conduction conditions. Thus, by switching the mode of each configurable boundary scanning unit pair, the number of scanning chains can be flexibly configured. Moreover, the structure is simple, no additional components are required during the testing process, and it is lightweight and has low manufacturing cost based on three-dimensional stacked packaging technology.

[0054] Example 3

[0055] Based on Example 1, such as Figure 5 As shown, Embodiment 3 of the present invention also provides a test method for a configurable parallel test circuit of a three-dimensional stacked packaged chip. The parallel input and output ports of the test circuit are respectively connected to the input and output ports of a TAP module used to implement the IEEE-1149.1 protocol. To support dynamically configurable parallel testing, two new instructions, confCBC and startCPT, and a data register storing CBC configuration bits are added to the TAP module. In the test architecture of the present invention, there are two types of scan chains: the traditional JTAG chain is used to control the instructions and data register of the TAP module, and the parallel scan chain formed by the test circuit proposed in this invention is used for high-bandwidth shifting in and out of the test vector response. Figure 4 When the configuration information for the boundary cell pair (CBC-pair) is M4,M4,M4,M4,M4,M4,M4,M4,M4,M4,M4,M7, it will be configured as a traditional single boundary scan chain. For example... Figure 5 At the point where the first CBC-pair connects to the TAP module, there are two controlled buffer gates. These gates are only activated when the CBC-pair is configured as a single boundary scan chain, allowing the boundary scan chain to connect to the TAP module; otherwise, they are deactivated to isolate the JTAG chain and the parallel scan chain. The single boundary scan chain is designed for user debugging of the chip. Since the chip is already soldered onto the PCB at this point, the chip pins reused for parallel testing are used as functional pins, and only the JTAG interface is available.

[0056] In a three-dimensional stacked chip, no more small chips are connected above the topmost small chip, therefore the boundary scan register (CBC) in its top layer is not connected. Figure 1 Remove the DWR and retain only the remaining logic gates. To allow for more options for length-balanced scan chain configurations, the total number of CBC-pairs is preferably a multiple of 12 or 20, and should not be set to a prime number.

[0057] This invention supports the EXTEST and optional INTEST test modes specified by the IEEE-1149.1 protocol; it also features a parallel test mode and a user debugging mode.

[0058] In parallel testing mode, the host computer controls the test vectors to reorder and segment the configured scan chain according to the configurable boundary scan units. Each segment of data is simultaneously fed into the entry point of the parallel scan chain corresponding to the test circuit via the test machine. The response of the test vector is obtained from the exit points of the parallel scan chain when the next test vector enters the parallel scan chain corresponding to the test circuit. Specifically:

[0059] (1) Write the confCBC instruction to the instruction register of the TAP module to mount the CBC configuration register onto the JTAG chain.

[0060] (2) All CBC configuration information of each small core is sent bit by bit serially to the CBC configuration register via the JTAG chain. This configuration information takes effect when the TAP-FSM is in updateDR state.

[0061] (3) Write the startCPT instruction to the instruction register of the TAP module to attach the bypass register to the JTAG chain, and unload the CBC configuration register attached in step (1) from the JTAG chain to protect the written data. In this step, the enCPT flag bit is set; the control clock of the TAP-FSM is ANDed with enCPT and then sent to the CBC-pair to prevent these parallel scan chains from starting before the test begins.

[0062] (4) On the test machine side, the test vectors are reordered and segmented in advance according to the order of the scan chain configured by CBC-pair; each segment is simultaneously sent to the entry of the corresponding parallel scan chain; the response of this test vector will be obtained from each exit of the parallel scan chain when the next test vector is moved into the parallel scan chain.

[0063] (5) Clear the enCPT instruction in the instruction register of the TAP module and exit the parallel test mode.

[0064] User debugging mode applies to single scan chains. When the configuration boundary unit is configured as a single scan chain, the host computer controls the serial injection of test vectors into this single scan chain. The response of this test vector will be obtained from the exit of the scan chain when the next test vector is moved into the scan chain. Specifically:

[0065] Steps (1) and (2) are similar to those in the parallel test mode, except that the configuration information written to the CBC configuration register is different. When the CBC-pair is configured as a traditional single scan chain, the enBS flag bit is set; the control clock of the TAP-FSM is ANDed with enBS and then sent to the CBC-pair.

[0066] (3) Write the EXTEST or INTEST instruction specified by the 1149.1 protocol to the instruction register of the TAP module to attach the above single scan chain to the JTAG chain.

[0067] (4) Test vectors are serially fed into the single scan chain via the TDI pin of the JTAG interface; the response of the test vector will be obtained from the exit of the scan chain (TDO pin of the JTAG interface) when the next test vector is moved into the scan chain.

[0068] (5) Clear the EXTEST or INTEST instruction in the instruction register of the TAP module and exit user debug mode.

[0069] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A configurable parallel test circuit for a three-dimensional stacked packaged chip, characterized in that, The 3D stacked packaged chip includes configurable boundary scan unit pairs. Each configurable boundary scan unit pair includes a first configurable boundary scan unit that can be connected to the I / O ports of the small chip and a second configurable boundary scan unit that can be connected to the I / O ports of the small chip. The I / O ports of the small chip include small chip input ports and small chip output ports. The two configurable boundary scan units in the configurable boundary scan unit pair are configured to different modes through different control signals. Multiple configurable boundary scan unit pairs are set on each layer of small chip. The multiple configurable boundary scan unit pairs on each layer of small chip are connected in series according to different modes. The configurable boundary scan unit pairs on adjacent layers of small chip are directly cascaded through the I / O ports of the small chip. The first configurable boundary scan unit and the second configurable boundary scan unit are configured into different modes through different control signals, including configuring the enI signal, enO signal, enS signal, enP signal, enI2 signal, enO2 signal, enS2 signal, and enP2 signal as binary signals of 0 or 1 respectively, forming seven configuration modes M1 to M7, where M1 is 01001001, M2 is 10100100, M3 is 10010100, M4 is 00100010, and M5 is 0100000.

1. M6 is 10100010, and M7 is 00010010; the three-dimensional stacked packaged chip has 3 layers of small chips, and each layer of small chips is provided with 12 configurable boundary scan unit pairs. The 12 configurable boundary scan unit pairs on each layer of small chips are physically connected in series with each other through input ports and output ports. By setting the mode of the configurable boundary scan unit pairs, different circuit conduction conditions are formed. The number of scan chains is different under different circuit conduction conditions. Thus, the number of scan chains can be configured by switching the mode of each configurable boundary scan unit pair. The configuration scheme for the number of scanning chains is as follows: The three layers of small chips in the three-dimensional stacked package chip are divided into a top layer, a middle layer, and a bottom layer. The 12 configurable boundary scan units of each layer are divided into two equal parts from the middle. The circuit mode configuration of the two equal parts is exactly the same. The configuration of the bottom layer small chip is that the configurable boundary scan unit modes are M1, M2, M4, M4, M4, M7 respectively; the configurable boundary scan unit modes of the middle layer small chip are M1, M2, M4, M4, M4, M7 respectively; and the configurable boundary scan unit modes of the top layer small chip are M5, M6, M4, M4, M4, M7. Alternatively, the configuration scheme for the number of scanning chains is as follows: the three layers of small chips in the three-dimensional stacked package chip are divided into a top layer, a middle layer, and a bottom layer. The 12 configurable boundary scanning units of each layer are divided into three equal parts. The circuit mode configuration of the three equal parts is exactly the same. The configuration of the bottom layer small chip is that the configurable boundary scanning unit mode is M1, M2, M4, M7; the configurable boundary scanning unit mode of the top layer small chip is M5, M6, M4, M7; and the configurable boundary scanning unit mode of the middle layer small chip is M1, M3, X, X, where X represents any value. Alternatively, the configuration scheme for the number of scanning chains is as follows: the three layers of small chips in the three-dimensional stacked package chip are divided into a top layer, a middle layer, and a bottom layer. The 12 configurable boundary scan units of each layer are divided into four equal parts. The circuit mode configuration of the four equal parts is exactly the same. The configuration of the bottom layer small chip is that the configurable boundary scan unit mode is M1, M2, M7; the configurable boundary scan unit mode of the middle layer small chip is M1, M2, M7; and the configurable boundary scan unit mode of the top layer small chip is M5, M6, M7.

2. The configurable parallel test circuit for a three-dimensional stacked packaged chip according to claim 1, characterized in that, The first configurable boundary scan unit includes a first DWR register, a UR register, a first scan path gating module, and a first scan chain segment. The first DWR register is connected to the UR register and is connected to one end of the first scan chain segment on the connection line. The other end of the first scan chain segment is connected to the first DWR register through the first scan path gating module.

3. The configurable parallel test circuit for a three-dimensional stacked packaged chip according to claim 2, characterized in that, The first scan path selection module includes a first controlled buffer gate to a fourth controlled buffer gate, a first selector, and a second selector. The first scan chain segment includes a first boundary scan chain segment, a first internal scan chain segment, a first NOT gate, and a fifth to a seventh controlled buffer gate. The clk terminal of the first DWR register receives the Control clock signal, and the clk terminal of the UR register receives the updateDWR signal. The D terminal of the first DWR register is connected to the output terminal of the first selector, and the Q terminal of the first DWR register is connected to the D terminal of the UR register, the input terminals of the fifth controlled buffer gate, and the input terminal of the sixth controlled buffer gate, respectively. The first terminal of the first selector serves as the input terminal CTI of the first configurable boundary scan unit and is connected to the CVO2 port of the second configurable boundary scan unit. The second terminal of the first selector receives the PAD signal and is connected to the first terminal of the second selector. The second terminal of the second selector is connected to the Q terminal of the UR register. The CFO output port of the second selector is connected to the small chip input port. The input terminals of the first NOT gate, the controlled terminals of the fifth controlled buffer gate, and the seventh controlled buffer gate all receive the enISC signal. The output terminal of the first NOT gate is connected to the controlled terminal of the sixth controlled buffer gate. The output terminal of the sixth controlled buffer gate is connected to the output terminal of the seventh controlled buffer gate and the input terminal of the first boundary scan chain segment. The output terminal of the fifth controlled buffer gate is connected to the input terminal of the seventh controlled buffer gate through the first internal scan chain segment. The output terminal of the first boundary scan chain segment is connected to... The input terminals of the first controlled buffer gate to the third controlled buffer gate are connected. The output terminal CVO of the first controlled buffer gate is connected to the CVI2 port of the second configurable boundary scan unit. The output terminal of the second controlled buffer gate serves as the output terminal CTO of the first configurable boundary scan unit. The input terminal of the fourth controlled buffer gate is connected to the output terminal of the third controlled buffer gate and receives the PAD signal. The output terminal of the fourth controlled buffer gate is connected to the first terminal of the first selector. The first controlled buffer gate to the fourth controlled buffer gate receive the enP signal, the enS signal, the enO signal, and the enI signal, respectively. The control terminals of the first selector and the second selector receive the captureDWR signal and the enTest signal, respectively.

4. The configurable parallel test circuit for a three-dimensional stacked packaged chip according to claim 3, characterized in that, The second configurable boundary scan unit includes a second DWR register, a second scan path gating module, and a second scan chain segment. The second scan path gating module includes an eighth to eleventh controlled buffer gate, a third selector, and a fifth selector. The second scan chain segment includes a second boundary scan chain segment, a second internal scan chain segment, a second NOT gate, and twelfth to fourteenth controlled buffer gates. The clk terminal of the second DWR register receives the Controlclock2 signal. The D terminal of the second DWR register is connected to the output terminal of the third selector. The Q terminal of the first DWR register is connected to the second terminal of the fourth selector, the input terminals of the twelfth and thirteenth controlled buffer gates, respectively. The second terminal of the third selector is connected to the first terminal of the fifth selector and to the small chip output port. The first terminal of the third selector serves as the input terminal CTI2 of the second configurable boundary scan unit. The inputs of the second NOT gate, the controlled terminals of the twelfth and thirteenth controlled buffer gates all receive the enISC signal. The output of the second NOT gate is connected to the controlled terminal of the thirteenth controlled buffer gate. The output of the thirteenth controlled buffer gate is connected to the output of the fourteenth controlled buffer gate and the input of the second boundary scan chain segment. The output of the twelfth controlled buffer gate is connected to the input of the fourteenth controlled buffer gate through the second internal scan chain segment. The output of the second boundary scan chain segment is connected to the inputs of the eighth to tenth controlled buffer gates. The output CVO2 of the eighth controlled buffer gate is connected to the CVI port of the first configurable boundary scan unit. The output of the ninth controlled buffer gate serves as the second configurable boundary scan... The unit's output terminal CTO2, the output terminal of the tenth controlled buffer gate is connected to the first terminal of the fourth selector, the output terminal of the fourth selector is connected to the second terminal of the fifth selector, the output terminal of the fifth selector is connected to the input terminal of the eleventh controlled buffer gate and receives the PAD2 signal, and the output terminal of the eleventh controlled buffer gate is connected to the first terminal of the third selector; the eighth to eleventh controlled buffer gates receive the enP2 signal, the enS2 signal, the enO2 signal, and the enI2 signal respectively; the control terminals of the third and fourth selectors receive the captureDWR signal, the AND signal of the captureDWR signal and the extest signal respectively; and the control terminal of the fifth selector receives the enTest signal.

5. A method for a configurable parallel test circuit for a three-dimensional stacked packaged chip according to any one of claims 1-4, characterized in that, The parallel input and output ports of the test circuit are connected to the input and output ports of the TAP module used to implement the IEEE-1149.1 protocol, respectively. The host computer controls the test vectors to be reordered and segmented according to the configurable boundary scan unit in the order of the scan chain in the configured mode. Each segment is simultaneously sent to the entry of the parallel scan chain corresponding to the test circuit. The response of the test vector will be obtained from each exit of the parallel scan chain when the next test vector moves into the parallel scan chain corresponding to the test circuit. When the configurable boundary unit is configured to use a single scan chain in the configured mode, the host computer controls the serial injection of test vectors into the single scan chain. The response of the test vector will be obtained from the exit of the scan chain when the next test vector moves into the scan chain.

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