Display panel

Abstract

A display panel includes a substrate, a sub-pixel, and a patterned metal layer. The sub-pixel is disposed on the substrate and includes a switching component, a pixel electrode, a transparent electrode, and a reflective electrode. The pixel electrode is disposed on the substrate and electrically connected to the switching component. The transparent electrode is disposed on the pixel electrode, the reflective electrode is disposed on the transparent electrode, and the patterned metal layer is disposed between the pixel electrode and the transparent electrode. The patterned metal layer includes a first metal pattern and a first opening disposed in the first metal pattern and on a side of the pixel electrode in a first direction. The reflective electrode covers a first portion of the first opening and does not cover a second portion of the first opening in a second direction, where the first direction is parallel to a surface of the substrate and the second direction is perpendicular to the surface of the substrate.

Description

Technical Field

[0001] The present invention relates to a display panel, and in particular to a display panel with higher storage capacitance. Background Art

[0002] In existing transflective display panels, scan lines or data lines are required to block light penetrating between adjacent sub-pixels to reduce crosstalk. This limits the space available for electrodes used to generate storage capacitance (Cst), resulting in a smaller electrode area and a smaller storage capacitance. This in turn can easily lead to image anomalies and reduced display quality. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to improve the display quality of a display panel.

[0004] To solve the above technical problems, the present invention provides a display panel comprising a substrate, a sub-pixel and a patterned metal layer. The sub-pixel is arranged on the substrate, and the sub-pixel comprises a switch component, a pixel electrode, a transparent electrode and a patterned metal layer. The switch component is arranged on the substrate. The pixel electrode is arranged on the substrate and on one side of the switch component in a first direction, and the pixel electrode is electrically connected to the switch component, wherein the first direction is parallel to a surface of the substrate. The transparent electrode is arranged on the pixel electrode and electrically connected to the pixel electrode. The reflective electrode is arranged on the transparent electrode and electrically connected to the transparent electrode. The patterned metal layer is arranged between the pixel electrode and the transparent electrode, wherein the patterned metal layer comprises a first metal pattern and a first opening, the first opening is arranged in the first metal pattern and on one side of the pixel electrode in the first direction, the reflective electrode covers a first portion of the first opening in a second direction and does not cover a second portion of the first opening, and the second direction is perpendicular to the surface of the substrate.

[0005] In the display panel of the present invention, a first metal pattern of a patterned metal layer is additionally used to block unnecessary penetrating light, so that the area of ​​the scan line and the data line can be reduced, and the area of ​​the electrode portion of the pixel electrode and / or the common line can be increased to improve the storage capacitance. In addition, the electrode portion of the common line, the pixel electrode and the insulating layer therebetween can generate a first capacitance, the pixel electrode, the first metal pattern and the insulating layer therebetween can generate a second capacitance, the first metal pattern, the transparent electrode and the insulating layer therebetween can generate a third capacitance, and the storage capacitance is the sum of the first capacitance, the second capacitance and the third capacitance, thereby also obtaining a larger storage capacitance. Therefore, the display panel of the present invention improves the problem of screen flickering and improves display quality through a higher storage capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic top view of a pixel structure of a display panel according to a first embodiment of the present invention.

[0007] Figure 2 FIG. 1 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention.

[0008] Figure 3 FIG. 1 is a schematic top view of a pixel structure of a display panel according to a second embodiment of the present invention.

[0009] Figure 4 FIG. 4 is a schematic cross-sectional view of a display panel according to a second embodiment of the present invention.

[0010] Explanation of reference numerals: 10 - display panel; 100, 300 - substrate; 100s - surface; 102, 104, 108, 118 - patterned metal layer; 106, 110, 112, 114 - insulating layer; 116 - patterned transparent conductive layer; 400 - liquid crystal layer; CE1, CE2 - portion; CH - semiconductor layer; CL - common line; CO1, CO2 - contact hole; D - drain; DL1, DL2, DL3 - data line; G - gate; GL1, GL2 - scanning Line; MP1-first metal pattern; MP21, MP23-second metal pattern; OP11, OP13-first opening; OP21, OP23-second opening; OP31, OP33-opening; P1-first part; P2-second part; PE1, PE2-pixel electrodes; RE1, RE2-reflective electrodes; S-source; S1-distance; SP1, SP2-sub-pixel; SW1, SW2-switch components; TE1, TE2-transparent electrodes; X, Y, Z-directions. DETAILED DESCRIPTION

[0011] In order to enable those skilled in the art to further understand the present invention, the following specifically lists the preferred embodiments of the present invention, and with the help of the accompanying drawings, the components of the present invention and the desired effects are described in detail. It should be noted that the accompanying drawings are simplified schematic diagrams, and therefore only show the components and combination relationships related to the present invention to provide a clearer description of the basic structure or implementation method of the present invention. The actual components and layout may be more complex. In addition, for the sake of convenience, the components shown in the various drawings of the present invention are not drawn to scale with the number, shape, and size of the actual implementation. The detailed scale can be adjusted according to the design requirements.

[0012] The following figures indicate a direction X, a direction Y (which may also be referred to as the first direction), and a direction Z (which may also be referred to as the second direction). Direction Z may be perpendicular to the surface 100s of the substrate 100, and directions X and Y may be parallel to the surface 100s of the substrate 100. Direction Z may be perpendicular to directions X and Y, and direction X may be perpendicular to direction Y. The following figures may describe the spatial relationships of the structures based on directions X, Y, and Z.

[0013] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic top view of a pixel structure of a display panel according to a first embodiment of the present invention, and Figure 2 FIG. 1 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention. Figure 2 The structure corresponds to Figure 1 The display panel of this embodiment takes a semi-transmissive and semi-reflective liquid crystal panel as an example, but the present invention is not limited thereto. Figure 1 As shown, the display panel 10 includes a substrate 100, a plurality of scan lines (such as scan lines GL1 and GL2), and a plurality of data lines (such as data lines DL1, DL2, and DL3), and the scan lines and data lines are arranged on the substrate 100. The scan lines GL1 and GL2 extend along direction X and are arranged in direction Y, and the data lines DL1, DL2, and DL3 extend along direction Y and are arranged in direction X. The display panel 10 includes a plurality of sub-pixels, and the plurality of sub-pixels can be formed by interlacing the scan lines and the data lines. For example, the display panel 10 includes a sub-pixel SP1 and a sub-pixel SP2 arranged on the substrate 100, and the sub-pixel SP1 and the sub-pixel SP2 are arranged adjacent to each other in direction X.

[0014] like Figure 1 As shown, each sub-pixel of the display panel 10 includes a switch component. For example, sub-pixel SP1 includes a switch component SW1, and sub-pixel SP2 includes a switch component SW2. The switch component SW1 and the switch component SW2 are disposed on the substrate 100. The switch component may include a thin film transistor. The thin film transistor may be, for example, a bottom-gate thin film transistor, but is not limited thereto. In other embodiments, the thin film transistor may also be a top-gate thin film transistor. Furthermore, the thin film transistor may be, but is not limited to, a low-temperature polysilicon (LTPS) thin film transistor, an indium gallium zinc oxide (IGZO) thin film transistor, or an amorphous silicon (a-Si) thin film transistor.

[0015] The thin film transistor includes a gate G, a source S, a drain D, and a semiconductor layer CH. Scan line GL1 is electrically connected to the gate G of the switch element SW2, and scan line GL2 is electrically connected to the gate G of the switch element SW1. Scan lines GL1 and GL2 provide switching signals to the gates G of the switch elements SW1 and SW2, respectively, to control the thin film transistor, thereby controlling the display image.

[0016] The data line DL1 is provided between the sub-pixel SP1 and the sub-pixel SP2 in the direction X. The source electrodes S of the switch components SW1 and SW2 are electrically connected to the data line DL1 and can provide the source electrodes S of the switch components SW1 and SW2 with a grayscale signal through the data line DL1.

[0017] The sub-pixel SP1 includes a pixel electrode PE1, and the sub-pixel SP2 includes a pixel electrode PE2, and the pixel electrodes PE1 and PE2 are disposed on the substrate 100. The pixel electrode PE1 and the pixel electrode PE2 are disposed adjacent to each other in the direction X and between the scan lines GL1 and GL2 in the direction Y. The pixel electrode PE1 is disposed on one side of the switch component SW1 in the direction Y, as shown in FIG. Figure 1 , the pixel electrode PE1 can be arranged above the switch component SW1 in the direction Y, but is not limited thereto. The pixel electrode PE2 is arranged on one side of the switch component SW2 in the direction Y, such as Figure 1 The pixel electrode PE2 may be disposed below the switch element SW2 in direction Y, but is not limited thereto. The pixel electrode PE1 is electrically connected to the drain electrode D of the switch element SW1, and the pixel electrode PE2 is electrically connected to the drain electrode D of the switch element SW2. In addition, the data line DL1 is disposed between the pixel electrode PE1 and the pixel electrode PE2 in direction X.

[0018] The display panel 10 includes a common line CL extending along a direction X and arranged between a scan line GL1 and a scan line GL2 in a direction Y. A portion CE1 of the common line CL is arranged between the pixel electrode PE1 and the substrate 100, and another portion CE2 of the common line CL is arranged between the pixel electrode PE2 and the substrate 100, and the portion CE1 and the portion CE2 are arranged adjacent to each other in the direction X. The common line CL may have a voltage (such as a reference voltage (Vcom)), wherein the portion CE1 may be used as a common electrode in the sub-pixel SP1, and the portion CE2 may be used as a common electrode in the sub-pixel SP2. Figure 1 , the area of ​​the portion CE1 of the common line CL may be larger than the area of ​​the pixel electrode PE1 , and the area of ​​the portion CE2 of the common line CL may be larger than the area of ​​the pixel electrode PE2 , but the present invention is not limited thereto.

[0019] Sub-pixel SP1 includes a transparent electrode TE1, which is disposed on and electrically connected to pixel electrode PE1. Sub-pixel SP2 includes a transparent electrode TE2, which is disposed on and electrically connected to pixel electrode PE2. Sub-pixel SP1 includes a reflective electrode RE1 disposed on and electrically connected to transparent electrode TE1, and sub-pixel SP2 includes a reflective electrode RE2 disposed on and electrically connected to transparent electrode TE2. Therefore, reflective electrode RE1 and transparent electrode TE1 can have the same voltage as pixel electrode PE1, and reflective electrode RE2 and transparent electrode TE2 can have the same voltage as pixel electrode PE2.

[0020] The display panel 10 includes a patterned metal layer 102 disposed between pixel electrodes (eg, pixel electrodes PE1 and PE2) and transparent electrodes (eg, transparent electrodes TE1 and TE2). Figure 2 ).like Figure 1 The patterned metal layer 102 includes a first metal pattern MP1 and a plurality of first openings (such as first openings OP11 and OP13), and the plurality of first openings are arranged in the first metal pattern MP1, wherein the first opening OP11 is arranged on one side of the pixel electrode PE1 (such as the upper edge) in the direction Y, and the first opening OP13 is arranged on one side of the pixel electrode PE2 (such as the lower edge) in the direction Y, but is not limited to this.

[0021] The reflective electrode RE1 covers a first portion P1 of the first opening OP11 and does not cover a second portion P2 of the first opening OP11 in the direction Z. The reflective electrode RE2 covers a first portion P1 of the first opening OP13 and does not cover a second portion P2 of the first opening OP13 in the direction Z. Thus, light from the backlight source can pass through the second portion P2 of the first opening OP11 and the second portion P2 of the first opening OP13, thereby enhancing the brightness of the display panel 10.

[0022] For example, the first metal pattern MP1 can overlap with the data lines DL1, DL2, and DL3 in direction Z, thereby reducing the amount of light leakage between adjacent sub-pixels. Compared to conventional display panels that use scan lines and data lines to block unnecessary penetrating light, the display panel 10 of the present invention uses a patterned metal layer 102 to block unnecessary penetrating light, thereby reducing the area of ​​the scan lines GL1, GL2 and the data lines DL1, DL2, and DL3. This allows the area of ​​the pixel electrodes PE1, PE2 and / or portions CE1 and CE2 of the common line CL to be increased to improve storage capacitance, thereby improving the problem of screen flicker and enhancing display quality. In addition, the reduced area of ​​the data lines DL1, DL2, and DL3 can also reduce the capacitance (Cgd) between the gate G and the drain D.

[0023] The patterned metal layer 102 further includes a plurality of second openings (e.g., second openings OP21 and OP23) and a plurality of second metal patterns (e.g., second metal patterns MP21 and MP23). The plurality of second openings are disposed within the first metal pattern MP1, wherein the second opening OP21 is disposed on the other side (e.g., the lower side) of the pixel electrode PE1 in the direction Y, and the second opening OP23 is disposed on the other side (e.g., the upper side) of the pixel electrode PE2 in the direction Y, but the present invention is not limited thereto. Furthermore, the second metal patterns are disposed within the second openings, for example, the second metal pattern MP21 is disposed within the second opening OP21, and the second metal pattern MP23 is disposed within the second opening OP23.

[0024] The second metal pattern and the semiconductor layer overlap in direction Z, as shown in FIG. Figure 1 or Figure 2 The second metal pattern MP21 and the semiconductor layer CH of the switch element SW1 overlap in the direction Z, and the second metal pattern MP23 and the semiconductor layer CH of the switch element SW2 overlap in the direction Z. The second metal patterns MP21 and MP23 are floating, so that the underlying switch elements SW1 and SW2 are not affected by the voltage of the second metal patterns MP21 and MP23.

[0025] Furthermore, the first metal pattern MP1 has a voltage (e.g., a reference voltage (Vcom)), and the distance (e.g., distance S1) between the second metal patterns MP21, MP23 and the first metal pattern MP1 is greater than or equal to 3.5 microns. This prevents the second metal patterns MP21, MP23 from being coupled by the voltage of the first metal pattern MP1, thereby preventing the switch elements SW1, SW2 beneath the second metal patterns MP21, MP23 from being affected.

[0026] like Figure 2 ,by Figure 1 Taking the cross-sectional schematic diagram of the sub-pixel SP1 in FIG. 1 as an example, the method for manufacturing the display panel 10 of this embodiment may include the following steps, but is not limited to the following description. In the following description, using a mask to perform a photolithography process to form a patterned metal layer or a patterned transparent conductive layer means first forming a metal film or a transparent conductive film, then performing an exposure process using a mask, and then performing a development process and an etching process to pattern the metal film or the transparent conductive film to form a patterned metal layer or a patterned transparent conductive layer; and using a mask to perform a photolithography process to form a semiconductor layer means first forming a semiconductor film, then performing an exposure process using a mask, and then performing a development process and an etching process to pattern the semiconductor film to form a semiconductor layer.

[0027] First, a substrate 100 is provided and a photolithography process is performed using a first mask to form a patterned metal layer 104 on the substrate 100. The patterned metal layer 104 includes Figure 1 The scanning lines GL1, GL2, the gates G of the switch elements SW1, SW2 and the common line CL (and the portions CE1, CE2 thereof), but not limited thereto, are formed. Next, an insulating layer 106 is formed on the patterned metal layer 104 and can serve as a gate insulating layer.

[0028] Next, a second mask is used to perform a photolithography process to form a semiconductor layer CH on the insulating layer 106. The semiconductor layer CH may be disposed correspondingly on the gate G in the direction Z, and the semiconductor layer CH may be, for example, amorphous silicon, polycrystalline silicon, or a metal oxide (such as indium gallium zinc oxide), but is not limited thereto.

[0029] Next, a third mask is used to perform a photolithography process to form a patterned metal layer 108 on the insulating layer 106. The patterned metal layer 108 includes Figure 1 The data lines DL1, DL2, DL3, the pixel electrodes PE1, PE2 and the source S and drain D of the switch components SW1, SW2 are shown in FIG. Figure 2 The drain electrode D in the patterned metal layer 108 can be directly connected to the pixel electrode PE1. Next, an insulating layer 110 (or a third insulating layer) is formed on the patterned metal layer 108.

[0030] Next, a fourth mask is used to perform a photolithography process to form a patterned metal layer 102 on the insulating layer 110. The patterned metal layer 102 includes Figure 1 The first metal pattern MP1, the second metal pattern MP21, MP23, the first openings OP11, OP13 and the second openings OP21, OP23 in the patterned metal layer 102 are not limited thereto. In addition, the insulating layer 110 may be disposed on the patterned metal layer 102 (eg Figure 2 The first metal pattern MP1 in the embodiment and the patterned metal layer 108 (such as Figure 2 Between the pixel electrodes PE1).

[0031] Next, an insulating layer 112 (or second insulating layer) is formed on the patterned metal layer 102. Next, an insulating layer 114 (or first insulating layer) is formed on the insulating layer 112, such that the insulating layer 112 is disposed between the insulating layer 114 and the patterned metal layer 102. Furthermore, a fifth mask is used to perform an exposure process and a development process to form a plurality of contact holes CO1 (or first contact holes) in the insulating layer 114.

[0032] Next, a sixth mask is used to perform an exposure process, and then a development process and an etching process are performed to form a plurality of contact holes CO2 (or second contact holes) in the insulating layer 112 and the insulating layer 110. Figure 2In this embodiment, the insulating layer 114 includes a contact hole CO1, and the insulating layer 112 and the insulating layer 110 include a contact hole CO2. The contact hole CO1 and the contact hole CO2 are connected and expose the surface of the pixel electrode PE1.

[0033] Next, a seventh mask is used to perform a photolithography process to form a patterned transparent conductive layer 116 on the insulating layer 114. The patterned transparent conductive layer 116 includes transparent electrodes TE1 and TE2, but is not limited thereto. Figure 2 The insulating layer 114 is disposed between the transparent electrode TE1 and the patterned metal layer 102. Furthermore, the transparent electrode TE1 extends into the contact hole CO1 and the contact hole CO2, and the transparent electrode TE1 contacts the pixel electrode PE1, but the present invention is not limited thereto. Therefore, the transparent electrode TE1 can have the same voltage as the pixel electrode PE1.

[0034] like Figure 2 The portion CE1 of the common line CL, the pixel electrode PE1, and the insulating layer 106 therebetween form a first capacitor. The pixel electrode PE1, the first metal pattern MP1, and the insulating layer 110 therebetween form a second capacitor. The first metal pattern MP1, the transparent electrode TE1, and the insulating layers 112 and 114 therebetween form a third capacitor. The storage capacitor is the sum of the first, second, and third capacitors. This improves the storage capacitance, thereby alleviating flicker and enhancing display quality.

[0035] Next, an eighth mask is used to perform a photolithography process to form a patterned metal layer 118 on the patterned transparent conductive layer 116. The patterned metal layer 118 includes, but is not limited to, reflective electrodes RE1 and RE2. Figure 2 , the reflective electrode RE1 also extends into the contact hole CO1 and the contact hole CO2 along with the transparent electrode TE1 , and the reflective electrode RE1 , the transparent electrode TE1 and the pixel electrode PE1 may be electrically connected to each other, but not limited thereto.

[0036] like Figure 2 When ambient light enters the display panel 10, it may be reflected by the back surface of the patterned metal layer 118 (e.g., the reflective electrode RE1) and remain within the display panel 10, potentially being absorbed by the underlying semiconductor layer CH. However, in the present invention, since the second metal pattern MP21 and the semiconductor layer CH of the switch element SW1 overlap in the direction Z, the second metal pattern MP21 can shield the semiconductor layer CH, thereby preventing the semiconductor layer CH from being affected by this light and causing optical leakage.

[0037] In addition, since the patterned metal layer 102 is disposed between the patterned transparent conductive layer 116 and the patterned metal layer 108, Figure 1When the first metal pattern MP1 blocks the data line DL1 , the first metal pattern MP1 can provide a shielding effect to reduce the influence of the signal of the transparent electrode TE1 on the signal of the data line DL1 , thereby reducing the crosstalk problem.

[0038] The patterned metal layer 102, the patterned metal layer 104, the patterned metal layer 108, and / or the patterned metal layer 118 may comprise a single metal layer such as aluminum, copper, titanium, tungsten, or silver, or a composite metal layer such as molybdenum / aluminum / molybdenum, titanium / aluminum / titanium, titanium / copper / titanium, titanium / copper, etc., but are not limited thereto. The patterned transparent conductive layer 116 may comprise indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum zinc oxide (AZO), but are not limited thereto. The insulating layer 106, the insulating layer 110, the insulating layer 112, and / or the second insulating layer 114 may comprise an inorganic insulating material, an organic insulating material, or a combination thereof, but are not limited thereto.

[0039] In addition, if Figure 2 The display panel 10 includes a substrate 300 and a liquid crystal layer 400. The substrate 300 is disposed opposite to the substrate 100 in the direction Z, and the liquid crystal layer 400 is disposed between the substrates 300 and 100. The substrates 100 and 300 may comprise rigid substrates such as glass, plastic, quartz, or sapphire, or may be flexible substrates such as polyimide (PI) or polyethylene terephthalate (PET), but are not limited thereto. The liquid crystal layer 400 may comprise any suitable type of liquid crystal, but is not limited thereto.

[0040] The display panel of the present invention is not limited to the above-mentioned embodiment. Other embodiments of the present invention will be further disclosed below. However, in order to simplify the description and highlight the differences between the various embodiments or variations, the same reference numerals are used below to mark the same components, and repeated parts will not be repeated.

[0041] Please refer to Figure 3 and Figure 4 , Figure 3 is a top view schematically showing a pixel structure of a display panel according to a second embodiment of the present invention, and Figure 4 FIG. 4 is a schematic cross-sectional view of a display panel according to a second embodiment of the present invention. Figure 4 The structure corresponds to Figure 3 In this embodiment, the patterned transparent conductive layer 116 (such as transparent electrodes TE1 and TE2) is disposed between the insulating layer 114 and the insulating layer 112. Figure 4The insulating layer 114 is disposed between the reflective electrode RE1 (ie, the patterned metal layer 118) and the transparent electrode TE1 (ie, the patterned transparent conductive layer 116), and the insulating layer 112 is disposed between the transparent electrode TE1 (ie, the patterned transparent conductive layer 116) and the first metal pattern MP1 (ie, the patterned metal layer 102).

[0042] In this embodiment, after the insulating layer 112 is formed, a fifth mask is used to perform an exposure process, and then a development process and an etching process are performed to form a plurality of contact holes CO2 in the insulating layer 112 and the insulating layer 110. Figure 4 The insulating layer 112 and the insulating layer 110 include a contact hole CO2, and the contact hole CO2 exposes the surface of the pixel electrode PE1.

[0043] Next, a sixth mask is used to perform a photolithography process to form a patterned transparent conductive layer 116 on the insulating layer 112. Figure 4 , the transparent electrode TE1 extends into the contact hole CO2, and the transparent electrode TE1 contacts the pixel electrode PE1, but the present invention is not limited thereto. On the other hand, since there is only the insulating layer 112 between the patterned transparent conductive layer 116 and the patterned metal layer 102, the distance between them is relatively close. In order to prevent the floating second metal pattern MP21 from being coupled by the voltage in the patterned transparent conductive layer 116 and then affecting the switch element SW1 below, the patterned transparent conductive layer 116 includes an opening OP31 disposed on the second metal pattern MP21. In addition, the patterned transparent conductive layer 116 also includes an opening OP33 disposed on the second metal pattern MP23 (such as Figure 3 ).

[0044] Next, an insulating layer 114 is formed on the patterned transparent conductive layer 116. In addition, a seventh mask is used to perform an exposure process and a development process to form a plurality of contact holes CO1 in the insulating layer 114. Figure 4 The insulating layer 114 includes a contact hole CO1, and the contact hole CO1 exposes the surface of the transparent electrode TE1. In this embodiment, the contact hole CO1 and the contact hole CO2 are separated.

[0045] Next, an eighth mask is used to perform a photolithography process to form a patterned metal layer 118 on the insulating layer 114. Figure 4 , the reflective electrode RE1 extends into the contact hole CO1 and contacts the transparent electrode TE1, so that the reflective electrode RE1, the transparent electrode TE1 and the pixel electrode PE1 can be electrically connected to each other.

[0046] In this embodiment, since only the insulating layer 112 but not the insulating layer 114 is provided between the transparent electrode TE1 and the first metal pattern MP1, the first metal pattern MP1, the transparent electrode TE1, and the insulating layer 112 therebetween can generate a larger third capacitance, thereby further increasing the storage capacitance, improving the problem of screen flicker, and enhancing the display quality.

[0047] In summary, in the display panel of the present invention, a first metal pattern of a patterned metal layer is additionally used to block unnecessary penetrating light, so that the area of ​​the scan line and the data line can be reduced, and the area of ​​the electrode portion of the pixel electrode and / or the common line can be increased to improve the storage capacitance. In addition, the electrode portion of the common line, the pixel electrode and the insulating layer therebetween can generate a first capacitance, the pixel electrode, the first metal pattern and the insulating layer therebetween can generate a second capacitance, the first metal pattern, the transparent electrode and the insulating layer therebetween can generate a third capacitance, and the storage capacitance is the sum of the first capacitance, the second capacitance and the third capacitance, thereby also obtaining a larger storage capacitance. Therefore, the display panel of the present invention improves the problem of screen flickering and improves display quality through a higher storage capacitance.

[0048] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: a substrate; a sub-pixel disposed on the substrate, the sub-pixel comprising: a switch assembly, disposed on the substrate; a pixel electrode disposed on the substrate and on one side of the switch component in a first direction, and electrically connected to the switch component, wherein the first direction is parallel to a surface of the substrate; a transparent electrode disposed on the pixel electrode and electrically connected to the pixel electrode; and a reflective electrode disposed on the transparent electrode and electrically connected to the transparent electrode; and a patterned metal layer disposed between the pixel electrode and the transparent electrode, wherein the patterned metal layer includes a first metal pattern and a first opening, the first opening being disposed in the first metal pattern and on one side of the pixel electrode in the first direction, the reflective electrode covering a first portion of the first opening and not covering a second portion of the first opening in a second direction, and the second direction being perpendicular to the surface of the substrate.

2. The display panel according to claim 1, wherein The patterned metal layer further includes a second opening and a second metal pattern. The second opening is arranged in the first metal pattern and on the other side of the pixel electrode in the first direction, and the second metal pattern is arranged in the second opening.

3. The display panel according to claim 2, wherein: The switch component includes a semiconductor layer, and the second metal pattern and the semiconductor layer overlap in the second direction.

4. The display panel according to claim 2, wherein: The first metal pattern has a voltage, and the second metal pattern is floating.

5. The display panel according to claim 1, wherein The invention also includes a first insulating layer arranged between the transparent electrode and the patterned metal layer.

6. The display panel according to claim 5, wherein: Also includes: a second insulating layer disposed between the first insulating layer and the patterned metal layer; as well as a third insulating layer, disposed between the patterned metal layer and the pixel electrode, The first insulating layer includes a first contact hole, the second insulating layer and the third insulating layer include a second contact hole, and the first contact hole is connected to the second contact hole.

7. The display panel according to claim 6, wherein: The transparent electrode and the reflective electrode extend into the first contact hole and the second contact hole, and the transparent electrode contacts the pixel electrode.

8. The display panel according to claim 1, wherein: The invention further comprises a first insulating layer disposed between the reflective electrode and the transparent electrode, wherein the first insulating layer comprises a first contact hole, and the reflective electrode extends into the first contact hole and contacts the transparent electrode.

9. The display panel according to claim 8, wherein: Also includes: a second insulating layer disposed between the transparent electrode and the patterned metal layer; as well as a third insulating layer, disposed between the patterned metal layer and the pixel electrode, The second insulating layer and the third insulating layer include a second contact hole, the first contact hole and the second contact hole are separated, and the transparent electrode extends into the second contact hole and contacts the pixel electrode.

10. The display panel according to claim 1, wherein A common line is also included and is arranged between the pixel electrode and the substrate.

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