SiC mosfet power module with low parasitic inductance

Abstract

The application discloses a SiC MOSFET power module with low parasitic inductance, comprising a substrate base plate, a lining plate is arranged on the substrate base plate, a circuit pattern is etched on the top of the lining plate, and a plurality of SiC power chips and a plurality of SiC reverse recovery diodes with equal quantity are arranged on the lining plate, the SiC power chips and the SiC reverse recovery diodes are reversely connected in parallel one by one, and a power positive terminal, a power negative terminal and an alternating current terminal are arranged on the lining plate. The SiC MOSFET power module with low parasitic inductance can significantly reduce the parasitic inductance of a traditional SiC MOSFET power module without increasing the process difficulty.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology and relates to SiC MOSFET power modules with low parasitic inductance. Background Technology

[0002] With the continuous development of industries such as power electronics and electric vehicles, the requirements for power modules are constantly increasing, such as gradually increasing power density and operating frequency. Traditional SiC MOSFET power modules use the SiIGBT packaging structure. In practical applications, the SiIGBT packaging structure introduces a large amount of parasitic inductance. This parasitic inductance, along with di / dt, interacts with the SiC power chip, generating voltage stress. When the voltage stress exceeds the rated voltage of the SiC power chip, it can cause chip damage. Therefore, to fully utilize the fast switching advantage of SiC MOSFET power modules, it is necessary to optimize the parasitic inductance introduced by the packaging structure. Summary of the Invention

[0003] The purpose of this invention is to provide a SiC MOSFET power module with low parasitic inductance, which can effectively reduce the parasitic inductance inside the power module without increasing the difficulty of the manufacturing process.

[0004] The technical solution adopted in this invention is a SiC MOSFET power module with low parasitic inductance, including a substrate, a liner on the substrate, a circuit pattern etched on the top of the liner, and a plurality of equal numbers of SiC power chips and a plurality of SiC reverse recovery diodes disposed on the liner. The SiC power chips and SiC reverse recovery diodes are connected in parallel in reverse in a one-to-one correspondence. The module also includes a power positive terminal, a power negative terminal, and an AC terminal disposed on the liner.

[0005] The circuit topology of the SiC MOSFET power module is a dual-chip parallel half-bridge structure circuit. The SiC power chips are symmetrically distributed on the substrate. There are four SiC power chips: SiC power chip A, SiC power chip B, SiC power chip C, and SiC power chip D. There are also four SiC reverse recovery diodes: SiC reverse recovery diode A, SiC reverse recovery diode B, SiC reverse recovery diode C, and SiC reverse recovery diode D. The SiC power chips and SiC reverse recovery diodes are distributed in two rows on the chip solder layer. One row, from one end to the other, is SiC reverse recovery diode A, SiC power chip A, SiC power chip B, and SiC reverse recovery diode B. This row is the upper arm of the half-bridge structure circuit. The other row, from one end to the other, is SiC power chip C, SiC reverse recovery diode C, SiC reverse recovery diode D, and SiC power chip D. This row is the lower arm of the half-bridge structure circuit. The positions of SiC reverse recovery diode A and SiC power chip C correspond.

[0006] The positive power terminal, AC terminal, and negative power terminal are arranged from top to bottom. The positive power terminal is located between SiC power chip A and SiC power chip B. The positive power terminal is used to connect the drain of the upper bridge arm MOSFETs of the half-bridge circuit to the positive voltage of the external bus. The negative power terminal is located between SiC reverse recovery diode C and SiC reverse recovery diode D. The negative power terminal is used to connect the source of the lower bridge arm MOSFETs of the half-bridge circuit to the negative voltage of the bus. SiC power chip A and SiC reverse recovery diode C are located on the same side, and SiC power chip B and SiC reverse recovery diode D are located on the same side, respectively. The AC terminal is located between the positive power terminal and the negative power terminal and is connected to the load.

[0007] The invention is further characterized in that,

[0008] A substrate solder layer is coated on the substrate, and a backing plate is placed on the substrate solder layer.

[0009] The substrate is a DBC composite substrate, which has a three-layer structure, consisting of an upper copper layer, a ceramic layer, and a lower copper layer from top to bottom. The circuit pattern is etched on the upper copper layer, and the SiC power chip, SiC reverse recovery diode, power positive terminal, power negative terminal, and AC terminal are also located on the upper copper layer.

[0010] The upper copper layer of the DBC composite substrate is connected to different electrodes of the SiC power chip via bonding wires.

[0011] The substrate is coated with a chip solder layer, and the SiC power chip and SiC reverse recovery diode are connected to the substrate through the chip solder layer.

[0012] The beneficial effects of this invention are:

[0013] This invention relates to a SiC MOSFET power module with low parasitic inductance. By placing the commutation devices on one side, such as SiC power chip A and SiC reverse recovery diode C on the same side, and SiC power chip B and SiC reverse recovery diode D on the same side, the parasitic inductance on the DBC layout is reduced by physically shortening the commutation path. This changes the traditional power terminal layout, placing the AC terminal between the DC positive terminal and the DC negative terminal. The magnetic flux cancellation between adjacent conductors reduces the parasitic inductance on the power terminals. Finally, by optimizing the DBC layout and power terminals, a SiC MOSFET package structure with low parasitic inductance is achieved. This invention's SiC MOSFET power module significantly reduces the parasitic inductance of traditional SiC MOSFET power modules without increasing the difficulty of the manufacturing process. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of the SiC MOSFET power module with low parasitic inductance of the present invention;

[0015] Figure 2 This is an equivalent spice circuit diagram of the SiC MOSFET power module with low parasitic inductance of the present invention;

[0016] Figure 3 This is a structural diagram of the comparison module;

[0017] Figure 4 This is a circuit diagram of the comparison module;

[0018] Figure 5 This is a diagram showing the double-pulse turn-on waveform of the present invention and the comparison module;

[0019] Figure 6 This is a diagram showing the dual-pulse turn-off waveform of the present invention and the comparison module.

[0020] In the diagram, 1. Substrate, 2. Substrate solder layer, 3. Backing plate, 4. Chip solder layer, 5. SiC power chip A, 6. SiC power chip B, 7. SiC power chip C, 8. SiC power chip D, 9. SiC reverse recovery diode A, 10. SiC reverse recovery diode B, 11. SiC reverse recovery diode C, 12. SiC reverse recovery diode D, 13. Bonding wire, 14. Power positive terminal, 15. Power negative terminal, 16. AC terminal. Detailed Implementation

[0021] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0022] Example

[0023] This embodiment provides a SiC MOSFET power module with low parasitic inductance, such as... Figure 1 As shown, the device includes a substrate 1, on which a substrate 3 is disposed. The substrate 3 is a DBC composite substrate with a three-layer structure, consisting of an upper copper layer, a ceramic layer, and a lower copper layer from top to bottom. The upper copper layer is etched with circuit patterns. Four SiC power chips and four SiC reverse recovery diodes are disposed on the substrate 3. The SiC power chips and SiC reverse recovery diodes are connected in parallel. The upper copper layer of the DBC composite substrate is connected to different electrodes of the SiC power chips via bonding wires 13. The device also includes a power positive terminal 14, a power negative terminal 15, and an AC terminal 16 disposed sequentially from top to bottom on the substrate. The SiC power chips, SiC reverse recovery diodes, and the power positive terminal 14, power negative terminal 15, and AC terminal 16 are also disposed on the upper copper layer. The equivalent SPICE circuit diagram of the SiC MOSFET power module of the present invention is shown below. Figure 2 As shown.

[0024] The substrate 1 has a length of 33.76 mm, a width of 29.76 mm, and a thickness of 3 mm, and is made of Cu material. A substrate solder layer 2 is coated on the substrate 1. The substrate solder layer 2 has a length of 30.76 mm, a width of 25.97 mm, and a thickness of 0.1 mm, and is made of Sn-Ag-Cu material. A backing plate 3 is disposed on the substrate solder layer 2.

[0025] The DBC composite substrate has a lower copper layer thickness of 0.3mm (material Cu), a ceramic layer thickness of 0.6mm (material AlSiC), and an upper copper layer thickness of 0.3mm (material Cu). The upper copper layer is etched to form a circuit pattern. The middle ceramic layer is used to achieve electrical isolation between the heat dissipation substrate and the upper copper layer. The lower copper layer is a whole copper foil connected to the heat dissipation substrate.

[0026] A chip solder layer 4 is coated on the substrate 3. The SiC power chip and the SiC reverse recovery diode are both connected to the substrate 3 through the chip solder layer 4. The chip solder layer 4 serves as a connection layer and includes a solder layer (3.1 mm long, 3.36 mm wide, and 0.1 mm thick) below the SiC power chip and a solder layer (3.08 mm long, 3.08 mm wide, and 0.1 mm thick) below the SiC recovery diode, both composed of SnAgCu.

[0027] SiC power chips and SiC reverse recovery diodes are the core switching devices of the power module. The SiC power chip model is CPM2-1200-0080B, with a thickness of 0.2mm. The four SiC power chips are SiC power chip A5, SiC power chip B6, SiC power chip C7, and SiC power chip D8. The SiC reverse recovery diode model is CPW4-1200-S020B, with a thickness of 0.37mm. The four SiC reverse recovery diodes are SiC reverse recovery diode A9, SiC reverse recovery diode B10, SiC reverse recovery diode C11, and SiC reverse recovery diode D12.

[0028] The SiC MOSFET power module circuit topology in this embodiment is a half-bridge structure circuit with two chips connected in parallel. The SiC power chips are symmetrically distributed on the substrate (3). The SiC power chips and SiC reverse recovery diodes are distributed in two rows on the chip solder layer 4. One row consists of SiC reverse recovery diode A9, SiC power chip A5, SiC power chip B6, and SiC reverse recovery diode B10 from left to right. This row is the upper bridge arm of the half-bridge structure circuit. The other row consists of SiC power chip C7, SiC reverse recovery diode C11, SiC reverse recovery diode D12, and SiC power chip D8 from left to right. This row is the lower bridge arm of the half-bridge structure circuit. The positions of SiC reverse recovery diode A9 and SiC power chip C7 are corresponding.

[0029] The positive power terminal 14, AC terminal 16, and negative power terminal 15 are arranged from top to bottom. The positive power terminal 14 is located between SiC power chip A5 and SiC power chip B6. The positive power terminal 14 is used to connect the drain of the upper bridge arm MOSFETs of the half-bridge structure circuit to the positive voltage of the external bus. The negative power terminal 15 is located between SiC reverse recovery diode C11 and SiC reverse recovery diode D12. SiC power chip A5 and SiC reverse recovery diode C11 are located on the same side, and SiC power chip B6 and SiC reverse recovery diode D12 are located on the same side, respectively. The negative power terminal 15 is used to connect the source of the lower bridge arm MOSFETs of the half-bridge structure circuit to the negative voltage of the bus. The AC terminal 16 is located between the positive power terminal 14 and the negative power terminal 15. The AC terminal 16 is connected to the load.

[0030] The above-mentioned emission method places the commutation devices on one side. Taking the upper bridge SiC power chip A5 and SiC power chip B6 as the switching transistors as an example, the upper bridge SiC power chip A5 and the lower bridge SiC reverse recovery diode C11, which participate in the commutation circuit during the switching process, are placed on the same side of the power terminals (power positive terminal 14, power negative terminal 15). It is also ensured that the upper and lower positions of SiC power chip A5 and SiC reverse recovery diode C11 are on the same vertical side. SiC power chip B6 and SiC reverse recovery diode D12 are on the other side of the power terminals, and their upper and lower positions are also on the same vertical line. The layout is symmetrical. Therefore, looking only at the power terminal side, the commutation devices are all on the same side and on a vertical line, which physically shortens the commutation path and reduces the internal parasitic inductance.

[0031] Bonding wire 13 is used for circuit connection. It is equipped with two types of A1 bonding wires: 5mil wire for connecting the gate and Kelvin source, and 12mil bonding wire for connecting the power circuit. The power circuit is equipped with four bonding wires according to the current level. According to the power level of this module 1200V / 60A, the bonding wires of the power circuit are connected in parallel with four bonding wires.

[0032] The positive power terminal 14, negative power terminal 15, and AC terminal 16 are all composed of 1mm thick Cu material. The AC terminal 16 is equidistant from the positive power terminal 14 and the negative power terminal 15 by 0.8mm. The relative area of ​​the AC terminal 16 used for flux cancellation is composed of Cu material with a length of 27.76mm and a width of 23mm. The AC terminal 16 has an elliptical through-hole with a short diameter of 3.25mm and a long diameter of 3.5mm for external circuit connection. Furthermore, considering the electrical clearance requirements for 1200V voltage levels in electrical design codes, a material with a high insulating dielectric will be placed between the three layers to achieve electrical isolation. Figure 1 Arrange the power terminals in sequence so that the AC terminal is in the middle. This ensures that there is always magnetic flux cancellation between a set of terminals during the turn-on and turn-off phases, thereby reducing the parasitic inductance between the terminals.

[0033] The working principle of the SiC MOSFET power module with low parasitic inductance of this invention is as follows:

[0034] When the dual-pulse signal is applied to the gates of SiC power chips C7 and D8, and the turn-off signal is applied to the gates of SiC power chips A5 and B6, an external inductive load L is connected to the negative power terminal 15 and the AC terminal 16. When the circuit is turned on, the current flows from the positive power terminal 14 through the inductive load L, through SiC power chips C7 and D8, and finally out. At this time, it can be seen that the current at the AC terminal 16 and the negative power terminal 15 inside the module is the same in magnitude but opposite in direction. When the circuit is turned off, due to the freewheeling effect of the external inductive load L, the current flows through the SiC reverse recovery diodes A9 and B10 and finally flows back to the positive power terminal 14. It can be seen that at the same time of turn-off, there is also a set of currents with the same magnitude but opposite direction at the positive power terminal 14 and the AC terminal 16.

[0035] Both during the turn-on and turn-off phases, there exists a set of terminal currents of the same magnitude but opposite direction. Utilizing the characteristic that adjacent conductors have the same current magnitude but opposite direction, resulting in negative mutual inductance, parasitic inductance on the power terminals is reduced. The commutation loop path runs from the positive power terminal 14 through the drain and source terminals of SiC power chips A5 and B6, the pad, bonding wire 13, the copper layer on the DBC composite substrate 3, SiC reverse recovery diodes C11 and D12, and finally reaches the negative AC terminal via bonding wire 13. By placing the AC terminal in the middle of the DC terminal, the commutation path length is effectively reduced, thus lowering parasitic inductance.

[0036] Will as Figure 3 The conventionally packaged power module shown is used as a comparative module of the present invention. A circuit diagram of the conventionally packaged power module is shown below. Figure 4 As shown, the parasitic inductance of these two structures was extracted using Q3D electromagnetic simulation software. Referring to Table 1, it can be seen that the parasitic inductance of the power circuit in the package structure of this invention is superior to that of the comparative module. This demonstrates the effectiveness of the DBC layout and power terminal design of the package structure of the invention. Figure 5 and Figure 6 The SiCMOSFET power module of this invention, with its low parasitic inductance, shows significant advantages compared to the simulated dual-pulse waveform of the same dual-parallel chip. The parasitic inductance of the power circuit is 7.52018nH, the peak overshoot voltage is 1.301kV, and the peak current is 96.4A. In contrast, the parasitic inductance of the power circuit of the comparison module is 26.88nH, the peak overshoot voltage is 1.39kV, and the peak current is 103.9A.

[0037] Table 1

[0038] Power circuit parasitic inductance / nH Novel Packaging Structure 7.52 Comparison of packaging structures 26.88

[0039] As can be seen from the above, the SiC MOSFET power module of the present invention with low parasitic inductance can effectively reduce the parasitic inductance inside the power module, and achieve an internal parasitic inductance of less than 10nH without increasing the difficulty of the process.

Claims

1. A SiC MOSFET power module with low parasitic inductance, characterized in that, The device includes a substrate (1), a liner (3) is disposed on the substrate (1), a circuit pattern is etched on the top of the liner (3), and a plurality of SiC power chips and a plurality of SiC reverse recovery diodes are disposed on the liner (3), the SiC power chips and the SiC reverse recovery diodes are connected in parallel in opposite directions in a one-to-one correspondence, and also includes a power positive terminal (14), a power negative terminal (15), and an AC terminal (16) disposed on the liner; The circuit topology of the SiC MOSFET power module is a half-bridge structure circuit with two chips connected in parallel. The SiC power chips are symmetrically distributed on the substrate (3). There are four SiC power chips, namely SiC power chip A (5), SiC power chip B (6), SiC power chip C (7), and SiC power chip D (8). There are also four SiC reverse recovery diodes, namely SiC reverse recovery diode A (9), SiC reverse recovery diode B (10), SiC reverse recovery diode C (11), and SiC reverse recovery diode D (12). The SiC power chips and SiC reverse recovery diodes The tubes are arranged in two rows on the chip solder layer (4). One row, from one end to the other, consists of SiC reverse recovery diode A (9), SiC power chip A (5), SiC power chip B (6), and SiC reverse recovery diode B (10). This row is the upper arm of the half-bridge structure circuit. The other row, from one end to the other, consists of SiC power chip C (7), SiC reverse recovery diode C (11), SiC reverse recovery diode D (12), and SiC power chip D (8). This row is the lower arm of the half-bridge structure circuit. The SiC reverse recovery diode A (9) corresponds to the SiC power chip C (7). The positive power terminal (14), AC terminal (16), and negative power terminal (15) are arranged from top to bottom. The positive power terminal (14) is located between SiC power chip A (5) and SiC power chip B (6). The positive power terminal (14) is used to connect the drain of the upper arm MOSFETs of the half-bridge structure circuit to the positive voltage of the external bus. The negative power terminal (15) is located between SiC reverse recovery diode C (11) and SiC reverse recovery diode D (12). SiC power chip A (5) and SiC reverse recovery diode C (11) are located on the same side, and SiC power chip B (6) and SiC reverse recovery diode D (12) are located on the same side, and the negative power terminal (15) is used to connect the source of the lower arm MOSFETs of the half-bridge structure circuit to the negative voltage of the bus. The AC terminal (16) is located between the positive power terminal (14) and the negative power terminal (15). The AC terminal (16) is connected to the load.

2. The SiC MOSFET power module with low parasitic inductance according to claim 1, characterized in that, The substrate (1) is coated with a substrate solder layer (2), and the backing plate (3) is disposed on the substrate solder layer (2).

3. The SiC MOSFET power module with low parasitic inductance according to claim 1, characterized in that, The substrate (3) is a DBC composite substrate. The DBC composite substrate has a three-layer structure, consisting of an upper copper layer, a ceramic layer, and a lower copper layer from top to bottom. The circuit pattern is etched on the upper copper layer. The SiC power chip, SiC reverse recovery diode, power positive terminal (14), power negative terminal (15), and AC terminal (16) are also located on the upper copper layer.

4. The SiC MOSFET power module with low parasitic inductance according to claim 3, characterized in that, The upper copper layer of the DBC composite substrate is connected to different electrodes of the SiC power chip via bonding wires (13).

5. The SiC MOSFET power module with low parasitic inductance according to claim 1, characterized in that, The substrate (3) is coated with a chip solder layer (4), and the SiC power chip and the SiC reverse recovery diode are connected to the substrate (3) through the chip solder layer (4).

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