Semiconductor device and method for manufacturing the same

Abstract

A semiconductor substrate (1) has a surface and a back surface facing each other, and a through hole (9) penetrating from the back surface to the surface. A metal film (10) is formed on the surface in a ring shape so as to surround the through hole (9). A surface electrode (6) has wiring electrodes (11, 12) covering the through hole (9) and the metal film (10), and is bonded to the surface on the outside of the metal film (10). A back electrode (15) is formed on the back surface and the through hole (9), and is connected to the wiring electrodes (11, 12). The metal film (10) has a lower ionization tendency than the wiring electrodes (11, 12) and a higher work function than the wiring electrodes (11, 12).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a through hole for connecting a back electrode and a front electrode and a method for manufacturing the same. Background Art

[0002] Devices such as high electron mobility transistors (HEMT) for high-frequency operation are formed from compound semiconductors such as nitride semiconductors. Generally speaking, in such semiconductor devices, a through hole called a via hole is formed in the semiconductor substrate to connect the ground terminal as the back electrode and the surface electrode.

[0003] However, the thickness of semiconductor substrates such as GaN on SiC is generally around 50um to 100um. When a through hole is formed on the substrate by dry etching, a large amount of residue will be precipitated on the inner side wall and bottom surface of the through hole. Although the fluorine-based dry etching used in the selective etching of GaN is effective for the formation of through holes, it cannot suppress the generation of side wall residues and bottom surface residues. Therefore, it is necessary to remove the residue by using a strong acid solution such as concentrated hydrochloric acid.

[0004] In addition, when forming a through hole, the base layer of the surface electrode becomes a receiver metal for dry etching. The commonly used Ti-based ohmic electrode has a weak resistance to strong acid solutions and is dissolved at a high etching rate. As a result, reliability is reduced. If the base layer of the surface electrode is not formed by a stable metal with high etching selectivity, long-term reliability cannot be ensured due to penetration or side etching of the surface electrode. Therefore, the base layer of the surface electrode uses Pt (platinum) with a positive standard redox potential in the ionization tendency as the receiver metal for etching (for example, refer to Patent Document 1).

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-187342

[0006] However, Pt has a large film stress and has low adhesion to GaN. Therefore, if Pt is used as the base layer of the surface electrode, there is a high risk of peeling of the surface electrode, which affects the reliability of other materials. Summary of the invention

[0007] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a semiconductor device with high reliability and a method for manufacturing the same.

[0008] The semiconductor device involved in the present disclosure is characterized in that it comprises: a semiconductor substrate having a surface and a back surface facing each other, and a through hole penetrating from the back surface to the surface; a metal film formed in an annular shape on the surface so as to surround the through hole; a surface electrode having a wiring electrode covering the through hole and the metal film and bonded to the surface on the outside of the metal film; and a back electrode formed on the back surface and the through hole and connected to the wiring electrode, the metal film having a lower ionization tendency than the wiring electrode and a higher work function than the wiring electrode.

[0009] In the present disclosure, a metal film is formed on the surface of a semiconductor substrate in a manner that surrounds a through hole. Since the metal film has a lower ionization tendency than the surface electrode, it has high moisture resistance to a strongly acidic solution. Therefore, in the wet etching for removing the side wall residue after forming the through hole, the side etching of the surface electrode can be suppressed. In addition, the surface electrode is bonded to the surface of the semiconductor substrate outside the metal film with low adhesion. As a result, abnormalities such as metal floating of the surface electrode can be prevented, and reliability can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a top view showing the semiconductor device according to the first embodiment.

[0011] Figure 2 yes Figure 1 A cross-sectional view of the source pad portion of FIG.

[0012] Figure 3 yes Figure 1 An enlarged top view of the source pad portion of FIG.

[0013] Figure 4 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 5 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 6 It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 7 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Figure 8 It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Fig. 9 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0019] Fig.10 It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0020] Fig.11 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Fig.12 It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Fig.13 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Fig.14 It is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0024] Fig.15 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0025] Fig.16 It is a top view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0026] Fig.17 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0027] Fig.18 It is a top view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0028] Fig.19 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0029] Fig. 20 It is a top view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0030] Fig.21 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0031] Fig. 22 It is a top view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0032] Fig.23 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0033] Fig.24 It is a top view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0034] Fig.25 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0035] Fig.26 It is a top view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0036] Fig. 27 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0037] Fig.28 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0038] A semiconductor device and a method for manufacturing the same according to the embodiments will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and duplicate description may be omitted.

[0039] Implementation Method 1

[0040] Figure 1 1 is a top view showing a semiconductor device according to Embodiment 1. An active region 2 of a transistor is formed on a semiconductor substrate 1. A transistor having a plurality of source electrodes 3, a plurality of gate electrodes 4, and a plurality of drain electrodes 5 is formed on the active region 2. A source pad 6, a gate pad 7, and a drain pad 8 are provided on the semiconductor substrate 1. The source pad 6 is connected to the plurality of source electrodes 3. The gate pad 7 is connected to the gate electrode 4. The drain pad 8 is connected to the plurality of drain electrodes 5.

[0041] Figure 2 Yes means Figure 1 A cross-sectional view of the source pad portion of FIG. Figure 2 In the figure, the insulating film of the electrode, the gate electrode, the drain electrode, etc. are omitted. Figure 3 yes Figure 1 The semiconductor substrate 1 includes a SiC substrate 1a and a GaN layer 1b formed on the SiC substrate 1a. A through hole 9 penetrates from the back surface of the semiconductor substrate 1 to the front surface.

[0042] The metal film 10 is formed in an annular shape on the surface of the semiconductor substrate 1 so as to surround the through hole 9. The metal film 10 is a single layer metal composed of any one of Pt, Ni and Ta, or a multilayer metal having the above metal as the bottom layer.

[0043] The source pad 6 is formed on the surface of the semiconductor substrate 1. The source pad 6 has wiring electrodes 11 and 12, a surface power supply layer 13, and a surface plating layer 14 stacked in sequence. The wiring electrodes 11 and 12 cover the through hole 9 and the metal film 10. The wiring electrode 11 is bonded to the surface of the semiconductor substrate 1 on the outside of the metal film 10. The wiring electrode 11 is preferably a metal such as Ti because it is in contact with the GaN layer 1b. The formation range of the wiring electrodes 11 and 12 is smaller than the surface power supply layer 13 and the surface plating layer 14, and larger than the metal film 10.

[0044] The back electrode 15 is formed on the back surface of the semiconductor substrate 1 and inside the through hole 9, and is in direct contact with and connected to the wiring electrodes 11 and 12. The back electrode 15 includes a back power supply layer 16 and a back plating layer 17 stacked in sequence. The surface plating layer 14 and the back plating layer 17 are, for example, Au plating layers.

[0045] The metal film 10 has a lower ionization tendency and a higher work function than the wiring electrodes 11 and 12. Therefore, Pt is most preferable as a material of the metal film 10, but other metals such as Ni or Ta may be used instead.

[0046] Next, a method for manufacturing the semiconductor device according to this embodiment will be described. Figure 4 , 5 , 7, 9, 11, and 13 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. Figure 6 , 8 10 and 12 are plan views showing a method for manufacturing a semiconductor device according to Embodiment 1. A detailed description of the electrode forming method, thinning, etc. will be omitted.

[0047] First, if Figure 4 As shown, the semiconductor substrate 1 is formed by epitaxially growing a GaN layer 1 b on a SiC substrate 1 a .

[0048] Next, if Figure 5 as well as Figure 6 As shown, a metal film 10 is formed in a ring shape on the surface of a semiconductor substrate 1. In order to pattern the metal film 10 into a ring shape by lift-off, for example, a highly anisotropic sputtering method such as long throw sputtering is preferably used as a film forming method of the metal film 10. Alternatively, the metal film 10 can be formed in a ring shape by performing lift-off using a double-layer resist. From the viewpoint of adhesion, the thickness of the metal film 10 is preferably about several nm to several tens of nm.

[0049] Next, if Figure 7 as well as Figure 8As shown, wiring electrodes 11 and 12 are formed on the surface of semiconductor substrate 1 so as to cover metal film 10 having low adhesion to GaN layer 1b. Wiring electrode 11 is bonded to the surface of semiconductor substrate 1 outside metal film 10.

[0050] The wiring electrode 12 is used as a receiving metal during dry etching for forming the through hole 9, and is generally preferably a metal that is alloyed with Ti to form a stable metal. Therefore, the material of the wiring electrode 12 is preferably Au or the like, but it may also be a single-layer metal or a multi-layer metal. However, if the wiring electrode 12 contains the material of the metal film 10 such as Pt, a residue that is difficult to remove is generated when the through hole 9 is formed. Therefore, it is preferred that the wiring electrode 12 does not contain the material of the metal film 10.

[0051] Next, if Fig. 9 as well as Fig.10 As shown, the surface power supply layer 13 is formed to cover the entire surface of the wiring electrode 12. The material of the surface power supply layer 13 is preferably an alloy using Pt, such as Ti / Pt / Au, etc. In this way, by plating the outermost surface with an alloy containing Pt, Br corrosion can be suppressed and reliability can be improved.

[0052] Next, if Fig.11 as well as Fig.12 As shown, Au plating is performed to form a surface plating layer 14 on the surface power supply layer 13. In this step, the wafer process on the surface side is completed.

[0053] Next, if Fig.13 As shown, a metal mask 18 of Ni or the like having an opening at the through hole forming portion is formed. By selective dry etching using, for example, a fluorine-based gas, the SiC substrate 1a and the GaN layer 1b are sequentially etched from the back side of the semiconductor substrate 1 to form the through hole 9. The through hole 9 reaches the wiring electrodes 11 and 12 inside the annular metal film 10. At this time, the wiring electrode 11 at the bottom surface of the through hole 9 disappears due to dry etching, and the etching stops at the wiring electrode 12 that functions as a receiving metal.

[0054] During dry etching, residues are generated on the side walls of the through hole 9. For this reason, wet etching using a strong acid solution such as concentrated hydrochloric acid is performed to remove the residues. However, the wiring electrode 11 composed of Ti has low moisture resistance to strong acid solutions. Without the metal film 10, side etching is performed from the side walls of the bottom surface of the through hole 9, so that abnormalities such as metal floating of the source pad 6 occur, including reliability deterioration in moisture resistance. By providing the metal film 10, side etching can be suppressed.

[0055] Next, the metal mask 18 is removed by, for example, ion milling or wet etching. Figure 2 as well as Figure 3 As shown, a back power supply layer 16 made of, for example, Ti / Au is formed on the back surface of the semiconductor substrate 1 and in the through hole 9, and is connected to the wiring electrodes 11 and 12. Au plating is performed to form a back plating layer 17 on the back power supply layer 16. The back plating layer 17 is not limited to Au, and may also be Cu or the like.

[0056] As described above, in this embodiment, the metal film 10 is formed on the surface of the semiconductor substrate 1 so as to surround the through hole 9. Since the ionization tendency of the metal film 10 is lower than that of the source pad 6, the moisture resistance to the strong acid solution is high. Therefore, in the wet etching for removing the side wall residue after the through hole 9 is formed, the side etching of the source pad 6 can be suppressed. In addition, the source pad 6 is bonded to the surface of the semiconductor substrate 1 outside the metal film 10 with low adhesion. As a result, abnormalities such as metal floating of the source pad 6 can be prevented, and reliability can be improved.

[0057] In addition, when the metal film 10 is not formed in a ring shape but is formed in the entire formation area of ​​the through hole 9, the metal film 10 becomes a metal that bears dry etching. For example, in the case of dry etching using a fluorine-based gas, a residue containing Pt that cannot be removed even by strong hydrochloric acid treatment will be generated on the bottom surface of the through hole 9, which will cause problems in terms of reliability and appearance. By forming the metal film 10 in a ring shape, these problems can be prevented. In addition, by forming a high stress metal such as Pt, that is, the metal film 10, in a range as small as possible, it is possible to suppress the deterioration of adhesion.

[0058] In addition, the work function of the metal film 10 is higher than that of the source pad 6. Therefore, the material of the metal film 10 can also be used in the gate electrode 4 that is Schottky-bonded to the surface of the semiconductor substrate 1, so the metal film 10 can be formed simultaneously with the gate electrode 4 of the transistor. Therefore, there is no need to add a new process to form the metal film 10, so the increase in the number of processes and product costs can be prevented. In this case, the gate electrode 4 includes a film made of the same material as the metal film 10.

[0059] In addition, a portion of the wiring electrodes 11 and 12 in contact with the back electrode 15 formed in the through hole 9 is dry-etched when forming the through hole 9. In order to prevent the generation of residues containing Pt, the wiring electrodes 11 and 12 preferably do not contain Pt.

[0060] Implementation Method 2

[0061] Fig.14: is a cross-sectional view of a semiconductor device according to Embodiment 2. The figure magnifies the transistor in the active layer region. A source electrode 3, a gate electrode 4, and a drain electrode 5 are formed on the surface of a semiconductor substrate 1. Instead of forming a through hole 9 in a source pad 6 as in Embodiment 1, a through hole 9 is formed in each source electrode 3 in an active region 2. That is, the source electrode 3 is an ISV (individual source via) type source electrode. The back electrode 15 is connected to the source electrode 3 via the through hole 9. In addition to the structure of the source pad 6 of Embodiment 1, the source electrode 3 also has an ohmic electrode 19 that is ohmically bonded to the surface of the semiconductor substrate 1 at a position outside the metal film 10. The gate electrode 4 has a gate base metal 4a that is Schottky bonded to the surface of the semiconductor substrate 1, and a gate top metal 4b formed on the gate base metal 4a.

[0062] Next, a method for manufacturing the semiconductor device according to this embodiment will be described. Fig.15 , 17 , 19, 21, 23, 25, 27, and 28 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. Fig.16 , 18 , 20, 22, 24, and 26 are top views showing a method for manufacturing a semiconductor device according to Embodiment 2. A detailed description of the electrode forming method, thinning, etc. is omitted. In addition, although each top view shows both the source electrode 3 and the gate electrode 4, each cross-sectional view shows only the source electrode 3.

[0063] First, if Fig.15 as well as Fig.16 As shown in FIG. 1 , a semiconductor substrate 1 is formed by epitaxially growing a GaN layer 1b on a SiC substrate 1a. Fig.16 2 shows a source electrode forming region 20 where an ISV type source electrode 3 is formed in a later step, and a gate electrode forming region 21 where a gate electrode 4 is formed.

[0064] Next, if Fig.17 as well as Fig.18 As shown, an ohmic electrode 19 is formed at the outer peripheral portion of the source electrode forming region 20 to be ohmically bonded to the surface of the semiconductor substrate 1. The ohmic electrode 19 is, for example, a single metal or a combination of multiple metals such as Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, and Mo. The ohmic electrode 19 is ohmically bonded to the semiconductor substrate 1.

[0065] In addition, the ohmic junction of the metal / semiconductor interface can be formed by forming a multi-element other than the metal element on the semiconductor substrate by a method such as evaporation, and performing a heat treatment such as annealing. After the heat treatment, a modified layer containing multiple elements is formed at the metal / semiconductor interface. As other methods, for example, a method of epitaxial growth by adding impurities, a method of diffusing impurities by ion implantation and thermal diffusion, or a method combining multiple of the above methods can be used.

[0066] Next, if Fig.19 as well as Fig. 20 As shown, a metal film 10 is formed in a ring shape on the surface of the semiconductor substrate 1 inside the ohmic electrode 19. The material of the metal film 10 is the same as that of the first embodiment, and Pt metal is used here.

[0067] In addition, the metal film 10 is also formed in the gate electrode forming region 21 and used as the gate base metal 4a of the gate electrode 4. By forming the gate base metal 4a of the gate electrode 4 simultaneously with the metal film 10, it is possible to avoid an increase in the number of steps. The metal film 10 and the ohmic electrode 19 are on the same surface or overlap. In addition, although not shown in the figure, the form of the drain electrode 5 does not need to be the same as the ISV type source electrode 3 of this embodiment.

[0068] Next, if Fig.21 as well as Fig. 22 As shown, wiring electrodes 11 and 12 are formed to cover the metal film 10 having low adhesion to the GaN layer 1b. The wiring electrode 11 is preferably made of a metal having high adhesion such as Ti. The wiring electrodes 11 and 12 are formed inside the ohmic electrode 19 forming an ohmic junction.

[0069] Before forming the wiring electrodes 11 and 12, a gate top metal 4b is formed on the metal film 10 in the gate electrode forming region 21, thereby forming the gate electrode 4. In addition, the gate electrode 4 may be a single layer of the metal film 10. In the case of a single layer, since a gate cross-sectional area capable of withstanding the current capacity applied to one gate electrode 4 is required, the film thickness of the metal film 10 needs to be increased.

[0070] The wiring electrode 12 is preferably a metal including Au, but may also be a single metal or a combination of multiple metals such as Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, Mo, etc. However, if the wiring electrode 12 includes the material of the metal film 10 such as Pt, a residue that is difficult to remove is generated when the through hole 9 is formed. Therefore, it is preferred that the wiring electrode 12 does not include the material of the metal film 10.

[0071] Next, if Fig.23 as well as Fig.24As shown, the surface power supply layer 13 is formed in a manner covering the entire surface of the wiring electrode 12. The surface power supply layer 13 is formed so as to be located inside the ohmic electrode 19 and outside the wiring electrodes 11 and 12. The material of the surface power supply layer 13 is preferably an alloy using Pt, such as Ti / Pt / Au. This can suppress Br corrosion.

[0072] Next, if Fig.25 as well as Fig.26 As shown, Au plating is performed to form a surface plating layer 14 on the surface power supply layer 13. In this step, the wafer process on the surface side is completed.

[0073] Next, if Fig. 27 As shown, a metal mask 18 is formed in the same manner as in Embodiment 1, and a through hole 9 is formed by selective dry etching or the like. In a plan view, the through hole 9 is formed inside the ring-shaped metal film 10. In order to remove the side wall residue generated on the side wall of the through hole 9 during dry etching, wet etching is performed. By providing the metal film 10, side etching is suppressed, and abnormalities such as metal floating are prevented, thereby improving reliability.

[0074] Finally, if Fig.28 As shown, the metal mask 18 is removed, and a back power supply layer 16 and a back plating layer 17 are formed on the back surface of the semiconductor substrate 1 and in the through hole 9 .

[0075] As described above, the source electrode 3 is an ISV type source electrode and has the same structure as the source pad 6 of the first embodiment. Therefore, the same effect as the first embodiment can be obtained. However, the metal film 10 composed of Pt or the like with a high work function is not preferred as an ohmic electrode in terms of characteristics. For this reason, an ohmic electrode 19 is provided instead of the metal film 10 on the outer peripheral portion of the lower surface of the source electrode 3. Thus, the deterioration of the contact resistance can be suppressed.

[0076] Description of Reference Numerals

[0077] 1...semiconductor substrate; 3...source electrode (surface electrode); 4...gate electrode; 6...source pad (surface electrode); 9...through hole; 10...metal film; 11, 12...wiring electrodes; 13...surface power supply layer; 14...surface plating layer; 15...back electrode; 19...ohmic electrode.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A semiconductor substrate having a front surface and a back surface facing each other, and a through hole penetrating from the back surface to the front surface; a metal film formed in an annular shape on the surface so as to surround the through hole; a surface electrode having a wiring electrode covering the through hole and the metal film and bonded to the surface outside the metal film; as well as a back electrode formed on the back surface and the through hole and connected to the wiring electrode, The metal film has a lower ionization tendency than the wiring electrode and a higher work function than the wiring electrode.

2. The semiconductor device according to claim 1, wherein: The metal film is a single-layer metal composed of any one of Pt, Ni, and Ta, or a multi-layer metal having the metal as the bottom layer.

3. The semiconductor device according to claim 1 or 2, characterized in that: A gate electrode is further provided, the gate electrode being in Schottky junction with the surface and including a film made of the same material as the metal film.

4. The semiconductor device according to claim 1 or 2, characterized in that: The wiring electrode does not contain Pt.

5. The semiconductor device according to claim 1 or 2, characterized in that: The surface electrode comprises: a surface power supply layer formed on the wiring electrode, and a surface plating layer formed on the surface power supply layer. The surface power supply layer includes Pt.

6. The semiconductor device according to claim 1 or 2, characterized in that: The surface electrode is a source pad connected to a plurality of source electrodes of the transistor.

7. The semiconductor device according to claim 1 or 2, characterized in that: The surface electrode is a source electrode of a transistor and has an ohmic electrode in ohmic contact with the surface.

8. A method for manufacturing a semiconductor device, characterized in that: The following processes are available: A step of forming a metal film in a ring shape on the surface of a semiconductor substrate; A step of forming a surface electrode having a wiring electrode covering the metal film on the surface and bonding the surface electrode to the surface outside the metal film; A step of etching the semiconductor substrate from the back side to form a through hole in the semiconductor substrate that reaches the wiring electrode inside the ring-shaped metal film; as well as After forming the through hole, performing wet etching using a strong acid solution to remove residues generated on the side wall of the through hole; as well as a step of forming a back electrode on the back surface and the through hole and connecting the back electrode to the wiring electrode; The metal film has a lower ionization tendency than the wiring electrode and a higher work function than the wiring electrode.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The method further includes forming a gate electrode that forms a Schottky junction with the surface simultaneously with the metal film.

10. The method for manufacturing a semiconductor device according to claim 8 or 9, characterized in that: The metal film is formed by a sputtering method.

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