A wafer-level packaging method and packaging structure for reducing warpage

Abstract

The present invention discloses a wafer-level packaging method and packaging structure for reducing warpage, comprising the following steps: rerouting the wafer, opening the silicon etching groove at the cutting path position, cutting the functional layer, and then wrapping the solder mask at the cutting path position; subsequently, only pre-curing the solder mask, opening the opening for growing solder balls and the opening for reducing warpage on the solder mask at the same time or in sequence according to the photolithography resolution of the solder mask, and then finally curing the solder mask; finally, growing solder balls, and then cutting the wafer into single chips. The wafer-level packaging method and packaging structure for reducing warpage provided by the present invention solve the problem of failure caused by internal cracks and delamination of the wafer, reduce the situation where the warpage is too large to complete the subsequent process, and at the same time solve the risks of excessive vacuum adsorption, solder ball drop, solder ball deviation and tin infiltration in the subsequent solder ball process.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a wafer-level packaging method and packaging structure for reducing warping. Background Art

[0002] Today, the functions of electronic products are becoming increasingly rich, and the functional development of terminal products has put forward higher requirements for chip manufacturing and chip packaging. In the image sensor chip industry, low dielectric constant materials are generally used to achieve high performance of wafers, and stacking processes are widely used to achieve high integration of wafers. The update of wafer manufacturing technology brings challenges to wafer-level packaging. For example, in the wafer-level packaging process, cutting vibration or process warping can easily cause tiny cracks, which gradually expand during post-process packaging and later use, eventually leading to device failure.

[0003] When there are many chips on a wafer, for example, tens of thousands of chips, the warping during wafer-level packaging will be very large, which may not only form tiny cracks or delamination, but may also make it impossible to complete the post-process.

[0004] Therefore, the present invention provides a wafer-level packaging method and packaging structure for reducing warpage. Summary of the invention

[0005] In order to solve the technical problems existing in the prior art, an object of the present invention is to provide a wafer-level packaging method and packaging structure for reducing warping.

[0006] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0007] A wafer-level packaging method for reducing warpage comprises the following steps:

[0008] Re-route the wafer, open the silicon etching groove at the cutting path position, cut the functional layer, and then wrap the solder mask layer at the cutting path position;

[0009] Subsequently, only the solder mask layer is pre-cured, and the openings for growing solder balls and the openings for reducing warpage on the solder mask layer are opened simultaneously or in sequence according to the photolithography resolution of the solder mask, and then the solder mask layer is finally cured;

[0010] Finally, solder balls are added and the wafer is cut into individual chips.

[0011] Furthermore, before rewiring the wafer, the wafer is first bonded, thinned and silicon-etched, and then an isolation layer is set on the surface of the wafer.

[0012] Furthermore, the isolation layer is made of passivation glue or insulation glue by spin coating or spraying, and has a thickness of 1-20 μm.

[0013] Furthermore, the isolation layer is made of silicon oxide or silicon nitride by chemical vapor deposition and has a thickness of 0.5-5 μm.

[0014] Furthermore, the silicon etching groove is a straight hole or an inclined hole.

[0015] Furthermore, in view of the relatively high photolithography resolution of the solder resist, opening I for growing solder balls and opening II for reducing warping on the solder resist layer are opened simultaneously through photolithography exposure and development, but a wrapping edge is left, and the opening II is the opening between adjacent wafers. The final curing of the solder resist layer is carried out in an oven, and the curing temperature is controlled at 120-200°C, and the curing time is controlled at 2-5h.

[0016] Furthermore, in case that the photolithography resolution of the solder resist is not high, the opening I for growing solder balls is first opened by photolithography exposure and development, and then a blade or laser is used to open the opening II for reducing warpage but leaving a wrapping edge, wherein the opening II is the opening between adjacent wafers.

[0017] Furthermore, in view of the fact that the photolithography resolution of the solder resist is not high, the pre-curing of the solder resist layer is carried out by UV light irradiation or an oven or a baking plate, the temperature of the oven is 50-100°C, the time is 60-100 minutes, and the temperature of the baking plate is 100-120°C, the time is 5-10 minutes.

[0018] Furthermore, in view of the fact that the photolithography resolution of the solder resist is not high, the final curing of the solder resist layer is carried out in an oven, the curing temperature is controlled at 120-200° C., and the curing time is controlled at 2-5 hours.

[0019] The present invention also discloses a wafer-level packaging structure with reduced warpage, which is prepared by using the wafer-level packaging method with reduced warpage as described above, comprising:

[0020] Glass substrate;

[0021] Cofferdams are arranged on the glass substrate at intervals;

[0022] A wafer, which is disposed on the cofferdam;

[0023] An isolation layer is disposed on the wafer;

[0024] A circuit layer is arranged on the isolation layer;

[0025] The solder resist layer wraps the circuit layer and has an opening I and an opening II. The opening I is used for growing solder balls, and the opening II is an opening between adjacent wafers for releasing stress and reducing warpage.

[0026] The solder ball is arranged on the opening Ⅰ.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention discloses a wafer-level packaging method and packaging structure for reducing warpage, comprising the following steps: rerouting the wafer, opening the silicon etching groove at the cutting path position, cutting the functional layer, and then wrapping the solder mask at the cutting path position; subsequently, only pre-curing the solder mask, opening the opening for growing solder balls and the opening for reducing warpage on the solder mask at the same time or in sequence according to the photolithography resolution of the solder mask, and then finally curing the solder mask; finally, growing solder balls, and then cutting the wafer into single chips. The wafer-level packaging method and packaging structure for reducing warpage provided by the present invention solve the problem of failure caused by internal cracks and delamination of the wafer, reduce the situation where the warpage is too large to complete the subsequent process, and at the same time solve the risks of excessive vacuum adsorption, solder ball drop, solder ball deviation and tin infiltration in the subsequent solder ball process. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a structural schematic diagram of step 2) in a wafer-level packaging method for reducing warpage in embodiment 1 of the present invention;

[0030] Figure 2 This is a structural schematic diagram of step 3) in a wafer-level packaging method for reducing warpage in embodiment 1 of the present invention;

[0031] Figure 3-4 They are respectively structural schematic diagrams of step 4) in a wafer-level packaging method for reducing warpage in embodiment 1 of the present invention;

[0032] Figure 5 Schematic diagram of the structure of step 2) in a wafer-level packaging method for reducing warpage according to embodiment 2 of the present invention;

[0033] Figure 6 This is a structural schematic diagram of step 3) in a wafer-level packaging method for reducing warpage according to embodiment 2 of the present invention;

[0034] Figure 7 This is a structural schematic diagram of step 4) in a wafer-level packaging method for reducing warpage according to embodiment 2 of the present invention. DETAILED DESCRIPTION

[0035] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0036] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0037] like Figure 1-7 As shown, a wafer-level packaging method for reducing warpage is particularly used to reduce processes with large warpage variations, such as passivation layer and solder mask processes. Taking the solution of reducing the warpage of the solder mask process as an example, the wafer-level packaging method for reducing warpage includes the following steps:

[0038] 1), bonding, thinning and silicon etching the wafer 1;

[0039] 2), an isolation layer 2 is provided on the surface of the wafer 1, and a redistribution wiring layer 3 is completed, and then the silicon etching groove at the cutting path position is opened by dry etching, and the silicon etching groove is a straight hole or an inclined hole, and the functional layer at the bottom of the wafer 1 is cut by laser, and then a solder resist layer 4 is wrapped at the cutting path position; wherein, when the isolation layer 2 is made of passivation glue or insulating glue by spin coating or spraying, the thickness is 1-20 μm; when the isolation layer 2 is made of silicon oxide or silicon nitride by chemical vapor deposition, the thickness is 0.5-5 μm;

[0040] 3) Pre-curing only the solder resist layer 4, for the case where the photolithography resolution of the solder resist is relatively high, openings I5 and II6 are opened by photolithography exposure and development but the edges are left, and for the case where the photolithography resolution of the solder resist is not high, opening I5 is opened first, and then opening II6 is opened by a blade or laser but the edges are left, and then the solder resist layer 4 is finally cured; the design of opening II6 helps to reduce warping;

[0041] 4), solder balls 7 are grown on openings I 5, and then the wafer 1 is cut into individual chips.

[0042] In step 3), for the case where the photolithography resolution of the solder resist is relatively high, only the solder resist layer 4 is pre-cured by UV light irradiation or an oven or a baking plate, the temperature of the oven is 50-100°C, the time is 60-100min, the temperature of the baking plate is 100-120°C, the time is 5-10min, and then the openings I5 and II6 are opened simultaneously by photolithography exposure and development, but the edge is left, wherein the opening II6 is the opening between adjacent chips, which is used to release stress and reduce warping, and the edge is used to protect the functional layer to prevent water vapor from penetrating; the final curing of the solder resist layer 4 is carried out in an oven, the curing temperature is controlled at 120-200°C, and the curing time is controlled at 2-5h;

[0043] In case that the photolithography resolution of the solder resist is not high, the opening Ⅰ5 is first opened by photolithography exposure and development, and then the solder resist layer 4 is pre-cured by UV light irradiation or oven or baking plate. The temperature of the oven is 50-100℃, the time is 60-100min, and the temperature of the baking plate is 100-120℃, the time is 5-10min, and then a blade or laser is used to open the opening Ⅱ6 but the edge is left. After that, the solder resist layer 4 is finally cured. The final curing is also carried out in the oven. The curing temperature is controlled at 120-200℃ and the curing time is controlled at 2-5h. Because the solder resist raw material is a liquid glue, the present invention can only use knife cutting or laser cutting to open the opening Ⅱ6 after pre-curing. If there is no pre-curing, the knife cutting will wrap the blade so that it cannot be cut, and the laser cutting will be difficult to vaporize so that it is difficult to cut.

[0044] The present invention also discloses a wafer-level packaging structure for reducing warpage, comprising:

[0045] Glass substrate 9;

[0046] Cofferdams 8 are arranged at intervals on the glass substrate 9;

[0047] Wafer 1 is arranged on the cofferdam 8;

[0048] An isolation layer 2 is disposed on the wafer 1;

[0049] The circuit layer 3 is arranged on the isolation layer 2;

[0050] The solder resist layer 4 wraps the circuit layer 3 and has an opening I5 and an opening II6. The opening I5 is used for growing solder balls 7, and the opening II6 is an opening between adjacent wafers 1 for releasing stress and reducing warpage.

[0051] The solder ball is arranged on the opening Ⅰ.

[0052] Example 1

[0053] like Figure 1-4 As shown, a wafer-level packaging method for reducing warpage is used to reduce the process warpage of the solder mask layer, comprising the following steps:

[0054] 1), bonding, thinning and silicon etching the wafer 1;

[0055] 2) An isolation layer 2 is provided on the surface of the wafer 1, and a redistribution wiring layer 3 is completed, and then the silicon etching groove at the cutting path position is opened by dry etching, and the silicon etching groove is a straight hole, and the functional layer at the bottom of the wafer 1 is cut by laser, and then a solder resist layer 4 is wrapped at the cutting path position; wherein, the isolation layer 2 is made of insulating glue by spin coating or spraying, and the thickness is 3μm;

[0056] 3) In case that the photolithography resolution of the solder resist is relatively high, firstly, only the solder resist layer 4 is pre-cured in an oven at a temperature of 100°C for 60 minutes, and then the openings I5 and II6 are opened at the same time by photolithography exposure and development, but the edge wrapping is left, wherein the opening II6 is the opening between adjacent chips, which is used to release stress and reduce warpage, and the edge wrapping is used to protect the functional layer from water vapor penetration; then the solder resist layer 4 is finally cured, and the final curing of the solder resist layer 4 is carried out in an oven, and the curing temperature is controlled at 120°C and the curing time is controlled at 5 hours;

[0057] 4), solder balls 7 are grown on openings I 5, and then the wafer 1 is cut into individual chips.

[0058] A wafer-level packaging structure with reduced warpage, comprising:

[0059] Glass substrate 9;

[0060] Cofferdams 8 are arranged at intervals on the glass substrate 9;

[0061] Wafer 1 is arranged on the cofferdam 8;

[0062] An isolation layer 2 is disposed on the wafer 1;

[0063] The circuit layer 3 is arranged on the isolation layer 2;

[0064] The solder resist layer 4 wraps the circuit layer 3 and has an opening I5 and an opening II6. The opening I5 is used for growing solder balls 7, and the opening II6 is an opening between adjacent wafers 1 for releasing stress and reducing warpage.

[0065] The solder ball is arranged on the opening Ⅰ.

[0066] Example 2

[0067] like Figure 5-7 As shown, a wafer-level packaging method for reducing warpage includes the following steps:

[0068] 1), bonding, thinning and silicon etching the wafer 1;

[0069] 2) An isolation layer 2 is provided on the surface of the wafer 1, and a redistribution wiring layer 3 is completed, and then the silicon etching groove at the cutting path position is opened by dry etching, the silicon etching groove is an oblique hole, and the functional layer is cut by laser, and then a solder resist layer 4 is wrapped at the cutting path position;

[0070] 3) In case that the photolithography resolution of the solder resist is not high, the opening Ⅰ5 is first opened by photolithography exposure and development, and then the solder resist layer 4 is pre-cured in an oven at a temperature of 100°C for 60 minutes, and then the opening Ⅱ6 is opened with a blade or laser but the edge is left, and then the solder resist layer 4 is finally cured in an oven at a curing temperature of 120°C and a curing time of 5 hours;

[0071] 4), solder balls 7 are grown on openings I 5, and then the wafer 1 is cut into individual chips.

[0072] The rest is the same as in Example 1.

[0073] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0074] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A wafer-level packaging method for reducing warpage, characterized in that: The following steps are involved: Re-route the wafer, open the silicon etching groove at the cutting path position, cut the functional layer, and then wrap the solder mask layer at the cutting path position; Subsequently, only the solder mask layer is pre-cured, and the openings for growing solder balls and the openings for reducing warpage on the solder mask layer are opened simultaneously or in sequence according to the photolithography resolution of the solder mask, and then the solder mask layer is finally cured; Finally, solder balls are added and the wafer is cut into individual chips; In case that the photolithography resolution of the solder resist is relatively high, the opening I for growing solder balls and the opening II for reducing warpage on the solder resist layer are opened simultaneously by photolithography exposure and development, but the edge is left. The opening II is the opening between adjacent wafers. The final curing of the solder resist layer is carried out in an oven, and the curing temperature is controlled at 120-200°C and the curing time is controlled at 2-5h. In the case where the lithography resolution of the solder resist is not high, opening I for growing solder balls is first opened through lithography exposure and development, and then a blade or laser is used to open opening II for reducing warpage but leaving an edge, where opening II is the opening between adjacent wafers.

2. The wafer-level packaging method for reducing warpage according to claim 1, characterized in that: Before rewiring the wafer, the wafer is first bonded, thinned and silicon-etched, and then an isolation layer is set on the surface of the wafer.

3. The method for reducing warpage of wafer-level packaging according to claim 2, characterized in that: The isolation layer is made of passivation glue or insulation glue by spin coating or spray coating, and has a thickness of 1-20 μm.

4. The wafer-level packaging method for reducing warpage according to claim 2, characterized in that: The isolation layer is made of silicon oxide or silicon nitride by chemical vapor deposition and has a thickness of 0.5-5 μm.

5. The wafer-level packaging method for reducing warpage according to claim 1, characterized in that: The silicon etching groove is a straight hole or an inclined hole.

6. The wafer-level packaging method for reducing warpage according to claim 1, characterized in that: In view of the fact that the photolithography resolution of the solder resist is not high, the pre-curing of the solder resist layer is carried out by UV light irradiation or an oven or a baking plate. The temperature of the oven is 50-100°C for 60-100 minutes, and the temperature of the baking plate is 100-120°C for 5-10 minutes.

7. The wafer-level packaging method for reducing warpage according to claim 6, characterized in that: In view of the fact that the photolithography resolution of the solder resist is not high, the final curing of the solder resist layer is carried out in an oven, the curing temperature is controlled at 120-200° C., and the curing time is controlled at 2-5 hours.

8. A wafer-level packaging structure with reduced warpage, characterized in that: The method is prepared by using a wafer-level packaging method for reducing warpage as described in any one of claims 1 to 7, comprising: Glass substrate; Cofferdams are arranged on the glass substrate at intervals; A wafer, which is disposed on the cofferdam; An isolation layer is disposed on the wafer; A circuit layer is disposed on the isolation layer; The solder resist layer wraps the circuit layer and has an opening I and an opening II. The opening I is used for growing solder balls, and the opening II is an opening between adjacent wafers for releasing stress and reducing warpage. The solder ball is arranged on the opening Ⅰ.

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