A power factor correction circuit

Abstract

The application discloses a kind of rate factor correction circuits, including starting rectifier circuit, clamping circuit, high-frequency rectifier circuit, power frequency rectifier circuit, inductance, additional capacitor and output capacitor, inductance includes first and second windings, first winding one end and the midpoint of starting rectifier circuit simultaneously connect the first input end of power factor correction circuit, the midpoint of clamping circuit is simultaneously connected with the second input end of power factor correction circuit with the one end of second winding, the other end of first winding connects the midpoint of high-frequency rectifier circuit, the other end of second winding connects the midpoint of power frequency rectifier circuit, additional capacitor one end connects the negative output end of power factor correction circuit, the other end is used to connect ground;Wherein, starting rectifier circuit, clamping circuit, second winding and output capacitor can form loop limit current spike flowing through the switch tube in power frequency rectifier circuit;Inductance and additional capacitor parameter design meet the formation of bridge balance to reduce common-mode noise.The application can improve the reliability of circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power electronics, and particularly relates to a power factor correction circuit. BACKGROUND

[0002] With the rapid development of power electronics technology and its wide application in various industries, more stringent requirements are put forward for the efficiency and volume of primary rectifier modules, and high power density rectifier modules have become the focus at present.

[0003] At present, the peak efficiency of high power density rectifier module technology is required to reach 98% or more, the front stage adopts totem pole bridgeless power factor correction circuit, and control adopts critical control mode or continuous control mode. In order to realize the requirement of high power density, on the one hand, the working frequency can be improved to reduce the volume, and on the other hand, field effect tubes can be used to replace diode rectification to improve the efficiency.

[0004] However, increasing the working frequency will increase the loss of field effect tubes, so wide bandgap devices are used to replace field effect tubes to reduce the loss. However, with the increase of frequency and the application of wide bandgap devices, the voltage / current change rate is high, so it is difficult to deal with the problem of common mode noise. The conventional solution is to add a multi-stage filter circuit to the front stage, but this scheme increases the volume and increases the cost.

[0005] And using field effect tubes to replace diode rectification circuit, because the current impact resistance of field effect tubes is much lower than that of diodes, so the lightning resistance performance is reduced, and the possibility of module failure is increased. The conventional solution is to add a differential mode inductor to the input end of the module to suppress the input current, but this scheme also leads to a decrease in module efficiency, which is not suitable for application in high power density rectifier modules. SUMMARY

[0006] Therefore, the technical problem to be solved by the present application is to overcome the deficiencies of the prior art, and to provide a power factor correction circuit which at least can solve the above-mentioned deficiencies of the prior art to some extent.

[0007] To solve the above technical problems, the technical scheme of the embodiment of the power factor correction circuit provided by the present application is as follows:

[0008] A power factor correction circuit, wherein: the power factor correction circuit comprises a start-up rectifier circuit, a clamping circuit, a high-frequency rectifier circuit, a line-frequency rectifier circuit, an inductor, an additional capacitor and an output capacitor, the start-up rectifier circuit, the clamping circuit, the high-frequency rectifier circuit and the line-frequency rectifier circuit each comprise a bridge arm formed by two switching tubes, the inductor comprises a first winding and a second winding, the start-up rectifier circuit, the clamping circuit, the high-frequency rectifier circuit, the line-frequency rectifier circuit and the output capacitor are connected between a positive output end of the power factor correction circuit and a negative output end of the power factor correction circuit, one end of the first winding and a midpoint of the start-up rectifier circuit are connected to a first input end of the power factor correction circuit at the same time, one end of the second winding and a midpoint of the clamping circuit are connected to a second input end of the power factor correction circuit at the same time, the other end of the first winding is connected to a midpoint of the high-frequency rectifier circuit, the other end of the second winding is connected to a midpoint of the line-frequency rectifier circuit, one end of the additional capacitor is connected to the negative output end of the power factor correction circuit and the other end is used for connecting to the ground;

[0009] Wherein, the start-up rectifier circuit, the clamping circuit, the second winding and the output capacitor can form a loop under line-frequency switching to limit current spikes flowing through the switching tubes in the line-frequency rectifier circuit; the inductor and the additional capacitor are designed to meet the following formula:

[0010] ;

[0011] Wherein, is the impedance between the midpoint of the start-up rectifier circuit and the midpoint of the high-frequency rectifier circuit, is the impedance between the midpoint of the clamping circuit and the midpoint of the line-frequency rectifier circuit, is the impedance of the parasitic capacitance of the midpoint of the high-frequency rectifier circuit to the ground, is the impedance of the three capacitors in parallel, the three capacitors are respectively: the parasitic capacitance of the positive output end of the power factor correction circuit to the ground, the parasitic capacitance of the negative output end of the power factor correction circuit to the ground and the additional capacitor.

[0012] Further, the control logic of the start-up rectifier circuit, the clamping circuit, the high-frequency rectifier circuit and the line-frequency rectifier circuit is as follows:

[0013] When a positive half-wave voltage period is input, the line between the power frequency rectifier circuit midpoint and the positive output end of the power factor correction circuit is turned off, the line between the power factor correction circuit negative output end is turned on, the line between the starting rectifier circuit midpoint and the positive output end of the power factor correction circuit is turned off, the line between the power factor correction circuit negative output end is turned off, the line between the clamping circuit midpoint and the positive output end of the power factor correction circuit is turned off, and the line between the power factor correction circuit negative output end is turned off. At this time, if a negative phase differential mode lightning surge occurs, the line between the starting rectifier circuit midpoint and the power factor correction circuit negative output end and the line between the clamping circuit midpoint and the positive output end of the power factor correction circuit are both turned on, the line between the starting rectifier circuit midpoint and the positive output end of the power factor correction circuit and the line between the clamping circuit midpoint and the power factor correction circuit negative output end are both turned off, and the voltage across the second winding is clamped by the clamping circuit, thereby limiting the current spike flowing through the switch tube connected to the power factor correction circuit negative output end in the power frequency rectifier circuit.

[0014] When a positive half-wave voltage period is input, the line between the power frequency rectifier circuit midpoint and the positive output end of the power factor correction circuit is turned off, the line between the power factor correction circuit negative output end is turned on, the line between the starting rectifier circuit midpoint and the positive output end of the power factor correction circuit is turned off, the line between the power factor correction circuit negative output end is turned off, the line between the clamping circuit midpoint and the positive output end of the power factor correction circuit is turned off, and the line between the power factor correction circuit negative output end is turned off. At this time, if a negative phase differential mode lightning surge occurs, the line between the starting rectifier circuit midpoint and the power factor correction circuit negative output end and the line between the clamping circuit midpoint and the positive output end of the power factor correction circuit are both turned on, the line between the starting rectifier circuit midpoint and the positive output end of the power factor correction circuit and the line between the clamping circuit midpoint and the power factor correction circuit negative output end are both turned off, and the voltage across the second winding is clamped by the clamping circuit, thereby limiting the current spike flowing through the switch tube connected to the power factor correction circuit negative output end in the power frequency rectifier circuit.

[0015] Preferably, the clamping circuit comprises a first diode, a second diode, a first capacitor and a second capacitor, the cathode of the first diode is connected to the positive output end of the power factor correction circuit, the anode of the first diode is connected to one end of the first capacitor, the cathode of the second diode is connected to the other end of the first capacitor, the anode of the second diode is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the negative output end of the power factor correction circuit.

[0016] Preferably, the starting rectifier circuit includes two passive switching transistors connected in series; and / or the high-frequency rectifier circuit includes two active switching transistors connected in series; and / or the power frequency rectifier circuit includes two active switching transistors connected in series.

[0017] Preferably, the two passive switching transistors in the starting rectifier circuit are diodes, with the cathode of one diode connected to the positive output terminal of the power factor correction circuit, the anode of the other diode connected to the cathode of the other diode, and the anode of the other diode connected to the negative output terminal of the power factor correction circuit; and / or the two active switching transistors in the high-frequency rectifier circuit are field-effect transistors, IGBTs, SICMOS, or GANs; and / or the two active switching transistors in the power frequency rectifier circuit are field-effect transistors, IGBTs, SICMOS, or GANs.

[0018] Furthermore, the power factor correction circuit also includes an additional inductor, which comprises a winding connected in series between the other end of the first winding and the midpoint of the high-frequency rectifier circuit. The impedance between the midpoint of the starting rectifier circuit and the midpoint of the high-frequency rectifier circuit.

[0019] Further, the power factor correction circuit includes N high-frequency rectifier circuits and N inductors, where N is a natural number greater than or equal to 2; one end of the first winding of each inductor and the midpoint of the starting rectifier circuit are simultaneously connected to the first input terminal of the power factor correction circuit; the other end of the first winding of each inductor is connected to the midpoint of a high-frequency rectifier circuit or connected to the midpoint of a high-frequency rectifier circuit through an additional inductor; one end of the second winding of each inductor is connected to the second input terminal of the power factor correction circuit; the other end of the second winding of the previous inductor is connected to one end of the second winding of the next inductor; and the other end of the second winding of the last inductor is connected to the midpoint of the high-frequency rectifier circuit.

[0020] The parameters of each inductor and the additional capacitor are designed to individually satisfy the formula. For a given inductor and the additional capacitor, The impedance between the midpoint of the starting rectifier circuit and the midpoint of the corresponding high-frequency rectifier circuit. It includes N impedances connected in parallel, wherein the N impedances are: the impedance between the midpoint of the clamping circuit and the midpoint of the power frequency rectifier circuit, and the impedances of the midpoints of the other N-1 high-frequency rectifier circuits (excluding the corresponding high-frequency rectifier circuit) to the midpoint of the starting rectifier circuit. This is the impedance of the parasitic capacitance of the midpoint of the corresponding high-frequency rectifier circuit to the ground. The impedance of N+2 capacitors in parallel, the N+2 capacitors are respectively: the parasitic capacitance of the positive output end of the power factor correction circuit to the ground, the parasitic capacitance of the negative output end of the power factor correction circuit to the ground, the additional capacitor, and the parasitic capacitance of the midpoint of each of the other N-1 high-frequency rectifier circuits except the corresponding high-frequency rectifier circuit to the ground.

[0021] Further, the power factor correction circuit comprises M additional inductors, M is a natural number greater than or equal to 2, and M is less than or equal to N; the winding in each additional inductor is connected in series between the other end of the primary winding in one of the N inductors and the midpoint of the corresponding high-frequency rectifier circuit.

[0022] Further, the first winding and the second winding in the N inductors are reversely coupled or forwardly coupled.

[0023] Further, the N inductors and the M additional inductors are magnetically integrated.

[0024] The working principle of the present application will be analyzed in detail in combination with specific embodiments, which will not be described here. The scheme proposed by the present application overcomes the shortcomings of the prior art, and by using coupled inductors and clamping circuits, the lightning protection effect is achieved while reducing common mode noise, further reducing cost and size. Compared with the prior art, the beneficial effects of the present application are:

[0025] The power factor correction circuit of the embodiment of the present application places the second winding of the coupled inductor between the midpoint of the clamping circuit bridge arm and the midpoint of the power frequency rectifier circuit bridge arm. The clamping circuit can effectively realize voltage clamping for the second winding of the inductor during differential mode lightning surge and limit the current peak flowing through the switch tube in the power frequency rectifier circuit under power frequency switching, greatly reducing the possibility of failure of the power frequency rectifier circuit. In addition, the first winding, the second winding of the inductor, the midpoint of the high-frequency rectifier circuit bridge arm, and the parasitic capacitance of the two output ends of the power factor correction circuit to the ground form a Wheatstone bridge. By adjusting the proportion of the bridge through an additional capacitor, the bridge is balanced, the line impedance is stable, the common mode noise collected by the network resistance is zero, thereby reducing the common mode noise, realizing the miniaturization of the EMI circuit input by the power factor correction circuit in application, and being beneficial to reducing the volume and cost of the product, and greatly improving the reliability of the product. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a schematic diagram of the first power factor correction circuit of the present application;

[0027] Figure 2 It is a circuit schematic diagram of the second power factor correction circuit of the present application;

[0028] Figure 3A circuit schematic diagram of a two-phase interleaved power factor correction circuit according to the present invention;

[0029] Figure 4 A circuit schematic diagram of a multi-phase interleaved power factor correction circuit according to the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the embodiments and features of the present application can be combined with each other, if there is no conflict. The present application will be described in detail with reference to the drawings and embodiments below.

[0031] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0032] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances to describe the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0033] It should be understood that, in the specification, claims and drawings, when describing a step succeeding to another step, the step can directly succeed to the other step, or succeed to the other step through a third step; when describing an element / unit "succeeding" to another element / unit, the element / unit can be "directly connected" to the other element / unit, or "connected" to the other element / unit through a third element / unit.

[0034] In addition, the drawings of the present disclosure are only schematic and not necessarily to scale. Identical or similar reference signs in the drawings represent identical or similar parts, and thus repeated description thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities, which do not necessarily have to correspond to physically or logically independent entities. These functional entities can be implemented by software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0035] Figure 1 For the circuit principle diagram of the third power factor correction circuit, please refer to Figure 1 The power factor correction circuit comprises a start-up rectifier circuit, a clamping circuit, a high-frequency rectifier circuit, a power-frequency rectifier circuit, an inductor LT1, an additional capacitor Cadd and an output capacitor Co. The start-up rectifier circuit, the clamping circuit, the high-frequency rectifier circuit and the power-frequency rectifier circuit each comprise a bridge arm formed by two switching tubes. The inductor LT1 comprises a first winding P1-1 and a second winding S1-1. The start-up rectifier circuit, the clamping circuit, the high-frequency rectifier circuit, the power-frequency rectifier circuit and the output capacitor are connected between a positive output end of the power factor correction circuit and a negative output end of the power factor correction circuit. One end of the first winding is connected to a first input end A of the power factor correction circuit and a midpoint of the start-up rectifier circuit. One end of the second winding is connected to a second input end B of the power factor correction circuit and a midpoint of the clamping circuit. The other end of the first winding is connected to a midpoint of the high-frequency rectifier circuit. The other end of the second winding is connected to a midpoint of the power-frequency rectifier circuit. One end of the additional capacitor is connected to the negative output end of the power factor correction circuit, and the other end is used for connecting to the ground.

[0036] The start-up rectifier circuit, the clamping circuit, the second winding and the output capacitor can form a loop to limit the current peak flowing through the switching tube in the power-frequency rectifier circuit. The inductor and the additional capacitor are designed to meet the following formula:

[0037] ;

[0038] Wherein, is the impedance between the midpoint of the start-up rectifier circuit and the midpoint of the high-frequency rectifier circuit, is the impedance between the midpoint of the clamping circuit and the midpoint of the power-frequency rectifier circuit, is the impedance of the parasitic capacitance of the midpoint of the high-frequency rectifier circuit to the ground, is the impedance of the parallel connection of the three capacitors, which are the parasitic capacitance of the positive output end of the power factor correction circuit to the ground, the parasitic capacitance of the negative output end of the power factor correction circuit to the ground and the additional capacitor.

[0039] Further, the control logic of the start-up rectifier circuit, the clamping circuit, the high-frequency rectifier circuit and the power-frequency rectifier circuit is as follows:

[0040] When the positive half-wave voltage period is input, the line between the power frequency rectifier circuit midpoint and the positive output end of the power factor correction circuit is closed, the line between the power frequency rectifier circuit midpoint and the negative output end of the power factor correction circuit is opened, the line between the rectifier circuit midpoint and the positive output end of the power factor correction circuit is closed, the line between the rectifier circuit midpoint and the negative output end of the power factor correction circuit is closed, the line between the clamp circuit midpoint and the positive output end of the power factor correction circuit is closed, and the line between the clamp circuit midpoint and the negative output end of the power factor correction circuit is closed. At this time, if the negative phase differential mode lightning surge is generated, the line between the rectifier circuit midpoint and the negative output end of the power factor correction circuit and the line between the clamp circuit midpoint and the positive output end of the power factor correction circuit are both opened, the line between the rectifier circuit midpoint and the positive output end of the power factor correction circuit and the line between the clamp circuit midpoint and the negative output end of the power factor correction circuit are both closed, and the voltage between the two ends of the second winding is clamped through the clamp circuit, thereby limiting the current peak flowing through the switch tube connected between the power frequency rectifier circuit and the negative output end of the power factor correction circuit.

[0041] When the negative half-wave voltage period is input, the line between the power frequency rectifier circuit midpoint and the positive output end of the power factor correction circuit is opened, the line between the power frequency rectifier circuit midpoint and the negative output end of the power factor correction circuit is closed, the line between the rectifier circuit midpoint and the positive output end of the power factor correction circuit is closed, the line between the rectifier circuit midpoint and the negative output end of the power factor correction circuit is closed, the line between the clamp circuit midpoint and the positive output end of the power factor correction circuit is closed, and the line between the clamp circuit midpoint and the negative output end of the power factor correction circuit is closed. At this time, if the positive phase differential mode lightning surge is generated, the line between the rectifier circuit midpoint and the negative output end of the power factor correction circuit and the line between the clamp circuit midpoint and the positive output end of the power factor correction circuit are both closed, the line between the rectifier circuit midpoint and the positive output end of the power factor correction circuit and the line between the clamp circuit midpoint and the negative output end of the power factor correction circuit are both opened, and the voltage between the two ends of the second winding is clamped through the clamp circuit, thereby limiting the current peak flowing through the switch tube connected between the power frequency rectifier circuit and the positive output end of the power factor correction circuit.

[0042] As preferred, the clamp circuit is as follows Figure 1, including the first diode D3, the second diode D4, the first capacitor C1 and the second capacitor C2, the cathode of the first diode D3 is connected with the positive output end of the power factor correction circuit, the anode of the first diode D3 is connected with one end of the first capacitor C1, the cathode of the second diode D4 is connected with the other end of the first capacitor C1, the anode of the second diode D4 is connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is connected with the negative output end of the power factor correction circuit, wherein when the input positive half-wave voltage period, the second winding S1-1 charges the second capacitor C2 through the diode D4 and the lower switch tube in the power frequency rectifier circuit, when the input negative half-wave voltage period, the second winding S1-1 charges the first capacitor C1 through the diode D3 and the upper switch tube in the power frequency rectifier circuit, so that the first diode D3 and the second diode D4 of the clamping circuit cannot form clamping to the second winding S1-1 of the inductor when the high-frequency rectifier circuit is under high-frequency switching.

[0043] As preferred, the starting rectifier circuit refers to Figure 1 , including two passive switch tubes in series, specifically, the diode D1 and the diode D2 in series, wherein the cathode of the diode D1 is connected with the positive output end of the power factor correction circuit, the anode of the diode D1 is connected with the cathode of the diode D2, and the anode of the diode D2 is connected with the negative output end of the power factor correction circuit, and therefore the starting rectifier circuit preferably includes two passive switch tubes in series in view of cost, control complexity and circuit reliability.

[0044] As preferred, the high-frequency rectifier circuit includes two active switch tubes in series, specifically, the MOS tube Q1H and the MOS tube Q1L in series, and the switch tube type of the MOS tube Q1H and the MOS tube Q1L can be replaced by IGBT, SICMOS or GAN, and the specific type of switch tube is not limited in the application, and the person skilled in the art can select according to the actual situation.

[0045] As preferred, the power frequency rectifier circuit includes two active switch tubes in series, specifically, the MOS tube QT1 and the MOS tube QT2 in series, and the switch tube type of the MOS tube QT1 and the MOS tube QT2 can be replaced by IGBT, SICMOS or GAN, and the specific type of switch tube is not limited in the application, and the person skilled in the art can select according to the actual situation.

[0046] Figure 1 The circuit is in the positive half cycle of the alternating current input, the main switch tube is the MOS tube Q1L, and the freewheeling tube is the MOS tube Q1H; in the negative half cycle of the alternating current input, the main switch tube is the MOS tube Q1H, and the freewheeling tube is the MOS tube Q1L. Figure 1 The working principle of the power factor correction circuit of the application is analyzed in detail as follows:

[0047] When the positive half cycle of the AC input, MOS tube QT1 is configured to turn off, MOS tube QT2 is configured to turn on, the voltage across the output capacitor Co is greater than the voltage of the input voltage source AC, diode D1, D2, D3 and D4 are all reverse-biased cut-off. Inductor LT1 excitation MOS tube Q1L is configured to turn on, MOS tube Q1H is configured to turn off, the current flow direction is coupled inductor LT1 first winding P1-1→ MOS tube Q1L→ MOS tube QT2→ coupled inductor LT1 second winding S1-1→ input voltage source AC→ coupled inductor LT1 first winding P1-1; inductor LT1 demagnetization MOS tube Q1L is configured to turn off, MOS tube Q1H is configured to open, the current flow direction is coupled inductor LT1 first winding P1-1→ MOS tube Q1H→ output capacitor Co→ MOS tube QT2→ coupled inductor LT1 second winding S1-1→ input voltage source AC→ coupled inductor LT1 first winding P1-1.

[0048] At this time, if the positive phase difference mode lightning surge is generated, the voltage peak makes diode D1 and diode D4 positive bias open, diode D2 and diode D3 reverse-biased cut-off, the surge current path includes two, respectively: input voltage source AC A end→ diode D1→ output capacitor Co→ second clamping capacitor C2→ diode D4→ input voltage source AC B end, and input voltage source AC A end→ diode D1→ output capacitor Co→ MOS tube QT2→ coupled inductor LT1 second winding S1-1→ input voltage source AC B end, thereby clamping the voltage across the second winding S1-1 of inductor LT1 to the voltage of the second capacitor C2, to limit the current peak flowing through MOS tube QT2. If the negative phase difference mode lightning surge is generated, the voltage peak makes diode D2 and diode D3 positive bias open, diode D1 and diode D4 reverse-biased cut-off, the surge current path includes two, respectively: input voltage source AC B end→ first clamping capacitor C1→ diode D3→ output filter capacitor Co→ diode D2→ input voltage source AC A end, and input voltage source AC B end→ coupled inductor LT1 second winding S1-1→ MOS tube QT2→ diode D2→ input voltage source AC A end, thereby clamping the voltage across the S1-1 of inductor LT1 to the sum of the voltage of the output capacitor Co and the first capacitor C1, to limit the current peak flowing through MOS tube QT2.

[0049] When the negative half cycle of the AC input, MOS tube QT1 is configured to turn on, MOS tube QT2 is configured to turn off, because the voltage across the output capacitor Co is greater than the voltage of the input voltage source AC, diode D1, D2, D3 and D4 are all reverse-biased off. Inductor LT1 excitation MOS tube Q1H is configured to turn on, MOS tube Q1L is configured to turn off, the current flow direction is coupled inductor LT1 first winding P1-1→ input voltage source AC→ coupled inductor LT1 second winding S1-1→ MOS tube QT1→ MOS tube Q1H→ coupled inductor LT1 first winding P1-1, coupled inductor LT1 demagnetization MOS tube Q1H is configured to turn off, MOS tube Q1L is configured to open, the current flow direction is inductor LT1 first winding P1-1→ input voltage source AC→ coupled inductor LT1 second winding S1-1→ MOS tube QT1→ output capacitor Co→ MOS tube Q1L→ inductor LT1 first winding P1-1.

[0050] At this time, if the negative phase difference mode lightning surge occurs, the voltage peak makes diode D2 and diode D3 forward-biased on, diode D1 and diode D4 are reverse-biased off, the surge current path includes two, respectively: input voltage source AC B end→ first capacitor C1→ diode D3→ output capacitor Co→ diode D2→ input voltage source AC A end, and input voltage source AC B end→ MOS tube QT1→ coupled inductor LT1 second winding S1-1→ output capacitor Co→ diode D2→ input voltage source AC A end, thereby clamping the voltage across the second winding S1-1 of inductor LT1 to the voltage of first capacitor C1, to limit the current peak flowing through MOS tube QT1. If the positive phase difference mode lightning surge occurs, diode D1 and diode D4 are forward-biased on, diode D2 and diode D3 are reverse-biased off, the surge current path includes two, respectively: input voltage source AC A end→ diode D1→ output filter capacitor Co→ second capacitor C2→ diode D4→ input voltage source AC B end, and input voltage source AC A end→ diode D1→ MOS tube QT1→ coupled inductor LT1 second winding S1-1→ input voltage source AC B end, thereby clamping the voltage across the second winding S1-1 of inductor LT1 to the sum of the voltage of output capacitor Co and first capacitor C2, to limit the current peak flowing through MOS tube QT1.

[0051] When the difference mode lightning surge occurs, the lightning current through the second winding S1-1 of coupled inductor LT1 is suppressed, the expression is as follows: , wherein V is the voltage across the second winding S1-1, dt is a certain period of time, L is the inductance of the second winding S1-1, di is the current flowing through the second winding S1-1 in the period of time; the appropriate inductance can be set by the formula to suppress the inductor current.

[0052] When the high frequency rectification circuit is in high frequency switching, because the voltage across the first capacitor C1 and the second capacitor C2 is both greater than the voltage across the second winding S1-1 of the inductor LT1, the high frequency voltage across the second winding S1-1 of the inductor LT1 is not clamped, and the second winding S1-1 of the inductor LT1 can be balanced to reduce common mode noise together with the first winding P1-1 of the inductor LT1, the parasitic capacitor between the midpoint of the high frequency rectification circuit and the ground, and the parasitic capacitor between the two output terminals of the power factor correction circuit and the ground. The clamping circuit can ensure that the second winding S1-1 of the inductor LT1 can prevent lightning surge, and at the same time, the second winding S1-1 of the inductor LT1 can be balanced to reduce common mode noise.

[0053] The common mode noise is generated due to the large voltage / current change rate of the switching tube, and therefore, the main common mode noise is generated by the main switching tube Q1L. According to the superposition theorem, when the voltage waveform of the main switching tube is taken as a noise source, the input voltage source AC is short-circuited, the output capacitor Co is short-circuited, the freewheeling tube Q1H and the power frequency tube QT1 are open-circuited, a Wheatstone bridge can be formed, the first impedance is the impedance between the midpoint of the starting rectification circuit and the midpoint of the high frequency rectification circuit, i.e. the impedance of the first winding P1-1 of the coupling inductor LT1, the second impedance is the impedance between the midpoint of the clamping circuit and the midpoint of the power frequency rectification circuit, i.e. the impedance of the second winding S1-1 of the coupling inductor LT1, the third impedance is the impedance of the parasitic capacitor Ca between the drain of the main switching tube and the ground, and the fourth impedance includes the impedance of the parallel connection of three capacitors, i.e. the parasitic capacitor between the positive output terminal of the power factor correction circuit and the ground, the parasitic capacitor between the negative output terminal of the power factor correction circuit and the ground, and the additional capacitor Cadd.

[0054] Supposing that the turn ratio of the coupling inductor LT1 is n, the mutual inductance is M, the inductance of the first winding P1-1 is Lp, the inductance of the second winding S1-1 is Ls, the capacitance of the parasitic capacitor Ca between the drain of the main switching tube and the ground is Ca, the sum of the capacitances of the parasitic capacitor between the positive output terminal of the power factor correction circuit and the ground and the parasitic capacitor between the negative output terminal of the power factor correction circuit and the ground is Cb, and the capacitance of the additional capacitor Cadd is Cadd, according to the bridge balance, if , the common mode noise voltage collected by the line impedance stabilization network resistance is zero, and therefore, the common mode noise can be greatly reduced.

[0055] The line impedance stabilization network resistance in the application refers to the device for testing the conducted disturbance of the switching power supply.

[0056] Figure 2 The circuit principle diagram of the second power factor correction circuit in the application is shown in Fig. 2, and the circuit principle diagram of the third power factor correction circuit in the application is shown in Fig. 3. Figure 1The difference lies in that the power factor correction circuit also includes an additional inductor L1, which consists of a winding connected in series between the other end of the first winding and the midpoint of the high-frequency rectifier circuit. The impedance between the midpoint of the starting rectifier circuit and the midpoint of the high-frequency rectifier circuit is calculated. Specifically, assuming the inductance of the additional inductor L1 is L1, then according to the bridge balance, Figure 2 The circuit needs to meet the following requirements: . Figure 2 The purpose of adding the accessory inductor L1 is to allow for the use of a discrete inductor structure, which facilitates layout and heat dissipation.

[0057] Figure 1 The power factor correction circuit is unidirectional. This circuit can be extended to two-phase and multi-phase interleaved bridgeless PFC circuits. The purpose of extending it to two-phase and multi-phase interleaved circuits is to further improve the power rating of the power factor correction circuit and reduce the current ripple of the output capacitor Co. At this time, with... Figure 1 The difference lies in that the power factor correction circuit includes N high-frequency rectifier circuits and N inductors, where N is a natural number greater than or equal to 2; one end of the first winding of each inductor and the midpoint of the starting rectifier circuit are simultaneously connected to the first input terminal of the power factor correction circuit; the other end of the first winding of each inductor is connected to the midpoint of a high-frequency rectifier circuit in a high-frequency rectifier circuit, or each is connected to the midpoint of a high-frequency rectifier circuit in a high-frequency rectifier circuit through an additional inductor; one end of the second winding of each inductor is connected to the second input terminal of the power factor correction circuit; the other end of the second winding of the previous inductor is connected to one end of the second winding of the next inductor; and the other end of the second winding of the last inductor is connected to the midpoint of the high-frequency rectifier circuit.

[0058] In this design, the parameters of each inductor and additional capacitor are individually designed to satisfy the formula. For a given inductor and additional capacitor, To establish the impedance between the midpoint of the starting rectifier circuit and the corresponding midpoint of the high-frequency rectifier circuit, It includes N impedances connected in parallel. The N impedances are: the impedance between the midpoint of the clamping circuit and the midpoint of the power frequency rectifier circuit, and the impedances of the midpoints of the other N-1 high-frequency rectifier circuits (excluding the corresponding high-frequency rectifier circuit) to the midpoint of the starting rectifier circuit. This is the impedance of the parasitic capacitance between the midpoint of the corresponding high-frequency rectifier circuit and ground. The impedance is the result of N+2 capacitors connected in parallel. The N+2 capacitors are: the parasitic capacitance of the positive output terminal of the power factor correction circuit to ground, the parasitic capacitance of the negative output terminal of the power factor correction circuit to ground, the additional capacitor, and the parasitic capacitance of the midpoint of each of the other N-1 high-frequency rectifier circuits to ground, excluding the corresponding high-frequency rectifier circuit.

[0059] Figure 3A circuit schematic diagram of a two-phase interleaved power factor correction circuit according to the present application, Figure 4 A circuit schematic diagram of a multi-phase interleaved power factor correction circuit according to the present application, the principle of surge current suppression and common mode noise reduction is similar to the first embodiment, and will not be repeated here.

[0060] Further, the power factor correction circuit comprises M additional inductors, M is a natural number greater than or equal to 2, and M is less than or equal to N; the windings in each additional inductor are connected in series between the other end of the primary winding in one of the N inductors and the midpoint of the corresponding high-frequency rectifier circuit, so that multi-path interleaving can be realized and the total power of the conversion circuit can be improved.

[0061] Preferably, the first winding and the second winding in the N inductors are reversely coupled or forwardly coupled. The meaning of reverse coupling is that the one end of the first winding and the one end of the second winding of each inductor are the same name or opposite name, which can reduce the number of turns of the second winding, reduce the volume, weaken the lightning protection advantage, and focus on reducing common mode noise; the meaning of forward coupling is that the one end of the first winding and the other end of the second winding of each inductor are the same name or opposite name, which can increase the number of turns of the second winding, the volume is slightly larger, and the focus is on surge protection, while the common mode noise can also be reduced.

[0062] Further, the N inductors and the M additional inductors are magnetically integrated, so that the total volume of the inductors can be reduced.

[0063] The above is only a preferred embodiment of the present application, and those skilled in the art of the present application can also make changes and modifications to the above specific embodiments. Therefore, the present application is not limited to the specific control methods disclosed and described above, and some modifications and changes of the present application should also fall within the protection scope of the claims of the present application. In addition, although some specific terms are used in the present specification, these terms are only for convenience of explanation and do not constitute any limitation on the present application.

Claims

1. A power factor correction circuit, characterized in that: The power factor correction circuit includes a startup rectifier circuit, a clamping circuit, a high-frequency rectifier circuit, a power frequency rectifier circuit, an inductor, an additional capacitor, and an output capacitor. Each of the startup rectifier circuit, the clamping circuit, the high-frequency rectifier circuit, and the power frequency rectifier circuit includes a bridge arm formed by two switching transistors. The inductor includes a first winding and a second winding. The startup rectifier circuit, the clamping circuit, the high-frequency rectifier circuit, the power frequency rectifier circuit, and the output capacitor are all connected between the positive output terminal and the negative output terminal of the power factor correction circuit. One end of the first winding and the midpoint of the startup rectifier circuit are simultaneously connected to the first input terminal of the power factor correction circuit. One end of the second winding and the midpoint of the clamping circuit are simultaneously connected to the second input terminal of the power factor correction circuit. The other end of the first winding is connected to the midpoint of the high-frequency rectifier circuit, and the other end of the second winding is connected to the midpoint of the power frequency rectifier circuit. One end of the additional capacitor is connected to the negative output terminal of the power factor correction circuit, and the other end is connected to ground. The starting rectifier circuit, the clamping circuit, the second winding, and the output capacitor, under power frequency switching, can form a loop to limit the current spikes flowing through the switching transistor in the power frequency rectifier circuit; the inductor and the additional capacitor are designed to satisfy the following formula: ； in, The impedance between the midpoint of the starting rectifier circuit and the midpoint of the high-frequency rectifier circuit. The impedance between the midpoint of the clamping circuit and the midpoint of the power frequency rectifier circuit. The impedance of the parasitic capacitance between the midpoint of the high-frequency rectifier circuit and the ground is given. The impedance is the result of three capacitors connected in parallel. The three capacitors are: the parasitic capacitance of the positive output terminal of the power factor correction circuit to the ground, the parasitic capacitance of the negative output terminal of the power factor correction circuit to the ground, and the additional capacitor.

2. The power factor correction circuit according to claim 1, characterized in that: The control logic for the starting rectifier circuit, the clamping circuit, the high-frequency rectifier circuit, and the power frequency rectifier circuit is as follows: When the positive half-wave voltage cycle is input, the line between the midpoint of the power frequency rectifier circuit and the positive output terminal of the power factor correction circuit is turned off, and the line between the midpoint of the rectifier circuit and the negative output terminal of the power factor correction circuit is turned on. The line between the midpoint of the starting rectifier circuit and the positive output terminal of the power factor correction circuit is turned off, and the line between the midpoint of the clamping circuit and the positive output terminal of the power factor correction circuit is turned off, and the line between the midpoint of the clamping circuit and the negative output terminal of the power factor correction circuit is also turned off. At this time, if a negative phase difference mode lightning surge occurs... The lines between the midpoint of the starting rectifier circuit and the negative output terminal of the power factor correction circuit, and between the midpoint of the clamping circuit and the positive output terminal of the power factor correction circuit, are both turned on. The lines between the midpoint of the starting rectifier circuit and the positive output terminal of the power factor correction circuit, and between the midpoint of the clamping circuit and the negative output terminal of the power factor correction circuit, are both turned off. The voltage across the second winding is clamped by the clamping circuit, thereby limiting the current spike flowing through the switching transistor connected to the negative output terminal of the power factor correction circuit in the power frequency rectifier circuit. When a negative half-wave voltage cycle is input, the line between the midpoint of the power frequency rectifier circuit and the positive output terminal of the power factor correction circuit is turned on, and the line between the midpoint of the starting rectifier circuit and the positive output terminal of the power factor correction circuit is turned off. Similarly, the line between the midpoint of the clamping circuit and the positive output terminal of the power factor correction circuit is turned off, and the line between the midpoint of the clamping circuit and the negative output terminal of the power factor correction circuit is also turned off. At this time, if a positive phase-differential mode lightning surge occurs... The lines between the midpoint of the starting rectifier circuit and the negative output terminal of the power factor correction circuit, and between the midpoint of the clamping circuit and the positive output terminal of the power factor correction circuit, are both turned off. The lines between the midpoint of the starting rectifier circuit and the positive output terminal of the power factor correction circuit, and between the midpoint of the clamping circuit and the negative output terminal of the power factor correction circuit, are both turned on. The voltage across the second winding is clamped by the clamping circuit, thereby limiting the current spike flowing through the switching transistor connected to the positive output terminal of the power factor correction circuit in the power frequency rectifier circuit.

3. The power factor correction circuit according to claim 1, characterized in that: The clamping circuit includes a first diode, a second diode, a first capacitor, and a second capacitor. The cathode of the first diode is connected to the positive output terminal of the power factor correction circuit, the anode of the first diode is connected to one end of the first capacitor, the cathode of the second diode is connected to the other end of the first capacitor, the anode of the second diode is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the negative output terminal of the power factor correction circuit.

4. The power factor correction circuit according to claim 1, characterized in that: The starting rectifier circuit includes two passive switching transistors connected in series; and / or the high-frequency rectifier circuit includes two active switching transistors connected in series; and / or the power frequency rectifier circuit includes two active switching transistors connected in series.

5. The power factor correction circuit according to claim 4, characterized in that: The two passive switching transistors in the starting rectifier circuit are diodes, with the cathode of one diode connected to the positive output terminal of the power factor correction circuit, the anode of the first diode connected to the cathode of the second diode, and the anode of the second diode connected to the negative output terminal of the power factor correction circuit; and / or the two active switching transistors in the high-frequency rectifier circuit are field-effect transistors, IGBTs, SICMOS, or GAns; and / or the two active switching transistors in the power frequency rectifier circuit are field-effect transistors, IGBTs, SICMOS, or GAns.

6. The power factor correction circuit according to claim 1, characterized in that: The power factor correction circuit further includes an additional inductor, which comprises a winding connected in series between the other end of the first winding and the midpoint of the high-frequency rectifier circuit. The impedance between the midpoint of the starting rectifier circuit and the midpoint of the high-frequency rectifier circuit.

7. The power factor correction circuit according to any one of claims 1 to 6, characterized in that: The power factor correction circuit includes N high-frequency rectifier circuits and N inductors, where N is a natural number greater than or equal to 2. One end of the first winding of each inductor and the midpoint of the starting rectifier circuit are simultaneously connected to the first input terminal of the power factor correction circuit. The other end of the first winding of each inductor is connected to the midpoint of a high-frequency rectifier circuit or connected to the midpoint of a high-frequency rectifier circuit through an additional inductor. One end of the second winding of each inductor is connected to the second input terminal of the power factor correction circuit. The other end of the second winding of the previous inductor is connected to one end of the second winding of the next inductor. The other end of the second winding of the last inductor is connected to the midpoint of the high-frequency rectifier circuit. The parameters of each inductor and the additional capacitor are designed to individually satisfy the formula. For a given inductor and the additional capacitor, The impedance between the midpoint of the starting rectifier circuit and the midpoint of the corresponding high-frequency rectifier circuit. It includes N impedances connected in parallel, wherein the N impedances are: the impedance between the midpoint of the clamping circuit and the midpoint of the power frequency rectifier circuit, and the impedances of the midpoints of the other N-1 high-frequency rectifier circuits (excluding the corresponding high-frequency rectifier circuit) to the midpoint of the starting rectifier circuit. This is the impedance of the parasitic capacitance of the midpoint of the corresponding high-frequency rectifier circuit to the ground. The impedance is the result of N+2 capacitors connected in parallel. The N+2 capacitors are: the parasitic capacitance of the positive output terminal of the power factor correction circuit to the ground, the parasitic capacitance of the negative output terminal of the power factor correction circuit to the ground, the additional capacitor, and the parasitic capacitance of the midpoint of each of the other N-1 high-frequency rectifier circuits (excluding the corresponding high-frequency rectifier circuit) to the ground.

8. The power factor correction circuit according to claim 7, characterized in that: The power factor correction circuit includes M additional inductors, where M is a natural number greater than or equal to 2 and M is less than or equal to N; the windings of each additional inductor are connected in series between the other end of the primary winding of one of the N inductors and the midpoint of the corresponding high-frequency rectifier circuit.

9. The power factor correction circuit according to claim 7, characterized in that: The first and second windings of the N inductors are either reverse-coupled or forward-coupled.

10. The power factor correction circuit according to claim 7, characterized in that: The N inductors and M additional inductors are magnetically integrated.

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