Burst frame, burst frame transmission method and device, equipment and storage medium

Abstract

The application discloses a burst frame, a burst frame transmission method and device, equipment and a storage medium. The burst frame comprises a preamble and a payload. The preamble is modulated by using a first modulation format. The payload is modulated by using a second modulation format. The preamble and the payload of the burst frame adopt different modulation formats. In this way, on the one hand, the payload can be modulated by using a high code rate modulation format, and on the other hand, the preamble of the burst frame can adopt a low code rate modulation format, so that clock synchronization can be realized by using the original system, and therefore, the old device for clock synchronization at the receiving end has good compatibility.

Description

[0001] This application is a divisional application of the application with the application date of "December 25, 2018", the application number of "201811594792.4", and the application title of "burst clock synchronization, burst frame transmission method and device, equipment and storage medium". TECHNICAL FIELD

[0002] The present application relates to the technical field of communication but is not limited to the technical field of communication, and in particular relates to a burst frame, a burst frame transmission method and device, equipment and a storage medium. BACKGROUND

[0003] Passive optical network (PON) is a kind of optical fiber network with point-to-multipoint topology structure, which includes an optical line terminal (OLT) at the local end, an optical distribution network (ODN), and an optical network unit (ONU) at the user side. In the downlink direction, the OLT sends data to each ONU in the form of broadcast. Since the downlink is in continuous mode, each ONU can easily recover the data and clock signal for frequency synchronization in the uplink direction. However, in the uplink direction, the ONU sends burst frames carrying data to the OLT in a burst manner, and the time of each ONU arriving at the OLT is inconsistent, and the phase of the clock is random. In order to avoid data collision, only one ONU is allowed to occupy the uplink channel in a time window. In order to improve the uplink efficiency, the receiving end of the OLT is required to recover the clock information in a limited time to realize the synchronization of the clock frequency and phase.

[0004] Ethernet passive optical network (EPON) and gigabit-capable PON (GPON) use burst clock data recovery (BCDR) chips to realize the synchronization of the clock frequency and phase. This synchronization is based on hardware circuit, and the circuit structure is complex, the hardware size is large, and the power consumption is high. Moreover, the BCDR chip can only perform clock synchronization for non-return to zero (NRZ) code type. Therefore, it is impossible to realize clock synchronization by using a general DSP circuit. SUMMARY

[0005] Therefore, the embodiments of the present application expect to provide a burst clock synchronization method and device, a burst frame transmission method and device, a communication device and a computer storage medium, which at least partially solve the above problems.

[0006] To achieve the above object, the technical scheme of the present application is implemented as follows:

[0007] In the first aspect, the present application provides a burst frame, which comprises a preamble and a payload.

[0008] The preamble is modulated by using a first modulation format; and the payload is modulated by using a second modulation format.

[0009] Optionally, the order of the first modulation format is not higher than the order of the second modulation format.

[0010] Optionally, the baud rate of the preamble is equal to the baud rate of the payload.

[0011] Optionally, the first modulation format is a non-return-to-zero (NRZ) modulation.

[0012] The second modulation format is a pulse amplitude modulation (PAM) or a duobinary modulation.

[0013] Optionally, the preamble further comprises a burst delimiter, which is used to indicate the starting position of the payload in the burst frame.

[0014] Optionally, the preamble comprises a synchronization header, which comprises a synchronization sequence, and the synchronization sequence is used for signal clock synchronization at a receiving end.

[0015] In the second aspect, the present application provides a burst frame transmission method, which comprises the following steps.

[0016] Transmitting a burst frame; wherein the burst frame comprises a preamble and a payload; the preamble is modulated by using a first modulation format; and the payload is modulated by using a second modulation format.

[0017] Optionally, in the case that a transmitting end needs to transmit the burst frame, the transmission method comprises the following steps.

[0018] Modulating the preamble by using the first modulation format;

[0019] Modulating the payload by using the second modulation format;

[0020] Transmitting the burst frame.

[0021] Optionally, the preamble comprises a synchronization header, which comprises a synchronization sequence; in the case that a receiving end receives the burst frame, the transmission method comprises the following steps.

[0022] Receiving the burst frame;

[0023] Sampling the burst frame to obtain a sampling signal;

[0024] extracting the sync header from the sampling signal;

[0025] performing digital signal processing (DSP) on the sync header to obtain a phase error;

[0026] performing clock synchronization based on the phase error.

[0027] In a third aspect, an embodiment of the present application provides a burst frame transmission device, comprising:

[0028] a transmission module configured to transmit a burst frame, wherein the burst frame comprises a preamble and a payload; the preamble is modulated by using a first modulation format; and the payload is modulated by using a second modulation format.

[0029] In a fourth aspect, an embodiment of the present application provides a communication device, comprising a transceiver, a memory, a processor, and a computer program stored in the memory and executed by the processor;

[0030] The processor is connected with the transceiver and the memory respectively, and is configured to execute the computer program, so as to realize the burst frame transmission method in the second aspect.

[0031] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program; the computer program is executed to realize the burst frame transmission method in the second aspect.

[0032] The burst frame, the burst frame transmission method and device, the equipment and the storage medium provided by the embodiment of the present application have at least the following beneficial effects: the clock synchronization can be realized by using the general DSP circuit, so that the special hardware circuit is not used for clock synchronization, the cost caused by the design of the special hardware circuit can be reduced, and the problems of large size, complex structure, high power consumption and the like of the hardware circuit are avoided. In addition, the phase error is obtained by digital signal processing, and the clock synchronization is performed, so that the general DSP circuit can be used for realization, and the burst frame formed by various modulation formats can be applied, which is not limited to a certain modulation format, and has the characteristics of good universality. At the same time, the efficiency of clock synchronization can be accelerated by using the DSP processing. The preamble and the payload of the burst frame use different modulation formats, so that on the one hand, the payload can be adjusted by using the modulation format with high code rate, and on the other hand, the preamble of the burst frame can use the original modulation format with low code rate, so that the clock synchronization can be realized by using the original system, and therefore the old device for clock synchronization in the receiving end has good compatibility.

[0033] Other features and advantages of the present application will be set forth in the following specification, and in part will be apparent from the description, or can be learned by practice of the application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1A A flowchart of a burst clock synchronization method is provided for an embodiment of the present application;

[0035] Figure 1B A flowchart of another burst clock synchronization method is provided for an embodiment of the present application;

[0036] Figure 2 A structure diagram of a burst frame is provided for an embodiment of the present application;

[0037] Figure 3 A flowchart of a burst frame transmission method is provided for an embodiment of the present application;

[0038] Figure 4 A flowchart of another burst frame transmission method is provided for an embodiment of the present application;

[0039] Figure 5 A structure diagram of a clock synchronization device is provided for an embodiment of the present application;

[0040] Figure 6 A structure diagram of a communication device is provided for an embodiment of the present application;

[0041] Figure 7 A structure diagram of an OLT is provided for an embodiment of the present application;

[0042] Figure 8 A structure diagram of an analog-to-digital converter and a DSP module is provided for an embodiment of the present application;

[0043] Figure 9 A structure diagram of another analog-to-digital converter and a DSP module is provided for an embodiment of the present application;

[0044] Figure 10 A structure diagram of still another analog-to-digital converter and a DSP module is provided for an embodiment of the present application;

[0045] Figure 11 A flowchart of another burst frame transmission method is provided for an embodiment of the present application;

[0046] Figure 12 A flowchart of a burst frame processing method is provided for an embodiment of the present application;

[0047] Figure 13 A waveform diagram of a burst frame provided by an embodiment of the present application;

[0048] Figure 14 A phase detection effect diagram of a burst frame clock signal provided by an embodiment of the present application;

[0049] Figure 15 A flow diagram of another burst frame transmission method provided by an embodiment of the present application;

[0050] Figure 16 A flow diagram of another burst frame processing method provided by an embodiment of the present application;

[0051] Figure 17 A waveform diagram of another burst frame provided by an embodiment of the present application;

[0052] Figure 18 A phase detection effect diagram of another burst frame clock signal provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] The technical solutions of the present application are further described in detail below in combination with the accompanying drawings and specific embodiments.

[0054] As shown in Figure 1A , the present embodiment provides a burst clock synchronization method, comprising:

[0055] Step S110: receiving a burst frame;

[0056] Step S120: sampling the burst frame to obtain a sampling signal;

[0057] Step S130: extracting a synchronization header from the sampling signal;

[0058] Step S140: performing DSP on the synchronization header to obtain a phase error;

[0059] Step S150: performing clock synchronization based on the phase error.

[0060] For example, further, the burst clock synchronization method can comprise, as shown in Figure 1B , comprising:

[0061] Step S110': receiving a burst frame;

[0062] Step S120': sampling the burst frame with a local sampling clock to obtain a sampling signal;

[0063] Step S130': extracting a synchronization header from the sampling signal;

[0064] Step S140: DSP is performed on the synchronization header to obtain a phase error of the local sampling clock and the signal clock;

[0065] Step S150': synchronization of the signal clock and the local sampling clock is performed based on the phase error.

[0066] The burst clock synchronization method provided in the embodiment can be a method applied to a receiving end, which can be an OLT. In the embodiment, the burst frame is a data frame sent by a sending end, which can be an ONU. The burst clock synchronization method is synchronization of a local sampling clock of the receiving end and a signal clock of the sending end. The local sampling clock is a clock in the receiving end; and the signal clock can be a clock of the sending end for sending the burst frame.

[0067] The synchronization clock is a clock signal kept synchronized between the receiving end and the sending end.

[0068] In the embodiment, the clock synchronization can be achieved after DSP processing by a general DSP circuit, so that a hardware circuit specially designed for clock synchronization is not needed. The general DSP circuit itself has the characteristics of simple structure, small size, good versatility and low power consumption compared with a pure hardware circuit.

[0069] In the embodiment, since the DSP is used for clock synchronization, the analog signal of the burst frame is first sampled in the embodiment, so that the analog signal is discretized to form the discretized sampling signal.

[0070] The synchronization header is carried in the burst frame, and the synchronization header is known in advance by the sending end and the receiving end. The sending end carries the synchronization header in the preamble when sending the burst frame.

[0071] The analog-to-digital converter can be used to sample the burst frame of the analog signal transmission, so as to obtain the sampling signal in a discrete form.

[0072] The extracted synchronization header is subjected to DSP in step S140 to obtain a phase error.

[0073] Based on the calculated phase error, the error between the sampling phase for forming the sampling signal and the phase of the burst frame can be known, so that the sampling signal can be adjusted based on the error to achieve clock synchronization, or the sampling phase is adjusted and then resampling is performed, which is equivalent to alignment of the sampling phase of the local sampling clock and the phase of the burst frame, so that the clock synchronization can also be achieved.

[0074] The step S110 can include: blindly sampling the burst frame and obtaining the sampling signal. In the embodiment, the blind sampling is sampling by a local sampling clock, and the phase of the sampling clock is not controlled and the sampling of the signal is performed with a random initial phase.

[0075] Optionally, there are various ways to determine the phase error, for example, a front feed or feedback type can be used to perform DSP processing on the sync header, so as to obtain the phase error of the local sampling clock and the signal clock.

[0076] For example, when the front feed type is used to perform DSP processing on the sync header, the step S140 can include: N times sampling of all or part of the sync header to obtain an N times sampling signal; N is a positive integer greater than or equal to 1; and phase detection is performed on the N times sampling signal to obtain a phase error sampling signal of the signal clock and the local sampling clock.

[0077] After N times sampling, a sufficient number of sampling signals can be formed for phase error detection.

[0078] In the embodiment, the sync header is N times sampled, for example, N equals 2 or 4, and here, N can be 4. If N times sampling is performed, the original sync header including M signal values will form N*M signal values. Then, phase detection is performed on the sampled signal to obtain the phase error. For example, amplitude angle operation is performed on the up-sampled signal to obtain the phase error. There are various ways to perform amplitude angle operation, and an optional way is provided as follows:

[0079]

[0080] In the formula, N is the up-sampling multiple. k is the serial number of the sampling signal before up-sampling; X(k / N) is the signal value of the sampling signal before up-sampling; arg is a function of amplitude angle; L is the number of the used sync header symbols; LN is the signal length of the sampling signal after up-sampling; and ξ is the calculated phase error. N (k / N) is the signal value of the sampling signal before up-sampling. arg is a function of amplitude angle; L is the number of the used sync header symbols; LN is the signal length of the sampling signal after up-sampling; and ξ is the calculated phase error.

[0081] When the feedback type is used to perform DSP on the sync header, the step S140 can include:

[0082] Interpolation operation is performed on the sync header with an initial clock phase error

[0083] Timing error detection is performed on the signal obtained by the interpolation operation to obtain a timing error;

[0084] Based on the timing error, a clock phase error used for interpolation operation is determined.

[0085] In the embodiment, the timing error is detected first to obtain the timing error, and then the timing error is converted into the phase error. If the timing error is extracted first, the sampling multiple can be appropriately reduced. For example, the timing error can be extracted by twice sampling the sync head. After the timing error is extracted, the phase error is calculated based on the timing error, so that the calculation amount required for the phase error detection can be saved, the calculation rate of the phase error can be improved, and the efficiency of the clock synchronization can be improved.

[0086] The synchronization between the local sampling clock and the signal clock based on the timing error can include:

[0087] The phase error is formed based on the timing error by a certain algorithm to perform the interpolation operation, and then the phase error is iterated until the phase error approaches zero. For example, the phase error of the signal clock and the local sampling clock is gradually converged and tracked, the next group or multiple groups of sampling signals are interpolated based on the obtained phase error, the clock error detection is performed again, the new phase error is formed, and the next group or multiple groups of sampling signals are interpolated based on the phase error, and the above process is repeated until the error converges to zero.

[0088] There are various ways to calculate the timing error, and an optional way to calculate the timing error is provided below, which is not limited to the following method:

[0089] ξ(k) = X(k-1 / 2) [X(k)-X(k-1)]

[0090] X(k) is the kth signal value in the sampling signal; X(k-1) is the (k-1)th signal value in the sampling signal; X(k-1 / 2) is the signal value between the kth signal value and the (k-1)th signal value. ξ(k) is the timing error of the kth signal.

[0091] The phase error is calculated based on the timing error:

[0092] g(k) = k p ξ(k) + k i [ξ(k) + ξ(k-1)]

[0093] g(k) is the kth calculated phase error. k p is a propagation coefficient; k i is an integration coefficient.

[0094] In some embodiments, the step S150 can include performing interpolation operation on the next group of sampling signals based on the phase error to achieve clock synchronization.

[0095] In the clock synchronization, the phase of the sampling signal can be directly adjusted according to the phase error to complete the clock synchronization, or the phase of the next group of sampling signals can be adjusted according to the current detected phase error to complete the clock synchronization.

[0096] The clock synchronization can be achieved by an interpolation algorithm. The interpolation operation can be one or more of linear interpolation, parabolic interpolation, exponential interpolation, Lagrange cubic interpolation, etc., but the implementation is not limited to any of the above.

[0097] In some embodiments, the step S120 can include that the phase of the local sampling clock is controlled based on a digital signal processing (DSP) module and the sampling of the signal is performed at an initial phase. In addition, the step S140 can include that the phase of the local sampling clock is adjusted based on the phase error of the local sampling clock and the signal clock and by the DSP module; thus the DSP module directly adjusts the local sampling clock to achieve synchronization of the local sampling clock with the signal clock of the sending end. Further, the step S140 can include that the timing error of the signal clock and the local sampling clock is obtained by the DSP based on the synchronization header; the phase error is generated based on the timing error; and the phase of the local sampling clock is adjusted by the DSP module based on the phase error.

[0098] In some other embodiments, the step S150 can include that the clock synchronization is achieved by adjusting the sampling phase of the burst frame according to the phase error.

[0099] In the present embodiment, the phase of the sampling clock of the analog-to-digital converter is calibrated according to the phase error to achieve the clock synchronization.

[0100] In the present embodiment, the clock synchronization can include frequency synchronization and phase synchronization of the clock.

[0101] In some embodiments, the sampling is performed by an analog-to-digital converter of the receiving end according to a local sampling clock, and in the present embodiment, the sampling phase of the local sampling clock is adjusted to adjust the sampling phase of the analog-to-digital converter.

[0102] Therefore, in the present embodiment, the clock synchronization can be achieved in multiple ways, one of which is to adjust the phase of the sampling signal after sampling by interpolation operation to achieve the clock synchronization, and the other of which is to adjust the phase of the local sampling clock to achieve the clock synchronization of the sampling signal after sampling.

[0103] Optionally, the burst frame includes a preamble modulated by a first modulation format and a payload modulated by a second modulation format; and the preamble includes the synchronization header. The structure of the burst frame can be as shown in Figure 2 ​

[0104] The first modulation format and the second modulation format are different. For example, the first modulation format is NRZ code modulation; and the second modulation format is pulse amplitude modulation (PAM) or duobinary modulation. In some embodiments, the modulation order of the first modulation format can be lower than the modulation order of the second modulation format.

[0105] In the embodiment, the preamble and the payload of the burst frame adopt different modulation formats. In this way, on the one hand, the payload can be adjusted by using a high code rate modulation format; and on the other hand, the preamble of the burst frame can still use the original modulation format with a lower code rate, so that the clock synchronization can be realized by using the original system, and therefore the old device for clock synchronization at the receiving end has good compatibility.

[0106] Optionally, the baud rate of the preamble is the same as the baud rate of the payload.

[0107] As shown in Figure 2 The burst frame includes a preamble and a payload, wherein the preamble includes the synchronization header and further includes a burst delimiter between the synchronization header and the payload. The burst delimiter can be used to determine the position of the payload during demodulation, so as to facilitate the receiving end to switch the demodulation mode for demodulating the payload.

[0108] As shown in Figure 3 The embodiment provides a burst frame transmission method, which includes the following steps.

[0109] Step S200: transmitting a burst frame, wherein the burst frame includes a preamble and a payload; the preamble is obtained by adjusting by using a first modulation format; and the payload is obtained by adjusting by using a second modulation format.

[0110] In the embodiment, the step S200 can include: transmitting the burst frame by a sending end; and / or receiving the burst frame by a receiving end.

[0111] For example, if the burst frame transmission method is applied to a sending end, as shown in Figure 4 The method can include the following steps.

[0112] Step S201: modulating the preamble by using a first modulation format.

[0113] Step S202: modulating the payload by using a second modulation format.

[0114] Step S203: transmitting the burst frame.

[0115] In this embodiment, the transmitting end can be an OLT. The OLT modulates the preamble by using a first modulation format, and modulates the payload by using a second modulation format. The payload is the data signal that the transmitting end needs to send to the receiving end. In some embodiments, the order of the first modulation format is not higher than the order of the second modulation format.

[0116] In this embodiment, the synchronization header can be used for clock synchronization, and can also be used for setting parameters of a Trans Impedance Amplifier (TIA) in the receiving end. For example, the amplitude of the TIA can be set. The TIA can convert the sampling signal in the form of current into the sampling signal in the form of voltage.

[0117] In this embodiment, the first modulation format and the second modulation format are different modulation formats. For example, the first modulation format is an NZR modulation format, and the second modulation format can be a PAM modulation format or a duobinary modulation format. Different modulation formats adopt different modulation principles. For another example, the modulation orders of the first modulation format and the second modulation format are different. For example, the modulation order of the first modulation format can be lower than the modulation order of the second modulation format. That is, the first modulation format can be a low-order modulation format, and the second modulation format can be a high-order modulation format. The code rate of the high-order modulation format is higher than the code rate of the low-order modulation format. In some embodiments, the order of the first modulation format is not higher than the order of the second modulation format.

[0118] In this embodiment, the burst frame including the preamble and the payload is transmitted. Obviously, at this time, the preamble and the payload included in the burst frame are formed by using different modulation formats, and different demodulation manners need to be used when demodulation is performed.

[0119] In this embodiment, the preamble includes a synchronization header, and the synchronization header can include a synchronization sequence and can be used for clock synchronization of a signal in the receiving end.

[0120] In some embodiments, the baud rate of the preamble is equal to the baud rate of the payload. The baud rate can be the number of symbol bits transmitted per unit time. In this embodiment, the preamble and the payload adopt different modulation formats, but the same baud rate is adopted after modulation and coding. If the baud rates of the preamble and the payload are the same, the receiving end can directly switch from the preamble to the payload in the DSP processing such as equalization, demodulation, or decision, without switching the baud rate, so as to realize smooth transition of demodulation and avoid complex operations in subsequent DSP processing such as demodulation and decoding caused by different baud rates.

[0121] For example, the first modulation format is NRZ code modulation; and the second modulation format is PAM or duobinary modulation.

[0122] In some embodiments, the preamble further comprises a burst delimiter, the burst delimiter being used to indicate a starting position of the payload in the burst frame.

[0123] The burst delimiter is located between the synchronization header and the payload, and an end of the burst delimiter is the starting position of the payload. In this way, the receiving end can locate the starting position of the payload according to the burst delimiter, so as to demodulate the payload.

[0124] As shown in FIG. 1, the embodiment provides a clock synchronization device, comprising: Figure 5

[0125] A receiving module 110 is configured to receive a burst frame.

[0126] A sampling module 120 is configured to sample the burst frame to obtain a sampling signal.

[0127] An extracting module 130 is configured to extract a synchronization header from the sampling signal.

[0128] A processing module 140 is configured to perform digital signal processing (DSP) on the synchronization header to obtain a phase error.

[0129] A synchronization module 150 is configured to perform clock synchronization based on the phase error.

[0130] In the embodiment, the receiving module 110, the sampling module 120, the extracting module 130, the processing module 140, and the synchronization module 150 can be program modules, which can realize the reception of the burst frame, the sampling of the signal, the extraction of the synchronization header, and the calculation of the phase error after being executed by a processor, and finally can perform clock synchronization based on the phase error.

[0131] In the embodiment, the clock synchronization device can be a device applied to a receiving end, which can comprise a processor and a memory. The processor can be connected to the memory through an integrated circuit bus. The memory can comprise various types of storage media, and can be used to store computer programs, various calculation parameters in calculation processes, and the like. The processor can be a central processing unit, a microprocessor, a digital signal processor, an application processor, an application-specific integrated circuit, or the like.

[0132] Optionally, the sampling module 120 is specifically configured to perform blind sampling on the burst frame to obtain the sampling signal.

[0133] In the embodiment, the blind sampling on the burst frame can be sampling of the analog signal of the burst frame by using a random sampling phase.​

[0134] Optionally, the processing module 140 is specifically configured to perform DSP on the synchronization header in a feedforward or feedback manner to obtain a phase error of the local sampling clock and the signal clock. For example, the processing module 140 can be configured to perform N times sampling on all or part of the synchronization header to obtain an N times sampling signal; N is a positive integer not less than 1; and perform phase detection on the N times sampling signal to obtain the phase error of the signal clock and the local sampling clock.

[0135] Optionally, the processing module 140 is further configured to perform interpolation operation on the synchronization header with an initial clock phase error; perform timing error detection on a signal obtained by the interpolation operation to obtain a timing error; and determine the clock phase error used for the interpolation operation based on the timing error.

[0136] Optionally, the synchronization module 150 is configured to perform interpolation operation on the current group of sampling signals based on the phase error to realize clock synchronization.

[0137] In some embodiments, the synchronization module 150 is configured to perform interpolation operation on a next group of sampling signals according to the phase error to realize clock synchronization.

[0138] In some other embodiments, the synchronization module 150 is specifically configured to adjust a sampling phase of the burst frame according to the phase error to realize clock synchronization.

[0139] In still another embodiment, the local sampling clock is controlled by a DSP module of a receiving end clock, and the receiving end initially performs sampling on a signal at a certain initial phase according to the local sampling clock. The processing module 140 is configured to adjust the phase of the local sampling clock based on a phase error of the local sampling clock and the signal clock and through the DSP module. For example, the processing module 140 can be configured to perform DSP on the synchronization header to obtain a timing error of the signal clock and the local sampling clock; generate a phase error based on the timing error; and perform phase adjustment on the local sampling clock based on the phase error.

[0140] Optionally, the burst frame includes a preamble and a payload; the preamble includes the synchronization header; the preamble is obtained by adjusting a first modulation format; and the payload is obtained by adjusting a second modulation format.

[0141] Further, a baud rate of the preamble is the same as a baud rate of the payload.

[0142] In some embodiments, the order of the first modulation format is higher than the order of the second modulation format. For example, the first modulation format is a non-return-to-zero (NRZ) code modulation; and the second modulation format is a pulse amplitude modulation (PAM) or a duobinary modulation. The second modulation format can be a pulse coded modulation. In some embodiments, the order of the first modulation format is not higher than the order of the second modulation format. In yet some embodiments, the baud rate of the preamble is equal to the baud rate of the payload.

[0143] The embodiments provide a burst frame transmission apparatus, comprising:

[0144] a transmission module, configured to transmit a burst frame, wherein the burst frame comprises a preamble and a payload; the preamble is obtained by adjusting a first modulation format; and the payload is obtained by adjusting a second modulation format.

[0145] In the embodiments, the transmission module can also be a program module, which can be executed by a processor through the transmission module, and can control a transceiver in a sending end and / or a receiving end to send and / or receive the burst frame. In the embodiments, the burst frame comprises the preamble, and the preamble and the payload are modulated by different modulation formats.

[0146] Optionally, the order of the first modulation format is not higher than the order of the second modulation format.

[0147] Optionally, the baud rate of the preamble is equal to the baud rate of the payload. For example, the first modulation format is a non-return-to-zero (NRZ) code modulation; and the second modulation format is a pulse amplitude modulation (PAM) or a duobinary modulation.

[0148] In addition, the preamble further comprises a burst delimiter, which is used to indicate a starting position of the payload in the burst frame.

[0149] In some embodiments, the burst frame transmission apparatus further comprises:

[0150] a first modulation module, configured to modulate the preamble by a first modulation format;

[0151] a second modulation module, configured to modulate the payload by a second modulation format;

[0152] a transmission module, configured to transmit the burst frame comprising the preamble and the payload.

[0153] As shown in FIG. 2, Figure 6 The embodiments provide a communication device, comprising a transceiver 210, a memory 220, a processor 230, and a computer program stored in the memory 220 and executed by the processor 230;

[0154] The processor 230, connected with the transceiver 210 and the memory 220 respectively, is configured to execute the computer program, and can implement the burst clock synchronization method provided by one or more of the foregoing technical solutions, or implement the burst frame transmission method provided by one or more of the foregoing technical solutions.

[0155] The transceiver 210 can correspond to a communication interface, for example, can be an optical fiber interface between an OLT and an ONU, etc.

[0156] The memory 220 can be various types of memories, for example, random memories, read-only memories, flash memories, or various storage media such as solid state disks.

[0157] The processor 230 can be a central processing unit, a microprocessor, a digital signal processor, an application processor, or an application specific integrated circuit, which can be connected with the transceiver and the memory through a bus such as an integrated circuit bus, and can be used to implement one or more of the methods provided by any of the foregoing embodiments, for example, one or more of the methods shown in FIG. 1, Figure 12 and Figure 16 The processor 230 can also be used to implement one or more of the burst frame transmission methods provided by any of the foregoing embodiments, for example, one or more of the methods shown in FIG. 1, Figures 3-4 .

[0158] The communication device can be the ONU or the OLT.

[0159] The embodiment also provides a computer storage medium storing a computer program; the computer program, when executed, can implement one or more of the burst clock synchronization methods provided by the foregoing technical solutions, or implement one or more of the burst frame transmission methods provided by the foregoing technical solutions; for example, one or more of the methods shown in FIG. 1, Figure 12 and Figure 16 The computer storage medium can also be used to implement one or more of the burst frame transmission methods provided by any of the foregoing embodiments, for example, one or more of the methods shown in FIG. 1, Figures 3-4 .

[0160] The computer storage medium can include various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks. Optionally, the computer storage medium can be a non-transitory storage medium.

[0161] The following provides several specific examples in combination with any of the foregoing embodiments:

[0162] Example 1:

[0163] The example provides a burst clock synchronization method based on DSP burst frame, comprising:

[0164] The burst clock synchronization method and its implementation device, including the clock synchronization method and device based on feedforward and feedback burst clock synchronization method and device.

[0165] The passive optical network digital burst clock synchronization method and device provided by the example has a basic structure as shown in Figure 7 In the passive optical network, signals from different ONUs arrive at the OLT in burst mode. The OLT detects the burst frame from the ONU, performs photoelectric conversion using a photoelectric conversion machine, and obtains the photoelectrically converted signal. The signal is then sampled by an analog-to-digital converter (ADC). However, due to the randomness of the clock phase of the burst frame, the OLT needs to extract the signal clock within a limited number of symbols or time units and restore it to a clock-synchronized signal, so that the signal obtained by the OLT is at the optimal center sampling point of the signal. To this end, the example uses a DSP-based clock synchronization output synchronized signal to realize clock extraction and synchronization of burst frames.

[0166] The clock synchronization problem of the next-generation high-order modulation PON system is solved, and the uplink burst data can be recovered within a limited number of symbols. The low-order modulation signal is used for clock synchronization and synchronization, so that the burst clock synchronization method of the high-order modulation system becomes simple, and it is compatible with the existing low-order modulation system without additional method adjustment.

[0167] This method is based on digital clock synchronization, and the DSP burst clock synchronization method has low complexity, stable performance, and is more direct for signal processing, and can process more information.

[0168] This method can be implemented by a DSP chip, and has better compatibility. It is suitable for any high-order modulation system with the same baud rate as the low-order modulation signal, and does not need to develop different DSP chips for specific high-order modulation systems, thereby reducing the cost of system upgrade.

[0169] Example 2:

[0170] The feedforward full-sampling signal processing burst clock synchronization method and implementation device proposed in the present application are shown in Figure 8 The main function of the sampling signal processing (DSP) module is to reconstruct and synchronize the signal.

[0171] The analog-digital converter samples based on a local sampling clock, and a digital signal sampled by the analog-digital converter is detected by using a burst frame detection. In the implementation device, the analog-digital converter performs free blind sampling, i.e. the phase of the local sampling clock is not controlled, and the sampling of the signal is performed with a random initial phase; the reconstruction and synchronization of the signal are performed in a DSP module, and the clock synchronization is also performed in the DSP module, without the need of a feedback signal to adjust the local sampling clock for frequency or phase. Meanwhile, the DSP module is implemented by using a feedforward structure, i.e. the phase extraction of the clock of the signal in the DSP module does not depend on the feedback signal, but directly extracts the corresponding clock phase of the signal, and the clock is reconstructed and recovered by using interpolation operation. The feedforward clock synchronization has the characteristic of open loop, and has the characteristic of fast clock synchronization. In the example, after the burst frame detection, the DSP module divides the detected sampling signal into two paths, one of which is directly transmitted to an interpolation operation module, and the other of which is transmitted to a module for extracting a synchronization header. After the extraction of the synchronization header, N times of upsampling is performed, then the sampling signal is discarded to perform M times of power operation, and then phase detection is performed. The interpolation operation is performed based on the phase error obtained by the phase detection, to realize the clock synchronization.

[0172] The feedforward burst clock synchronization method proposed in the example is specifically based on N times of power budget and phase detection. After the detection of the burst frame, the DSP module extracts a synchronization header, performs N times of upsampling operation on the signal to obtain N(N>=4) sampling data per symbol, then performs M times (M>=2) power operation, and then performs phase detection. To ensure stable and accurate extraction of the clock, N should be greater than or equal to 4, and M should be greater than or equal to 2.

[0173] The specific calculation method is determined by the following formula. Assuming that the signal sampled by the ADC after N times of upsampling is XN(k / N), the obtained sampling phase error is:

[0174]

[0175] Wherein, L is the number of synchronization header symbols, and arg(.) is an argument function. A typical clock feedforward recovery method is 4 times of upsampling and square detection, i.e. N=4 and M=2.

[0176] The interpolation operation usually includes but is not limited to linear interpolator, parabolic interpolation, exponential interpolation, Lagrange cubic interpolation, etc. In actual application, optimization should be performed according to complexity and performance.

[0177] Example 3:

[0178] The feedback type burst clock synchronization method and implementation device for full sampling signal processing are as follows: Figure 9As shown, the signal reconstruction and synchronization are mainly performed by a sampling signal processing (DSP) module. In this implementation, the ADCs are also free-running blind samplers, and the signal reconstruction and synchronization are all performed in the DSP module, and the clock synchronization is also performed in the DSP module without the need of feedback signals to adjust the local sampling clock of the ADCs in frequency or phase. However, unlike the feedforward scheme, the feedback DSP scheme needs a feedback loop to track the frequency and phase variations. The feedback clock synchronization can be implemented by using the Gardner timing error detection method, which includes a timing error detection DSP module, a loop filter module, a digital oscillator module, and an interpolation operation module for the synchronization head signal. To ensure stable operation of the method, the signal for clock synchronization should be 2 times the sampling input. If the sampling clock of the ADC is less than 2 times the sampling, a 2 times sampling signal input should be obtained through digital resampling or interpolation operation. In this example, after the burst frame detects the sampling signal, it is directly output to the interpolation operation. If the sampling signal is received for the first time, the sampling signal is directly transmitted backward. If the sampling signal is not received for the first time, interpolation operation is performed based on the synchronization head extraction, the timing error detection, the phase error obtained by the loop filter based on the timing error detection, and the phase error maintained by the digital oscillator based on the phase error, so that the next group of sampling signals can be clock-synchronized.

[0179] The calculation of the timing error of the Gardner timing error detection method can use the following formula

[0180] ξ(k) = X(k-1 / 2) [X(k)-X(k-1)]

[0181] where X(k-1), X(k-1 / 2) and X(k) are the signal values of the three consecutive samples, respectively. The clock error obtained by this method needs to be loop-filtered to ensure stability, and the loop filtering can be implemented by using a commonly used second-order loop filter. The filter parameters include the propagation coefficient k p and the integral coefficient k i , and the phase error is obtained by the following formula

[0182] g(k) = k p ξ(k) + k i [ξ(k)+ξ(k-1)]

[0183] According to the clock phase error, the digital oscillator obtains the corresponding time coordinate and phase error input to the interpolator for signal reconstruction. Similarly, the interpolation operation usually includes but is not limited to linear interpolator, parabolic interpolation, exponential interpolation, Lagrange cubic interpolation, etc. In practical applications, optimization should be performed according to complexity and performance.

[0184] Through the loop feedback, the Gardner timing error detection tends to 0, so that the loop converges, and the burst clock obtains the corresponding clock phase and reconstructs the signal; meanwhile, due to the existence of the second-order feedback loop, the clock synchronization module can track the frequency change.

[0185] When clock synchronization is performed, the synchronization header should be recovered first; after the loop converges, phase and frequency tracking or stop tracking can be selected as needed. Since the method is transparent to the modulation format, it is suitable for various high-order PAM-N modulation signals.

[0186] In addition, the convergence speed and stability can be controlled by changing the ratio of k p and k i . The larger k p / k i , the faster the convergence but the greater the fluctuation; on the contrary, the smaller k p / k i , the smaller the fluctuation and the higher the stability but the slower the convergence. For optimization of this problem, a larger k p / k i value can be selected first to quickly converge, and then the value of k p / k i is gradually reduced as the number of calculated symbols increases, so that the system is more stable.

[0187] Example 4:

[0188] The burst clock synchronization method and implementation device of the feedback sampling signal processing hybrid voltage-controlled phase-locked loop are as shown in Figure 10 The device includes a voltage-controlled local sampling clock source, which drives an analog-to-digital converter ADC to sample, a DSP module to extract and loop filter the sampling timing error, and an analog-to-digital converter DAC to convert the feedback signal into a voltage-controlled frequency and phase control signal and input the control into the voltage-controlled local sampling clock source to change the frequency and phase accordingly.

[0189] Unlike the previous examples 2 and 3, the clock synchronization of this scheme is not a complete sampling signal processing scheme, but a hybrid of sampling signal processing and analog voltage-controlled phase-locked loop. The former mainly completes the timing error detection, and the latter mainly realizes the adjustment of the local ADC clock. Therefore, in this implementation device, the ADC analog-to-digital converter is not blind sampling, but strictly controlled by the voltage-controlled local sampling clock. The sampling phase of the local sampling clock is adjusted according to the detected phase error, and clock synchronization can also be achieved.

[0190] The feedback clock synchronization can also be realized by using the Gardner timing error detection method. For the synchronization head signal, the method comprises a timing error detection DSP module and a loop filter module. To ensure stable operation of the method, the signal for clock synchronization should be 2 times the sampling input. If the sampling clock of the ADC is less than 2 times the sampling, the 2 times sampling signal input should be obtained through digital resampling or interpolation operation.

[0191] Similarly, the core of the method is the Gardner timing error detection method, and the calculation of the timing error uses the following formula:

[0192] ξ(k) = X(k-1 / 2) [X(k)-X(k-1)]

[0193] Where X(k-1), X(k-1 / 2) and X(k) are three consecutive sampling values. The clock error obtained by the method needs to be loop filtered to ensure stability. The loop filtering can be realized by using a commonly used second-order loop filter, and the filter parameters include the propagation coefficient k p and the integral coefficient k i , and the phase error is obtained by the following formula

[0194] g(k) = k p ξ(k) + k i [ξ(k) + ξ(k-1)]

[0195] According to the clock phase error, the analog-to-digital converter normalizes and converts the signal into a voltage-controlled analog signal, which is used to control the sampling frequency and phase of the local sampling clock source. By changing the voltage-controlled signal, a new sampling point is obtained for the DSP module, and the loop Gardner timing error detection tends to 0, and the loop converges. Similarly, due to the existence of the second-order feedback loop, the clock synchronization module can track the frequency change.

[0196] Similarly to example 3, the convergence speed and stability can be controlled by changing the ratio of k p and k i . The larger k p / k i , the faster the convergence but the larger the oscillation fluctuation; on the contrary, the smaller k p / k i , the smaller the fluctuation and the higher the stability but the slower the convergence. For the optimization of this problem, a larger k p / k i value can be selected first to quickly converge, and then the value of k p / k i is gradually reduced as the number of calculation symbols increases, so that the system is more stable

[0197] Example 5:

[0198] The schematic diagram of the burst frame design scheme of the PON system with the modulation format of PAM_N is shown in Figure 11 The preamble based on the NRZ code type is mainly used, the preamble includes the synchronization header and the burst delimiter, the payload part is the PAM_N signal to be transmitted, and the prerequisite is that the baud rate of the preamble is equal to the baud rate of the payload, so as to realize the direct transition from the preamble to the payload. The synchronization header is mainly used for the TIA parameter setting and clock synchronization of the receiving end. The design idea of the code type of the synchronization header is to provide the periodic waveform with the highest frequency under the given line rate, and meanwhile, rich clock information is contained, for example, the code of "101010..." (not limited to this code type in practice) can be used. The burst delimiter is mainly used to find the starting point of the payload signal, and the burst delimiter can be selected as a code type with high autocorrelation and low repetition rate of the received data pattern. By performing the correlation operation between the delimiter and the received data, the obvious synchronization peak value can be obtained, and the position of the peak value can indicate the starting point position of the payload.

[0199] Taking the clock synchronization of the single-wavelength 50 Gb / s PAM4 (not limited to this rate and modulation format in practice) system as an example, the specific implementation process of the burst clock synchronization method provided in the application is described in detail, as shown in Figure 12 .

[0200] First, the burst frame structure design is performed on the schematic diagram of the uplink data reference Figure 11 For the 50 Gb / s PAM4 system, the clock rate of the electrical signal is 25 Gb / s, and the frame structure can be designed in the form of 25 Gb / s NRZ preamble + 50 Gb / s PAM4 payload. After the laser is turned on, the preamble based on the 25 Gb / s NRZ code type is used, the preamble includes the synchronization header and the burst delimiter, and the payload part is the 50 Gb / s PAM4 signal to be transmitted. The synchronization header is mainly used for the TIA parameter setting and clock synchronization of the receiving end. The code type of the synchronization header first uses the 101010... code (not limited to this code type and bit number in practice) of 1000 bits (symbols), and the 101010 signal can provide the periodic waveform with the highest frequency under the given line rate, and contains rich clock information.

[0201] When the uplink data arrives at the OLT receiving end, the OLT detects the burst frame from the ONU, performs frame detection through the receiver, performs coarse synchronization based on the synchronization header, configures the amplitude and other parameters of the TIA at the receiver end, and realizes the stable work of the TIA.

[0202] Subsequently, the electrical signal converted from the optical signal is sampled through analog-to-digital conversion (ADC);

[0203] After that, the burst clock information extraction and recovery is realized by using the DSP method. The burst clock synchronization method can be based on the feedforward full-sampling signal processing burst clock synchronization method described in the specific example 2, can be based on the feedback full-sampling signal processing burst clock synchronization method described in the specific example 3, or can be based on the feedback sampling signal processing hybrid ADC phase-locked loop burst clock synchronization method described in the specific example 4.

[0204] By accurately synchronizing to the starting point of the payload signal through the delimiter in the preamble, the burst delimiter can adopt a 66-bit code type (such as "01 1101 0110 0001 1111 0001 1011 0100 1000 0001 1011 0001 1010 00100111 1101 0101", and the actual code type is not limited to this). By using the correlation function operation, a clear synchronization peak value can be obtained, and the point where the peak value is located can indicate the starting point position of the payload. In addition, since noise is random and almost has no correlation, when the error rate is relatively high, the burst delimiter can still accurately synchronize to the starting point of the PAM4 payload signal.

[0205] Finally, without any switching, the high-order modulation signal of the same baud rate can be directly subjected to DSP processing such as equalization and decoding, so as to finally realize the detection and processing of the uplink burst signal of the OLT to the ONU.

[0206] The waveform diagram of the 50Gb / s PAM4 system generated according to the uplink burst frame structure provided in the present application is shown in Figure 13 The waveform diagram contains part of the preamble, the burst delimiter and part of the PAM4 payload. Figure 13 The waveform diagram of the 50Gb / s PAM4 system generated according to the uplink burst frame structure provided in the present example.

[0207] The experimental test results of the 50Gb / s PAM4 system show that the effect of the clock synchronization (Gardner) method based on the feedback full-sampling signal processing described in the specific example 3 is shown in Figure 14 . Figure 14 The horizontal coordinate represents the number of symbols required for clock synchronization, and the vertical coordinate represents the phase of the clock signal under the condition of low signal-to-noise ratio (SNR). As can be seen from the figure, by using the burst clock synchronization method and device provided in the present application, less than 100 symbols can be used to extract the clock and effectively perform clock synchronization and signal extraction. For the 50Gb / s PAM4 system, 100 symbols correspond to 4 nanoseconds, so the burst clock synchronization method and device provided in the present application can perform clock synchronization and signal extraction in less than 4 nanoseconds, and the method is simple and stable in performance.

[0208] For higher rate PAM_N (N=8, 16, 32...) system, the digital burst clock synchronization method and device provided by the present application can still be used. Specifically, as described above, the frame structure is designed in the form of NRZ (preamble) + PAM_N (payload), wherein the rate of the adopted NRZ preamble is equal to the baud rate of the PAM_N signal. The specific implementation process is similar to that of the PAM4 system described above.

[0209] Example 6:

[0210] As shown in Figure 15 , the modulation format of the payload of the burst frame can be Duo-Binary. Its basic functional modules are similar to those of the PAM_N system, the preamble includes a synchronization header and a burst delimiter, and the payload part is the Duo-Binary signal to be transmitted. However, since the Duo-Binary modulation can be generated by a device with limited bandwidth, the clock rate of the corresponding electrical signal does not decrease. Taking a 50Gb / s Duo-Binary system (not limited to this rate and modulation format) as an example, it can use a 25G bandwidth optoelectronic device to realize the modulation, transmission and reception of the signal, but the clock rate of the system electrical signal is still 50Gb / s, which cannot share the 25Gb / s NRZ signal clock. Therefore, it is necessary to redesign the clock extraction method of the 50Gb / s Duo-Binary system. The preamble of the 50Gb / s Duo-Binary system provided by the present application is designed to use a 50Gb / s NRZ signal. Due to the bandwidth limitation of the device, the 50Gb / s NRZ signal becomes a 50Gb / s Duo-Binary signal after delay addition in the system. The code type design idea of the synchronization header and the burst delimiter is the same as that described in embodiment four.

[0211] Taking the clock synchronization of a single-wavelength 50Gb / s Duo-Binary (not limited to this rate) system as an example, the specific implementation process of the burst clock synchronization method provided by the present application is described in detail, as shown in Figure 16 .

[0212] First, the uplink data reference Figure 15The burst frame structure is designed according to the schematic diagram, for a 50Gb / s Duo-Binary system, the clock rate of the electrical signal is 50Gb / s, and the frame structure can be designed in the form of 50Gb / s NRZ / Duo-Binary preamble + 50Gb / s Duo-Binary payload. After the laser is turned on, the 50Gb / s NRZ / Duo-Binary preamble is used, the preamble contains a synchronization header and a burst delimiter, and the payload part is the 50Gb / s Duo-Binary signal to be transmitted. The synchronization header is mainly used for TIA parameter setting and clock synchronization at the receiving end. For the 50Gb / s Duo-Binary payload signal after pre-coding, the code type of the synchronization header can be a 101010... code of 1000 bits (symbols), and the 101010 signal can provide the periodic waveform with the highest frequency under a given line rate, and contains rich clock information. In addition, for the 50Gb / s Duo-Binary payload signal without pre-coding, a pseudo-random binary sequence (PRBS) code can also be used as the synchronization header.

[0213] When the uplink data arrives at the OLT receiving end, the OLT detects the burst frame from the ONU, detects the frame through the receiver, performs coarse synchronization based on the synchronization header, configures the amplitude and other parameters of the TIA at the receiver end, and realizes stable operation of the TIA.

[0214] Then, the electrical signal after photoelectric conversion is sampled through analog-to-digital conversion (ADC);

[0215] Then, the burst clock information extraction and recovery are realized by using a DSP method. The burst clock synchronization method can be based on the feedforward full-sampling signal processing burst clock synchronization method described in the specific example 2, can be based on the feedback full-sampling signal processing burst clock synchronization method described in the specific example 3, or can be based on the feedback sampling signal processing hybrid ADC phase-locked loop burst clock synchronization method described in the specific example 4.

[0216] The delimiter in the preamble is used to accurately synchronize to the start point of the payload signal, the burst delimiter can adopt a code type of 66 bits (such as 01 1101 0110 0001 1111 0001 1011 0100 1000 0001 1011 0001 1010 00100111 11010101, and the actual code type is not limited to this), and by using a correlation function operation, a clear synchronization peak value can be obtained, and the point where the peak value is located can indicate the start point position of the payload. In addition, since the noise is random and almost has no correlation, when the bit error rate is relatively high, the burst delimiter can still be used to accurately synchronize to the start point of the Duo-Binary payload signal.

[0217] Finally, the same high-order modulation signal of the same baud rate can be directly equalized, decoded and processed by DSP without any switching, so as to realize the detection and processing of the uplink burst signal of the ONU by the OLT.

[0218] The waveform diagram of the 50Gb / s Duo-Binary system generated according to the uplink burst frame structure provided by the present application is shown in Figure 17 The waveform diagram contains a partial synchronization header, a burst delimiter and a partial Duo-Binary payload.

[0219] The experimental test results of the 50Gb / s Duo-Binary system show that the 50Gb / s Duo-Binary system designed according to the uplink burst frame structure provided by the present application has the effect of the clock synchronization (Square) method based on the feedforward full-sampling signal processing as described in the specific example 2, as shown in Figure 18 The horizontal coordinate in the diagram represents the number of symbols required for clock synchronization, and the vertical coordinate represents the phase of the clock signal under the condition of low signal-to-noise ratio (SNR). The circle and square represent two different clock phases. As can be seen from the diagram, 16 symbols are sufficient to extract the clock and effectively synchronize the clock and extract the signal by using the burst clock synchronization method and device provided by the present application. For the 50Gb / s Duo-Binary system, 100 symbols correspond to 2 nanoseconds, so the burst clock synchronization method and device provided by the present application can synchronize the clock and extract the signal in less than 1 nanosecond, which is simple and stable in performance. Figure 18 The performance of the clock synchronization (Square) method for the Duo-Binary PON system is shown in Figure 18 It can be seen that the clock synchronization provided by the present example can be completed in about 4 symbols, thereby having the characteristic of high synchronization rate.

[0220] In addition, the digital burst clock synchronization method and device provided by the present application can also be compatible with the NRZ system. For the NRZ system, the payload part in the frame structure design is designed as NRZ data, and the preamble also uses the same rate of NRZ code. The code type design idea of the synchronization header and the burst delimiter is the same as described in the specific embodiment five. The specific implementation process of the DSP method and system that can be used is the same as the above-described Duo-Binary system, and does not need to be more complex in system compatibility processing. The difference between this embodiment and the NRZ system based on the prior art is that the method provided by the present embodiment is a clock synchronization realized by DSP, which is stable in performance and simple; while the prior art is based on a digital hardware circuit, which is complex in structure, large in hardware size and high in power consumption.

[0221] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The described device embodiments are merely illustrative, for example, the division of the units is only a logical function division, and there can be another division manner for actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0222] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, can be located in one place or distributed on multiple network units; part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0223] In addition, each functional unit in each embodiment of the present application can be integrated into one processing module, or each unit can be separately implemented as a unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional unit.

[0224] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps including the above-mentioned method embodiments when executed.

[0225] The above is merely specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A burst frame transmission apparatus characterized by comprising: The method comprises: transmitting a burst frame, wherein the burst frame comprises a preamble and a payload; the preamble is modulated by using a first modulation format; the payload is modulated by using a second modulation format; the first modulation format and the second modulation format are different modulation formats, or the modulation orders of the first modulation format and the second modulation format are different; wherein the baud rate of the preamble is equal to the baud rate of the payload, the burst frame is used for obtaining a phase error by performing digital signal processing (DSP) on a synchronization header at a receiving end, performing clock synchronization based on the phase error, and performing DSP processing on the payload to reconstruct a signal.

2. The burst frame transmission apparatus of claim 1, wherein The order of the first modulation format is not higher than the order of the second modulation format.

3. The burst frame transmission device according to claim 2, wherein the first modulation format is a non-return-to-zero (NRZ) code modulation; the second modulation format is pulse amplitude modulation (PAM) or duobinary modulation.

4. The burst frame transmission device according to any one of claims 1 to 3, wherein the preamble further comprises a burst delimiter, which is used to indicate the starting position of the payload in the burst frame.

5. The burst frame transmission apparatus of claim 1, wherein The preamble comprises a synchronization header, and the synchronization header comprises a synchronization sequence, which is used for signal clock synchronization at the receiving end.

6. A burst frame transmission method characterized by comprising: The method comprises: transmitting a burst frame, wherein the burst frame comprises a preamble and a payload; the preamble is modulated by using a first modulation format; the payload is modulated by using a second modulation format; the first modulation format and the second modulation format are different modulation formats, or the modulation orders of the first modulation format and the second modulation format are different; wherein the baud rate of the preamble is equal to the baud rate of the payload; The method further comprises: performing digital signal processing (DSP) on a synchronization header to obtain a phase error, and performing clock synchronization based on the phase error; performing DSP processing on the payload to reconstruct a signal.

7. The transmission method of claim 6, wherein, The preamble comprises a synchronization header, and the synchronization header comprises a synchronization sequence; in the case where the burst frame is received at the receiving end, the performing of the DSP on the synchronization header to obtain the phase error and the performing of the clock synchronization based on the phase error comprise: receiving the burst frame; sampling the burst frame to obtain a sampling signal; extracting the synchronization header from the sampling signal; performing DSP on the synchronization header to obtain the phase error; performing clock synchronization based on the phase error.

8. A communication device, characterized by The apparatus comprises: a transceiver, a memory, a processor, and a computer program stored in the memory and executed by the processor; the processor is connected with the transceiver and the memory respectively, and is configured to execute the computer program, and is capable of implementing the burst frame transmission method provided in any one of claims 6 to 7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores the computer program; after the computer program is executed, the burst frame transmission method provided in any one of claims 6 to 7 can be implemented.

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