Low Dropout Regulators

Abstract

A low-dropout voltage regulator includes: a power supply voltage connection point; a load voltage output connection point; a load voltage output control circuit including a pass transistor; an adaptive bias circuit including a bias transistor; and an operational transconductance amplifier (OTA) circuit including a first OTA transistor and a second OTA transistor; and an adaptive compensation circuit including: (i) a first compensation capacitor, (ii) a second compensation capacitor, and (iii) a first compensation transistor, wherein a second electrode of the first compensation capacitor is coupled to a first region of the first compensation transistor, a first electrode of the second compensation capacitor is coupled to a second region and a gate region of the first compensation transistor, and a first region of the second OTA transistor is coupled to: (i) the power supply voltage connection point, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of the bias transistor. The second electrode of the second compensation capacitor is coupled to the first region of the bias transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of voltage regulators, and in particular, to the field of low dropout voltage regulators. Background Art

[0002] A voltage regulator can be used to provide a more stable power supply voltage. For example, a power supply such as a battery can be connected to a load to power the load. Due to changes in the characteristics of the power supply and the load, the power supply voltage provided to the load from the power supply may vary. Examples of these characteristics that may vary include: load impedance, temperature, the voltage output by the battery, the length of time the two have been connected, etc. For example, when a battery is almost discharged, the output voltage of the battery may be half of the output voltage of the battery when the battery is fully charged. A voltage regulator is designed to receive a power supply voltage from a power supply and provide a load voltage to a load, wherein the power supply voltage is expected to be relatively constant over time. It would be advantageous to provide an improved low dropout voltage regulator, wherein the load voltage from the regulator is more stable than the load voltage of previous low dropout voltage regulators, i.e., provides better load voltage regulation. Summary of the Invention

[0003] Various aspects of the disclosure are listed in the independent claims, with optional features listed in the dependent claims. Various aspects of the disclosure may be provided in combination with each other, and features of one aspect may be applied to other aspects.

[0004] In one aspect, a low-dropout regulator is provided, comprising: a supply voltage connection point for receiving a supply voltage; a load voltage output connection point for providing a load voltage to a load; a load voltage output control circuit comprising a pass transistor configured to adjust a load voltage based on a voltage at a gate region of the pass transistor; an adaptive bias circuit comprising: a bias transistor configured to adjust a voltage provided to a gate region of the pass transistor based on a voltage provided to the gate region of the bias transistor, and an operational transconductance amplifier (OTA) circuit comprising a first OTA transistor and a second OTA transistor, wherein the gate region of the first OTA transistor is arranged to receive a reference voltage and the gate region of the second OTA transistor is arranged to receive a voltage indicative of the load voltage; and an adaptive compensation circuit comprising: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to the first region of the first compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to the second region and the gate region of the first compensation transistor. A first region of the second OTA transistor is coupled to: (i) a supply voltage connection point, (ii) a first electrode of a first compensation capacitor, and (iii) a gate region of the bias transistor. A second electrode of the second compensation capacitor is coupled to the first region of the bias transistor.

[0005] Embodiments of the present disclosure enable the provision of an improved low-dropout regulator, as the low-dropout regulator of the present disclosure can have greater stability. That is, the low-dropout regulator of the present disclosure can enable the output pole (for the regulator transfer function) to be compensated (e.g., offset) by the zero point of the regulator. A low-dropout regulator with good phase margin under all operating conditions can be provided. A separate compensation capacitor can improve stability and good phase margin without affecting the DC operating conditions of the regulator.

[0006] The first region of the pass transistor can be coupled to a power supply voltage connection point, and the second region of the pass transistor can be coupled to a load voltage output connection point. The voltage regulator can also include a sensing circuit. The sensing circuit includes a sensing transistor, a gate region of the sensing transistor coupled to a gate region of the pass transistor, and a first region of the sensing transistor coupled to the power supply voltage connection point. The sensing circuit can include a first current mirror, the first current mirror coupled to the sensing transistor and the adaptive compensation circuit. The first current mirror can include a first mirror transistor, a first region of the first mirror transistor coupled to: (i) a first electrode of a second compensation capacitor, (ii) a gate region of the first compensation transistor, and (iii) a second region of the first compensation transistor. The first current mirror can include a first mirrored transistor. The second region of the sensing transistor can be coupled to: (i) a first region of the first mirrored transistor, (ii) a gate region of the first mirrored transistor, and (iii) a gate region of the first mirror transistor.

[0007] The adaptive compensation circuit may include a second compensation transistor. The first region of the first compensation transistor may be coupled to a power supply voltage connection point via the second compensation transistor. The first region of the second compensation transistor may be coupled to the power supply voltage connection point, and the second region of the second compensation transistor may be shorted to the gate region and coupled to the second electrode of the first compensation capacitor and the first region of the first compensation transistor. The adaptive compensation circuit may further include a compensation resistor disposed between the second electrode of the second compensation capacitor and the first region of the bias transistor.

[0008] The gate region of the pass transistor may be coupled to a power supply voltage connection point via one or more resistors. The first region of the bias transistor may be coupled to the power supply voltage connection point via the one or more resistors. The low-dropout regulator may further include a resistor transistor, the gate region of the resistor transistor being coupled to the gate region of the pass transistor, and the first region and second region of the resistor transistor being coupled to the power supply voltage connection point. At least one of the first region and the second region of the resistor transistor may be coupled to the power supply voltage connection point via one of the one or more resistors. The gate region and the second region of the resistor transistor are short-circuited. The first region of the bias transistor may be coupled to the second region of the resistor transistor.

[0009] The adaptive bias circuit may include a current buffer. The gate region of the bias transistor may be coupled to a power supply voltage connection point, a first electrode of a first compensation capacitor, and a first region of a second OTA transistor via the current buffer. The current buffer may include a first transistor, a first region of the first transistor being coupled to: (i) the power supply voltage connection point, (ii) the first electrode of the first compensation capacitor, and (iii) the first region of the second OTA transistor, and a second region of the first transistor being coupled to the gate region of the bias transistor. The current buffer may include a second transistor, a first region of the second transistor being coupled to the power supply voltage connection point and the first region of the first OTA transistor. The gate region of the first transistor of the current buffer may be coupled to the gate region of the second transistor of the current buffer. The second region of the second transistor of the current buffer may be coupled to the first electrode of a third compensation capacitor. The second electrode of the third compensation capacitor may be coupled to the load voltage output connection point. The voltage regulator may include a tail transistor. The second region of each of the first and second OTA regions may be coupled to the first region of the tail transistor. The gate region of the tail transistor may be arranged to receive the bias voltage.

[0010] The load voltage output connection point can be coupled to: (i) a coupling port for connecting the low-dropout regulator to a load, and (ii) a first electrode of an output capacitor. The second electrode of the output capacitor can be coupled to a reference voltage, such as ground. The low-dropout regulator can include a second current mirror. The second current mirror can be coupled to the current buffer and the gate region of the bias transistor. The second current mirror can also be coupled to the first electrode of a third compensation capacitor. The low-dropout regulator can include a controlled current source arranged to couple the power supply voltage connection point to the first region of a first OTA transistor and the first region of a second OTA transistor, the first electrode of the first compensation capacitor, and the gate region of the bias transistor. The controlled current source includes: a first transistor, the first region of the first transistor being coupled to the power supply voltage connection point, and the second region of the first transistor being coupled to the first region of the first OTA transistor; and a second transistor, the first region of the second transistor being coupled to the power supply voltage connection point, and the second region of the second transistor being coupled to the first electrode of the compensation capacitor, the first region of the second OTA transistor, and the gate region of the bias transistor. The gate region of the first transistor of the controlled current source can be coupled to the gate region of the second transistor of the controlled current source.

[0011] In another aspect, a circuit is provided that includes a load and a low-dropout regulator. The low-dropout regulator is coupled to the load and configured to regulate a load voltage provided to the load. The low-dropout regulator includes: a voltage input connection point for receiving a power supply voltage; a load voltage output circuit including a pass transistor, the pass transistor including a first region, a second region, and a gate region, wherein the second region of the pass transistor is coupled to the load, and wherein the pass transistor is configured to regulate the load voltage provided to the load based on a voltage at the gate region of the pass transistor; an adaptive bias circuit including: a bias transistor configured to regulate a voltage provided to the gate region of the pass transistor based on a voltage provided to the gate region of the bias transistor, and an operational transconductance amplifier (OTA) circuit including a first OTA transistor and a second OTA transistor, wherein the gate region of the first OTA transistor is arranged to receive a reference voltage, and the gate region of the second OTA transistor is arranged to receive a voltage indicative of the load voltage; and an adaptive compensation circuit including: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a compensation transistor. wherein a second electrode of the first compensation capacitor is coupled to the first region of the compensation transistor, and wherein a first electrode of the second compensation capacitor is coupled to the second region of the compensation transistor and a gate region of the compensation transistor. The first region of the second OTA transistor is coupled to: (i) a supply voltage connection point, (ii) a first electrode of the first compensation capacitor, and (iii) a gate region of the bias transistor. The second electrode of the second compensation capacitor is coupled to the first region of the bias transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Some examples of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0013] Figure 1 A schematic circuit diagram of an exemplary low dropout regulator is shown.

[0014] Figure 2 A schematic diagram illustrating the relationship between various components of an exemplary low dropout regulator is shown.

[0015] Figure 3 A schematic circuit diagram of an exemplary low dropout regulator is shown.

[0016] In the drawings, like reference numerals are used to denote like elements. DETAILED DESCRIPTION

[0017] Overview

[0018] Disclosed herein is an example of a low-dropout voltage regulator that includes an adaptive compensation circuit to provide a variable time constant for the operation of the regulator. The adaptive compensation circuit includes a first compensation capacitor and a second compensation capacitor separated by a first compensation resistor. A first region of a first compensation transistor is coupled to the first compensation capacitor, and a gate region and a second region of the first compensation transistor are both coupled to the second compensation capacitor. The disclosed regulator also includes a load voltage output control circuit for regulating a load voltage output from the regulator. An adaptive bias circuit is also included to control the operation of the voltage output control circuit. A sensing circuit is also included that can be used to change the time constant of the adaptive compensation circuit.

[0019] The load voltage output control circuit includes a pass transistor that varies the load voltage output from the regulator based on the voltage of its gate region. The adaptive bias circuit includes a bias transistor that varies the voltage of the pass transistor's gate region based on the voltage of its own gate region. If a higher voltage is applied to the bias transistor's gate region, more current will flow through the bias transistor and out of the pass transistor, thereby lowering the voltage at the pass transistor's gate region. This, in turn, causes more current to flow through the pass transistor, increasing the load voltage output by the regulator.

[0020] The adaptive bias circuit includes a voltage-controlled current source, such as a transconductance operational amplifier circuit. The voltage-controlled current source is arranged to receive a load voltage and control a current flowing through the voltage-controlled current source based on the load voltage. As the load voltage increases, the current flowing through the voltage-controlled current source also increases (and vice versa). The voltage-controlled current source is coupled to the gate region of the bias transistor such that the voltage at the gate region of the bias transistor will depend on the current flowing through the voltage-controlled current source and, therefore, on the load voltage. As more current flows through the voltage-controlled current source (in response to an increase in the load voltage), the voltage applied to the gate region of the bias transistor will decrease, thereby causing the voltage applied to the gate region of the pass transistor to decrease, and thus the load voltage output to also decrease.

[0021] A sensing circuit is arranged to control a current flowing through the adaptive compensation circuit. The sensing circuit includes a sensing transistor having a gate region coupled to a gate region of the pass transistor. Thus, the amount of current flowing through the sensing transistor will correspond to the amount of current flowing through the pass transistor. The sensing circuit is arranged to vary the current flowing through the adaptive compensation circuit based on the current flowing through the sensing transistor.

[0022] The adaptive compensation circuit is coupled to the adaptive bias circuit and the sensing circuit. A first compensation capacitor is coupled to a voltage-controlled current source and a gate region of a bias transistor. A second compensation capacitor is coupled to a first region of the bias transistor. The second compensation capacitor and the second region and gate region of the first compensation transistor are all coupled to the sensing circuit. The sensing circuit's control of current flowing through the adaptive compensation circuit in turn affects current flowing to the bias transistor, thereby changing the load voltage output by the voltage regulator.

[0023] This arrangement, in which the adaptive compensation circuit provides a variable time constant for the regulator, enables the regulator to achieve good phase margin under all operating conditions. The adaptive compensation circuit with discrete capacitors provides tracking of its associated zero without compromising the regulator's DC operation, as the regulator is configured to provide appropriate output pole tracking using the load voltage output control circuit and the adaptive bias circuit. Consequently, embodiments can provide a more stable low-dropout regulator.

[0024] Specific instructions

[0025] Now refer to Figure 1 An example of a low dropout voltage regulator is described. Figure 2 The function and operation of this low dropout voltage regulator are described and will be referred to later. Figure 3 Additional and alternative features of such a low dropout regulator are described.

[0026] Figure 1 A low dropout voltage regulator 100 is shown. The voltage regulator 100 includes an adaptive compensation circuit 130 including a first compensation capacitor 131 , a second compensation capacitor 132 , a first compensation transistor 133 , a compensation resistor 134 and a second compensation transistor 135 .

[0027] The voltage regulator 100 includes a circuit for receiving a power supply voltage V DD The voltage regulator 100 further includes a load voltage output control circuit 110 , which includes a load voltage output connection point 112 , a pass transistor 111 , a third compensation capacitor 113 , an output capacitor 114 , and a load coupling port 115 . Figure 1 The voltage regulator 100 also includes a first resistor 170 .

[0028] The voltage regulator 100 includes a sensing circuit 140 including a sensing transistor 141 and a first current mirror 145. The first current mirror 145 includes a first mirror transistor 146 and a first mirrored transistor 147.

[0029] The voltage regulator 100 includes an adaptive bias circuit. The adaptive bias circuit includes a voltage-controlled current source, shown as an operational transconductance amplifier (OTA) circuit 120. The OTA circuit 120 includes a first OTA transistor 121, a second OTA transistor 122, and a tail transistor 125. The adaptive bias circuit also includes a bias transistor 150 and a current buffer 160. The current buffer 160 includes a first transistor 161 and a second transistor 162. The adaptive bias circuit also includes a second current mirror 180, which includes a second mirror transistor 181 and a second mirrored transistor 182. The adaptive bias circuit also includes a controlled current source 190, which includes a first transistor 191 and a second transistor 192.

[0030] exist Figure 1 In the voltage regulator 100 , each transistor is a field effect transistor, such as a metal oxide semiconductor field effect transistor. Figure 1 All transistors in the transistor have a source connection point (identified by arrows) for connecting to the source region of the transistor, a drain connection point for connecting to the drain region of the transistor, and a gate connection point (between the source connection point and the drain connection point) for connecting to the gate region of the transistor. Figure 1 An N-channel transistor is shown with an arrow pointing away from its gate region. Figure 1 A P-channel transistor is shown with an arrow pointing from its source connection point to its gate region. Connection points between conductors are shown with black circles.

[0031] exist Figure 1 In the circuit shown, voltages are supplied to the circuit in three regions. These three voltages are the power supply voltage V DD , reference voltage V 参考 and bias voltage VN 偏置 . Power supply voltage V DD The power supply voltage V DD The components of the circuit are provided via a supply voltage connection point 101, which is coupled to the first resistor 170 and the source regions of each of the following transistors: the first transistor 191 and the second transistor 192 of the controlled current source 190, the second compensation transistor 135, the sense transistor 141, and the pass transistor 111. The gate connection point of the first OTA transistor 121 is arranged to receive a reference voltage. The gate connection point of the tail transistor 125 is arranged to receive a bias voltage.

[0032] Both the first OTA transistor 121 and the second OTA transistor 122 are N-channel transistors. The drain region of the first OTA transistor is coupled to the power supply voltage connection point 101 via the controlled current source transistor 191, and the drain region of the second OTA transistor is coupled to the power supply voltage connection point 101 via the controlled current source transistor 192. The source region of the first OTA transistor 121 is coupled to the source region of the second OTA transistor 122. The connection point between the source regions of the first OTA transistor 121 and the second OTA transistor 122 is coupled to the drain region of the tail transistor 125. The source region of the tail transistor 125 is coupled to ground.

[0033] The first OTA transistor 121 is coupled to the power supply voltage connection point 101 via the first transistor 191 of the controlled current source 190. The drain region of the first OTA transistor 121 is coupled to the drain region of the first transistor 191 of the controlled current source 190. The first transistor 191 and the second transistor 192 of the controlled current source 190 are both P-channel transistors. The source region of the first transistor 191 of the controlled current source 190 is coupled to the power supply voltage connection point 101, and the source region of the second transistor 192 of the controlled current source 190 is also coupled to the power supply voltage connection point 101. The gate region of the first transistor 191 of the controlled current source 190 is coupled to the gate region of the second transistor 192 of the controlled current source 190. The second OTA transistor 122 is coupled to the power supply voltage connection point 101 of the controlled current source 190 via the second transistor 192 of the controlled current source 190. The drain region of the second OTA transistor 122 is coupled to the drain region of the second transistor 192 of the controlled current source 190.

[0034] The first transistor 191 of the controlled current source 190 is also coupled to the current buffer 160. Specifically, the drain region of the first transistor 191 of the controlled current source 190 is coupled to the source region of the second transistor 162 of the current buffer 160. The first transistor 161 and the second transistor 162 of the current buffer 160 are both P-channel transistors. Since the first transistor 191 of the controlled current source 190 is also coupled to the first OTA transistor 121, the connection point between the first OTA transistor 121 and the first transistor 191 of the controlled current source 190 is coupled to the second transistor 162 of the current buffer 160. In other words, the conduction path starting from the drain region of the first transistor 191 of the controlled current source 190 splits into two paths: one path to the drain region of the first OTA transistor 121, and the other path to the source region of the second transistor 162 of the current buffer 160.

[0035] The second transistor 192 of the controlled current source 190 is also coupled to each of the current buffer 160, the compensation circuit 130, and the OTA circuit 120. Specifically, the drain region of the second transistor 192 of the controlled current source 190 is coupled to the first electrode of the first compensation capacitor 131, the source region of the first transistor 161 of the current buffer 160, and the drain region of the second OTA transistor 122. In other words, the conduction path starting from the drain region of the second transistor 192 of the controlled current source 190 is divided into three paths, a first path to the first electrode of the first compensation capacitor 131, a second path to the drain region of the second OTA transistor 122, and a third path to the source region of the first transistor 161 of the current buffer 160.

[0036] First transistor 161 of current buffer 160 is also coupled to each of bias transistor 150 and second current mirror 180. Specifically, the drain region of first transistor 161 of current buffer 160 is coupled to the drain region of second mirror transistor 181 and the gate region of bias transistor 150. Second mirror transistor 181 and second mirrored transistor 182 are both N-channel transistors. Bias transistor 150 is an N-channel transistor.

[0037] Second transistor 162 of current buffer 160 is also coupled to each of third compensation capacitor 113 and second current mirror 180. Specifically, the drain region of second transistor 162 of current buffer 160 is coupled to the first electrode of third compensation capacitor 113 and the drain region of second mirrored transistor 182 of second current mirror 180. The gate and drain regions of second mirrored transistor 182 are shorted together in the manner of a diode-connected transistor. The gate region of second mirrored transistor 182 and the gate region of second mirror transistor 181 are also interconnected. Thus, connections exist between second transistor 162 of current buffer 160, third compensation capacitor 113, the gate and drain regions of second mirrored transistor 182, and the gate region of second mirror transistor 181. The source region of each of second mirrored transistor 182 and second mirror transistor 181 is respectively coupled to ground.

[0038] Adaptive compensation circuit 130 is coupled to power supply voltage connection point 101. Specifically, a source region of second compensation transistor 135 is coupled to power supply voltage connection point 101. Second compensation transistor 135 comprises a P-channel transistor having a gate region and a drain region short-circuited. A second electrode of first compensation capacitor 131 is coupled to the connection point between the gate region and the drain region of second compensation transistor 135. First compensation transistor 133 comprises a P-channel transistor. The drain region and the gate region of second compensation transistor 135 and the second electrode of first compensation capacitor 131 are coupled to the source region of first compensation transistor 133. The gate region and the drain region of first compensation transistor 133 are coupled to each other (e.g., the gate region and the drain region of first compensation transistor 133 are diode-coupled). The second region and the gate region of first compensation transistor 133 are also coupled to the first electrode of second compensation capacitor 132. Therefore, the first compensation capacitor and the second compensation capacitor effectively represent a combined compensation capacitor separated across first compensation transistor 133.

[0039] The gate and drain regions of first compensation transistor 133 are also coupled to the drain region of first mirror transistor 146. First mirror transistor 146 and first mirrored transistor 147 of first current mirror 145 are both N-channel transistors. A second electrode of second compensation capacitor 132 is coupled to compensation resistor 134.

[0040] Bias transistor 150 is coupled to power supply voltage connection point 101 via first resistor 170. Specifically, the drain region of bias transistor 150 is coupled to each of compensation resistor 134, the gate region of sense transistor 141, the gate region of pass transistor 111, and first resistor 170. Pass transistor 111 and sense transistor 141 are both P-channel transistors. For example, pass transistor 111 and sense transistor 141 can be identical (for example, pass transistor 111 and sense transistor 141 can have the same width-to-length ratio). Power supply voltage connection point 101 is coupled to the gate region of pass transistor 111 and the gate region of sense transistor 141 via first resistor 170. In other words, there is a conduction path from power supply voltage connection point 101 through first resistor 170, where the path is divided into a path directed to the respective gate regions of each of sense transistor 141 and pass transistor 111, and a path directed to the drain region of bias transistor 150 and compensation resistor 134. The source region of bias transistor 150 is coupled to ground.

[0041] A source region of sense transistor 141 is coupled to power supply voltage connection point 101. A gate region of sense transistor 141 is coupled to a gate region of pass transistor 111. Sense transistor 141 is coupled to a first current mirror 145. A drain region of sense transistor 141 is coupled to a drain region and a gate region of a first mirrored transistor 147 of first current mirror 145 (the gate region and drain region of first mirrored transistor 147 are diode-shorted). A gate region of first mirrored transistor 147 and a gate region of first mirror transistor 146 are interconnected. A source region of each of first mirrored transistor 147 and first mirror transistor 146 is coupled to ground.

[0042] The source region of the pass transistor 111 is coupled to the power supply voltage connection point 101. The drain region of the pass transistor 111 is coupled to the load voltage output connection point. The load voltage output connection point 112 is coupled to the second electrode of the third compensation capacitor 113, the first electrode of the output capacitor 114, and the load 116. The output capacitor 114 is connected in parallel with the load 116. The voltage output connection point 112 is coupled to the load 116 via the coupling port 115. The second electrode of the output capacitor 114 is coupled to the ground. Figure 1 In the example shown, the second electrode of the output capacitor 114 is coupled to the output terminal of the load 116, and the connection point between the two is coupled to ground. Figure 1 Not explicitly shown, a coupling is provided between a gate region of the second OTA transistor 122 and the load voltage output connection point 112 for the second OTA transistor 122 to receive the load voltage or an indication of the load voltage.

[0043] The controlled current source 190 is configured to receive a power supply voltage V DD And provide a controlled current output. The transistor 191 and the transistor 192 of the controlled current source 190 are gate-coupled to provide a stable current output. The two transistors of the controlled current source 190 can be identical so that the current output from the drain region of each transistor is the same. The voltage regulator 100 is arranged so that the current output from the first transistor 191 of the controlled current source 190 can flow to each of the first OTA transistor 121 and the second transistor 162 of the current buffer 160. The voltage regulator 100 is arranged so that the current output from the second transistor 192 of the controlled current source 190 can flow to each of the first compensation capacitor 131, the second OTA transistor 122, and the first transistor 161 of the current buffer 160.

[0044] The reference voltage applied to the first OTA transistor 121 can be constant, for example, so that the amount of current drawn by the first OTA transistor 121 remains constant. The first OTA resistor is configured to draw an amount of current through its drain region that is proportional to the reference voltage applied to its gate region. Similarly, the second OTA resistor is configured to draw an amount of current through its drain region that is proportional to the voltage applied to its gate region, i.e., proportional to the load voltage. The second OTA resistor is configured to draw more current through its gate region as the load voltage increases and less current as the load voltage decreases. Thus, the voltage regulator 100 is arranged such that the current flow between the second transistor 192 of the controlled current source 190 and the first electrode of the first compensation capacitor 131, as well as the second transistor 162 of the current buffer 160, will vary with changes in the load voltage. Specifically, the voltage regulator 100 is arranged such that the current flowing from the second transistor 192 of the controlled current source 190 to the gate region of the bias transistor 150 will vary with changes in the current flowing through the second OTA transistor 122 (and therefore with changes in the load voltage). Tail transistor 125 may receive a constant bias voltage, for example, to provide a consistent current output (to ground).

[0045] The current buffer 160 is arranged as a common-gate current buffer 160 (the gates of the two transistors of the current buffer 160 are coupled to each other). The current buffer 160 is arranged to prevent components coupled to the output of the current buffer 160 (e.g., the second current mirror 180, the third compensation capacitor 113, and / or the bias transistor 150) from interfering with the operation of components coupled to the input of the current buffer 160 (e.g., preventing the output from loading the input). Thus, the current buffer 160 can be configured to prevent current flowing to the third compensation capacitor 113 / bias transistor 150 from interfering with current flowing to the first OTA transistor 121 / second OTA transistor 122.

[0046] The voltage at the gate region of the bias transistor 150 will depend on the amount of current drawn by the second OTA transistor 122. In other words, the voltage regulator 100 is arranged such that the voltage at the gate region of the bias transistor 150 will vary as the load voltage varies. For example, the voltage regulator 100 is arranged such that, if the load voltage increases, the voltage supplied to the gate region of the bias transistor 150 will decrease, and if the load voltage decreases, the voltage supplied to the gate region of the bias transistor 150 will increase.

[0047] Second current mirror 180 is configured such that the output current of second mirror transistor 181 (e.g., the source region of second mirror transistor 181) will correspond to the output current of second mirrored transistor 182. For example, the two transistors of second current mirror 180 can be identical (e.g., they can have the same width-to-length ratio). Therefore, the amount of current directed from first transistor 161 of current buffer 160 to the gate region of bias transistor 150 will also depend on the amount of current flowing through second mirrored transistor 182. This is because the amount of current flowing from first transistor 161 of current buffer 160 to second mirror transistor 181 will correspond to the amount of current flowing through second mirrored transistor 182. The amount of current flowing through second mirrored transistor 182 will also depend on the amount of current flowing into or out of the first electrode of third compensation capacitor 113.

[0048] The second compensation transistor 135 is configured to provide a unidirectional conduction path from the supply voltage connection point 101 to the source region of the first compensation transistor 133 and the second electrode of the first compensation capacitor 131. The adaptive compensation circuit 130 is arranged so that the current provided to the source region of the first compensation transistor 133 varies with the supply voltage V DD and the charge on the first compensation capacitor 131. For example, when the first compensation capacitor 131 is charging, that is, when the first electrode of the first compensation capacitor 131 is accumulating negative charge, the current flowing to the first compensation transistor 133 may increase, and / or when the first compensation capacitor 131 is discharging, the current flowing to the first compensation transistor 133 may decrease.

[0049] First compensation transistor 133 is configured to provide a conduction path to each of second compensation capacitor 132 and first mirror transistor 146 of first current mirror 145. Second compensation capacitor 132 is arranged to charge / discharge depending on the operating state of the mirror transistors. When the current flowing through first mirror transistor 146 increases, second compensation capacitor 132 will charge at a slower rate or begin to discharge / discharge at a faster rate because more current will be drawn to first mirror transistor 146 relative to the current drawn to the first electrode of second compensation capacitor 132. When the current flowing through first mirror transistor 146 decreases, the first electrode of second compensation capacitor 132 will accumulate more charge or lose charge at a slower rate. The magnitude and direction of the current flowing through compensation resistor 134 will depend on the state of second compensation capacitor 132, and therefore the operating state of first mirror transistor 146.

[0050] The compensation circuit 130 is arranged to provide a discrete capacitor. The compensation circuit 130 is arranged so that the discrete capacitors effectively act in series without affecting the DC operating conditions of the regulator 100. The compensation circuit 130 is arranged to compensate the output pole (wp2) of the regulator transfer function with the zero point (wz2) of the regulator transfer function. The compensation circuit 130 can be arranged to provide a variable time constant.

[0051] The first resistor 170 is arranged to provide a power supply voltage V DD and a voltage drop between the voltage supplied to the gate region of each of the sensing transistor 141 and the transfer transistor 111 .

[0052] The sensing circuit 140 is configured to regulate the current flowing out of the first compensation transistor 133 and the first plate of the second compensation capacitor 132 through the first current mirror 145. The sensing transistor 141 is configured to control the current flowing from the power supply voltage connection point 101 through the first current mirror 145 based on the voltage applied to its gate region. The sensing transistor 141 is configured so that when the voltage applied to the gate region of the sensing transistor 141 increases, the current flowing through the sensing transistor 141 to the first current mirror 145 decreases, and when the voltage applied to the gate region of the sensing transistor 141 decreases, the current flowing through the sensing transistor 141 to the first current mirror 145 increases. The sensing transistor 141 is configured to receive a power supply voltage V DD (eg, at the source connection point of the sense transistor 141 ), and selectively outputs current based on the voltage at the gate region of the sense transistor 141 . The sense transistor 141 provides a selective conduction path between the supply voltage connection point 101 and the first current mirror 145 .

[0053] First current mirror 145 is arranged so that the current flowing from first mirror transistor 146 corresponds to the current flowing from first mirrored transistor 147. First mirror transistor 146 can be identical to first mirrored transistor 147 (e.g., have the same width-to-length ratio), and the current flowing from first mirror transistor 146 and first mirrored transistor 147 can be the same. First mirrored transistor 147 is diode-shorted, so that the current flowing through sense transistor 141 to first current mirror 145 is connected to ground via first mirrored transistor 147. A corresponding current (or the same current if both transistors are identical) then flows through first mirror transistor 146. The current flowing through first mirror transistor 146 serves to reflect the current from sense transistor 141; for example, if the current flowing through sense transistor 141 increases, the current flowing through first mirror transistor 146 will also increase. The first mirror transistor 146 is configured to draw this current from the first compensation transistor 133, e.g., such that as the current flowing through the sense transistor 141 increases, more current is drawn from the drain region of the first compensation transistor 133 (and optionally, from the first electrode of the second compensation capacitor 132, or less current may be delivered from the first compensation transistor 133 to the first electrode).

[0054] Voltage regulator 100 is arranged so that the current flowing out of first compensation transistor 133 and the first plate of second compensation capacitor 132 depends on the voltage applied to the gate region of sense transistor 141. The voltage applied to the gate region of sense transistor 141 will correspond to the voltage applied to the gate region of pass transistor 111 (e.g., the voltage applied to the gate region of sense transistor 141 can be the same as the voltage applied to the gate region of pass transistor 111). Voltage regulator 100 is arranged so that the voltages applied to these gate regions depend on the operating state of adaptive compensation circuit 130 and the operating state of bias transistor 150. Current can flow toward or away from the connection point with adaptive compensation circuit 130. The magnitude and direction of this current will vary depending on the state of second compensation capacitor 132 (e.g., whether second compensation capacitor 132 is charging, charged, or discharging), which can vary depending on the magnitude of the current flowing through first mirror transistor 146.

[0055] The magnitude of the current flowing through the bias transistor 150 will vary depending on the voltage applied to the gate region of the bias transistor 150. The voltage regulator 100 is arranged so that the output of both the sense transistor and the pass transistor will vary depending on the voltage applied to the gate region of the bias transistor 150. The voltage applied to the gate region of the bias transistor 150 will vary depending on the operation of the second OTA transistor 122 (the magnitude of the current drawn by the second OTA transistor 122), and this operation of the second OTA transistor 122 will vary depending on the load voltage. Therefore, the voltage regulator 100 is configured to adjust the output of the pass transistor 111 (and therefore the load voltage) based on the load voltage. For example, the voltage regulator 100 is configured such that when the load voltage increases or begins to increase, the increase causes the pass transistor 111 to transmit less current, thereby reducing the load voltage (or preventing it from increasing). Similarly, when the load voltage decreases or begins to decrease, the decrease causes the pass transistor 111 to transmit more current, thereby increasing the load voltage (or preventing it from decreasing).

[0056] Pass transistor 111 provides a selective conduction path between supply voltage connection point 101 and load voltage output connection point 112. Conduction through this path from supply voltage connection point 101 to load voltage output connection point 112 will vary depending on changes in the voltage at the gate region of pass transistor 111 (and therefore, depending on the operating state of bias transistor 150 and / or adaptive compensation circuit 130). When the voltage at the gate region of pass transistor 111 increases, pass transistor 111 will draw less current, and when the voltage at the gate region decreases, pass transistor 111 will draw more current.

[0057] The load coupling port 115 is configured to provide a coupling for a load 116. In some examples, the load 116 can be included as part of the voltage regulator circuit, in which case the load coupling port 115 can effectively include a conductor coupled to the input terminal of the load 116. In other examples, the load 116 can be a component independent of the voltage regulator circuit, in which case the coupling port 115 can include an electrical coupling to enable the load 116 to be coupled to the voltage regulator 100 to receive the load voltage from the voltage regulator 100. The load coupling port 115 is arranged to transmit the load voltage to the load 116. The load voltage output control circuit 70 is configured to provide a regulated load voltage to the load 116. The charge on the second electrode of the third compensation capacitor 113 (and therefore the current flowing to / from the second electrode) will vary depending on the charge provided to the first electrode of the third compensation capacitor 113.

[0058] It should be understood that, in the context of the present disclosure, the characteristics of the voltage regulator 100 can be selected to provide a selected value of the load voltage. For example, the transistors, resistors, and / or capacitors of the circuit can be selected to provide relevant operating characteristics so that the load voltage reaches its expected value. The capacitance value of one or more capacitors can be selected based on the pole compensation that the capacitor is expected to be used for. For example, the capacitance value of each of the first compensation capacitor, the second compensation capacitor, and the third compensation capacitor 113 (as well as the resistance of the compensation resistor 134) can be selected to provide stability for the voltage regulator 100 over a range of load currents.

[0059] Now refer to Figure 2 The functionality of the exemplary voltage regulator 100 is described.

[0060] Figure 2 A block diagram illustrating the functional relationship between the various components of the voltage regulator 100 is shown. Figure 2 For each component in the diagram shown, an arrow leaving (eg, away from) the component indicates an output, and an arrow entering the component indicates an input, eg, indicating that the output of the component to which the arrow points may be affected by the input.

[0061] Figure 2 An adaptive bias circuit ("ABC" - for example, Figure 1 The OTA circuit 120, the bias transistor 150, the current buffer 160, the second current mirror 180 and the controlled current source 190 of the regulator 100 are provided), an adaptive compensation circuit ("ACC" - for example, Figure 1 The compensation circuit 130 of the voltage regulator 100 is provided), the load voltage output control circuit ("LVOCC" - for example, Figure 1 The output control circuit 110 and the first resistor 170 of the regulator 100 are provided), and the sensing circuit ("SC" - for example, Figure 1 The sensing circuit 140 and the first resistor 170 of the regulator 100 are provided).

[0062] Although not in Figure 2 As shown, but the power supply voltage V DD Provide to Figure 2 The components shown in (e.g., by Figure 1 The power supply voltage V DD can be provided to each of ABC, ACC, LVOCC, and SC. The operation of each of these components will depend at least in part on the supply voltage. In addition, as will be understood, the operation of each of these components will also depend on the operation of other components of the regulator 100.

[0063] The ABC (particularly the OTA circuit 120) also receives the load voltage as an input. The output of the OTA circuit (the current flowing through the second OTA transistor 122) will depend on the load voltage received by the OTA circuit, and therefore, the operation of the ABC will depend on the load voltage. This operation of the ABC will affect the current flowing to / from the first compensation capacitor 131 of the ACC (e.g., Figure 2 In addition, the current flowing through the second OTA transistor 132 of ABC will affect the voltage applied to the gate region of the bias transistor 150 of ABC. The voltage applied to the gate region of the bias transistor 150 will affect the current flowing to / from the compensation resistor 134 (as shown by the arrow in FIG. Figure 2 The voltage applied to the gate region of bias transistor 150 will also affect the operation of SC and LVOCC (as indicated by the arrows in FIG. Figure 2 This is because the voltage applied to the gate region of bias transistor 150 will affect the voltage applied to the gate region of sense transistor 141 of SC 140 and the voltage applied to the gate region of pass transistor 111 of LVOCC 110.

[0064] Specifically, if the load voltage increases, the second OTA transistor 122 of ABC will draw more current. Less current will be directed to the first compensation capacitor 131, and the gate voltage of the bias transistor 150 will decrease. This, in turn, will reduce the current flowing through the bias transistor 150 and, therefore, increase the voltage applied to the gate region of each of the sense transistor 141 and the pass transistor 111.

[0065] The operation of SC will affect the operation of ACC. Specifically, SC will affect the magnitude of the current flowing out of the first compensation transistor 133 and the second compensation capacitor 132 (e.g. Figure 2 As more current flows through the sense transistor 141 of the SC (e.g., in response to a decrease in the gate voltage of the sense transistor 141), the SC will cause more current to flow from the first compensation transistor 133 and the second compensation capacitor 132. This, in turn, will affect the current flowing to / from the second electrode of the second compensation capacitor 132 via the compensation resistor 134 (and therefore, also the voltage provided to the gate region of each of the sense transistor 141 and the pass transistor 111). Thus, the operation of the SC will affect the operation of the LVOCC (e.g., Figure 2 ).

[0066] Therefore, the operation of SC affects the current flowing out of the drain region of first compensation transistor 133. The operation of ABC affects the current flowing to and from first compensation capacitor 131 and compensation resistor 134. Depending on these inputs from ACC, the charge stored on the two capacitors will differ. These two capacitors act as if they were connected in series, so the total capacitance associated with ACC is the total capacitance of the two series-connected capacitors. First compensation transistor 133 is used to provide a variable resistance based on the operation of second compensation capacitor 132. The voltage associated with ACC then affects the voltage applied to the gate regions of each of sense transistor 141 and pass transistor 111.

[0067] To further illustrate the function of the voltage regulator 100, reference will now be made to Figure 1 Several examples of the operation of the voltage regulator 100 are described. It should be understood that in the context of the present disclosure, the low dropout voltage regulator 100 is self-regulating. The following operational examples are described as a series of events, but it should be understood that in practice, these events occur simultaneously when the voltage regulator 100 is self-regulating.

[0068] The voltage regulator 100 is configured to provide a stable voltage output. Therefore, examples of how the voltage regulator 100 reacts to increases and decreases in the load voltage output will be described. These examples refer to V DD The change of V causes the output voltage to increase / decrease. It should be understood that there are multiple connections to the supply voltage connection point 101. Therefore, the supply voltage V DD An increase or decrease in the output voltage will affect several different components simultaneously. However, for simplicity, the following description will be as if the events occurred in sequence, as this will help illustrate how self-regulation occurs. It should also be understood that there may be other reasons for the increase / decrease in the output voltage, such as depending on the load current drawn by the load.

[0069] At the power supply voltage V DDWhen the voltage applied to the source region of each of the pass transistor 111 and the sense transistor 141 increases, the voltage applied to the source region of each of the pass transistor 111 and the sense transistor 141 will also increase. The voltage applied to the first resistor 170 will also increase, and the corresponding voltage drop across the first resistor 170 will also increase. Conversely, the increase in voltage at the source region of each of the sense transistor 141 and the pass transistor 111 will be greater than the increase in voltage at the corresponding gate region of each of the sense transistor 141 and the pass transistor 111. As a result, the gate-source voltage of each of the pass transistor 111 and the sense transistor 141 will increase negatively, and the output of each transistor will increase. This will cause an increase in the load voltage and, therefore, an increase in the gate voltage of the second OTA transistor 122. As a result, the current flowing through the second OTA transistor 122 will increase, causing the voltage at the gate region of the bias transistor 150 to drop. Less current will then flow through the bias transistor 150, causing the voltage at the gate region of each of the pass transistor 111 and the sense transistor 141 to increase relative to their respective source voltages, thereby reducing the load voltage (e.g., returning to the expected value of the load voltage).

[0070] It should also be understood that during this regulation period, the sensing circuit 140 (including the first current mirror 145), the second current mirror 180, and the adaptive compensation circuit 130 may also be used for compensation operations of the regulator 100. The output of the sensing transistor 141 will correspond to the output of the pass transistor 111. Therefore, the first current mirror 145 will output a larger current and thus draw more current from the drain region of the first compensation transistor 133 and the first electrode of the second compensation capacitor 132. This may cause the second compensation capacitor 132 to discharge and thereby affect the voltage provided to the gate region of the sensing transistor 141 and the pass transistor 111. In response to the larger V DD , the second compensation transistor 135 and / or the first compensation capacitor 131 can operate to provide a larger input to the first compensation transistor 133. Furthermore, the operation of the third compensation capacitor 113 can also affect the current flowing through the second mirrored transistor 182. This, in turn, will also affect the current flowing through the second mirror transistor 181 and, therefore, the voltage at the gate region of the bias transistor 150.

[0071] At the power supply voltage V DD In the case of a decrease, the situation will be the opposite of the above. That is, the load voltage may decrease, which will cause the current flowing through the second OTA transistor 122 to decrease. As a result, the voltage at the gate region of the bias transistor 150 will be higher, and more current will flow through the bias transistor 150. This, in turn, will cause the gate voltage of the sense transistor and the pass transistor to decrease relative to their source voltage, thereby increasing the load voltage.

[0072] Embodiments may provide improved low dropout regulators. Specifically, embodiments may provide low dropout regulators with improved stability (e.g., good phase margin under all operating conditions). This may be apparent with reference to the poles and zeros of the regulator. Specifically, the output pole (wp2) may be compensated with the zero (wz2). For example, the equations for wp2 and wz2 may be derived as:

[0073] and

[0074] in,

[0075] It can be seen that in the wp2 equation, gm L Varies with load current. In the wz2 equation, gm MPC varies with the load, while all other parameters in the two equations do not change with the load current. Therefore, as in the above-mentioned regulator 100, by controlling CC2, (CC1_1||CC1_2) and RC, the regulator 100 can be stable over the entire load current range. By implementing CC1_1 and CC1_2 with separate compensation capacitors, the DC operating conditions of the regulator 100 can be unaffected while still providing this increased stability. Providing a current buffer 160 can prohibit the presence of a feedforward path, which can enable the zero point to be converted from the right half plane zero point to the left half plane zero point (for example, to facilitate pole cancellation). Additionally or alternatively, including the first compensation transistor 133 can facilitate this zero point conversion to the left half plane zero point.

[0076] Now refer to Figure 3 Additional and / or alternative features of a low dropout voltage regulator are described.

[0077] Figure 3 The arrangement is similar to Figure 1 The following description will focus on the following components that are different from the Figure 1 The voltage regulator 100 Figure 3 Features of the arrangement.

[0078] Figure 3 A voltage regulator 300 is shown. Figure 1 In addition to the components of the regulator 100, Figure 3 The voltage regulator 300 further includes a resistance component 370, which includes a drain resistor 371, a source resistor 372 and a resistance transistor 373. Figure 1 The voltage regulator is 100 different, Figure 3The voltage regulator 300 also includes a second current mirror component 380 and a load voltage output control circuit 310. The current mirror component 380 includes a first transistor 381, a second transistor 382, ​​a third transistor 383, and a fourth transistor 384. The output control circuit includes a first output resistor 3171, a second output resistor 3172, a third output resistor 3181, a first output transistor 3182, a current source 3191, and a second output transistor 3192.

[0079] The resistor assembly 370 is arranged to replace Figure 1 The first resistor 170 of the voltage regulator 100 is coupled to the first resistor 170 of the voltage regulator 100. A resistor transistor 373 is coupled to each of the power supply voltage connection point 301, the sense transistor 341, the pass transistor 311, the adaptive compensation circuit 330, and the bias transistor 350. The resistor transistor 373 is a P-channel transistor. The gate region of the resistor transistor is coupled to the gate region of the sense transistor 341 and the gate region of the pass transistor 311. The source region of the resistor transistor 373 is coupled to the power supply voltage connection point 301. The drain region of the resistor transistor 373 is coupled to the compensation resistor 334 (and therefore to the second electrode of the second compensation capacitor 332) and the drain region of the bias transistor 350. In addition, the drain region of the resistor transistor 373 is also coupled to the power supply voltage connection point 301. The source region of the resistor transistor 373 is coupled to the power supply voltage connection point 301 via the source resistor 372, and the drain region of the resistor transistor 373 is coupled to the power supply voltage connection point 301 via the drain resistor 371. The drain region and gate region of the resistor transistor 373 are coupled (to provide a diode-shorted transistor).

[0080] The gate region of the pass transistor 311 and the gate region of the sense transistor 341 are both coupled to the power supply voltage input connection point 301 via the resistance transistor 373. Specifically, the gate region of the sense transistor 341 and the gate region of the pass transistor 311 are coupled to the gate region and drain region of the resistance transistor 373, and the source region and drain region of the resistance transistor 373 are coupled to the power supply voltage connection point. The drain region of the bias transistor 350 and the compensation resistor 334 are both coupled to the gate region and drain region of the resistance transistor 373 (and therefore to the gate region of the sense transistor 341 and the gate region of the pass transistor 311).

[0081] The second current mirror component 380 includes transistors with a ratio Figure 1The second current mirror 180 of the voltage regulator 100 uses two more transistors. All transistors of the second current mirror component 380 are N-channel transistors. The second current mirror component 380 is coupled to the current buffer 360, the bias transistor 350 and the third compensation capacitor 313. Specifically, the drain region of the first transistor 381 of the second current mirror component 380 is coupled to the drain region of the second transistor 362 of the current buffer 360 and the first electrode of the third compensation capacitor 313. The drain region of the second transistor 382 of the second current mirror component 380 is coupled to the drain region of the first transistor 361 of the current buffer 360 and the gate region of the bias transistor 350. The drain region of the second transistor 382 of the second current mirror component 380 can also be coupled to the gate region of the second output transistor 3192 (as shown in FIG. Figure 3 shown).

[0082] The gate region of the first transistor 381 of the second current mirror component 380 is coupled to the gate region of the second transistor 382 of the second current mirror component 380. The source region of the first transistor 381 of the second current mirror component 380 is coupled to the drain region of the third transistor 383 of the second current mirror component 380. The source region of the second transistor 382 of the second current mirror component 380 is coupled to the drain region of the fourth transistor 384 of the second current mirror component 380. The gate region of the third transistor 383 of the second current mirror component 380 is coupled to the gate region of the fourth transistor 384 of the second current mirror component 380. The gate regions of the first transistor 381 and the second transistor 382 of the second current mirror component 380 are also coupled to the drain region of the first transistor 381 of the second current mirror component 380. The drain region of the first transistor 381 of the second current mirror component 380 may also be coupled to the gate regions of the third transistor 383 and the fourth transistor 384 of the second current mirror component 380 (e.g., the gate regions of all four transistors of the second current mirror component 380 may be interconnected).

[0083] The load voltage output connection point 312 is coupled (via a coupling port 315) to a load 316 and an output capacitor 314, which are arranged in parallel with each other. The load voltage output connection point 312 is also coupled to other components of the voltage output control circuit 310. For example, the load voltage output connection point is coupled to the first output resistor 3171 and, via the first output resistor 3171, to the second output resistor 3172. The load voltage output connection point is coupled to the third output resistor 3181 and, via the third output resistor 3181, to the first output transistor 3182. The load voltage output connection point is also coupled to the current source 3191 and, via the current source 3191, to the second output transistor 3192. Both the first output transistor 3182 and the second output transistor 3192 are N-channel transistors. The load voltage output connection point is coupled to the drain region of the first output transistor 3182 via the third resistor 3181. The drain region of the second output transistor 3192 is coupled to the load voltage output connection point via the current source 3191 and is also coupled to the gate region of the first output transistor 3182. The source region of each output transistor is respectively coupled to ground.

[0084] In addition, if Figure 3 As shown, the load voltage output connection point 312 is coupled to the gate region of the second OTA transistor 322. Specifically, a connection is provided from between the first output resistor 3171 and the second output resistor to the gate region of the second OTA transistor 322. The output control circuit 310 can be arranged to scale the voltage provided to the second OTA transistor 322, for example by providing a voltage divider so that the voltage provided to the second OTA transistor 322 is reduced relative to the load voltage. The amount of scaling (e.g., reduction) provided to the load voltage can be selected to control the maximum change in the operating conditions of the regulator 300, for example, to limit the maximum change in the voltage at the gate region of the pass transistor 311. For example, the values ​​of the first output resistor 3171 and the second output resistor 3172 can be selected accordingly.

[0085] It should be understood that in the context of the present disclosure, the embodiments described herein are examples of low dropout regulators of the present disclosure. However, these examples are not considered to be limiting. For example, it should be understood that the specific arrangement of transistors (and their respective channel arrangements) should not be considered to be limiting. For example, different arrangements of N / P channel transistors can be used to provide the desired functionality, and / or different (e.g., non-FET) transistors can be used. Similarly, the capacitors are shown with curled lines to indicate the stacking on the circuit board (e.g., the curled lines are the lower layer). However, other arrangements of these capacitors can be used. In some examples, the sensing circuit 140 and the feedback it enables can alternatively be provided by the transfer transistor 111 and the output control circuit 70. Alternatively, where the load voltage is used to regulate the second OTA transistor 122, an indication of the load voltage can be substituted, for example, this can come from the output of the sensing transistor 141.

[0086] In the examples described herein, resistors have been illustrated and discussed. However, in the context of this disclosure it should be understood that one or more of these resistors may have an effective resistance of zero. For example, in Figure 3 In FIG, the first resistor 3171 and the second resistor 3172 can be used to scale the voltage provided to the gate region of the second OTA transistor 322. However, one or more of these resistors may not provide a voltage drop (e.g., to control scaling or provide a single scaling). Similarly, one or both of the drain resistor 371 and the source resistor 372 may have no resistance.

[0087] It will be understood from the above discussion that the examples shown in the accompanying drawings are merely exemplary and include features that may be generalized, removed, or replaced as described herein and in the claims. With reference to the accompanying drawings as a whole, it will be understood that schematic functional block diagrams are used to indicate the functionality of the systems and devices described herein. However, it should be understood that the functionality is not necessarily divided in this manner and should not be construed to imply any particular hardware structure other than the hardware described and claimed below. The functionality of one or more elements shown in the accompanying drawings may be further subdivided and / or distributed throughout the apparatus of the present disclosure. In some examples, the functionality of one or more elements shown in the accompanying drawings may be integrated into a single functional unit.

[0088] As will be understood by readers of this art in the context of this disclosure, each example described herein can be implemented in a variety of different ways. Any feature of any aspect of the present disclosure can be combined with any other aspect of the present disclosure. For example, method aspects can be combined with device aspects, and features described with reference to the operation of specific elements of a device can be provided in a method that does not use those specific types of devices. In addition, each feature of each example can be separated from the features described in conjunction with it, unless it is explicitly stated that certain other features are necessary for its operation. Each of these separable features can of course be combined with any other feature of the example in which it is described, or combined with any other feature or combination of features of any other example described herein. In addition, equivalents and modifications not described above may also be adopted without departing from the present invention.

[0089] Other examples and variations of the present disclosure will be apparent to those skilled in the art in light of the context of this disclosure.

Claims

1. A low dropout voltage regulator, comprising: a power supply voltage connection point for receiving a power supply voltage; Load voltage output connection point, used to provide load voltage to the load; a load voltage output control circuit comprising a pass transistor configured to regulate the load voltage based on a voltage at a gate region of the pass transistor; Adaptive bias circuit, including: a bias transistor configured to adjust the voltage supplied to the gate region of the pass transistor based on a voltage supplied to the gate region of the bias transistor; and An operational transconductance amplifier (OTA) circuit includes a first OTA transistor and a second OTA transistor, wherein a gate region of the first OTA transistor is arranged to receive a reference voltage, and a gate region of the second OTA transistor arranged to receive a voltage indicative of the load voltage; and An adaptive compensation circuit comprising: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a first compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to a first region of the first compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to a second region and a gate region of the first compensation transistor; wherein the first region of the second OTA transistor is coupled to: (i) the supply voltage connection point, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of the bias transistor; and The second electrode of the second compensation capacitor is coupled to the first region of the bias transistor.

2. The low dropout voltage regulator according to claim 1, wherein: A first region of the pass transistor is coupled to the power supply voltage connection point, and a second region of the pass transistor is coupled to the load voltage output connection point.

3. The low dropout voltage regulator according to claim 2, further comprising a sensing circuit, wherein: The sensing circuit includes a sensing transistor having a gate region coupled to the gate region of the pass transistor and a first region coupled to the supply voltage connection point.

4. The low dropout voltage regulator according to claim 3, wherein: The sensing circuit includes a first current mirror coupled to the sensing transistor and the adaptive compensation circuit.

5. The low dropout voltage regulator according to claim 4, wherein: The first current mirror includes a first mirror transistor having a first region coupled to: (i) the first electrode of the second compensation capacitor, (ii) the gate region of the first compensation transistor, and (iii) the second region of the first compensation transistor.

6. The low dropout voltage regulator according to claim 5, wherein: The first current mirror includes a first mirrored transistor, and wherein the second region of the sensing transistor is coupled to: (i) a first region of the first mirrored transistor, (ii) a gate region of the first mirrored transistor, and (iii) a gate region of the first mirror transistor.

7. The low dropout voltage regulator according to any one of claims 1 to 6, wherein: The adaptive compensation circuit includes a second compensation transistor, and wherein the first region of the first compensation transistor is coupled to the supply voltage connection point via the second compensation transistor.

8. The low dropout voltage regulator according to claim 7, wherein: A first region of the second compensation transistor is coupled to the power supply voltage connection point, and a second region of the second compensation transistor is shorted to a gate region and coupled to the second electrode of the first compensation capacitor and the first region of the first compensation transistor.

9. The low dropout voltage regulator according to any one of claims 1 to 6, wherein: The adaptive compensation circuit further includes a compensation resistor disposed between the second electrode of the second compensation capacitor and the first region of the bias transistor.

10. The low dropout voltage regulator according to any one of claims 1 to 6, wherein: The gate region of the pass transistor is coupled to the supply voltage connection via one or more resistors.

11. The low dropout voltage regulator according to claim 10, wherein: The first region of the bias transistor is coupled to the supply voltage connection point via the one or more resistors.

12. The low dropout voltage regulator according to claim 10, wherein: The low-dropout regulator further comprises a resistance transistor having a gate region coupled to the gate region of the pass transistor, a first region and a second region of the resistance transistor coupled to the supply voltage connection point, and wherein at least one of the first region and the second region of the resistance transistor is coupled to the supply voltage connection point via one of the one or more resistors.

13. The low dropout voltage regulator according to claim 12, wherein: The gate region and the second region of the resistance transistor are short-circuited.

14. The low dropout voltage regulator according to claim 12, wherein: The first region of the bias transistor is coupled to the second region of the resistance transistor.

15. The low dropout voltage regulator according to any one of claims 1 to 6, wherein: The adaptive bias circuit includes a current buffer, and wherein the gate region of the bias transistor is coupled to the supply voltage connection point, the first electrode of the first compensation capacitor, and the first region of the second OTA transistor via the current buffer.

16. The low dropout voltage regulator according to claim 15, wherein: The current buffer includes a first transistor, a first region of the first transistor being coupled to: (i) the supply voltage connection point, (ii) the first electrode of the first compensation capacitor, and (iii) the first region of the second OTA transistor, and a second region of the first transistor being coupled to the gate region of the bias transistor.

17. The low dropout voltage regulator according to claim 16, wherein: The current buffer includes a second transistor having a first region coupled to the supply voltage connection point and a first region of the first OTA transistor.

18. The low dropout voltage regulator according to claim 17, wherein: A gate region of the first transistor of the current buffer is coupled to a gate region of the second transistor of the current buffer.

19. The low dropout voltage regulator according to claim 17, wherein: A second region of the second transistor of the current buffer is coupled to a first electrode of a third compensation capacitor, and wherein a second electrode of the third compensation capacitor is coupled to the load voltage output connection point.

20. The low dropout voltage regulator according to any one of claims 1 to 6, wherein: The load voltage output connection point is coupled to: (i) a coupling port for connecting the low dropout regulator to the load, and (ii) a first electrode of an output capacitor.

21. The low dropout voltage regulator according to claim 19, wherein: The low dropout regulator includes a second current mirror, and wherein the second current mirror is coupled to the current buffer and the gate region of the bias transistor.

22. The low dropout voltage regulator according to claim 21, wherein: The second current mirror is also coupled to the first electrode of the third compensation capacitor.

23. The low dropout voltage regulator according to any one of claims 1 to 6, wherein: The low dropout regulator comprises a controlled current source arranged to couple the supply voltage connection point to the first region of the first and second OTA transistors, the first electrode of the first compensation capacitor and the gate region of the bias transistor.

24. The low dropout voltage regulator according to claim 23, wherein: The controlled current source comprises: a first transistor, a first region of the first transistor being coupled to the supply voltage connection point, and a second region of the first transistor being coupled to the first region of the first OTA transistor; and a second transistor, a first region of the second transistor being coupled to the supply voltage connection point, and a second region of the second transistor being coupled to the first electrode of the first compensation capacitor, the first region of the second OTA transistor, and the gate region of the bias transistor; The gate region of the first transistor of the controlled current source is coupled to the gate region of the second transistor of the controlled current source.

25. The low dropout voltage regulator according to claim 20, wherein A second electrode of the output capacitor is coupled to a reference voltage.

26. The low dropout voltage regulator according to claim 20, wherein: A second electrode of the output capacitor is grounded.

27. A circuit comprising a load and a low dropout voltage regulator, wherein: The low dropout regulator is coupled to the load and configured to regulate a load voltage provided to the load; Wherein, the low voltage dropout regulator comprises: a power supply voltage connection point for receiving a power supply voltage; a load voltage output circuit comprising a pass transistor including a first region, a second region, and a gate region, wherein the second region of the pass transistor is coupled to the load, and wherein the pass transistor is configured to adjust the load voltage provided to the load based on a voltage at the gate region of the pass transistor; Adaptive bias circuit, including: a bias transistor configured to adjust the voltage supplied to the gate region of the pass transistor based on a voltage supplied to the gate region of the bias transistor; and An operational transconductance amplifier (OTA) circuit includes a first OTA transistor and a second OTA transistor, wherein a gate region of the first OTA transistor is arranged to receive a reference voltage, and a gate region of the second OTA transistor arranged to receive a voltage indicative of the load voltage; and An adaptive compensation circuit comprising: (i) a first compensation capacitor having a first electrode and a second electrode, (ii) a second compensation capacitor having a first electrode and a second electrode, and (iii) a compensation transistor, wherein the second electrode of the first compensation capacitor is coupled to a first region of the compensation transistor, and wherein the first electrode of the second compensation capacitor is coupled to a second region of the compensation transistor and a gate region of the compensation transistor; wherein the first region of the second OTA transistor is coupled to: (i) the supply voltage connection point, (ii) the first electrode of the first compensation capacitor, and (iii) the gate region of the bias transistor; and The second electrode of the second compensation capacitor is coupled to the first region of the bias transistor.

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