A high-density test chip super-speed measurement method and a test system thereof

Abstract

The application provides a high-density test chip super-speed measurement method, preset signals required for testing are written into a function generator and a source measurement unit; the function generator and the source measurement unit are controlled to generate synchronous trigger CLK signals and DF signals respectively, an address register connected with the function generator switches addresses according to waveform transformation of the CLK signals, the source measurement unit continuously samples different addresses according to the DF signal frequency, a plurality of sampling data corresponding to each address is determined, and effective measurement values corresponding to each signal address of the function generator are determined from the plurality of sampling data and are aligned. The super-speed test is realized by means of hardware synchronous triggering and cooperation of the SMU continuous sampling mode, each address is measured multiple times, data analysis is cooperated to realize alignment of the test address and the effective data, the test data misplacement problem can be avoided, and the test data stability is effectively improved. A test system with corresponding advantages is also provided.

Description

Technical Field

[0001] This invention belongs to the technical field of semiconductor design and manufacturing, and particularly relates to an ultra-high-speed measurement method and testing system for a high-density test chip. Background Technology

[0002] Traditional semiconductor manufacturing typically uses short-range test chips to assess defect rates and yields during production. These can be categorized into two types based on their placement within the wafer: stand-alone test chips (MPWs) and test chips placed in scribe lines. Stand-alone test chips are larger, occupying a chip's space, which means the semiconductor manufacturer must pay for the mask manufacturing cost for that area. Scribe lines, on the other hand, are spaces reserved on the wafer for chip dicing. Placing test chips in scribe lines eliminates the need for chip space, allowing semiconductor manufacturers to avoid the expensive mask costs and significantly reduce expenses.

[0003] Especially for ultra-high-density test chips, the objective requirement is for ultra-high-speed testing. Traditional testing methods require a huge amount of time to complete the test, which simply cannot meet practical needs. Currently, each module (test unit) contains tens of thousands to hundreds of thousands of test keys (test structures / test units), such as... Figure 1 As shown, address switching is achieved by switching the clock signal (CLK) port level (from low to high potential), thereby realizing the switching of the test key under test. Measurements are performed at ports such as DF to obtain the electrical parameters of the test key under test.

[0004] The existing testing method uses a conventional testing algorithm: a pulse is applied to the CLK, the DF is measured using the SMU, and this process is repeated until all test keys have been tested. This method is entirely controlled by algorithm commands, and each step involves hardware-software communication and hardware initialization, making the entire testing process very lengthy. For example, measuring a dense array module containing 327K test keys using this method would take approximately 5 days; moreover, it is prone to problems such as test data misalignment. Summary of the Invention

[0005] To achieve one, some, or all of the above-mentioned objectives, or other objectives, this invention provides, on one hand, an ultra-high-speed measurement method for high-density test chips. This method achieves ultra-high-speed testing through hardware triggering combined with continuous sampling by the SMU (System-Modulated Module). Hardware-software communication and initialization are performed only at the very beginning of the test, while the entire testing process is controlled by the hardware itself. This significantly improves testing efficiency and, combined with data analysis, ensures test data alignment, avoiding issues such as test data misalignment, effectively improving test data stability and optimizing the reliability of test results. On the other hand, this invention also provides a test system that supports synchronous triggering of the function generator and SMU, as well as continuous SMU sampling.

[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.

[0007] This invention provides an ultra-high-speed measurement method for high-density test chips. The test equipment includes a function generator, an address register connected to the function generator, and a source measurement unit. The ultra-high-speed measurement method includes the following steps:

[0008] The signals required for the preset test are written into the memory of the function generator and the source measurement unit accordingly;

[0009] The function generator and the source measurement unit are controlled to generate synchronously triggered CLK and DF signals respectively; the address register switches the address according to the waveform change in the CLK signal, triggering the source measurement unit to continuously sample different addresses according to the frequency of the DF signal;

[0010] Acquire sampling data and determine the valid measurement value corresponding to each address from the sampling data.

[0011] The sampling frequency of the source measurement unit for continuous sampling is set to a multiple of the address switching frequency; each address corresponds to one or more of the sampled data, and the effective measurement value corresponding to each address is obtained by analyzing the sampled data.

[0012] The ultra-high-speed measurement method is executed based on a preset test algorithm. The test algorithm presets the configuration information of the signal and controls the transmission of the trigger signal. The test equipment receives and transmits the trigger signal, and synchronously triggers the function generator and the source measurement unit.

[0013] The trigger signal includes the frequency parameter of the CLK signal and the sampling continuity time of the source measurement unit.

[0014] The test equipment is equipped with a programmable logic device, a synchronous trigger module, and a clock module. The programmable logic device acquires the trigger signal of the test algorithm and transmits it to the synchronous trigger module. The synchronous trigger module controls the function generator and the clock module to synchronously generate a CLK signal and a clock signal. The clock signal from the clock module is transmitted to the source measurement unit to generate a synchronous trigger DF signal.

[0015] The programmable logic device includes: Field Programmable Gate Array (FPGA).

[0016] The sampling data includes SO voltage and DF current. The method for determining the valid measurement value corresponding to each address from multiple sampling data points for each address includes:

[0017] The stable range in each address is determined by the SO voltage switching behavior;

[0018] Analyze the multiple DF currents to determine the effective measurement values ​​located within the stable interval of each address;

[0019] The analyzed valid measurement values ​​are assigned to each address.

[0020] The determination of the stable range in each address based on SO voltage switching includes:

[0021] Arrange the measured SO voltages in the order of measurement;

[0022] The voltage level of each SO voltage is determined sequentially based on the numerical relationship between the SO voltage and the operating voltage VDD.

[0023] The voltage level change of each SO voltage is determined based on the difference between the voltage level of the previous SO voltage and the voltage level of the previous SO voltage.

[0024] The effective measurement points belonging to the stable range are determined based on the voltage level changes of adjacent SO voltages.

[0025] The specific steps to determine the valid measurement points belonging to the stable interval are as follows:

[0026] If the voltage of SO does not change with the voltage of the adjacent SO points before and after it, then it is selected as a valid measurement point.

[0027] The methods for selecting valid measurement values ​​include:

[0028] Take the first current measurement value in the stable interval;

[0029] Take the average current of multiple DF currents in the stable interval;

[0030] Take the median of multiple DF currents in the stable interval.

[0031] Another technical solution of the present invention provides a test system, including a function generator, a source measurement unit, and a programmable logic device. The programmable logic device acquires the trigger signal of the test algorithm and transmits it to the function generator and the source measurement unit. The function generator and the source measurement unit are synchronously triggered to generate CLK signal and DF signal respectively. The address register connected to the function generator switches the address according to the CLK signal. The source measurement unit performs continuous sampling according to the synchronously triggered DF signal, and each address corresponds to multiple sampled data.

[0032] Another technical solution of the present invention provides a test system, including a function generator, a source measurement unit, a programmable logic device, a synchronous trigger module, and a clock module. The programmable logic device acquires the trigger signal of the test algorithm and transmits it to the synchronous trigger module. The synchronous trigger module controls the function generator and the clock module to synchronously generate clock signals of different frequencies. The address register connected to the function generator switches addresses according to the waveform changes in the clock signal. The clock signal of the clock module is transmitted to the source measurement unit to generate a synchronous trigger DF signal and perform continuous sampling. Each address corresponds to one or more sampled data.

[0033] The testing system includes a data processing software unit for determining the valid measurement value corresponding to each address from the sampled data.

[0034] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0035] This invention achieves parallel execution by decoupling address switching and source measurement unit testing through hardware synchronous triggering. Hardware-software communication and initialization are only performed at the very beginning of the test, eliminating the need for test algorithm reading and setting after each device under test (DUT) is measured and before the next DUT is measured. This eliminates the need for traditional communication steps, effectively improving test speed and reducing error rates. Specifically, the ultra-high-speed testing achieved through this method can reach speeds of 2K / sec, or even 40K / sec, representing a 100-4000 times improvement in testing efficiency compared to traditional methods.

[0036] This invention collects a large amount of data by continuously sampling multiple times within an address switching cycle using the source measurement unit. Subsequent data processing ensures that almost no test keys are missed and that stable measurement values ​​are obtained.

[0037] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This diagram illustrates the process of obtaining the electrical parameters of the test key in the prior art.

[0040] Figure 2 A schematic diagram of an ultra-high-speed measurement provided in an embodiment of this application is shown.

[0041] Figure 3 A schematic diagram of ultra-high-speed measurement of another integrated testing algorithm provided in an embodiment of this application is shown.

[0042] Figure 4 A schematic diagram of the signal timing triggering at the CLK / DF terminal provided in an embodiment of this application is shown.

[0043] Figure 5 A schematic diagram of the hardware configuration provided in an embodiment of this application is shown.

[0044] Figure 6 A schematic diagram illustrating the relevant signal input and hardware measurement behavior provided in the embodiments of this application is shown.

[0045] Figure 7 A schematic diagram showing the signal frequencies and sampling conditions provided in the embodiments of this application is shown.

[0046] Figure 8 A schematic diagram of the data processing results provided in an embodiment of this application is shown.

[0047] Figure 9 A schematic diagram of the test system provided in an embodiment of this application is shown. Detailed Implementation

[0048] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0049] It should be noted that the address register includes a scan data output signal (SO) output port. This port outputs the least significant bit of the address signal to confirm whether the DUT being tested is correct. The devices under test can form a DUT array. During testing, DUTs within the same DUT array are selected sequentially according to their addresses and tested one by one. Therefore, a DUT array contains all addresses for the total test duration.

[0050] An embodiment provides an ultra-high-speed measurement method for a high-density test chip, including a function generator and a source measurement unit (SMU) located in a test device. The function generator is connected to the CLK pad of the address register in the test chip via a probe card. The source measurement unit (SMU) is a measurement SMU connected to the test pads (i.e., the switching circuit terminals) DF and DL in the test chip via a probe card, thereby providing voltage and data testing for the test chip. Figure 2 As shown, it includes the following steps:

[0051] Step S1: Preset the signals required for the test and write them into the memory of the function generator and the source measurement unit. The preset signals can be PGU signals (CLK / clock signal) and SMU signals (DF signal / test signal), that is, the frequency at which the function generator performs waveform transformation for what time length, and the sampling rate at which the source measurement unit performs continuous sampling for what time length.

[0052] In step S2, the control function generator and the source measurement unit generate synchronously triggered CLK and DF signals respectively, that is, the signals at the CLK / DF terminals are triggered simultaneously in terms of timing. The address register switches the address according to the waveform change in the CLK signal received by its CLK pad, and triggers the source measurement unit to continuously sample different addresses according to the frequency of the DF signal.

[0053] Step S3: Obtain the sampling data and determine the valid measurement value corresponding to each address from the sampling data.

[0054] In some embodiments, the function generator is exemplary configured as a pulse generator (PGU), and the source measurement unit is configured as a measurement unit (SMU).

[0055] In some embodiments, such as Figure 3 As shown, this embodiment also provides a testing algorithm.

[0056] By pre-setting the configuration information of the signals required for testing the device under test in the test algorithm, the configuration information may include relevant information of the pulse generator PGU (CLK) signal and the source measurement unit SMU (DF) signal, such as: the operating voltage (VDD) of the pulse generator PGU and the source measurement unit SMU, the frequency (freq) of the PGU, the power line cycle of the source measurement unit SMU / the cycle of the sampling power supply (PLC), the sampling continuous time (seqtime), and other parameters, where the sampling continuous time (seqtime) determines the test duration.

[0057] After setting the PGU / SMU signals in the test algorithm, the corresponding information is written into the memory of the pulse generator PGU and the source measurement unit SMU. To start the test, a trigger signal is sent through the test algorithm. The test equipment receives and transmits the trigger signal to synchronously trigger the pulse generator PGU and the source measurement unit SMU, specifically by generating synchronous trigger CLK and DF signals. The signal timing at the CLK and DF terminals is as follows: Figure 4 As shown.

[0058] In some embodiments, the trigger signal may include the frequency parameter of the CLK signal and the sampling continuity time of the source measurement unit. Furthermore, to ensure that there are no issues with missed measurements of the device under test (DUT) or incorrect address data, the sampling rate of the source measurement unit (SMU) can be several times the frequency of the pulse generator (PGU). For example, if the frequency of the PGU (CLK) signal is set to f, then the source measurement unit (SMU) will perform measurements at a frequency of N×f, where N is a positive integer greater than or equal to 1.

[0059] In some embodiments, when N is 1, each test data point can be assigned to each address through data alignment analysis, avoiding test data misalignment issues in existing technologies. In other embodiments, when N is greater than 1, a stable interval can be determined from multiple test points corresponding to each address through data analysis. Then, the most accurate valid measurement value is determined from the test points within the stable interval and finally assigned to each address. This approach better and more comprehensively avoids the problems of test data misalignment and missed test keys in existing technologies.

[0060] In some embodiments, to achieve the technical objective of synchronous triggering, at the hardware configuration level, such as Figure 5As shown, the test equipment is also equipped with a programmable logic device (PLD). The output of the PLD is electrically connected to the function generator and the source measurement unit. The PLD acquires the trigger signal of the test algorithm and transmits it to the function generator and the source measurement unit, controlling the function generator to generate a CLK signal. At the same time, the PLD generates a clock signal, which is transmitted to the source measurement unit to generate a synchronously triggered DF signal and perform continuous sampling. This enables the synchronously triggered function generator and the source measurement unit to generate CLK and DF signals respectively. The address register connected to the function generator switches the address according to the CLK signal. The source measurement unit performs continuous sampling according to the synchronously triggered DF signal, with each address corresponding to multiple sampled data.

[0061] In some embodiments, to achieve the technical objective of synchronous triggering, at the hardware configuration level, such as Figure 5 As shown, the test equipment also includes a programmable logic device, a synchronous trigger module, and a clock module. The output of the programmable logic device is electrically connected to the input of the synchronous trigger module and the clock module. The synchronous trigger module includes two synchronous output ports. One synchronous output port is electrically connected to the function generator (FGen), and the other synchronous output port is electrically connected to the input of the clock module. The output of the clock module is electrically connected to the source measurement unit (SMU).

[0062] The programmable logic device (PLD) acquires the trigger signal of the test algorithm and transmits it to the synchronous trigger module. The synchronous trigger module controls the function generator and clock module to synchronously generate the CLK signal and clock signal. The clock signal from the clock module is transmitted to the source measurement unit (SMU). The SMU determines the DF signal (measurement signal) based on the clock signal for continuous sampling. The function generator (pulse generator PGU) inputs the clock signal (CLK) into the address register through the CLK pad for address switching. Each device in the test chip has a different address bit, which is matched with the address bit device in the test chip through the CLK signal. The test equipment continuously samples each address bit device through the source measurement unit (SMU). The test results are temporarily stored in the source measurement unit (SMU) or external memory. After the test, the test machine extracts all test data through the test algorithm and stores it in the database, and analyzes the test results through an online analysis engine.

[0063] In some embodiments, the programmable logic device can be a field-programmable gate array (FPGA), or other programmable logic devices, such as programmable array logic (PAL), generic array logic (GAL), etc. In the embodiments of this application, the programmable logic device is an FPGA.

[0064] In some embodiments, the sampling data may include SO voltage (output signal voltage) and DF current, and determining the valid measurement value corresponding to each address from multiple sampling data specifically includes:

[0065] The stable range in each address is determined by the SO voltage switching behavior;

[0066] Analyze multiple DF currents to determine the effective measurement values ​​within the stable range of each address;

[0067] The analyzed valid measurement values ​​are assigned to each address.

[0068] In some embodiments, determining the stable range in each address based on SO voltage switching further includes:

[0069] The measured SO voltages can be arranged in the order of measurement by arranging the SO voltages of all measurement points in a DUT array in the order of measurement.

[0070] The voltage level of each SO voltage is determined sequentially based on the numerical relationship between SO voltage and operating voltage VDD.

[0071] The voltage level change of each SO voltage is determined based on the difference between its voltage level and the previous SO voltage; valid measurement points belonging to the stable range are determined based on the voltage level changes of adjacent SO voltages. (Reference) Figure 7 As shown, for example, V12 and V13 are a measurement relationship before and after, where V12 is the SO voltage preceding V13.

[0072] In some embodiments, to more clearly illustrate the data processing procedure, a specific case will be described. The waveform input frequency of the CLK pad is set to f, and the source measurement unit (SMU) measures at a frequency of 5×f. Under synchronous triggering, as shown... Figure 6 As shown, the CLK pad triggers the address switching, and the source measurement unit (SMU) triggers the synchronous measurement of the voltage / current signals at the port.

[0073] Based on the corresponding frequency settings, the SO voltage at each address will be measured 5 times, and the current at each address's analog signal port (DFx) will be measured 5 times, resulting in the following: Figure 7 The signal frequency and sampling conditions are shown.

[0074] The most accurate current value within the stable range of the corresponding address will be selected from the 5 current measurements of DFx (In1~In5, n∈[1, last address number] and are integers). In addition, ADDR0 is measured before the signal is triggered and is not in the periodic measurement loop.

[0075] Specifically, the stable interval in each address is determined by the SO voltage switching situation, including the following steps:

[0076] Arrange the measured SO voltages in the measurement order. Optionally, all measurement points V(SO) within a DUT array can be arranged in the measurement order;

[0077] Add a parameter level for calculating the SO output voltage level. The parameter level is calculated by the following formula: level = if{V(SO) < Vdd / 2, 0:1} (Vdd is the operating voltage, and in the example, Vdd = 0.9), that is, when the SO voltage is less than half of the operating voltage, its parameter level is 0, otherwise it is 1;

[0078] Add a parameter transition indicating that the voltage level of level changes. The parameter transition is calculated by the following formula: transition = if{abs(level_(n + 1) - level_n) > 0, 1:0}, that is, calculate whether the absolute value of the difference between the parameter levels of the two consecutive SO voltages is greater than 0. If it is greater than 0, the parameter transition is 1, otherwise it is 0;

[0079] Add a parameter validmeasure indicating whether the measurement point is a valid measurement point within the stable interval. The parameter validmeasure is calculated by the following formula:

[0080] validmeasure = if{OR(transition_(n - 1) = 1, transition_n = 1, transition_(n + 1) = 1), 0:1}, that is, determine whether it is a valid measurement point within the stable interval by whether the parameters transition of the two adjacent SO voltages before and after are both 1. Only when all three parameters transition are 0 does it belong to the valid measurement point within the stable interval.

[0081] When a stable interval contains multiple valid measurement points, the ways to select one of the valid measurement values include:

[0082] Take the first current measurement value in the stable interval;

[0083] Take the average value of the currents of multiple DF currents in the stable interval;

[0084] Take the median of multiple DF currents in the stable interval.

[0085] Such as Figure 8As shown, the left side shows the specific details of the parameters level, transition, and validmeasure calculated after data processing. Then, the first current measurement value is selected from those with a validmeasure value of 1 and assigned as the valid measurement point to each address.

[0086] This embodiment also provides a testing system, in conjunction with reference. Figure 5 and 9 As shown, the system includes a database, an online analysis engine, a function generator (FGen), a switch matrix module (SWM), and at least six source measurement units (SMUs), which, together with an addressable test chip with a multi-purpose address register and probe cards, constitute a complete test system.

[0087] In the aforementioned test system, the first source measurement unit of the test instrument is connected to a probe card, which is connected to the addressable test chip via power pads VDD and VSS. The second source measurement unit is connected to a switch matrix (SWM), which is connected to a multi-purpose address register via input pads SE (shift enable signal) and SI (shift input signal). The multi-purpose address register is connected to the addressing circuit signal input terminal in the addressable test chip. The third source measurement unit is connected to the multi-purpose address register via input pad RST (reset signal), and the function generator (FGen) is connected to the multi-purpose address register via input pad CLK (clock signal). The fourth, fifth, and sixth source measurement units are connected to the probe card, which is connected to the switching circuit via pads DF, DL, GF, GL, SF, SL, and BF (signal lines of the device under test). The multi-purpose address register... The Register is connected to the Addressing Circuit via pads; the Online Analysis Engine is connected to the Database, Function Generator (FGen), and Measurement Source Measurement Unit.

[0088] Based on this, the test system in this embodiment also includes a programmable logic device (FPGA). The output of the FPGA is electrically connected to the function generator and the source measurement unit. The FPGA acquires the trigger signal of the test algorithm and transmits it to the function generator and the source measurement unit, controlling the function generator to generate a CLK signal. At the same time, the FPGA generates a clock signal, which is transmitted to the source measurement unit to generate a synchronously triggered DF signal and perform continuous sampling. This enables the synchronously triggered function generator and the source measurement unit to generate CLK and DF signals respectively. The address register connected to the function generator switches addresses according to the CLK signal, and the source measurement unit performs continuous sampling according to the synchronously triggered DF signal. Each address corresponds to one or more sampled data.

[0089] Based on this, in this embodiment, the test system preferably includes a programmable logic device (FPGA), a synchronous trigger module, and a clock module. The programmable logic device acquires the trigger signal of the test algorithm and transmits it to the synchronous trigger module. The synchronous trigger module controls the function generator and the clock module to synchronously generate clock signals of different frequencies. The multi-purpose address register (Address Register) connected to the function generator (FGen) switches addresses according to the waveform changes in the clock signal. The clock signal of the clock module is transmitted to the source measurement unit for continuous sampling according to the frequency of its clock signal, and each address corresponds to multiple sampled data.

[0090] The output of the programmable logic device is electrically connected to the input of the synchronous trigger module and the clock module. The synchronous trigger module contains two synchronous output ports, one of which is electrically connected to the function generator (FGen). The output of the clock module is electrically connected to the fourth source measurement unit (SMU).

[0091] The programmable logic device (PLD) acquires the trigger signal of the test algorithm and transmits it to the synchronous trigger module. The synchronous trigger module controls the function generator and clock module to synchronously generate the CLK signal and clock signal. The clock signal from the clock module is transmitted to the fourth source measurement unit (SMU). The SMU determines the DF signal (measurement signal) based on the clock signal for continuous sampling. The function generator (which can be a pulse generator PGU) inputs the clock signal (CLK) into the address register through the CLK pad for address switching. Each device in the test chip has a different address bit, which is matched with the device at each address bit in the test chip through the CLK signal. The test equipment continuously samples each device at each address bit through the fourth source measurement unit (SMU). The test results are temporarily stored in the fourth source measurement unit (SMU) or external memory. After the test, the test machine extracts all test data through the test algorithm and stores it in the database. The test results are analyzed by the online analysis engine / data processing software (which can be located in the online analysis engine) to determine the valid measurement value corresponding to each address from multiple sampled data.

[0092] Ultra-high-speed testing is achieved by using hardware synchronous triggering in conjunction with SMU continuous sampling. Only the hardware-software communication and hardware initialization steps are required at the very beginning of the test. During the test, the hardware is completely controlled by itself, which can greatly improve test efficiency and effectively improve the stability of test data.

[0093] The above description is merely a preferred embodiment of this specification and should not be construed as limiting the scope of the invention. All simple equivalent variations and modifications made according to the claims and specification of this invention are still within the scope of this patent. Furthermore, no embodiment or claim of this invention needs to achieve all the objectives, advantages, or features disclosed in this invention. In addition, the abstract and title are only used to assist in patent document retrieval and are not intended to limit the scope of the invention. Moreover, the terms "first," "second," etc., mentioned in this specification or claims are only used to name elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements.

Claims

1. A high-speed measurement method for a high-density test chip, wherein the test equipment is equipped with a function generator, an address register connected to the function generator, and a source measurement unit; characterized in that, The ultra-high-speed measurement method includes the following steps: The CLK and DF signals required for the test are preset and written into the memory of the function generator and the source measurement unit, respectively. The function generator and the source measurement unit are controlled to generate synchronously triggered CLK and DF signals respectively; the address register switches the address according to the waveform change in the CLK signal, triggering the source measurement unit to continuously sample different addresses according to the frequency of the DF signal; Acquire sampling data and determine the valid measurement value corresponding to each address from the sampling data.

2. The ultra-high-speed measurement method according to claim 1, characterized in that, The sampling frequency of the source measurement unit for continuous sampling is set to a multiple of the address switching frequency; each address corresponds to one or more of the sampled data, and the effective measurement value corresponding to each address is obtained by analyzing the sampled data.

3. The ultra-high-speed measurement method according to claim 2, characterized in that, The sampling frequency of the source measurement unit for continuous sampling is more than twice the address switching frequency.

4. The ultra-high-speed measurement method according to claim 1, characterized in that, The ultra-high-speed measurement method is executed based on a preset test algorithm. The test algorithm presets the configuration information of the signal and controls the transmission of the trigger signal. The test equipment receives and transmits the trigger signal, and synchronously triggers the function generator and the source measurement unit.

5. The ultra-high-speed measurement method according to claim 4, characterized in that, The trigger signal includes the frequency parameter of the CLK signal and the sampling continuity time of the source measurement unit.

6. The ultra-high-speed measurement method according to claim 4, characterized in that, The test equipment is equipped with a programmable logic device, a synchronous trigger module, and a clock module; the programmable logic device acquires the trigger signal of the test algorithm and transmits it to the synchronous trigger module; the synchronous trigger module controls the function generator and the clock module to synchronously generate a CLK signal and a clock signal; the clock signal of the clock module is transmitted to the source measurement unit to generate a synchronous trigger DF signal.

7. The ultra-high-speed measurement method according to claim 2, characterized in that, The sampling data includes SO voltage and DF current. The method for determining the valid measurement value corresponding to each address from multiple sampling data points for each address includes: The stable range in each address is determined by the SO voltage switching behavior; Analyze the multiple DF currents to determine the effective measurement values ​​located within the stable interval of each address; The analyzed valid measurement values ​​are assigned to each address.

8. The ultra-high-speed measurement method according to claim 7, characterized in that, The determination of the stable range in each address based on SO voltage switching includes: Arrange the measured SO voltages in the order of measurement; The voltage level of each SO voltage is determined sequentially based on the numerical relationship between the SO voltage and the operating voltage VDD; The voltage level change of each SO voltage is determined based on the difference between the voltage level of the previous SO voltage and the voltage level of the previous SO voltage. The effective measurement points belonging to the stable range are determined based on the voltage level changes of adjacent SO voltages.

9. The ultra-high-speed measurement method according to claim 8, characterized in that, The specific steps to determine the valid measurement points belonging to the stable interval are as follows: If the voltage level change of a given SO voltage and the adjacent SO voltages before and after it are both 0, then it is selected as a valid measurement point.

10. The ultra-high-speed measurement method according to claim 7, characterized in that, The methods for selecting valid measurement values ​​include: Take the first current measurement value in the stable interval; Take the average current of multiple DF currents in the stable interval; Take the median of multiple DF currents in the stable interval.

11. A testing system, characterized in that, It includes a function generator, a source measurement unit, a programmable logic device, a synchronous trigger module, and a clock module. The programmable logic device acquires the trigger signal of the test algorithm and transmits it to the synchronous trigger module. The synchronous trigger module controls the function generator and the clock module to synchronously generate clock signals of different frequencies. The address register connected to the function generator switches addresses according to the waveform changes in the clock signal. The clock signal from the clock module is transmitted to the source measurement unit to generate a synchronous trigger DF signal and perform continuous sampling. Each address corresponds to one or more sampled data.

12. The testing system according to claim 11, characterized in that, It includes a data processing software unit for determining the valid measurement value corresponding to each address from the sampled data.

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