LDO regulation circuit, power management chip and LDO regulation method

Abstract

The present application discloses an LDO regulation circuit, a power management chip, and an LDO regulation method. The LDO regulation circuit includes a power tube module, an error amplification module, a buffer, and a compensation module. The buffer is connected between the power supply terminal and the ground terminal. The input terminal of the buffer is connected to the amplified output terminal of the error amplification module, and the output terminal of the buffer is connected to the power tube module. The buffer is used to separate the main pole and the secondary pole. The main pole is set at the voltage output terminal, and the secondary pole is set at the amplified output terminal of the error amplification module. The compensation module is connected to the amplified output terminal of the error amplification module. The compensation module is used to adjust the pole frequency of the secondary pole according to the magnitude of the load current when the load current flowing through the power tube module is less than the current limiting threshold. In this design, the compensation module adjusts the pole frequency of the secondary pole according to the magnitude of the load current to keep the pole frequency of the secondary pole away from the pole frequency of the main pole, thereby improving the stability of the LDO loop.

Description

Technical Field

[0001] The present application relates to the technical field of low-voltage linear regulators, and in particular to an LDO regulation circuit, a power management chip, and an LDO regulation method. Background Art

[0002] LDO (Low Dropout Regulator) can work within the range of several hundred millivolts between the input voltage and the output voltage to perform linear voltage reduction.

[0003] LDOs are divided into two types: fully integrated and with off-chip capacitors. For LDOs with off-chip capacitors, the main pole position is usually set at the voltage output end, and the secondary point position is usually set at the output end of the error amplifier.

[0004] However, in related technologies, under heavy load conditions, the primary pole frequency of an LDO with external capacitors approaches the secondary pole frequency, resulting in poor stability. Improving the stability of the LDO by increasing the capacitance of the external capacitors reduces the loop bandwidth and increases costs. Therefore, effectively improving the stability of LDOs with external capacitors under heavy load conditions has become an urgent issue. Summary of the Invention

[0005] The embodiments of the present application provide an LDO regulation circuit, a power management chip, and an LDO regulation method, which can solve the problem of poor stability of LDOs with off-chip capacitors under heavy load conditions in the related art.

[0006] In a first aspect, an embodiment of the present application provides an LDO regulation circuit; the LDO regulation circuit includes a power tube module, an error amplification module, a buffer, and a compensation module, the power tube module is connected to the power supply end, the power tube module has a voltage output end, the voltage output end is used to connect an external load, the error amplification module is connected between the power supply end and the ground end, the buffer is connected between the power supply end and the ground end, the input end of the buffer is connected to the amplification output end of the error amplification module, the output end of the buffer is connected to the power tube module, the buffer is used to separate the main pole and the secondary pole, the main pole is set at the voltage output end, the secondary pole is set at the amplification output end of the error amplification module, the compensation module is connected to the amplification output end of the error amplification module, and the compensation module is used to adjust the pole frequency of the secondary pole according to the size of the load current when the load current flowing through the power tube module is less than the current limiting threshold.

[0007] Based on the LDO regulation circuit of the embodiment of the present application, when the load current flowing through the power tube module is large and less than the current limiting threshold, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current, so that the pole frequency of the secondary pole gradually moves away from the pole frequency of the main pole, thereby improving the stability of the LDO loop.

[0008] In a second aspect, an embodiment of the present application provides a power management chip, which includes the above-mentioned LDO regulation circuit.

[0009] Based on the power management chip in the embodiment of the present application, the power management chip has the above-mentioned LDO regulation circuit. When the load current flowing through the power tube module is large and less than the current limiting threshold, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current, so that the pole frequency of the secondary pole gradually moves away from the pole frequency of the main pole, thereby improving the stability of the LDO loop, thereby improving the working stability of the power management chip when the load current is too large.

[0010] In a third aspect, an embodiment of the present application provides an LDO regulation method, which is applied to the LDO regulation circuit of the first aspect and any one of its implementations. The LDO regulation method includes:

[0011] When the load current flowing through the power tube module is less than the current limiting threshold, the compensation module adjusts the pole frequency of the secondary pole according to the magnitude of the load current.

[0012] Based on the LDO regulation method in the embodiment of the present application, when the load current flowing through the power tube module is large and less than the current limiting threshold, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current, so that the pole frequency of the secondary pole gradually moves away from the pole frequency of the main pole, thereby improving the stability of the LDO loop.

[0013] In a fourth aspect, an embodiment of the present application provides a circuit board on which an off-chip capacitor and a power management chip are soldered, and the off-chip capacitor is connected to the voltage output terminal of the power management chip.

[0014] Based on the circuit board in the embodiment of the present application, the circuit board with the above-mentioned power management chip, when the load current flowing through the power tube module is large and less than the current limiting threshold, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current, so that the pole frequency of the secondary pole gradually moves away from the pole frequency of the main pole, thereby improving the stability of the LDO loop, thereby improving the working stability of the circuit board when the load current is too large.

[0015] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a housing and the above-mentioned circuit board. The housing has a receiving cavity, and the circuit board is arranged in the receiving cavity.

[0016] Based on the electronic device in the embodiment of the present application, the electronic device having the above-mentioned circuit board, when the load current flowing through the power tube module is large and less than the current limiting threshold, the compensation module can adjust the pole frequency of the secondary pole according to the magnitude of the load current, so that the pole frequency of the secondary pole gradually moves away from the pole frequency of the main pole, thereby improving the stability of the LDO loop, thereby improving the operating stability of the electronic device when the load current is too large. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a schematic diagram of the structural framework of an LDO regulation circuit in one embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of the structural framework of an LDO regulation circuit in another embodiment of the present application;

[0020] Figure 3 Schematic diagram of the circuit structure of an LDO regulation circuit in one embodiment of the present application;

[0021] Figure 4 for Figure 3 Schematic diagram of part of the circuit structure of the LDO regulation circuit;

[0022] Figure 5 Schematic diagram of the structural framework of an LDO regulation circuit in another embodiment of the present application;

[0023] Figure 6 This is a schematic diagram of the structural framework of an LDO regulation circuit in another embodiment of the present application;

[0024] Figure 7 for Figure 3 Schematic diagram of the circuit structure of the remaining part of the LDO regulation circuit;

[0025] Figure 8 This is a flow chart of an LDO regulation method in one embodiment of the present application.

[0026] Reference numerals: 10, power tube module; MP, first power tube; MS, second power tube; 20, error amplification module; EA, error amplifier; 21, current limiting element; Buffer, buffer; 30, compensation module; 40, current limiting module; 50, feedback module; R F1 , the first feedback resistor; RF2 , second feedback resistor; MP1, first PMOS transistor; MP2, second PMOS transistor; MP3, third PMOS transistor; MP4, fourth PMOS transistor; MP5, fifth PMOS transistor; MP6, sixth PMOS transistor; MP7, seventh PMOS transistor; MP8, eighth PMOS transistor; MP9, ninth PMOS transistor; MP10, tenth PMOS transistor; MP11, eleventh PMOS transistor; MP12, twelfth PMOS transistor; MN1, first NMOS transistor; MN2, second NMOS transistor; MN3, third NMOS transistor; MN4, fourth NMOS transistor; MN5, fifth NMOS transistor; MN6, sixth NMOS transistor; MN7, seventh NMOS transistor; MN8, eighth NMOS transistor; MN9, ninth NMOS transistor; MN10, tenth NMOS transistor; MN11, eleventh NMOS transistor; MN12, twelfth NMOS transistor; MN13, thirteenth NMOS transistor; R1, first resistor; R2, second resistor; R3, third resistor; C1, first capacitor; C L , external capacitor; R L , load resistance; R S , the first current limiting resistor; R EF , second current limiting resistor; COMP, comparator; L1, first node; L2, second node; L3, third node; L4, fourth node; L5, fifth node; V OUT , voltage output terminal; V ref , reference voltage; I D , current source; V DD , power supply terminal; GND, ground terminal; P1, main pole; P2, secondary pole; P3, another secondary pole. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0028] Please refer to Figure 1 As shown, the first aspect of the present application proposes an LDO regulation circuit, which can effectively improve the stability of the LDO loop.

[0029] The LDO regulation circuit includes a power tube module 10, an error amplification module 20, a buffer Buffer and a compensation module 30; the power tube module 10 is connected to the power supply terminal V DD The power tube module 10 has a voltage output terminal V OUT , voltage output terminal V OUT Used to connect external load; the error amplifier module 20 is connected to the power supply terminal V DDBetween the ground terminal GND; the buffer Buffer is connected to the power supply terminal V DD The input end of the buffer Buffer is connected to the amplified output end of the error amplifier module 20, and the output end of the buffer Buffer is connected to the power tube module 10. The buffer Buffer is used to separate the main pole P1 and the secondary pole P2. The main pole P1 is set at the voltage output terminal V OUT The secondary pole P2 is set at the amplification output end of the error amplification module 20; the compensation module 30 is connected to the amplification output end of the error amplification module 20, and the compensation module 30 is used to adjust the pole frequency of the secondary pole P2 according to the size of the load current when the load current flowing through the power tube module 10 is less than the current limiting threshold.

[0030] The following combination Figure 1-Figure 7 The specific circuit structure of the LDO regulation circuit is introduced in detail.

[0031] like Figure 1 As shown, the LDO regulation circuit includes a power tube module 10 , an error amplification module 20 , a buffer Buffer and a compensation module 30 .

[0032] The power tube module 10 serves as a circuit structure for connecting to an external load to provide an output voltage to the external load.

[0033] The power tube module 10 has a voltage input terminal and a voltage output terminal V OUT Among them, the "voltage input terminal of the power tube module 10" is the port in the power tube module 10 for input voltage access. The voltage input terminal of the power tube module 10 is connected to the power supply terminal V DD Connected to receive input voltage from an external power source. The voltage output terminal V OUT ” is a port in the power tube module 10 for outputting the output voltage. The voltage output terminal V OUT Used to connect an external load to provide output voltage to the external load.

[0034] The LDO regulation circuit further includes a feedback module 50 , which can generate a feedback voltage according to the output voltage.

[0035] One end of the feedback module 50 is connected to the voltage output terminal V OUT The other end of the feedback module 50 is connected to the ground terminal GND, that is, the feedback module 50 is connected in series with the power tube module 10 and connected to the power supply terminal V DD Between the ground terminal GND.

[0036] The feedback module 50 has a feedback output terminal, which is used to output a feedback voltage. Figure 2As shown, specifically, the feedback module 50 may include a first feedback resistor R F1 and the second feedback resistor R F2 , the first feedback resistor R F1 The first end of the power tube module 10 is connected to the voltage output terminal V OUT Connect the first feedback resistor R F1 The second end of the second feedback resistor R F2 The first end of the second feedback resistor R F2 The second end of the first feedback resistor R is connected to the ground terminal GND, and the first feedback resistor R F1 The second end of the second feedback resistor R F2 The node formed between the first end of the feedback resistor R F1 and the second feedback resistor R F2 The partial pressure on.

[0037] like Figure 1 As shown, the error amplification module 20 is used to amplify the above feedback voltage and the reference voltage V ref Compare and generate corresponding error signal. Error amplifier module 20 is connected to power supply terminal V DD and the ground terminal GND. The specific circuit structure of the error amplification module 20 will be described in detail below.

[0038] The error amplifying module 20 has a first amplifying input terminal, a second amplifying input terminal and an amplifying output terminal.

[0039] The first amplifier input terminal is used to connect to the reference voltage V ref The second amplifier input terminal is connected to the feedback output terminal to receive the feedback voltage. The error amplifier module 20 combines the feedback voltage with the reference voltage V ref An error signal is generated by comparison, and the error amplification module 20 amplifies the error signal, and the amplified error signal is output from the amplification output terminal.

[0040] The buffer Buffer can process the amplified error signal and transmit the processed error signal to the power tube module 10. The buffer Buffer is connected to the power supply terminal V DD Between the ground terminal GND.

[0041] The input end of the buffer Buffer is connected to the amplified output end of the error amplifier module 20 (and connected to the first node L1), and the output end of the buffer Buffer is connected to the power tube module 10. The amplified error signal enters the input end of the buffer Buffer, is processed by the buffer Buffer, and is output from the output end of the buffer Buffer and transmitted to the power tube module 10. The power tube module 10 adjusts the voltage output terminal V according to the error signal.OUT output voltage, thus forming a negative feedback loop.

[0042] Specifically, if Figure 3 As shown, the buffer Buffer may include a third resistor R3, an eleventh PMOS transistor MP11, and a twelfth PMOS transistor MP12; a first end of the third resistor R3 is connected to the power supply terminal VDD, a second end of the third resistor R3 is connected to the source of the eleventh PMOS transistor MP11, a drain of the eleventh PMOS transistor MP11 is connected to the ground terminal GND, and a gate of the eleventh PMOS transistor MP11 is connected to the first node L1 as an input end of the buffer Buffer; a drain of the twelfth PMOS transistor MP12 is short-circuited with the gate of the twelfth PMOS transistor MP12, and a source of the twelfth PMOS transistor MP12 is connected to the power supply terminal VDD. DD The drain of the twelfth PMOS transistor MP12 is connected to the second end of the third resistor R3; the gate of the twelfth PMOS transistor MP12 is connected to the gate of the first power transistor MP as the output end of the buffer Buffer.

[0043] The buffer is used to separate the main pole P1 and the secondary pole P2 of the LDO regulation circuit. The main pole P1 is set at the voltage output terminal V OUT , the secondary pole P2 is set at the amplification output end of the error amplification module 20.

[0044] It should be noted that the voltage output terminal V OUT As the main pole P1 of the LDO regulation circuit, when the load current flowing through the power tube module 10 is small, the pole frequency of the main pole P1 satisfies:

[0045] P1=1 / 2π(R F1 +R F2 ||R L )C L ------Formula 1

[0046] Among them, R L Represents the load resistance R L , C L Represents the off-chip capacitance C L .

[0047] In order to meet the low power consumption design requirements of the LDO regulation circuit, the designer will adjust the first feedback resistor R F1 and the second feedback resistor R F2 The resistance value is designed to be large. As the load current increases, the load resistance R L Gradually decreases. When the load current is too large, the load resistance R L will become very small, and the load resistance R L , the first feedback resistor RF1 and the second feedback resistor R F2 satisfy:

[0048] R F1 +R F2 >>R L ------Formula 2

[0049] Substituting the above "Formula 2" into the above "Formula 1", it can be simplified to:

[0050] P1'≈1 / 2πR L C L ------Formula 3

[0051] By comparing the above “Formula 1” and the above “Formula 3”, it can be concluded that when the load current is too large, the pole frequency of the main pole P1 will be pushed higher.

[0052] It is understandable that when the load current is too large and the pole frequency of the main pole P1 is pushed up, the pole frequency of the main pole P1 will gradually approach the pole frequency of the secondary pole P2. The proximity of the pole frequency of the main pole P1 to the pole frequency of the secondary pole P2 will reduce the stability of the LDO loop.

[0053] The compensation module 30 is a circuit structure for adjusting the pole frequency of the secondary pole P2 according to the magnitude of the load current. The compensation module 30 is connected to the amplification output terminal of the error amplification module 20. The specific circuit structure of the compensation module 30 will be described in detail below.

[0054] The compensation module 30 is a circuit structure for adjusting the pole frequency of the secondary pole P2 according to the magnitude of the load current when the load current flowing through the power tube module 10 is less than the current limit threshold, so that the pole frequency of the secondary pole P2 gradually moves away from the pole frequency of the main pole P1, thereby improving the stability of the LDO loop.

[0055] It should be noted that the specific value of the current-limit threshold is not limited here. The current-limit threshold is set according to the specific application conditions of the LDO regulation circuit, and designers can set different values ​​based on different application conditions. It is worth mentioning that when the load current flowing through the power tube module 10 is less than the current-limit threshold, the compensation module 30 adjusts the pole frequency of the secondary pole P2 according to the load current throughout the entire voltage loop operation process.

[0056] Based on the LDO regulation circuit in the embodiment of the present application, when the load current flowing through the power tube module 10 is large and less than the current limit threshold, the compensation module 30 can adjust the pole frequency of the secondary pole P2 according to the magnitude of the load current, so that the pole frequency of the secondary pole P2 gradually moves away from the pole frequency of the main pole P1, thereby improving the stability of the LDO loop. It is worth mentioning that at the voltage output terminal VOUT Connect the external capacitor C L When the external capacitor C L It can also improve the stability of the LDO loop, and the external capacitor C L The larger the capacity, the higher the stability of the LDO loop. Since the compensation module 30 in this application can also be used to improve the stability of the LDO loop, this application provides a voltage output terminal V OUT Connect the external capacitor C L The capacity is small (that is, the small external capacitor C L ), through the compensation module 30 and the voltage output terminal V OUT Connect a small off-chip capacitor C L The cooperation of the two ensures the stability of the LDO loop; compared with the related art, the voltage output terminal V OUT Connect a large-capacity off-chip capacitor C L In terms of L cost, and reduce the overall size of the power management chip.

[0057] Further, if Figure 3-Figure 4 As shown, it can be understood that E 总 =E1*E2*[gm*(R L ||R F1 +R F2 )], where E 总 is the total gain of the LDO loop, E1 is the gain of the error amplifier module 20, E2 is the gain of the buffer Buffer, gm is the transconductance of the first power tube MP (described below) of the power tube module 10, and R F1 +R F2 >>R L , so E 总 ≈E1*E2*(gm*R L Considering that when the load current is large, the load resistance RL is small, which leads to the total gain E of the LDO loop. 总 The total gain of the LDO loop, E 总 Although reducing can improve the stability of the LDO loop, the total gain E of the LDO loop 总The positive impact of the reduction is not enough to offset the negative impact of the reduction in the loop phase margin caused by the phase lag of the main pole P1 and the secondary pole P2, so the overall stability of the LDO loop will still be reduced. In order to enable the compensation module 30 to adjust the pole frequency of the secondary pole P2 according to the magnitude of the load current when the load current is large and less than the current limiting threshold, so that the pole frequency of the secondary pole P2 is far away from the pole frequency of the main pole P1, thereby improving the stability of the LDO loop. Therefore, in some embodiments, the compensation module 30 includes a first PMOS tube MP1 and a first resistor R1; the drain of the first PMOS tube MP1 is short-circuited with the gate of the first PMOS tube MP1, and the source of the first PMOS tube MP1 is connected to the power supply terminal V DD a first end of the first resistor R1 is connected to the drain of the first PMOS tube MP1, and a second end of the first resistor R1 is connected to the amplification output end of the error amplification module 20 (and connected to the first node L1).

[0058] It is understandable that the amplified output end of the error amplifying module 20 serves as the secondary pole P2 of the LDO regulating circuit. When the first PMOS transistor MP1 and the first resistor R1 are not designed, the pole frequency of the secondary pole P2 satisfies:

[0059] P2=1 / 2π(r on,MP3 ||r on,MN3 )C L1 ------Formula 4

[0060] Among them, r on,MP3 represents the small signal impedance of MP3 (a subcomponent of the error amplifier module 20, which will be introduced below), r on,MN3 represents the impedance of MN3 (another subcomponent of the error amplifier module 20, which will be introduced below), C L1 represents the parasitic capacitance of the first node L1.

[0061] According to the above "Formula 3" and "Formula 4", when the load current is too large and the pole frequency of the main pole P1 is pushed up, the pole frequency of the main pole P1 will gradually approach the pole frequency of the secondary pole P2 (that is, P1' ≈ P2). The proximity of the pole frequency of the main pole P1 and the pole frequency of the secondary pole P2 will reduce the stability of the LDO loop.

[0062] However, after designing the first PMOS transistor MP1 and the first resistor R1, the pole frequency of the secondary pole P2 satisfies:

[0063] P2=1 / 2π(r on,MP3 ||r on,MN3 ||(1 / g m,MP1 +R1))C L1 ------Formula 5

[0064] Among them, g m,MP1 represents the transconductance of the first PMOS transistor MP1, and R1 represents the first resistor R1.

[0065] It should be noted that in order to improve the stability of the LDO loop, the designer will make the impedance of MP3 much larger than the sum of the inverse of the transconductance of the first PMOS tube MP1 and the resistance of the first resistor R1 (that is, r on,MP3 >>(1 / g m,MP1 + R1); and the impedance of MN3 will be much greater than the sum of the inverse of the transconductance of the first PMOS tube MP1 and the resistance of the first resistor R1 (that is, r on,MN3 >>(1 / g m,MP1 +R1); therefore, the above “Formula 5” can be simplified to:

[0066] P2'=1 / 2π(1 / g m,MP1 +R1)C L1 ------Formula 6

[0067] By comparing the above "Formula 6" with the above "Formula 4", it can be concluded that when the load current is too large and less than the current limit threshold, the pole frequency of the secondary pole P2 is pushed up by the design of the first PMOS transistor MP1 and the first resistor R1, so that the pole frequency of the secondary pole P2 is far away from the pole frequency of the main pole P1, thereby effectively improving the stability of the LDO loop.

[0068] Further, if Figure 3-Figure 4 As shown, considering the total loop gain E 总 A decrease in the voltage at the output terminal V OUT The output accuracy is reduced, in order to increase the voltage output terminal V OUT Therefore, in some embodiments, the compensation module 30 further includes a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2; the source of the second PMOS transistor MP2 is connected to the power supply terminal V DD The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1; the drain of the first NMOS transistor MN1 is short-circuited with the gate of the first NMOS transistor MN1, the drain of the first NMOS transistor MN1 is connected to the drain of the second PMOS transistor MP2, and the source of the first NMOS transistor MN1 is connected to the ground terminal GND; the drain of the second NMOS transistor MN2 is connected to the amplification output terminal of the error amplification module 20 (and connected to the first node L1), the source of the second NMOS transistor MN2 is connected to the ground terminal GND, and the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1.

[0069] For ease of understanding, after designing the first PMOS tube MP1 and the first resistor R1, the voltage output terminal V OUT The reason for the decrease in output accuracy is that the specific circuit structure of the error amplifier module 20 is now described in detail. The error amplifier module 20 includes an error amplifier EA, which includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. The source of the third PMOS transistor MP3 is connected to the power supply terminal V DD The drain of the third PMOS transistor MP3 (i.e., the output terminal of the error amplifier EA) is connected to the first node L1 as the amplified output terminal of the error amplification module 20; the drain of the fourth PMOS transistor MP4 is short-circuited with the gate of the fourth PMOS transistor MP4, and the source of the fourth PMOS transistor MP4 is connected to the power supply terminal V DD The gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3; the source of the fifth PMOS tube MP5 is connected to the power supply terminal V DD The drain of the sixth PMOS tube MP6 is short-circuited with the gate of the sixth PMOS tube MP6, and the source of the sixth PMOS tube MP6 is short-circuited with the power supply terminal V DD The gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP5; the drain of the third NMOS transistor MN3 is connected to the first node L1, and the source of the third NMOS transistor MN3 is connected to the ground terminal GND; the drain of the fourth NMOS transistor MN4 is short-circuited with the gate of the fourth NMOS transistor MN4, the drain of the fourth NMOS transistor MN4 is connected to the drain of the sixth PMOS transistor MP6, the source of the fourth NMOS transistor MN4 is connected to the ground terminal GND, and the gate of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3; the drain of the fifth NMOS transistor MN5 is connected to the drain of the fourth PMOS transistor MP4, and the gate of the fifth NMOS transistor MN5 (i.e., the non-inverting input terminal of the error amplifier EA) serves as the second amplification input terminal of the error amplification module 20 and is connected to the feedback output terminal; the drain of the sixth NMOS transistor MN6 is connected to the drain of the fifth PMOS transistor MP5, and the gate of the sixth NMOS transistor MN6 (i.e., the inverting input terminal of the error amplifier EA) serves as the first amplification input terminal of the error amplification module 20 for receiving the reference voltage V ref The drain of the seventh NMOS transistor MN7 is connected to the source of the fifth NMOS transistor MN5 and the source of the sixth NMOS transistor MN6, and the source of the seventh NMOS transistor MN7 is connected to the ground terminal GND; the drain of the eighth NMOS transistor MN8 is short-circuited with the gate of the eighth NMOS transistor MN8, and the drain of the eighth NMOS transistor MN8 is connected to the power supply terminal VDD The source of the eighth NMOS transistor MN8 is connected to the ground terminal GND, and the gate of the eighth NMOS transistor MN8 is connected to the gate of the seventh NMOS transistor MN7.

[0070] It should be noted that, from Figure 4 As can be seen from FIG, since the fourth PMOS transistor MP4 and the third PMOS transistor MP3 form a current mirror, the current flowing through the fourth PMOS transistor MP4 is equal to the current flowing through the third PMOS transistor MP3 (ie, I MP4 =I MP3 Since the fifth NMOS tube MN5 and the fourth PMOS tube MP4 are on the same branch, the current flowing through the fifth NMOS tube MN5 is equal to the current flowing through the fourth PMOS tube MP4 (ie, I MN5 =I MP4 Since the fourth NMOS transistor MN4 and the third NMOS transistor MN3 form a current mirror, the current flowing through the fourth NMOS transistor MN4 is equal to the current flowing through the third NMOS transistor MN3 (that is, I MN4 =I MN3 Since the sixth PMOS tube MP6 and the fourth NMOS tube MN4 are on the same branch, the current flowing through the sixth PMOS tube MP6 is equal to the current flowing through the fourth NMOS tube MN4 (ie, I MP6 =I MN4 Since the fifth PMOS tube MP5 and the sixth PMOS tube MP6 form a current mirror, the current flowing through the fifth PMOS tube MP5 is equal to the current flowing through the sixth PMOS tube MP6 (ie, I MP5 =I MP6 Since the sixth NMOS tube MN6 and the fifth PMOS tube MP5 are on the same branch, the current flowing through the sixth NMOS tube MN6 is equal to the current flowing through the fifth PMOS tube MP5 (ie, I MN6 =I MP5 ).

[0071] Before the first PMOS transistor MP1 and the first resistor R1 are designed, for the secondary pole P2, the current flowing through the third PMOS transistor MP3 is equal to the current flowing through the third NMOS transistor MN3 (ie, I MP3 =I MN3 From the above analysis, it can be seen that when the current flowing through the third PMOS transistor MP3 is equal to the current flowing through the third NMOS transistor MN3, the current flowing through the fifth NMOS transistor MN5 is equal to the current flowing through the sixth NMOS transistor MN6 (that is, I MN5 =I MN6 ), the transconductance of the fifth NMOS transistor MN5 is equal to the transconductance of the sixth NMOS transistor MN6 (that is, g m,MN5 =g m,MN6), at this time, the gain of the LDO loop is stable, and the voltage output terminal V OUT The output accuracy is high.

[0072] After the first PMOS transistor MP1 and the first resistor R1 are designed, and before the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 are designed, for the secondary pole P2, the sum of the current flowing through the third PMOS transistor MP3 and the current flowing through the first PMOS transistor MP1 is equal to the current flowing through the third NMOS transistor MN3 (i.e., I MP3 +I MP1 =I MN3 ), since the current flowing through the first PMOS tube MP1 is not zero (ie I MP1 ≠0), so the current flowing through the third PMOS transistor MP3 is not equal to the current flowing through the third NMOS transistor MN3 (that is, I MP3 ≠I MN3 From the above analysis, it can be seen that when the current flowing through the third PMOS transistor MP3 is not equal to the current flowing through the third NMOS transistor MN3, the current flowing through the fifth NMOS transistor MN5 is not equal to the current flowing through the sixth NMOS transistor MN6 (that is, I MN5 ≠I MN6 ), the transconductance of the fifth NMOS transistor MN5 is not equal to the transconductance of the sixth NMOS transistor MN6 (that is, g m,MN5 ≠g m,MN6 ), at this time the gain of the LDO loop decreases, and the voltage output terminal V OUT The output accuracy is reduced.

[0073] After designing the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2, for the secondary pole P2, the sum of the current flowing through the first PMOS transistor MP1, the current flowing through the second PMOS transistor MP2, and the current flowing through the third PMOS transistor MP3 is equal to the sum of the current flowing through the first NMOS transistor MN1, the current flowing through the second NMOS transistor MN2, and the current flowing through the third NMOS transistor MN3 (that is, I MP1 +I MP2 +I MP3 =I MN1 +I MN2 +I MN3 By designing the second PMOS transistor MP2, the first NMOS transistor MN1 and the second NMOS transistor MN2, Figure 4 As can be seen from FIG, since the second PMOS transistor MP2 and the first PMOS transistor form a current mirror, the current flowing through the second PMOS transistor MP2 is equal to the current flowing through the first PMOS transistor MP1 (ie, I MP2 =I MP1Since the first NMOS tube MN1 and the second PMOS tube MP2 are on the same branch, the current flowing through the first NMOS tube MN1 is equal to the current flowing through the second PMOS tube MP2 (ie, I MN1 =I MP2 Since the second NMOS tube MN2 and the first NMOS tube MN1 form a current mirror, the current flowing through the second NMOS tube MN2 is equal to the current flowing through the first NMOS tube MN1 (ie, I MN2 =I MN1 ). At this point, it can be concluded that the current flowing through the third PMOS transistor MP3 is equal to the current flowing through the third NMOS transistor MN3 (that is, I MP3 =I MN3 ), from the above analysis, it can be seen that when the current flowing through the third PMOS transistor MP3 is equal to the current flowing through the third NMOS transistor MN3, the current flowing through the fifth NMOS transistor MN5 is equal to the current flowing through the sixth NMOS transistor MN6 (that is, I MN5 =I MN6 ), the transconductance of the fifth NMOS transistor MN5 is equal to the transconductance of the sixth NMOS transistor MN6 (that is, g m,MN5 =g m,MN6 ), at this time, the gain of the LDO loop is stable, and the voltage output terminal V OUT The output accuracy is improved.

[0074] Further, if Figure 3-Figure 4 As shown, due to the design of the second PMOS transistor MP2 and the first NMOS transistor MN1, another secondary pole P3 different from the aforementioned secondary pole P2 will appear in the compensation module 30. Due to the presence of this secondary pole P3, when the load current is too large and the pole frequency of the main pole P1 is pushed up, the pole frequency of the main pole P1 will gradually approach the pole frequency of the secondary pole P3, thereby reducing the stability of the LDO loop. To eliminate the problem of reduced stability of the LDO loop caused by the secondary pole P3, it is designed that in some embodiments, the compensation module 30 further includes a second resistor R2 and a first capacitor C1; the first end of the second resistor R2 is connected to the gate of the first NMOS transistor MN1, and the second end of the second resistor R2 is connected to the gate of the second NMOS transistor MN2; the first plate of the first capacitor C1 is connected to the gate of the second NMOS transistor MN2, and the second plate of the first capacitor C1 is connected to the ground terminal GND.

[0075] It can be understood that the node formed between the drain of the second PMOS transistor MP2 and the drain of the first NMOS transistor MN1 is the aforementioned other secondary pole P3, and the pole frequency of the other secondary pole P3 is:

[0076] P3=1 / 2π(1 / g m,MN1 ||r on,MP2)C1------Formula 7

[0077] Among them, r on,MP2 represents the impedance of the second PMOS tube MP2, g m,MN1 represents the transconductance of the first NMOS transistor MN1, and C1 represents the parasitic capacitance of the node formed between the drain of the second PMOS transistor MP2 and the drain of the first NMOS transistor MN1.

[0078] According to the above "Formula 3" and "Formula 7", when the load current is too large and the pole frequency of the main pole P1 is pushed up, the pole frequency of the main pole P1 will gradually approach the pole frequency of the other secondary pole P3 (that is, P1' ≈ P3). The proximity of the pole frequency of the main pole P1 and the pole frequency of the other secondary pole P3 will reduce the stability of the LDO loop.

[0079] However, after designing the second resistor R2 and the first capacitor C1, a zero point is introduced into the compensation module 30, and the pole frequency of the zero point is:

[0080] Z C =1 / 2πR2C1------Formula 8

[0081] Wherein, R2 represents the second resistor R2, and C1 represents the first capacitor C1.

[0082] According to the above "Formula 7" and "Formula 8", by adjusting the parameters R1 / C1 / g m,MN1 / r on,MP2 , so that Z C ≈P3, so that the zero point can eliminate the problem of reduced stability of the LDO loop caused by the other pole P3 mentioned above, so as to further improve the stability of the LDO loop.

[0083] like Figure 5 As shown, considering that when the load current is greater than the above-mentioned current limiting threshold, there is a possibility of burning out the LDO circuit itself and the subsequent circuit. In order to avoid damage to the LDO circuit itself and the subsequent circuit, it is necessary to limit the load current to a certain current when the load current is greater than the current limiting threshold to prevent the load current from continuing to increase. Therefore, in some embodiments, the LDO regulation circuit further includes a current limiting module 40, which is connected to the power supply terminal V DD , the error amplification module 20, and the power tube module 10 are connected. The current limiting module 40 is used to limit the load current to the current limiting threshold when the load current exceeds the current limiting threshold. In this design, by designing the current limiting module 40, the current limiting module 40 can limit the load current to the current limiting threshold when the load current exceeds the current limiting threshold, thereby effectively preventing damage to the LDO circuit itself and subsequent circuits.

[0084] Specifically, the power tube module 10 includes a first power tube MP and a second power tube MS; the first connection end of the first power tube MP is connected to the power supply end, and the second connection end of the first power tube MP is connected to the voltage output end V OUT The controlled terminal (gate) of the first power tube MP is connected to the output terminal of the buffer Buffer; the first connection terminal of the second power tube MS is connected to the current limiting module 40, and the second connection terminal of the second power tube MS is connected to the voltage output terminal V OUT The controlled end (gate) of the second power tube MS is connected to the controlled end of the first power tube MP.

[0085] Further, if Figure 6 As shown, when the load current is greater than the current limiting threshold, the current limiting module 40 can limit the load current to the current limiting threshold, so it is designed that in some embodiments, the error amplification module 20 also has an amplification controlled end; the current limiting module 40 includes a first current limiting resistor R S , the second current limiting resistor R EF and comparator COMP; first current limiting resistor R S The first end and the power supply terminal V DD Connect the first current limiting resistor R S and the first connection end of the second power tube MS (and connected to the second node L2); the second current limiting resistor R EF The first end and the power supply terminal V DD The positive input terminal of the comparator COMP is connected to the first connection terminal of the second power tube MS (and connected to the second node L2), and the negative input terminal of the comparator COMP is connected to the second current limiting resistor R EF The second end of the comparator COMP is connected to the amplified controlled end.

[0086] It is understandable that when the load current is greater than the current limiting threshold, the current limiting loop may work and the voltage loop may not work accordingly; or the current limiting loop and the voltage loop may work simultaneously.

[0087] Among them, when the current limiting loop is working and the voltage loop is not working, at this time, the error amplifier module 20 also has an amplification control terminal, and the error amplifier module 20 also includes a current limiting element 21; the inverting input terminal of the error amplifier EA is used as the first amplification input terminal to access the reference voltage V refThe non-inverting input terminal of the error amplifier EA serves as the second amplification input terminal and is used to access the feedback voltage. The output terminal of the error amplifier EA serves as the amplification output terminal and is connected to the input terminal of the buffer Buffer (and is connected to the first node L1). The first connection terminal of the current limiting element 21 is connected to the output terminal of the error amplifier EA, the second connection terminal of the current limiting element 21 is connected to the error amplifier EA (specifically, the drain of the third NMOS transistor MN3), and the controlled terminal of the current limiting element 21 serves as the amplification controlled terminal and is connected to the output terminal of the comparator COMP.

[0088] When the load current is less than the current limiting threshold, the current limiting element 21 is in the on state, at this time the voltage loop works and the current limiting loop does not work. The load current gradually increases, making the load resistance R L Gradually decreases, the pole frequency of the main pole P1 is gradually pushed up, and the compensation module 30 pushes up the pole frequency of the above-mentioned secondary pole P2 according to the load current, so that the pole frequency of the above-mentioned secondary pole P2 is far away from the pole frequency of the main pole P1, thereby ensuring the stability of the LDO loop.

[0089] When the overload current exceeds the current-limit threshold, current-limiting element 21 is in the off state. The voltage loop is inoperative, and the current-limiting loop is operative. Current-limiting element 21 regulates the error signal at the output of error amplifier EA and, through buffer Buffer, adjusts the gate voltages of first power transistor MP and second power transistor MS to limit the load current to the current-limit threshold, thereby achieving current limiting.

[0090] It should be noted that the current-limiting element 21 has both a current-limiting function and an on-off function similar to a switch. The on-off function of the current-limiting element 21 means that the current-limiting element 21 has an on state and an off state. The current-limiting element 21 is a transistor or a field-effect transistor. For example, when the current-limiting element 21 is specifically a transistor, the transistor's "on state" is when the transistor's collector and emitter are conductive, and conversely, the transistor's "off state" is when the transistor's collector and emitter are disconnected.

[0091] Specifically, if Figure 4 As shown, the current limiting element 21 is a thirteenth NMOS transistor MN13, the drain of the thirteenth NMOS transistor MN13 is connected to the first node L1, the source of the thirteenth NMOS transistor MN13 is connected to the drain of the third NMOS transistor MN3, and the gate of the thirteenth NMOS transistor MN13 is connected to the output end of the comparator COMP as an amplification controlled end.

[0092] It is worth mentioning that the current limiting loop utilizes load current sampling, so it does not cause large power consumption overhead. When the current limiting loop is working, the current limiting element 21 cuts off the voltage loop, which can improve the current limiting point accuracy and the stability of the current limiting loop.

[0093] When the current limiting loop and the voltage loop operate simultaneously, the main difference from the above-mentioned case where the current limiting loop and the voltage loop do not operate simultaneously lies in the different connection methods of the thirteenth NMOS transistor MN13 and the third NMOS transistor MN3. Specifically, the drain of the thirteenth NMOS transistor MN13 and the drain of the third NMOS transistor MN3 are connected to the first node L1, the source of the thirteenth NMOS transistor MN13 and the drain of the third NMOS transistor MN3 are connected to the ground terminal GND, and the gate of the thirteenth NMOS transistor MN13 is connected to the output terminal of the comparator COMP as an amplification controlled terminal. That is, the thirteenth NMOS transistor MN13 and the third NMOS transistor MN3 are connected in parallel.

[0094] like Figure 3 and Figure 7 As shown, when the load current is greater than the current limiting threshold, the current limiting loop works and the voltage loop does not work. To facilitate understanding of the current limiting principle of the current limiting module 40, the specific circuit structure of the current limiting module 40 is now introduced. The current limiting module 40 includes the above-mentioned first current limiting resistor R S , the second current limiting resistor R EF , the comparator COMP and the current source I D The comparator COMP includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12. The source of the seventh PMOS transistor MP7 is connected to the second node L2 as the inverting input terminal of the comparator COMP and the first connection terminal of the second power transistor MS. The drain of the seventh PMOS transistor MP7 is connected to the third node L3 as the output terminal of the comparator COMP and the gate of the thirteenth NMOS transistor MN13. The drain of the eighth PMOS transistor MP8 is short-circuited with the gate of the eighth PMOS transistor MP8. The source of the eighth PMOS transistor MP8 is connected to the source of the seventh PMOS transistor MP7. The gate of the eighth PMOS transistor MP8 is connected to the gate of the seventh PMOS transistor MP7. The source of the ninth PMOS transistor MP9 is connected to the second current limiting resistor R as the non-inverting input terminal of the comparator COMP. EFThe second end of the ninth PMOS transistor MP9 is connected to the fourth node L4, the drain of the ninth PMOS transistor MP9 is short-circuited with the gate of the ninth PMOS transistor MP9 and is connected to the fifth node L5 with the drain of the eighth PMOS transistor MP8; the source of the tenth PMOS transistor MP10 is connected to the source of the ninth PMOS transistor MP9, and the gate of the tenth PMOS transistor MP10 is connected to the gate of the ninth PMOS transistor MP9; the drain of the ninth NMOS transistor MN9 is connected to the third node L3, and the source of the ninth NMOS transistor MN9 is connected to the ground terminal GND; the drain of the tenth NMOS transistor MN10 is connected to the tenth NMOS transistor MN9. The gate of the tenth NMOS transistor MN10 is short-circuited, the drain of the tenth NMOS transistor MN10 is connected to the drain of the tenth PMOS transistor MP10, the source of the tenth NMOS transistor MN10 is connected to the ground terminal GND, and the gate of the tenth NMOS transistor MN10 is connected to the gate of the ninth NMOS transistor MN9; the drain of the eleventh NMOS transistor MN11 is connected to the fifth node L5, and the source of the eleventh NMOS transistor MN11 is connected to the ground terminal GND; the drain of the twelfth NMOS transistor MN12 is short-circuited to the gate of the twelfth NMOS transistor MN12, and the drain of the twelfth NMOS transistor MN12 is connected to the current source I D The negative electrode of the twelfth NMOS transistor MN12 is connected, the source of the twelfth NMOS transistor MN12 is connected to the ground terminal GND, and the gate of the twelfth NMOS transistor MN12 is connected to the gate of the eleventh NMOS transistor MN11; the current source I D The positive terminal and the power supply terminal V DD connect.

[0095] It should be noted that, from Figure 7 As can be seen from FIG, since the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 form a current mirror, the current flowing through the seventh PMOS transistor MP7 is equal to the current flowing through the eighth PMOS transistor MP8 (ie, I MP7 =I MP8 Since the ninth PMOS tube MP9 and the tenth PMOS tube MP10 form a current mirror, the current flowing through the ninth PMOS tube MP9 is equal to the current flowing through the tenth PMOS tube MP10 (ie, I MP9 =I MP10 Since the ninth NMOS tube MN9 and the tenth NMOS tube MN10 form a current mirror, the current flowing through the ninth NMOS tube MN9 is equal to the current flowing through the tenth NMOS tube MN10 (ie, I MN9 =I MN10 Since the ninth NMOS tube MN9 and the seventh PMOS tube MP7 are on the same branch, the current flowing through the ninth NMOS tube MN9 is equal to the current flowing through the seventh PMOS tube MP7 (ie, I MN9 =I MP7Since the tenth NMOS tube MN10 and the tenth PMOS tube MP10 are on the same branch, the current flowing through the tenth NMOS tube MN10 is equal to the current flowing through the tenth PMOS tube MP10 (ie, I MN10 =I MP10 Therefore, the sum of the current flowing through the eighth PMOS transistor MP8 and the current flowing through the ninth PMOS transistor MP9 is equal to the current flowing through the eleventh NMOS transistor MN11 (I MP8 +I MP9 =I MN11 =2*I MP8 ).

[0096] Since the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 form a current mirror, the current flowing through the eleventh NMOS transistor MN11 is equal to the current flowing through the twelfth NMOS transistor MN12 (ie, I MN11 =I MN12 Since the twelfth NMOS tube MN12 is connected in series with the current source ID, the current flowing through the twelfth NMOS tube MN12 is equal to the current of the current source ID (ie, I MN12 =I D ).

[0097] Since the sum of the current flowing through the ninth PMOS transistor MP9 and the current flowing through the tenth PMOS transistor MP10 is equal to the current flowing through the second current limiting resistor REF (ie, I MP9 +I MP10 =I REF ), so it flows through the second current limiting resistor R EF The current flowing through the eleventh NMOS transistor MN11, the current flowing through the twelfth NMOS transistor MN12, the current source I D The currents are equal (that is, I REF =I MN11 =I MN12 =I D ).

[0098] from Figure 7 It can be seen that the sum of the current flowing through the second power tube MS and the current flowing through the seventh PMOS tube MP7 is equal to the current flowing through the first current limiting resistor R S The current (also known as I MS =I MP7 +I RS ).

[0099] When the load current is less than the current limit threshold, the voltage loop works and the current limit loop does not work.

[0100] At this time, the first current limiting resistor R S The voltage across the two ends is less than the second current limiting resistor R EFThe voltage across the terminals (V RS <V REF ), the voltage of the second node L2 is greater than the voltage of the fourth node L4 (ie, V L2 >V L4 ), the voltage of the third node L3 is pulled high, so that the thirteenth NMOS transistor MN13 is in a conducting state. The thirteenth NMOS transistor MN13 is turned on, the voltage loop works normally, and the current limiting loop does not work.

[0101] When the load current is greater than the current limit threshold, the current limit loop works and the voltage loop does not work.

[0102] At this time, the first current limiting resistor R S The voltage across the two ends is greater than the second current limiting resistor R EF The voltage across the terminals (V RS >V REF ), the voltage of the second node L2 is less than the voltage of the fourth node L4 (ie, V L2 <V L4 ), the voltage of the third node L3 is pulled down, so that the thirteenth NMOS transistor MN13 is in the off state. The thirteenth NMOS transistor MN13 is turned off, the current limiting loop works normally, and the voltage loop does not work.

[0103] When the load current is greater than the current limit threshold, the current limit loop works and limits the load current to the current limit threshold I limit , and the current limiting threshold I limit is calculated as follows:

[0104] V L1 =V DD -V RS ------Formula 9

[0105] V L2 =V DD -V REF ------Formula 10

[0106] Among them, V RS =[I MN11 +I LOAD *N / (N+M)]*R S ------Formula 11

[0107] V REF =I MN11 *R EF ------Formula 12

[0108] Wherein, M is the width-to-length ratio of the second power tube MS, N is the sum of the width-to-length ratios of the first power tube MP and the second power tube MS, the size ratio of the seventh PMOS tube MP7 and the eighth PMOS tube MP8 is 1:1, and the size ratio of the ninth PMOS tube MP9 and the tenth PMOS tube MP10 is 1:1;

[0109] When V L1 =V L2 When there is a current limiting threshold I limit , at this time I LOAD =I limit , and because I MN11 =I MN12 =I D ------Formula 13

[0110] Therefore, after substituting the above "Formula 13" into the above "Formula 11" and the above "Formula 12", we can get:

[0111] I limit =I LOAD =I D *(R EF / R S -1)*(N / M)------Formula 14

[0112] The second aspect of the present application proposes a power management chip (not shown in the figure), which includes the above-mentioned LDO regulation circuit. In this design, when the load current flowing through the power tube module 10 is large and less than the current limit threshold, the compensation module 30 of the power management chip with the above-mentioned LDO regulation circuit can adjust the pole frequency of the secondary pole P2 according to the magnitude of the load current, so that the pole frequency of the secondary pole P2 gradually moves away from the pole frequency of the main pole P1, thereby improving the stability of the LDO loop, thereby improving the operating stability of the power management chip when the load current is too large.

[0113] Please refer to Figure 8 As shown, the third aspect of the present application proposes an LDO regulation method, which is applied to the above Figure 1-Figure 7 The LDO regulation circuit shown in FIG. 1 includes the following steps:

[0114] In step S202 , when the load current flowing through the power tube module 10 is less than the current limiting threshold, the compensation module 30 adjusts the pole frequency of the secondary pole P2 according to the magnitude of the load current.

[0115] Based on the LDO regulation method in the embodiment of the present application, when the load current flowing through the power tube module 10 is large and less than the current limiting threshold, the compensation module 30 can adjust the pole frequency of the secondary pole P2 according to the magnitude of the load current, so that the pole frequency of the secondary pole P2 gradually moves away from the pole frequency of the main pole P1, thereby improving the stability of the LDO loop.

[0116] The fourth aspect of the present application proposes a circuit board (not shown in the figure) on which an off-chip capacitor C is soldered. L And the above power management chip, and the off-chip capacitor C L The voltage output terminal V of the power management chip OUT In this design, when the load current flowing through the power tube module 10 of the circuit board with the above-mentioned power management chip is large but less than the current limit threshold, the compensation module 30 can adjust the pole frequency of the secondary pole P2 according to the magnitude of the load current, so that the pole frequency of the secondary pole P2 gradually moves away from the pole frequency of the main pole P1, thereby improving the stability of the LDO loop and thus improving the operating stability of the circuit board when the load current is too large.

[0117] The fifth aspect of the present application proposes an electronic device (not shown in the figure), which includes a shell and the above-mentioned circuit board, the shell having a receiving cavity, and the circuit board is arranged in the receiving cavity. The electronic device may include but is not limited to a mobile power supply, a charging plug, a balance car or a handheld electric drill, etc. In this design, the electronic device with the above-mentioned circuit board, when the load current flowing through the power tube module 10 is large and less than the current limiting threshold, the compensation module 30 can adjust the pole frequency of the secondary pole P2 according to the magnitude of the load current, so that the pole frequency of the secondary pole P2 gradually moves away from the pole frequency of the main pole P1, thereby improving the stability of the LDO loop, thereby improving the working stability of the electronic device when the load current is too large.

[0118] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of this application, it should be understood that if the terms "upper", "lower", "left", "right", etc. indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the drawings. This is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0119] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An LDO regulation circuit, characterized in that: include: The power tube module is connected to the power supply terminal and has a voltage output terminal, wherein the voltage output terminal is used to connect to an external load; an error amplification module, connected between the power supply terminal and the ground terminal; a buffer connected between the power supply terminal and the ground terminal, wherein the input terminal of the buffer is connected to the amplified output terminal of the error amplification module, and the output terminal of the buffer is connected to the power tube module, and the buffer is used to separate a main pole and a secondary pole, wherein the main pole is provided at the voltage output terminal, and the secondary pole is provided at the amplified output terminal of the error amplification module; a compensation module connected to the amplification output end of the error amplification module, and configured to adjust the pole frequency of the secondary pole according to the magnitude of the load current when the load current flowing through the power tube module is less than a current limiting threshold, so that the pole frequency of the secondary pole gradually moves away from the pole frequency of the main pole; The compensation module includes: a first PMOS transistor, wherein a drain of the first PMOS transistor is short-circuited with a gate of the first PMOS transistor, and a source of the first PMOS transistor is connected to the power supply terminal; a first resistor, wherein a first end of the first resistor is connected to the drain of the first PMOS transistor, and a second end of the first resistor is connected to the amplification output end of the error amplification module; a second PMOS transistor, wherein a source of the second PMOS transistor is connected to the power supply terminal, and a gate of the second PMOS transistor is connected to the gate of the first PMOS transistor; a first NMOS transistor, wherein the drain of the first NMOS transistor is short-circuited with the gate of the first NMOS transistor, the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor, and the source of the first NMOS transistor is connected to the ground terminal; a second NMOS transistor, wherein the drain of the second NMOS transistor is connected to the amplification output end of the error amplification module, the source of the second NMOS transistor is connected to the ground end, and the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor.

2. The LDO regulation circuit according to claim 1, wherein: The compensation module further includes: a second resistor, wherein a first end of the second resistor is connected to the gate of the first NMOS transistor, and a second end of the second resistor is connected to the gate of the second NMOS transistor; A first capacitor, wherein a first plate of the first capacitor is connected to the gate of the second NMOS transistor, and a second plate of the first capacitor is connected to the ground terminal.

3. The LDO regulation circuit according to claim 1 or 2, wherein: The LDO regulation circuit also includes a current limiting module; The current limiting module is connected to the power supply end, the error amplification module and the power tube module. The current limiting module is used to limit the load current to the current limiting threshold when the load current is greater than the current limiting threshold.

4. The LDO regulation circuit according to claim 3, wherein: The power tube module includes: a first power tube, wherein a first connection end of the first power tube is connected to the power supply end, a second connection end of the first power tube is connected to the voltage output end, and a controlled end of the first power tube is connected to the output end of the buffer; A second power tube, wherein the first connection end of the second power tube is connected to the current limiting module, the second connection end of the second power tube is connected to the voltage output end, and the controlled end of the second power tube is connected to the controlled end of the first power tube.

5. The LDO regulating circuit according to claim 4, wherein: The error amplification module has an amplification controlled end; the current limiting module includes: a first current limiting resistor, wherein a first end of the first current limiting resistor is connected to the power supply end, and a second end of the first current limiting resistor is connected to the first connection end of the second power tube; a second current limiting resistor, wherein a first end of the second current limiting resistor is connected to the power supply end; A comparator, wherein the non-inverting input terminal of the comparator is connected to the first connection terminal of the second power tube, the inverting input terminal of the comparator is connected to the second terminal of the second current limiting resistor, and the output terminal of the comparator is connected to the amplified controlled terminal.

6. The LDO regulating circuit according to claim 5, wherein: The error amplification module includes: an error amplifier, wherein the inverting input terminal of the error amplifier is used to access a reference voltage, the non-inverting input terminal of the error amplifier is used to access a feedback voltage, and the output terminal of the error amplifier is connected to the input terminal of the buffer as the amplified output terminal; A current limiting element, wherein a first connection end of the current limiting element is connected to the output end of the error amplifier, a second connection end of the current limiting element is connected to the error amplifier, and a controlled end of the current limiting element is connected to the output end of the comparator as the amplified controlled end.

7. A power management chip, characterized in that: include: The LDO regulation circuit according to any one of claims 1 to 6.

8. A LDO regulation method, characterized in that: Applied to the LDO regulation circuit according to any one of claims 1 to 6, the LDO regulation method comprising: When the load current flowing through the power tube module is less than the current limiting threshold, the compensation module adjusts the pole frequency of the secondary pole according to the magnitude of the load current.

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