Method for manufacturing a coreless substrate

Abstract

The present application relates to chip technology field, specifically a kind of coreless substrate manufacturing method.It is characterized in that: including the following steps: S1, laser slot is opened on substrate, and chip is buried in slot;S2, filling colloid;S3, laser hole is shot;S4, filling laser hole, while using 3D printing to print L1 circuit layer;S5, form L2 copper layer;S6, form L2 circuit layer;S7, form L3 copper layer;S8, punch in L3 copper layer;S9, form L3 circuit layer, and connect L1 circuit layer, L2 circuit layer, L3 circuit layer;S10, make solder resist layer and copper surface opening;S11, cutting.Compared with prior art, in chip is placed on the substrate of organic polymer resin, with the rigidity of organic resin bearing, the yield can be avoided to be influenced because of board warping during manufacturing process.3D printing technology and traditional coreless substrate manufacturing technology can shorten the manufacturing process of substrate, save cost and substrate manufacturing time, can improve the efficiency of substrate manufacturing.

Description

Technical Field

[0001] This invention relates to the field of chip technology, specifically a method for manufacturing a coreless substrate. Background Technology

[0002] Currently, integrated circuit packaging technology uses three bonding methods: wire bonding, flip chip bonding, and tape automatic bonding. Among these, wire bonding and tape automatic bonding are costly but have relatively simple process flows, making them suitable for packages with fewer pins. Flip chip bonding, on the other hand, has a more complex process flow and requires very strict control over the size, volume, shape, and adhesion of the solder balls on the pad. Furthermore, the alignment accuracy between the solder balls and the pads is becoming increasingly demanding, further increasing the difficulty.

[0003] The conventional manufacturing process for coreless substrates involves coating both sides of a carrier board with temporary bonding adhesive, then laminating electrolytic copper foil and dielectric layers layer by layer using lamination technology. After lamination, metal circuitry is fabricated using etching technology. Following the standard coreless substrate manufacturing process, after multi-layer circuitry is fabricated on both sides of the carrier board, two multi-layer coreless boards with identical circuit patterns on both sides are separated from the carrier board surface using mechanical tools, resulting in an ultra-thin substrate containing an ultra-thin copper foil layer and two or more circuit layers. Finally, the separated ultra-thin substrate undergoes subsequent etching, solder masking, and surface treatment processes to obtain the final coreless substrate product.

[0004] However, the current coreless substrate manufacturing process has the following drawbacks: 1. The coreless substrate manufacturing process is complex, lengthy, and costly; 2. The separated coreless substrate structure is an ultra-thin board without core support, which is not strong enough and is prone to deformation and warping, causing inconvenience during production and leading to board creases and breakage at various stations, affecting yield; 3. Although the existing technology avoids the risk of insufficient production capacity of coreless thin boards on the production line to some extent, there is still the problem of material waste; 4. At present, coreless substrates use chemical electroplating for hole filling, which may cause contamination and penetration of electroplating chemicals during the electroplating process, resulting in a decrease in substrate reliability. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this invention provides a method for manufacturing a coreless substrate, which combines 3D printing technology with traditional coreless substrate manufacturing processes, thereby shortening the thin substrate production process and reducing costs.

[0006] To achieve the above objectives, a method for manufacturing a coreless substrate is designed, characterized by the following steps:

[0007] S1, a groove is laser-cut on the substrate, and a chip is embedded in the groove with the metal layer and conductive pad of the chip facing upwards.

[0008] S2, Fill the area around the chip with colloid to fix the chip in place;

[0009] S3, a dielectric layer is laminated onto the chip, and laser-etched holes are drilled on the dielectric layer corresponding to the chip pad position to form a pad opening;

[0010] S4, use solder paste to fill the laser-etched holes to connect with the chip pad, and at the same time use 3D printing to print the L1 circuit layer on the dielectric layer.

[0011] S5, a temporary bonding adhesive layer is coated on both sides of the dielectric layer, and a thin copper foil is stacked on one side of the temporary bonding adhesive layer and laminated to form the L2 copper layer;

[0012] S6, perform lamination, exposure, development, electroplating, stripping, and etching on the L2 copper layer to form the L2 circuit layer;

[0013] S7. A temporary bonding adhesive layer is coated on the circuit pattern of the L2 circuit layer, and a dielectric layer and copper foil are stacked to form the L3 copper layer.

[0014] S8, laser drilling is performed on the L3 copper layer, and the bottom of the hole falls on the surface of the L1 circuit layer;

[0015] S9, copper lamination, electroless plating, stripping, and etching are performed on the L3 layer to form the L3 circuit layer. Copper plating is then used to fill the laser holes in step S8 using the MASP process to connect the L1, L2, and L3 circuit layers and form a circuit.

[0016] S10, a solder resist layer and a copper opening are made on one side of the L3 circuit layer by applying a single-sided pressure solder resist film;

[0017] S11, cut to form a single encapsulated package.

[0018] Steps S3 to S11 are replaced with the following steps:

[0019] S-3, a dielectric layer is laminated onto the chip;

[0020] S-4 uses 3D printing technology to print the L1 circuit layer on the dielectric layer;

[0021] S-5, a temporary bonding adhesive layer is coated on both sides of the dielectric layer, and a thin copper foil is stacked on one side of the temporary bonding adhesive layer and laminated to form the L2 copper layer;

[0022] S-6 involves laminating, exposing, developing, electroplating, stripping, and etching circuit patterns on the L2 copper layer to form the L2 circuit layer.

[0023] S-7, a temporary bonding adhesive layer is coated on the circuit pattern of the L2 circuit layer, and a dielectric layer and copper foil are stacked to form the L3 copper layer;

[0024] S-8, laser drilling is performed on the L3 copper layer. The bottom of hole one falls on the surface of the L1 circuit layer, and the bottom of hole two falls on the surface of the chip pad.

[0025] S-9, a copper pillar is printed in hole one using 3D printing technology to connect the L1 circuit layer and the L2 circuit layer. A copper pillar is printed in hole two using 3D printing technology to connect the L1 circuit layer and the chip pad.

[0026] S-10, the second hole is filled with polymer material using 3D printing technology;

[0027] S-11, 3D print the L3 circuit layer on the L3 copper layer, and fill the holes through the 3D printing process to make the circuits of the L1 circuit layer, L2 circuit layer and L3 circuit layer conductive, and finally etch the excess copper between the circuits.

[0028] S-12, a solder resist layer and copper opening are made on one side of the L3 circuit layer by applying a single-sided pressure solder resist film;

[0029] S-13, cut to form a single encapsulated package.

[0030] The 3D printing process is as follows: CuO powder is used as raw material. H2 generated by water electrolysis equipment reacts with CuO to produce Cu powder particles. The Cu powder particles are then processed by an ion fan and grinding tools to form micro-nano Cu powder particles. The temperature of the 3D printing equipment is set to 300~1500℃ and the pressure to 10~50MPa to print the Cu powder particles.

[0031] The particle size of the micro-nano-sized Cu powder particles is 5~35um.

[0032] The CuO particles are conveyed to the melting chamber of the 3D printing equipment by positive pressure blowing of Ar gas, so that the generated Cu powder particles become semi-solid under high pressure and high temperature laser conditions, thereby completing the circuit printing.

[0033] The CuO powder contains a binder.

[0034] The adhesive is a mixture of J-2012 type epoxy resin adhesive and inorganic filler, and the coefficient of thermal expansion (CTE) of the adhesive is 10~20ppm / K.

[0035] The inorganic filler used is BaSO4.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] 1. By placing the chip on a substrate of organic polymer resin, the rigidity of the organic resin can prevent the substrate from warping during the manufacturing process, which would affect the yield.

[0038] 2. The inner layer of the coreless substrate uses 3D printing technology, which can produce relatively wide (tens of micrometers) linewidths. The L1 circuit layer uses 3D printing technology, which can avoid the chip being affected by chemical penetration and contamination.

[0039] 3. Combining 3D printing technology with traditional coreless substrate manufacturing technology can shorten the substrate manufacturing process, save costs and substrate manufacturing time, and improve the efficiency of substrate manufacturing. Attached Figure Description

[0040] Figure 1 This is a flowchart of Embodiment 1 of the present invention.

[0041] Figure 2 This is a schematic diagram of step S1 in Embodiment 1 of the present invention.

[0042] Figure 3 This is a schematic diagram of step S2 in Embodiment 1 of the present invention.

[0043] Figure 4 This is a schematic diagram of step S3 in Embodiment 1 of the present invention.

[0044] Figure 5 This is a schematic diagram of step S4 in Embodiment 1 of the present invention.

[0045] Figure 6 This is a schematic diagram of step S5 in Embodiment 1 of the present invention.

[0046] Figure 7 This is a schematic diagram of step S6 in Embodiment 1 of the present invention.

[0047] Figure 8 This is a schematic diagram of step S7 in Embodiment 1 of the present invention.

[0048] Figure 9 This is a schematic diagram of step S8 in Embodiment 1 of the present invention.

[0049] Figure 10 This is a schematic diagram of step S9 in Embodiment 1 of the present invention.

[0050] Figure 11 This is a schematic diagram of step S10 in Embodiment 1 of the present invention.

[0051] Figure 12 This is a schematic diagram of step S11 in Embodiment 1 of the present invention.

[0052] Figure 13 This is a flowchart of Embodiment 2 of the present invention.

[0053] Figure 14 This is a schematic diagram of step S1 in Embodiment 1 of the present invention.

[0054] Figure 15 This is a schematic diagram of step S2 in Embodiment 1 of the present invention.

[0055] Figure 16 This is a schematic diagram of step S3 in Embodiment 1 of the present invention.

[0056] Figure 17 This is a schematic diagram of step S4 in Embodiment 1 of the present invention.

[0057] Figure 18 This is a schematic diagram of step S5 in Embodiment 1 of the present invention.

[0058] Figure 19 This is a schematic diagram of step S6 in Embodiment 1 of the present invention.

[0059] Figure 20 This is a schematic diagram of step S7 in Embodiment 1 of the present invention.

[0060] Figure 21 This is a schematic diagram of step S8 in Embodiment 1 of the present invention.

[0061] Figure 22 This is a schematic diagram of step S9 in Embodiment 1 of the present invention.

[0062] Figure 23 This is a schematic diagram of step S10 in Embodiment 1 of the present invention.

[0063] Figure 24 This is a schematic diagram of step S11 in Embodiment 1 of the present invention.

[0064] Figure 25 This is a schematic diagram of step S11 in Embodiment 1 of the present invention.

[0065] Figure 26 This is a schematic diagram of step S11 in Embodiment 1 of the present invention.

[0066] Figure 27 This is a schematic diagram of the 3D printing process of the present invention. Detailed Implementation

[0067] The present invention will now be further described with reference to the accompanying drawings.

[0068] Example 1:

[0069] like Figures 1 to 12 As shown, this embodiment provides a method for manufacturing a coreless substrate, including the following steps:

[0070] S1, a groove is laser-cut on substrate 1, and chip 2 is embedded in the groove, with the metal layer and conductive pad 21 of chip 2 facing upwards.

[0071] S2, fill the area around chip 2 with colloid 3 to fix chip 2;

[0072] S3, press the dielectric layer 4 onto the chip 2, and drill a laser hole on the dielectric layer 4 corresponding to the position of chip pad 21 to form a pad opening;

[0073] S4, use solder paste 51 to fill the laser-etched holes and connect the circuit with chip pad 21. At the same time, use 3D printing to print L1 circuit layer 5 on dielectric layer 4.

[0074] S5, a temporary bonding adhesive layer is coated on both sides of the dielectric layer 4, and a thin copper foil is stacked on one side of the temporary bonding adhesive layer and pressed together to form the L2 copper layer 61.

[0075] S6, perform lamination, exposure, development, electroplating, stripping and etching of circuit patterns on L2 copper layer 61 to form L2 circuit layer 62;

[0076] S7, a temporary bonding adhesive layer is coated on the circuit pattern of the L2 circuit layer 62, and dielectric layer 4 and copper foil are stacked to form L3 copper layer 71;

[0077] S8, laser drilling is performed on the L3 copper layer 71, and the bottom of the hole falls on the surface of the L1 circuit layer 5.

[0078] S9, L3 copper lamination, chemical electroplating, film removal, and etching are performed to form L3 circuit layer 72. Copper is then plated using the MASP process to fill the laser holes in step S8, connecting L1 circuit layer 5, L2 circuit layer 62, and L3 circuit layer 72 to form a circuit.

[0079] S10, a solder resist layer 8 and a copper opening are made on one side of the L3 circuit layer 72 by applying a single-sided solder resist film.

[0080] S11, cut to form a single encapsulated package.

[0081] like Figure 27 As shown, the 3D printing process of this embodiment is as follows: CuO powder is used as raw material, and H2 generated by the water electrolysis device 11 reacts with CuO to produce Cu powder particles. The Cu powder particles are formed into micro-nano Cu powder particles by an ion fan and a grinding tool. Then, the temperature of the 3D printing device 10 is set to 300~1500℃ and the pressure is set to 10~50MPa to print the Cu powder particles.

[0082] The micro / nano-sized Cu powder particles have a particle size of 5-35 μm. Testing in this embodiment showed that the laser absorption rate of the Cu powder particles was 39.4%.

[0083] In the 3D printing process, CuO particles are conveyed to the melting chamber of the 3D printing equipment 10 by positive pressure blowing of Ar gas, so that the generated Cu powder particles become semi-solid under high pressure and high temperature laser conditions, thereby completing the circuit printing.

[0084] The CuO powder contains a binder. The binder is a mixture of J-2012 type epoxy resin adhesive and inorganic filler, with a coefficient of thermal expansion (CTE) of 10~20 ppm / K. The inorganic filler is BaSO4.

[0085] In this embodiment, the substrate 1 is made of organic polymer resin.

[0086] This invention embeds a chip 2 into a polymer substrate 1. The embedded chip 2 is then fabricated layer by layer using a combination of 3D printing technology and traditional coreless manufacturing processes such as lamination, electroplating, and etching, creating inner and outer circuit layers. Finally, a carrier board with the chip is obtained through single-sided lamination or screen printing solder resist. The circuit fabrication process utilizes the strength of the organic polymer substrate 1 for support, reducing the risk of board warping during production and improving yield.

[0087] This invention utilizes 3D printing via filling technology to simultaneously use copper pillars and polymer materials for 3D printing via filling during the production of coreless inner layer circuitry. This avoids the risks of chemical contamination and penetration caused by traditional coreless substrate electroplating / etching processes, thereby preventing chemical corrosion and interference to the chip and improving electrical performance.

[0088] The 3D printing of this invention adopts a green and environmentally friendly concept, combining renewable electrolysis technology with chemical oxidation-reduction method to produce printable copper powder nanoparticles. The exothermic reaction provides some of the energy for 3D printing. This reaction device is simple and easy to implement, and it does not pollute the environment.

[0089] Example 2:

[0090] like Figures 13 to 26 As shown, this embodiment provides a method for manufacturing a coreless substrate, including the following steps:

[0091] S-1, a groove is laser-cut on substrate 1, and chip 2 is embedded in the groove, with the metal layer and conductive pad 21 of chip 2 facing upwards.

[0092] S-2, fill the area around chip 2 with colloid 3 to fix chip 2;

[0093] S-3, a dielectric layer 4 is laminated onto chip 2;

[0094] S-4, using 3D printing technology to print the L1 circuit layer 5 on the dielectric layer 4;

[0095] S-5, a temporary bonding adhesive layer is coated on both sides of the dielectric layer 4, and a thin copper foil is superimposed on one side of the temporary bonding adhesive layer and pressed together to form the L2 copper layer 61.

[0096] S-6, on the L2 copper layer 61, a lamination, exposure, development, electroplating, stripping and etching of the circuit pattern are performed to form the L2 circuit layer 62.

[0097] S-7, a temporary bonding adhesive layer is coated on the circuit pattern of the L2 circuit layer 62, and dielectric layer 4 and copper foil are stacked to form L3 copper layer 71;

[0098] S-8, laser drilling is performed on the L3 copper layer 71. The bottom of hole 1 91 falls on the surface of L1 circuit layer 5, and the bottom of hole 2 92 falls on the surface of chip pad 21.

[0099] S-9, copper pillars are printed in hole 91 using 3D printing technology to connect L1 circuit layer 5 and L2 circuit layer 62. Copper pillars are printed in hole 92 using 3D printing technology to connect L1 circuit layer 5 and chip pad 21.

[0100] S-10, Hole 2 92 is filled with polymer material using 3D printing technology;

[0101] S-11, 3D print L3 circuit layer 72 on L3 copper layer 71, and fill the holes through 3D printing process to make the circuits of L1 circuit layer 5, L2 circuit layer 62 and L3 circuit layer 72 conductive, and finally etch the excess copper between the circuits.

[0102] S-12, a solder resist layer 8 and a copper surface opening are made on one side of the L3 circuit layer 72 by applying a single-sided pressure solder resist film;

[0103] S-13, cut to form a single encapsulated package.

[0104] The 3D printing process in this embodiment is the same as that in Embodiment 1.

Claims

1. A method for manufacturing a coreless substrate, characterized in that: Includes the following steps: S1, a groove is laser-cut on the substrate (1), and a chip (2) is embedded in the groove, with the metal layer and conductive pad (21) of the chip (2) facing upwards; S2, fill the chip (2) with colloid (3) to fix the chip (2); S3, press a dielectric layer (4) onto the chip (2), and drill a laser hole on the dielectric layer (4) corresponding to the position of the chip pad (21) to form a pad opening; S4, use solder paste (51) to fill the laser hole and connect the circuit with the chip pad (21), and at the same time use 3D printing to print the L1 circuit layer (5) on the dielectric layer (4). S5, a temporary bonding adhesive layer is coated on both sides of the dielectric layer (4), and a thin copper foil is stacked on one side of the temporary bonding adhesive layer for lamination to form the L2 copper layer (61). S6, perform lamination, exposure, development, electroplating, stripping, and etching on the L2 copper layer (61) to form the L2 circuit layer (62). S7, a temporary bonding adhesive layer is coated on the circuit pattern of the L2 circuit layer (62), and a dielectric layer (4) and copper foil are stacked to form the L3 copper layer (71). S8, laser drilling is performed on the L3 copper layer (71), and the bottom of the hole falls on the surface of the L1 circuit layer (5); S9, L3 copper lamination, chemical electroplating, film removal, and etching are performed to form L3 circuit layer (72), and copper plating is used to fill the laser holes in step S8 using MASP process to connect L1 circuit layer (5), L2 circuit layer (62), and L3 circuit layer (72) to form a path; S10, a solder resist layer (8) and a copper opening are made on one side of the L3 circuit layer (72) by applying a single-sided solder resist film; S11, cut to form a single encapsulated package.

2. The method for manufacturing a coreless substrate according to claim 1, characterized in that: Steps S3 to S11 are replaced with the following steps: S-3, a dielectric layer (4) is laminated onto the chip (2); S-4, L1 circuit layer (5) is printed on the dielectric layer (4) using 3D printing technology; S-5, a temporary bonding adhesive layer is coated on both sides of the dielectric layer (4), and a thin copper foil is stacked on one side of the temporary bonding adhesive layer for lamination to form the L2 copper layer (61). S-6, perform lamination, exposure, development, electroplating, stripping, and etching on the L2 copper layer (61) to form the L2 circuit layer (62). S-7, a temporary bonding adhesive layer is coated on the circuit pattern of the L2 circuit layer (62), and a dielectric layer (4) and copper foil are stacked to form the L3 copper layer (71). S-8, laser drilling is performed on the L3 copper layer (71). The bottom of hole one (91) falls on the surface of the L1 circuit layer (5), and the bottom of hole two (92) falls on the surface of the chip pad (21). S-9, copper pillars are printed in hole one (91) using 3D printing technology to connect L1 circuit layer (5) and L2 circuit layer (62), and copper pillars are printed in hole two (92) using 3D printing technology to connect L1 circuit layer (5) and chip pad (21). S-10, Hole 2 (92) is filled with polymer material using 3D printing technology. S-11, 3D print L3 circuit layer (72) on L3 copper layer (71), and fill the holes through 3D printing process to make the circuits of L1 circuit layer (5), L2 circuit layer (62) and L3 circuit layer (72) conductive, and finally etch the excess copper between the circuits. S-12, a solder resist layer (8) and a copper opening are made on one side of the L3 circuit layer (72) by applying a single-sided solder resist film; S-13, cut to form a single encapsulated package.

3. A method for manufacturing a coreless substrate according to claim 1 or 2, characterized in that: The 3D printing process is as follows: CuO powder is used as raw material. H2 generated by the water electrolysis equipment (11) reacts with CuO to produce Cu powder particles. The Cu powder particles are formed into micro-nano Cu powder particles by an ion fan and grinding tools. The temperature of the 3D printing equipment (10) is set to 300~1500℃ and the pressure is set to 10~50MPa to print the Cu powder particles.

4. The method for manufacturing a coreless substrate according to claim 3, characterized in that: The particle size of the micro-nano-sized Cu powder particles is 5~35um.

5. The method for manufacturing a coreless substrate according to claim 3, characterized in that: The CuO particles are conveyed to the melting chamber of the 3D printing equipment (10) by positive pressure blowing of Ar gas, so that the generated Cu powder particles become semi-solid under high pressure and high temperature laser conditions, thereby completing the circuit printing.

6. The method for manufacturing a coreless substrate according to claim 3, characterized in that: The CuO powder contains a binder.

7. The method for manufacturing a coreless substrate according to claim 6, characterized in that: The adhesive is a mixture of J-2012 type epoxy resin adhesive and inorganic filler, and the coefficient of thermal expansion (CTE) of the adhesive is 10~20ppm / K.

8. The method for manufacturing a coreless substrate according to claim 7, characterized in that: The inorganic filler used is BaSO4.

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