Semiconductor test structure and its failure location analysis method

Abstract

The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor test structure and a failure positioning analysis method thereof, the semiconductor test structure comprising a first comb-shaped metal line and a second comb-shaped metal line, the first comb-shaped metal line comprising a plurality of parallel linear metal lines, the second comb-shaped metal line comprising a plurality of parallel island-shaped metal lines, the linear metal lines and the island-shaped metal lines being spaced apart and parallel to each other, the island-shaped metal lines comprising a plurality of island-shaped portions arranged parallel to the linear metal lines, the adjacent two island-shaped portions being spaced apart and independent of each other, and the bottom of each island-shaped portion being further provided with a PN junction. By canceling the metal connecting line above the island-shaped metal line in the traditional comb-tooth interconnection structure, each island-shaped portion of the island-shaped metal line is independent of each other, and the PN junction is further provided at the bottom of each island-shaped portion, so that when the semiconductor test structure is electrically tested, the short-circuited island-shaped portion can be accurately positioned, and the success rate and efficiency of the failure sample analysis are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor test structure and its failure location analysis method. Background Technology

[0002] In the development of advanced semiconductor processes, various test structures are designed to reflect problems in the current process. By testing relevant electrical parameters, structures with abnormal parameters are identified to facilitate failure analysis, find the cause of failure, and subsequently improve online process conditions, ultimately accelerating the R&D progress. However, many current test structures are not designed for failure analysis.

[0003] For example, such as Figure 1 As shown, for the comb-like interconnection structure formed by the linear metal line and the island metal line in the monitoring section, when performing failure analysis on the sample of this structure, the linear metal line 1 and the island metal line 2 are usually led out through the upper metal connecting line 3 for electrical testing. The OBIRCH (laser beam resistance anomaly detection) / EBIRCH (electron beam resistance anomaly detection) is used for positioning. However, in the positioning process of this type of sample, the convergence hot spot cannot be captured, and it often manifests as a linear abnormal signal, which makes it impossible to locate the accurate position. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor test structure and its failure location analysis method, which solves the problem that the failure location cannot be accurately located when performing failure analysis on comb interconnect structures in the prior art.

[0005] To achieve the above objectives, the present invention provides a semiconductor testing structure, including a first comb-shaped metal line and a second comb-shaped metal line. The first comb-shaped metal line includes a plurality of parallel linear metal lines, and the second comb-shaped metal line includes a plurality of parallel island-shaped metal lines. The linear metal lines and the island-shaped metal lines are spaced apart from each other and arranged in parallel. The island-shaped metal lines include a plurality of island-shaped portions arranged parallel to the linear metal lines. Adjacent island-shaped portions are spaced apart and are independent of each other. A PN junction is also provided at the bottom of each island-shaped portion.

[0006] Optionally, a virtual metal etched line is provided on the upper layer of the island-shaped metal line.

[0007] Optionally, one end of each of the plurality of linear metal wires is connected to the first comb handle metal wire, and one end of each of the plurality of island-shaped metal wires is connected to the second comb handle metal wire, wherein the linear metal wires and the island-shaped metal wires are located between the first comb handle metal wire and the second comb handle metal wire.

[0008] Optionally, the end of the first comb handle metal wire is connected to a first solder pad, and the end of the second comb handle metal wire is connected to a second solder pad.

[0009] Based on this, the present invention also provides a failure location analysis method, comprising the following steps:

[0010] A test sample is provided, the test sample includes an insulating layer, and a semiconductor test structure is formed within the insulating layer. The semiconductor test structure includes a first comb-shaped metal line and a second comb-shaped metal line. The first comb-shaped metal line includes a plurality of parallel linear metal lines, and the second comb-shaped metal line includes a plurality of parallel island-shaped metal lines. The linear metal lines and the island-shaped metal lines are spaced apart from each other and arranged in parallel. The island-shaped metal lines include a plurality of island-shaped portions arranged parallel to the linear metal lines. Adjacent island-shaped portions are spaced apart and are independent of each other. A PN junction is also provided at the bottom of each island-shaped portion.

[0011] By monitoring whether the PN junction is turned on, it is possible to monitor whether there is a short circuit between the linear metal wire and the island-shaped part, and to locate the failure location.

[0012] Optionally, if the PN junction is on, the linear metal line at the corresponding position is short-circuited with the island portion; otherwise, the linear metal line at the corresponding position is open-circuited with the island portion.

[0013] Optionally, the conduction status of the PN junction can be determined by the diode's current-voltage characteristic curve.

[0014] Optionally, a light microscopy can be used to locate the failure site.

[0015] Optionally, after locating the failure location, the failure location analysis method further includes:

[0016] The sample is cut to the layer where the failure location is located, and the failure location is precisely located using a nanoprobe instrument.

[0017] Optionally, the sample can be cut to the layer where the failure location is located using a focused ion beam.

[0018] In the semiconductor test structure and its failure location analysis method provided by the present invention, by eliminating the metal connection line above the island metal line in the traditional comb interconnect structure, each island part of the island metal line becomes independent of each other. At the same time, a PN junction is also provided at the bottom of each island part, which facilitates the accurate location of the short-circuited island part when performing electrical tests on the semiconductor test structure, greatly improving the success rate and efficiency of failure sample analysis. Attached Figure Description

[0019] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0020] Figure 1 This is a schematic diagram of the comb-tooth interconnect structure in the prior art;

[0021] Figure 2 This is a schematic diagram of a semiconductor testing structure provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of a short circuit between a linear metal wire and an island-shaped portion, provided in an embodiment of the present invention.

[0023] In the attached image:

[0024] 1-Linear metal wire; 2-Island-shaped metal wire; 3-Metallic connecting wire;

[0025] 10 - Linear metal wire; 20 - Island-shaped metal wire; 21 - Island portion; 30 - PN junction; 31 - Active region; 32 - N-well region; 41 - First comb shank metal wire; 42 - Second comb shank metal wire; 51 - First through-hole; 52 - Second through-hole; 60 - Connecting metal wire; 71 - First solder pad; 72 - Second solder pad. Detailed Implementation

[0026] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the purpose of the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only used to complement the content disclosed in the specification, for those skilled in the art to understand and read, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, if they are the same as or similar to the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0027] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0028] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] Please refer to Figures 2-3 , Figure 2 This is a schematic diagram of a semiconductor testing structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a short circuit between linear metal lines and island-shaped portions according to an embodiment of the present invention. This embodiment provides a semiconductor test structure, including a first comb-shaped metal line and a second comb-shaped metal line. The first comb-shaped metal line includes multiple parallel linear metal lines 10, and the second comb-shaped metal line includes multiple parallel island-shaped metal lines 20. The linear metal lines 10 and island-shaped metal lines 20 are spaced apart and arranged in parallel. Each island-shaped metal line 20 includes multiple island-shaped portions 21 arranged parallel to the linear metal lines 10. Adjacent island-shaped portions 21 are spaced apart and independent of each other. A PN junction 30 is also provided at the bottom of each island-shaped portion 21.

[0030] By eliminating the metal connection line above the island metal line 20 in the traditional comb interconnect structure, each island portion 21 of the island metal line 20 becomes independent of each other. At the same time, a PN junction 30 is set at the bottom of each island portion 21, which facilitates the accurate location of the short-circuited island portion 21 when performing electrical tests on the semiconductor test structure, greatly improving the success rate and efficiency of failure sample analysis.

[0031] Preferably, a dummy metal line (not shown in the figure) is provided on the upper layer of the island metal line 20. In this embodiment, the metal connection line above the island metal line 20 in the traditional comb interconnect structure is replaced with a dummy metal line so that each island part 21 of the island metal line 20 can be independent of each other and not connected to each other without affecting the layout design.

[0032] In this embodiment, one end of each of the plurality of linear metal wires 10 is connected to the first comb handle metal wire 41, and one end of each of the plurality of island-shaped metal wires 20 is connected to the second comb handle metal wire 42. The linear metal wires 10 and the island-shaped metal wires 20 are located between the first comb handle metal wire 41 and the second comb handle metal wire 42. The first comb handle metal wire 41 is located on the upper layer of the linear metal wires 10 and is connected to the linear metal wires 10 through the first through hole 51. The second comb handle metal wire 42 is located on the same layer as the linear metal wires 10. The island-shaped portion 21 is connected to the connecting metal wire 60 on the lower layer through the second through hole 52. The PN junction 30 is disposed below the connecting metal wire 60. It can be understood that the linear metal wires 10 and the island-shaped metal wires 20 are located in the middle layer, the first comb handle metal wire 41 is located on the upper layer of the middle layer, and the connecting metal wire 60 is located on the lower layer of the middle layer.

[0033] Furthermore, a first solder pad 71 is connected to the end of the first comb shank metal wire 41. The first solder pad 71 is connected to one end of a plurality of linear metal wires 10 via the first comb shank metal wire 41. A second solder pad 72 is connected to the end of the second comb shank metal wire 42. An N-well region 32 is provided below each island-shaped metal wire 20. The second solder pad 72 is connected to the N-well region via the second comb shank metal wire 42. This design facilitates the application of voltage (e.g., high level) to the first comb shank metal wire 41 and the linear metal wires 10 via the first solder pad 71, and the application of voltage (e.g., low level) to the second comb shank metal wire 42 and the island-shaped portion 21 via the second solder pad 72 during testing.

[0034] In this embodiment, Figure 2 The dashed line with arrows illustrates the conduction path when a short circuit occurs. The voltage signal can be introduced through the first pad 71, and sequentially pass through the first comb metal line 41, the first through hole 51, the linear metal line 10, the short-circuit region, the island 21, the second through hole 52, the connecting metal line 60, and the active region 31 to reach the N-well region 32. Then, it passes through the N-well region 32, the connecting metal line 60, the second through hole 52, and the second comb metal line 42 to reach the second pad 72 and be led out.

[0035] Based on this, combined Figures 2-3 This invention also provides a failure location analysis method, comprising the following steps:

[0036] A test sample is provided, which includes an insulating layer. A semiconductor test structure is formed within the insulating layer. The semiconductor test structure includes a first comb-shaped metal line and a second comb-shaped metal line. The first comb-shaped metal line includes a plurality of parallel linear metal lines 10. The second comb-shaped metal line includes a plurality of parallel island-shaped metal lines 20. The linear metal lines 10 and the island-shaped metal lines 20 are spaced apart from each other and arranged in parallel. The island-shaped metal lines 20 include a plurality of island-shaped portions 21 arranged parallel to the linear metal lines 10. There is a gap between two adjacent island-shaped portions 21 and they are independent of each other. A PN junction 30 is also provided at the bottom of each island-shaped portion 21.

[0037] By monitoring whether the PN junction is turned on, the short circuit between the linear metal line 10 and the island section 21 can be monitored, and the failure location can be located.

[0038] In this embodiment, if the PN junction is on, the linear metal line 10 at the corresponding position is short-circuited with the island portion 21; otherwise, the linear metal line 10 at the corresponding position is open-circuited with the island portion 21.

[0039] Preferably, the conduction status of the PN junction is determined by the diode's current-voltage characteristic curve.

[0040] Preferably, if a short circuit occurs and the PN junction 30 is normally open, the photon recombination of electrons and holes can be used to locate the failure location using EMMI (microscopic microscopy). Since each island 21 is independent of each other, only the island 21 at the short circuit will show a hot spot, and no linear abnormal signal will appear.

[0041] Furthermore, after locating the failure site, the failure location analysis method also includes:

[0042] The sample is cut to the layer where the failure occurs, and the failure location is precisely located using a nanoprobe instrument.

[0043] Preferably, the sample is cut to the layer where the failure location is located using a focused ion beam.

[0044] In summary, the embodiments of the present invention provide a semiconductor test structure and its failure location analysis method. By eliminating the metal connection line above the island metal line 20 in the traditional comb interconnect structure, each island portion 21 of the island metal line 20 becomes independent of each other. At the same time, a PN junction 30 is provided at the bottom of each island portion 21. This facilitates accurate location of the short-circuited island portion 21 when performing electrical tests on the semiconductor test structure, greatly improving the success rate and efficiency of failure sample analysis.

[0045] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A semiconductor testing structure, characterized in that, It includes a first comb-shaped metal line and a second comb-shaped metal line. The first comb-shaped metal line includes a plurality of parallel linear metal lines, and the second comb-shaped metal line includes a plurality of parallel island-shaped metal lines. The linear metal lines and the island-shaped metal lines are spaced apart from each other and arranged in parallel. The island-shaped metal lines include a plurality of island-shaped portions arranged parallel to the linear metal lines. Adjacent island-shaped portions are spaced apart and are independent of each other. A PN junction is also provided at the bottom of each island-shaped portion. Virtual metal lines are provided on the upper layer of the island-shaped metal lines.

2. The semiconductor test structure according to claim 1, characterized in that, One end of each of the plurality of linear metal wires is connected to the first comb handle metal wire, and one end of each of the plurality of island-shaped metal wires is connected to the second comb handle metal wire. The linear metal wires and the island-shaped metal wires are located between the first comb handle metal wire and the second comb handle metal wire.

3. The semiconductor test structure according to claim 2, characterized in that, The first comb handle metal wire has a first solder pad at its end, and the second comb handle metal wire has a second solder pad at its end.

4. A failure location analysis method, characterized in that, Includes the following steps: A test sample is provided, the test sample includes an insulating layer, and a semiconductor test structure is formed within the insulating layer. The semiconductor test structure includes a first comb-shaped metal line and a second comb-shaped metal line. The first comb-shaped metal line includes a plurality of parallel linear metal lines, and the second comb-shaped metal line includes a plurality of parallel island-shaped metal lines. The linear metal lines and the island-shaped metal lines are spaced apart from each other and arranged in parallel. The island-shaped metal lines include a plurality of island-shaped portions arranged parallel to the linear metal lines. Adjacent island-shaped portions are spaced apart and are independent of each other. A PN junction is also provided at the bottom of each island-shaped portion. Virtual metal lines are provided on the upper layer of the island-shaped metal lines. By monitoring whether the PN junction is turned on, it is possible to monitor whether there is a short circuit between the linear metal wire and the island-shaped portion, and to locate the failure location.

5. The failure location analysis method according to claim 4, characterized in that, If the PN junction is on, the linear metal line at the corresponding position is short-circuited with the island portion; otherwise, the linear metal line at the corresponding position is open-circuited with the island portion.

6. The failure location analysis method according to claim 4 or 5, characterized in that, Whether the PN junction is conducting is determined by the diode's current-voltage characteristic curve.

7. The failure location analysis method according to claim 4, characterized in that, The location of the failure was determined using a light microscopy.

8. The failure location analysis method according to claim 4, characterized in that, After locating the failure location, the failure location analysis method further includes: The sample is cut to the layer where the failure location is located, and the failure location is precisely located using a nanoprobe instrument.

9. The failure location analysis method according to claim 8, characterized in that, The sample is cut to the layer where the failure location is located using a focused ion beam.

Images