Anti-static array substrate and liquid crystal display panel

Abstract

The present application provides an anti-static array substrate and a liquid crystal display panel. The anti-static array substrate includes a substrate, a display area, a non-display area, and an anti-static circuit; the anti-static circuit is located in the non-display area and includes a gate, a first insulating layer, an active layer, a photosensitive material semiconductor layer, a source electrode, and a drain electrode that are stacked in sequence; wherein, the source / drain electrode is opposite to the gate, and the orthographic projection of the source / drain electrode on the substrate surface is within the orthographic projection area of the gate on the substrate; the active layer is a continuous film layer structure, and the active layer is sandwiched between the gate and the source / drain electrode; the gate receives an alternating voltage signal, the source electrode receives a low-potential signal, and the drain electrode is left vacant. The anti-static array substrate of the present application has a strong ability to conduct free electrons and a good effect of shielding free electrons, and can protect the internal circuit of the liquid crystal display panel.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an anti-static array substrate and a liquid crystal display panel using the anti-static array substrate. Background Art

[0002] The liquid crystal display panel of a liquid crystal display (LCD) has the largest market share currently. There are four common types of liquid crystal display modes: twisted nematic (TN), vertical alignment (VA), in-plane switching (IPS), and fringe field switching (FFS). Among them, the IPS hard screen is adopted in industries such as aerospace, automotive, and subway that are constantly in motion. Due to the advantages of fast response speed, large viewing angle, true color, and excellent touch of the picture, it is also widely used in fields such as TVs, mobile phones, and notebooks.

[0003] In-plane switching liquid crystal display is driven by an electric field to rotate. Therefore, protecting the in-plane circuit and improving the static electricity protection level are crucial for improving the quality of IPS products. However, the existing anti-static measures for in-plane liquid crystal display panels can only shield part of the static electricity, and the static electricity conduction ability is insufficient. Summary of the Invention

[0004] In view of the above technical problems, the present application provides an anti-static array substrate and a liquid crystal display panel, which improve the ability of the anti-static array substrate to conduct free electrons and can basically shield all free electrons.

[0005] In a first aspect, an anti-static array substrate includes a substrate. The substrate includes a display area and a non-display area provided on the surface of the substrate. An anti-static circuit is provided on one side of the non-display area close to the edge of the substrate. The anti-static circuit includes:

[0006] A gate, provided on the surface of the substrate. The gate is a film layer structure with a first depression. The two regions of the gate opposite to each other with respect to the first depression are respectively defined as a first region and a second region;

[0007] A first insulating layer, provided on the surface of the gate facing away from the substrate and the surface of the substrate corresponding to the first depression, and the first insulating layer is a continuous film layer structure;

[0008] An active layer, provided on the surface of the first insulating layer facing away from the gate, and the active layer is a continuous film layer structure. The orthographic projection of the active layer on the surface of the substrate is within the orthographic projection area of the gate on the surface of the substrate;

[0009] A photosensitive material semiconductor layer, provided on the surface of the active layer facing away from the first insulating layer. The photosensitive material semiconductor layer is a film layer structure with a second depression, and the second depression coincides with the projection of the first depression of the gate on the surface of the substrate;

[0010] The source electrode and the drain electrode are disposed on the surface of the photosensitive material semiconductor layer facing away from the active layer and are separated from each other. The source electrode is disposed opposite to the first region of the gate electrode, and the drain electrode is disposed opposite to the second region of the gate electrode. Moreover, the orthographic projection of the source electrode on the substrate surface is within the region of the orthographic projection of the first region of the gate electrode on the substrate surface, and the orthographic projection of the drain electrode on the substrate surface is within the region of the orthographic projection of the second region of the gate electrode on the substrate surface.

[0011] The active layer is defined as including a first part, a second part, and a third part. The first part is sandwiched between the first region of the gate electrode and the source electrode, the second part is sandwiched between the second region of the gate electrode and the drain electrode, and the third part is disposed in the separated region between the source electrode and the drain electrode. The gate electrode receives an alternating voltage signal, the source electrode receives a low-potential signal, and the drain electrode is left open.

[0012] Optionally, at least two anti-static circuits are spaced apart and disposed on one side of the non-display area close to the edge of the substrate, and the gate electrode of each anti-static circuit receives an alternating voltage signal.

[0013] Optionally, the photosensitive material semiconductor layer includes hydrogenated amorphous silicon and / or low-temperature polycrystalline silicon.

[0014] Optionally, a second insulating layer is disposed on the surfaces of the source electrode and the drain electrode facing away from the active layer, and on the surface of the active layer in the separated region between the source electrode and the drain electrode. The material of the second insulating layer includes polyaluminum sulfate (PAS).

[0015] Optionally, the separation distance between the source electrode and the drain electrode is greater than 0 μm and less than 5 μm, and the line width of the source electrode and / or the drain electrode is greater than or equal to 3 μm and less than or equal to 50 μm.

[0016] Optionally, the alternating voltage signal is a clock pulse signal transmitted by an external clock pulse signal line, the low-potential signal is transmitted through a low-potential signal line, and the clock pulse signal line and the low-potential signal line are disposed in the non-display area between the anti-static circuit and the display area.

[0017] Optionally, a gate driving circuit is further formed on the substrate. The gate driving circuit is disposed between the low-potential signal line and the clock pulse signal line and the display area. The gate driving circuit is configured to receive the clock pulse signal transmitted by the external clock pulse signal line and transmit a gate driving signal to the display area.

[0018] Optionally, the distance between the gate electrode and the gate driving circuit is greater than 30 μm.

[0019] In a second aspect, an anti-static array substrate includes a substrate. The substrate includes a display area and a non-display area disposed on the surface of the substrate. An anti-static circuit is disposed on one side of the non-display area close to the edge of the substrate. The anti-static circuit includes:

[0020] The gate electrode is disposed on the surface of the substrate. The gate electrode is a film layer structure having a first recess. Two regions of the gate electrode that are oppositely disposed with respect to the first recess are respectively defined as a first region and a second region;

[0021] The first insulating layer is disposed on the surface of the gate electrode facing away from the substrate and on the surface of the substrate corresponding to the first recess, and the first insulating layer is a continuous film layer structure;

[0022] The active layer is disposed on the surface of the first insulating layer facing away from the gate electrode, and the active layer is a continuous film layer structure. The orthographic projection of the active layer on the substrate surface is within the region of the orthographic projection of the gate electrode on the substrate surface. The material of the active layer is a photosensitive semiconductor material;

[0023] The source electrode and the drain electrode are disposed on the surface of the active layer facing away from the first insulating layer and are separated from each other. The source electrode is disposed opposite to the first region of the gate electrode, and the drain electrode is disposed opposite to the second region of the gate electrode. Moreover, the orthographic projection of the source electrode on the substrate surface is within the region of the orthographic projection of the first region of the gate electrode on the substrate surface, and the orthographic projection of the drain electrode on the substrate surface is within the region of the orthographic projection of the second region of the gate electrode on the substrate surface.

[0024] The active layer is defined as including a first portion, a second portion, and a third portion. The first portion is sandwiched between the first region of the gate electrode and the source electrode, the second portion is sandwiched between the second region of the gate electrode and the drain electrode, and the third portion is disposed in the separation region between the source electrode and the drain electrode. The gate electrode receives an AC voltage signal, the source electrode receives a low-potential signal, and the drain electrode is left open.

[0025] In a third aspect, the present application provides a liquid crystal display panel including any one of the above antistatic array substrates.

[0026] Advantages of the present application: Different from the prior art, the anti-static array substrate of the present application is provided with an anti-static circuit on one side near the edge of the substrate in the non-display area. In the anti-static circuit, the source / drain and the gate are arranged opposite to each other. The positive projections of the source / drain on the substrate surface are both within the area of the positive projection of the gate on the substrate surface. The active layer is a continuous film layer structure, and both ends of the active layer are clamped between the source / drain and the gate, and the middle part is located in the separation area between the source and the drain. The gate receives an alternating voltage signal, the source receives a low-potential signal, and the drain is left vacant. When free electrons are generated on the substrate surface or outside the substrate, the potential of the drain increases, a potential difference is generated between the source and the drain, the free electrons are captured by the electric field, and the electron current formed by the captured free electrons conducts the channel between the source and the drain to conduct the free electrons to the source, and then conducts to the common electrode or the wire grounding end through the source, thereby playing a role in guiding static electricity. Moreover, the gate is connected to an alternating voltage, the electric field changes continuously, the free electrons move continuously, the ability of the free electrons to capture holes to form an electron current is enhanced, and the ability to capture free electrons is stronger, thereby enhancing the static electricity guiding ability of the anti-static array substrate. In addition, the anti-static circuit includes a photosensitive semiconductor material layer, and the source and the drain are separately arranged on the surface of the photosensitive material semiconductor layer. At the first recess of the gate, the backlight source can irradiate the photosensitive semiconductor material layer. The electron mobility of the photosensitive semiconductor material is relatively high, and the average drift velocity of the electrons generated under the unit electric field strength is relatively large, which can increase the current between the source and the drain. Therefore, it is easier to capture free electrons, that is, to enhance the free electron conduction ability, and thereby enhance the static electricity guiding ability of the anti-static array substrate. Therefore, the anti-static circuit forms a static electricity protection wall with strong free electron guiding ability on the anti-static array substrate. Therefore, the anti-static array substrate of the present application can basically shield all free electrons, and thereby can protect the internal circuit of the liquid crystal display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without any creative effort, other drawings can also be obtained based on these drawings.

[0028] Figure 1 FIG. is a schematic structural diagram of an anti-static array substrate provided by an embodiment of the present application;

[0029] Figure 2 FIG. is a schematic cross-sectional structure diagram of a gate provided by an embodiment of the present application;

[0030] Figure 3 FIG. is a schematic top view structure diagram of a gate provided by an embodiment of the present application;

[0031] Figure 4 is a circuit schematic diagram of an anti-static array substrate provided by an embodiment of the present application;

[0032] Figure 5 is a timing diagram of an anti-static array substrate provided by an embodiment of the present application;

[0033] Figure 6 is a structural schematic diagram of an anti-static array substrate provided by an embodiment of the present application;

[0034] Figure 7 is a structural schematic diagram of an anti-static array substrate and a gate provided by an embodiment of the present application;

[0035] Figure 8 is a circuit schematic diagram of an anti-static array substrate provided by an embodiment of the present application;

[0036] Figure 9 is a timing diagram of an anti-static array substrate provided by an embodiment of the present application;

[0037] Figure 10 is a cross-sectional structural schematic diagram of a gate provided by an embodiment of the present application.

[0038] Explanation of the reference numerals in the drawings:

[0039] Anti-static array substrate - 1, substrate - 11, display area - 12, non-display area - 13, anti-static circuit - 14, gate - 141, first depression - 1411, first area - 1412, second area - 1413, first insulating layer - 142, active layer - 143, first part 1431, second part 1432, third part 1433, source electrode - 144, drain electrode - 145, photosensitive material semiconductor layer - 146, second depression - 1461, second insulating layer 147, gate driving circuit - 15. Detailed implementation manners

[0040] The solutions of the embodiments of the present application will be described in detail below with reference to the drawings in the specification.

[0041] In the following description, specific details such as specific system structures, interfaces, and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the present application.

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0043] The terms "first" and "second" in this application are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0044] Referring to "embodiments" herein means that specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0045] The inventors of this application have found through research that due to the strong market demand for full-screen narrow-bezel products, the bezels of the products are continuously reduced, and the array traces are continuously approaching the edge of the substrate. In the existing anti-static substrates, only part of the static electricity can be shielded by coating indium tin oxide (International Trade Organization, ITO) on the back of the substrate; moreover, in the existing method of evacuating static electricity by setting wire ground terminal (GND) lines around the panel through a metal film layer, when the metal walks the GND line, there are insulating layers such as a gate insulating layer (GI) and polyarylene sulfone (PASS) on the upper part, resulting in insufficient static electricity receiving capacity.

[0046] Please refer to Figure 1 , the first embodiment of this application provides an anti-static array substrate 1, including a substrate 11. The substrate 11 includes a display area 12 and a non-display area 13 provided on the surface of the substrate. An anti-static circuit 14 is provided on one side of the non-display area 13 close to the edge of the substrate 11, and a gate driver (GOA) circuit 15 is provided in the non-display area 13 and located between the anti-static circuit 14 and the display area 12.

[0047] The substrate 11 can be any conventional substrate in an existing liquid crystal panel. The material of the substrate 11 can be a rigid material, a flexible material, a transparent material, an opaque material, etc. As an example, the material of the substrate 11 can include, but is not limited to, glass, silicon, polymethyl methacrylate (PMMA), etc. In this embodiment, the material of the substrate 11 is glass.

[0048] Please refer to Figure 2 and Figure 3 , the anti-static circuit 14 includes a gate 141, a first insulating layer 142, an active layer 143, a source electrode 144, a drain electrode 145, and a photosensitive material semiconductor layer 146. The gate 141 is disposed on the surface of the substrate 11, and the gate 141 is a film layer structure having a first recess 1411. The two regions of the gate 141 disposed opposite to each other with respect to the first recess 1411 are defined as a first region 1412 and a second region 1413, respectively. The first insulating layer 142 is disposed on the surface of the gate 141 facing away from the substrate 11 and the surface of the substrate 11 corresponding to the first recess 1411, and the first insulating layer 142 is a continuous film layer structure. The active layer 143 is a continuous film layer structure. The active layer 143 is disposed on the surface of the first insulating layer 142 facing away from the gate 141, and is sandwiched between the gate 141 and the source electrode 144 / drain electrode 145. The orthographic projection of the active layer 143 on the surface of the substrate 11 is within the region of the orthographic projection of the gate 141 on the surface of the substrate 11. The photosensitive material semiconductor layer 146 is a film layer structure having a second recess 1461, and is disposed on the surface of the active layer 143 facing away from the first insulating layer 142, and the projection of the second recess 1461 on the substrate surface coincides with the projection of the first recess 1411. The source electrode 144 and the drain electrode 145 are disposed on the surface of the photosensitive material semiconductor layer 146 facing away from the active layer 143 and are separated from each other. The source electrode 144 is disposed opposite to the first region 1412 of the gate 141, the drain electrode 145 is disposed opposite to the second region 1413 of the gate 141, and the orthographic projection of the source electrode 144 on the substrate surface is within the region of the orthographic projection of the first region 1412 of the gate 141 on the surface of the substrate 11, and the orthographic projection of the drain electrode 145 on the substrate 11 is within the region of the orthographic projection of the second region 1413 of the gate 141 on the surface of the substrate 11.

[0049] The gate 141 includes the first recess 1411. An opening is formed at the first recess 1411 of the gate 141, and the backlight source can irradiate the photosensitive material semiconductor layer 146. The photosensitive material semiconductor layer 146 has photosensitive characteristics, which can improve the electron mobility, increase the current between the source electrode 144 and the drain electrode 145, so it is easier to capture free electrons, that is, enhance the electron conduction ability, and further enhance the static electricity conduction ability of the anti-static circuit 14.

[0050] The material of the gate 141 can be any conventional gate material in a thin-film transistor. By way of example, the material of the gate 141 can include, but is not limited to, gold (Au), molybdenum (Mo), aluminum (Al), copper (Cu), or other metals or metal alloys, etc. In this embodiment, the material of the gate 141 is Al.

[0051] The materials of the source 144 and the drain 145 can be any conventional source 144 and drain 145 materials in a thin-film transistor. By way of example, the materials of the source 144 and the drain 145 can include, but are not limited to, gold (Au), molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or other metals or metal alloys, etc. In this embodiment, the materials of the source 144 and the drain 145 are Cu.

[0052] The first insulating layer 142 completely covers the gate 141. The material of the first insulating layer 142 can be any conventional gate insulating layer material in a thin-film transistor. By way of example, the material of the first insulating layer 142 can include, but is not limited to, silicon dioxide, silicon nitride, etc. In this embodiment, the material of the first insulating layer 142 is silicon dioxide.

[0053] The gate 141 receives an alternating voltage signal, the source receives a low-potential signal, and the drain is left open. Optionally, the gate 141 receives an alternating voltage that continuously switches between a high potential and a low potential. Please refer to Figure 4 and Figure 5 , in some embodiments, the gate 141 receives a CLK signal transmitted by an external clock pulse (CLK) signal line, the source 144 receives a low-potential (VGL) signal transmitted by a low-potential signal line, and the drain 145 is left open. When free electrons are generated on the substrate surface or outside the substrate, the potential of the drain 145 rises, a potential difference is generated between the source 144 and the drain 145, the free electrons are captured by the electric field, and the electron current formed by the captured free electrons conducts the channel between the source 144 and the drain 145 to conduct the free electrons to the source 144, and is conducted away through the source 144 to the common electrode, thereby playing a role in guiding static electricity. Moreover, the gate 141 is connected to an alternating voltage that continuously switches between high and low potentials, the electric field continuously changes, the free electrons continuously move, the ability of the free electrons to capture holes to form an electron current is enhanced, and the ability to capture free electrons is stronger, thereby enhancing the static electricity guiding ability of the anti-static array substrate 1. Therefore, the anti-static circuit 14 forms an anti-static protection wall on the anti-static array substrate 1 that has a guiding effect on external static electricity, can shield external static electricity, and thus can protect the internal circuit of the display panel.

[0054] The separation distance between the source electrode 144 and the drain electrode 145 can be selected according to actual needs. Optionally, the separation distance between the source electrode 144 and the drain electrode 145 is greater than 0 μm and less than 5 μm. The magnitude of the separation distance between the source electrode 144 and the drain electrode 145 determines the on - ability of the source electrode 144 and the drain electrode 145 in the device. The smaller the separation distance between the source electrode 144 and the drain electrode 145, the easier it is for the source electrode 144 and the drain electrode 145 to be turned on, and it is easier to transfer electrons to the low - potential signal line; the larger the separation distance between the source electrode 144 and the drain electrode 145, the stronger the ability to attract electrons. The separation distance between the source electrode 144 and the drain electrode 145 is greater than 0 μm and less than 5 μm, which can not only ensure a relatively strong ability to attract electrons, but also make it easier for the source electrode 144 and the drain electrode 145 to be turned on, and thus easier to transfer electrons to the low - potential signal line. Moreover, this interval distance results in less interference between the source electrode 144 and the drain electrode 145, and the anti - static array substrate 1 has a higher safety level.

[0055] The line widths of the source electrode 144 and the drain electrode 145 can be selected according to actual needs. For example, the line widths of the source electrode 144 and the drain electrode 145 can be equal to the minimum line width of the display area 12 on the substrate surface. Optionally, the line widths of the source electrode 144 and the drain electrode 145 are greater than or equal to 3 μm and less than or equal to 50 μm. This line width range is consistent with the in - plane line width and can ensure the processability under this line width range.

[0056] A second insulating layer 147 is provided on the surfaces of the source electrode 144 and the drain electrode 145 facing away from the photosensitive material semiconductor layer 146, and on the surface of the active layer 143 in the separated area between the source electrode 144 and the drain electrode 145. The second insulating layer 147 can prevent the source electrode 144 and the drain electrode 145 from being corroded. In this embodiment, the material of the second insulating layer 147 is polyaluminum sulfate (PAS). It can be understood that the second insulating layer 147 is an optional component and can be selected according to actual needs. For example, in some embodiments, the anti - static circuit 14 may not include the second insulating layer 147. Moreover, the material of the second insulating layer 147 is not limited to PAS, and can also be other insulating materials that can prevent the source electrode 144 and the drain electrode 145 from being corroded.

[0057] The anti - static circuit 14 is provided on one side of the non - display area 13 close to the edge of the substrate 11. The distance between the anti - static circuit 14 and the edge of the substrate 11 is selected according to actual needs. Optionally, the distance between the anti - static circuit 14 and the edge of the substrate 11 is greater than the cutting accuracy to prevent the anti - static circuit 14 from being damaged during the manufacturing process.

[0058] The active layer 143 is a continuous film structure. The active layer 143 includes a first part 1431, a second part 1432, and a third part 1433. The first part 1431 is sandwiched between the first region 1412 of the gate 141 and the source 144. The second part 1432 is sandwiched between the second region 1413 of the gate 141 and the drain 145. The third part 1433 is disposed in the separation region between the source 144 and the drain 145.

[0059] The material of the active layer 143 can be any conventional material for the active layer in existing thin film transistors. For example, the material of the active layer 143 can be, but is not limited to, amorphous silicon, polycrystalline silicon, organic semiconductor material, oxide semiconductor material, etc. In this embodiment, the material of the active layer is amorphous silicon semiconductor material.

[0060] The photosensitive material semiconductor layer 146 can be any semiconductor material with photosensitive properties. For example, the photosensitive material semiconductor layer 146 can be, but is not limited to, amorphous silicon or polycrystalline silicon, etc. Preferably, the photosensitive material semiconductor layer 146 is hydrogenated amorphous silicon (α-Si:H) or low-temperature polycrystalline silicon, etc. The electron mobility of α-Si:H is large and it is easy to capture free electrons. Therefore, the hydrogenated amorphous silicon semiconductor layer has strong static electricity conduction ability and can better achieve electrostatic protection of the display panel. In this embodiment, the photosensitive material semiconductor layer 146 is an n-type hydrogenated amorphous silicon (N + α-Si:H) layer.

[0061] The present invention also provides a method for manufacturing the anti-static circuit 14, including the following steps:

[0062] Step (S1): Deposit a first metal layer on the non-display area 13 of the substrate 11 on one side away from the substrate edge, and etch the first metal layer to obtain the gate 141;

[0063] Step (S2): Deposit a first insulating layer 142 on the surface of the gate 141 facing away from the substrate 11 and on the surface of the substrate 11 corresponding to the first recess 1411 of the gate 141;

[0064] Step (S3): Deposit the active layer 143 on the surface of the first insulating layer 142 facing away from the gate 141;

[0065] Step (S4): Deposit the photosensitive material semiconductor layer 146 on the surface of the active layer 143 facing away from the first insulating layer;

[0066] Step (S5): Deposit a second metal layer on the surface of the photosensitive material semiconductor layer 146, and etch the second metal layer to obtain the source 144 and the drain 145.

[0067] In some embodiments, after step (S5), there is further a step of depositing a second insulating layer 147 on the surfaces of the source electrode 144 and the drain electrode 145 facing away from the photosensitive material semiconductor layer 146 and on the surface of the active layer 143 between the separated regions of the source electrode 144 and the drain electrode 145.

[0068] The VGL signal line and the clock pulse signal line are disposed in the non-display area 13 between the anti-static circuit 14 and the display area 12. The clock pulse signal line is used to transmit the CLK signal, and the VGL signal line is used to transmit the VGL signal.

[0069] The gate driving circuit 15 is disposed between the VGL signal line and the clock pulse signal line and the display area 12. The gate driving circuit 15 is configured to receive the CLK signal transmitted by the external clock pulse signal line and transmit a gate driving signal to the display area 12. It can be understood that the gate driving circuit 15 is an optional component. For example, in some embodiments, the anti-static array substrate 1 may not include the gate driving circuit 15 either.

[0070] The distance between the gate 141 and the gate driving circuit 15 can be selected according to actual needs. Optionally, the distance between the gate 141 and the gate driving circuit 15 is greater than 30 μm, which can ensure that the electric field of the anti-static circuit 14 does not affect the signal transmission of the gate driving circuit 15.

[0071] Please refer to Figure 6 and Figure 7 , a second embodiment of the present application provides an anti-static array substrate 1. The anti-static array substrate 1 in this embodiment is substantially the same as the anti-static array substrate 1 in the first embodiment, and the difference is only that the anti-static array substrate 1 of this embodiment includes two anti-static circuits 14 disposed at intervals on one side of the non-display area 13 close to the substrate edge, and the external clock signal line transmits two CLK signals, and each gate 141 of the anti-static circuit 14 receives one CLK signal. It can be understood that the gate 141 is not limited to receiving the CLK signal, and can also receive other AC voltage signals. In some embodiments, the gate 141 receives an AC voltage signal that continuously switches between a high potential and a low potential.

[0072] In this embodiment, except that the number of the above anti-static array substrates 1 is different from that in the first embodiment, other features are the same as those in the first embodiment, including all other technical features described in the first embodiment, and will not be repeated here.

[0073] It can be understood that the number of the anti-static circuits 14 is not limited to one or two in the first embodiment and the second embodiment. The anti-static array substrate 1 may also include more than two anti-static circuits 14 disposed on one side of the non-display area 13 close to the substrate edge, and the gate of each anti-static circuit receives an AC voltage signal. In some embodiments, more than two CLK signals are transmitted through an external clock signal line, and the gate 141 of each anti-static circuit 14 receives one CLK signal.

[0074] Please refer to Figure 8 and Figure 9 , the gates 141 of two anti-static circuits 14 receive the CLK signals transmitted by an external clock pulse (CLK) signal line, the sources 144 receive the VGL signals transmitted by a low potential (VGL) signal line, and the drains 145 are left open. When free electrons are generated on the substrate surface or outside the substrate, the potential of the drain 145 rises, a potential difference is generated between the source 144 and the drain 145, the free electrons are captured by the electric field, and the electron current formed by the captured free electrons conducts the channel between the source 144 and the drain 145 to conduct the free electrons to the source 144, and is conducted away through the source 144 to the common electrode, thereby playing a role in guiding static electricity. Moreover, the gate 141 is connected to an AC voltage with a continuously switching potential, the electric field changes continuously, the free electrons move continuously, the ability of the free electrons to capture holes to form an electron current is enhanced, the ability to capture free electrons is stronger, and thus the static electricity guiding ability of the anti-static array substrate is enhanced. Therefore, the anti-static circuit 14 forms an electrostatic protection wall on the anti-static array substrate 1 that has a guiding effect on external static electricity, can shield all external static electricity, and thus can protect the internal circuit of the display panel. Moreover, multiple CLK signals can reduce the CLK load.

[0075] Please refer to Figure 10 , the third embodiment of the present application provides an anti-static array substrate 1. The anti-static array substrate 1 in this embodiment is basically the same as the anti-static array substrate 1 in the first embodiment, and the difference is only that the anti-static circuit 14 of the anti-static array substrate 1 in this embodiment is different from the anti-static circuit 14 in the first embodiment.

[0076] In this embodiment, the anti-static circuit 14 includes a gate 141, a first insulating layer 142, an active layer 143, a source electrode 144, and a drain electrode 145. The gate 141 is disposed on the surface of the substrate 11, and the gate 141 is a film layer structure having a first recess 1411. Two regions of the gate 141 disposed opposite to each other with respect to the first recess 1411 are respectively defined as a first region 1412 and a second region 1413. The first insulating layer 142 is disposed on the surface of the gate 141 facing away from the substrate 11 and the surface of the substrate 11 corresponding to the first recess 1411, and the first insulating layer 142 is a continuous film layer structure. The active layer 143 is a continuous film layer structure, the active layer 143 is disposed on the surface of the first insulating layer 142 facing away from the gate 141, and is sandwiched between the gate 141 and the source electrode 144 / drain electrode 145. The orthographic projection of the active layer 143 on the surface of the substrate 11 is within the region of the orthographic projection of the gate 141 on the surface of the substrate 11. The source electrode 144 and the drain electrode 145 are disposed on the surface of the active layer 143 facing away from the first insulating layer 142 and are separated from each other. The source electrode 144 is disposed opposite to the first region 1412 of the gate 141, the drain electrode 145 is disposed opposite to the second region 1413 of the gate 141, and the orthographic projection of the source electrode 144 on the substrate surface is within the region of the orthographic projection of the first region 1412 of the gate 141 on the surface of the substrate 11, and the orthographic projection of the drain electrode 145 on the surface of the substrate 11 is within the region of the orthographic projection of the second region 1413 of the gate 141 on the surface of the substrate 11.

[0077] The material of the active layer 143 includes a photosensitive semiconductor material. For example, the active layer 143 may be, but is not limited to, amorphous silicon or polycrystalline silicon, etc. Preferably, the active layer 143 is hydrogenated amorphous silicon (α-Si:H) or low-temperature polycrystalline silicon, etc. The electron mobility of α-Si:H is large and it is easy to capture free electrons. Therefore, the hydrogenated amorphous silicon active layer has strong static electricity conduction ability and can better achieve the static electricity protection of the display panel. In this embodiment, the active layer 143 is an n-type hydrogenated amorphous silicon (N + α-Si:H) layer.

[0078] In this embodiment, except that the photosensitive material semiconductor layer 146 is not provided in the anti-static circuit 14 and the material of the active layer 143 includes a photosensitive semiconductor material, which is different from the first embodiment, other features are the same as those in the first embodiment and will not be described in detail here.

[0079] In some other alternative embodiments, two or more anti-static circuits 14 in the third embodiment may be further disposed on the side of the non-display area 13 of the anti-static array substrate 1 close to the substrate edge, and the gate 141 of each anti-static circuit 14 receives an AC voltage signal. In some alternative embodiments, two or more CLK signals are transmitted through an external clock signal line, and the gate 141 of each anti-static circuit 14 receives a CLK signal.

[0080] The anti-static array substrate of the present application is provided with an anti-static circuit on one side close to the substrate edge in the non-display area. In the anti-static circuit, the source / drain and the gate are arranged opposite to each other. The orthographic projections of the source / drain on the substrate surface are both within the orthographic projection area of the gate on the substrate surface. The active layer is a continuous film layer structure, and both ends of the active layer are clamped between the source / drain and the gate, and the middle part is located in the separation area between the source and the drain. The gate receives an AC voltage signal, the source receives a low potential (VGL) signal, and the drain is left vacant. When free electrons are generated on the substrate surface or outside the substrate, the potential of the drain increases, a potential difference is generated between the source and the drain, the free electrons are captured by the electric field, and the electron current formed by the free electrons capturing holes conducts the channel between the source and the drain to conduct the free electrons to the source, and is conducted to the common electrode or the wire grounding end through the source, thereby playing a role in guiding static electricity. Moreover, the gate is connected to an AC voltage with a continuously switching potential, the electric field changes continuously, the free electrons move continuously, the ability of the free electrons to capture holes and form an electron current is enhanced, and the ability to capture free electrons is stronger, thereby enhancing the static electricity guiding ability of the anti-static array substrate. In addition, the anti-static circuit includes a photosensitive semiconductor material layer, and the source and the drain are separately arranged on the surface of the photosensitive semiconductor material layer. At the first recess of the gate, the backlight source can irradiate the photosensitive semiconductor material layer. The electron mobility of the photosensitive semiconductor material is relatively high, and the average drift velocity of the electrons generated under the unit electric field strength is relatively large, which can increase the current between the source and the drain, so it is easier to capture free electrons, that is, enhance the free electron conduction ability, thereby enhancing the static electricity guiding ability of the anti-static array substrate. Therefore, the anti-static circuit forms a static electricity protection wall with strong free electron guiding ability on the anti-static array substrate. Therefore, the anti-static array substrate of the present application can basically shield all free electrons, thereby protecting the internal circuit of the liquid crystal display panel.

[0081] The present application also provides a liquid crystal display panel, including any one of the anti-static array substrates 1 provided in the above embodiments. The technical features of the anti-static array substrate 1 will not be described in detail here.

[0082] The present application also provides a display device, including the above liquid crystal display panel. The display device can be any product or component with a display function. As an example, the display device can be, but is not limited to, various virtual display glasses, large screen projections, televisions, mobile phones, computers, etc.

[0083] The above is only the implementation mode of the present application, and does not limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be included in the patent protection scope of the present application by the same token.

Claims

1. An anti-static array substrate, comprising a substrate, the substrate including a display area and a non-display area disposed on the surface of the substrate, characterized in that, An anti-static circuit is disposed on one side of the non-display area close to the edge of the substrate. The anti-static circuit includes: a gate disposed on the surface of the substrate. The gate is a film layer structure having a first recess. Two regions of the gate oppositely disposed with respect to the first recess are respectively defined as a first region and a second region; a first insulating layer disposed on the surface of the gate facing away from the substrate and on the surface of the substrate corresponding to the first recess, and the first insulating layer is a continuous film layer structure; an active layer disposed on the surface of the first insulating layer facing away from the gate, and the active layer is a continuous film layer structure. A positive projection of the active layer on the substrate surface is within the region of a positive projection of the gate on the substrate surface; a photosensitive material semiconductor layer disposed on the surface of the active layer facing away from the first insulating layer. The photosensitive material semiconductor layer is a film layer structure having a second recess, and the second recess coincides with a projection of the first recess of the gate on the substrate surface; a source electrode and a drain electrode disposed on the surface of the photosensitive material semiconductor layer facing away from the active layer and separated from each other. The source electrode is disposed opposite to the first region of the gate, and the drain electrode is disposed opposite to the second region of the gate. A positive projection of the source electrode on the substrate surface is within the region of a positive projection of the first region of the gate on the substrate surface, and a positive projection of the drain electrode on the substrate surface is within the region of a positive projection of the second region of the gate on the substrate surface; the active layer is defined as including a first portion, a second portion, and a third portion. The first portion is sandwiched between the first region of the gate and the source electrode, the second portion is sandwiched between the second region of the gate and the drain electrode, and the third portion is disposed in a separated region between the source electrode and the drain electrode. The gate receives an alternating voltage signal, the source electrode receives a low potential signal, and the drain electrode is left open; 2. The anti-static array substrate according to claim 1, wherein at least two of the anti-static circuits are spaced apart and disposed on one side of the non-display area close to the edge of the substrate. The gate of each anti-static circuit receives one of the alternating voltage signals; 3. The anti-static array substrate according to claim 1, characterized in that, the photosensitive material semiconductor layer includes hydrogenated amorphous silicon and / or low-temperature polycrystalline silicon; 4. The anti-static array substrate according to claim 1, wherein a second insulating layer is disposed on the surfaces of the source electrode and the drain electrode facing away from the photosensitive material semiconductor layer and on the surface of the active layer in the separated region between the source electrode and the drain electrode. The material of the second insulating layer includes polyaluminum sulfate (PAS); 5. The anti-static array substrate according to any one of claims 1-4, characterized in that, a separation distance between the source electrode and the drain electrode is greater than 0 μm and less than 5 μm, and a line width of the source electrode and / or the drain electrode is greater than or equal to 3 μm and less than or equal to 50 μm; 6. The anti-static array substrate according to any one of claims 1-4, characterized in that, the alternating voltage signal is a clock pulse signal transmitted by an external clock pulse signal line, the low potential signal is transmitted through a low potential signal line, and the clock pulse signal line and the low potential signal line are disposed in the non-display area between the anti-static circuit and the display area.

7. The anti-static array substrate according to claim 6, wherein It further includes a gate driving circuit formed on the substrate. The gate driving circuit is disposed between the low-potential signal line, the external clock pulse signal line and the display area. The gate driving circuit is configured to receive the clock pulse signal transmitted by the external clock pulse signal line and transmit a gate driving signal to the display area.

8. The anti-static array substrate according to claim 7, wherein The distance between the gate and the gate driving circuit is greater than 30 μm.

9. An anti-static array substrate, comprising a substrate, wherein the substrate includes a display area and a non-display area disposed on the surface of the substrate, and is characterized in that An anti-static circuit is disposed on one side of the non-display area close to the edge of the substrate. The anti-static circuit includes: A gate disposed on the surface of the substrate. The gate is a film layer structure having a first recess. Two regions of the gate that are oppositely disposed with respect to the first recess are respectively defined as a first region and a second region. A first insulating layer disposed on the surface of the gate facing away from the substrate and the surface of the substrate corresponding to the first recess, and the first insulating layer is a continuous film layer structure. An active layer disposed on the surface of the first insulating layer facing away from the gate, and the active layer is a continuous film layer structure. The orthographic projection of the active layer on the substrate surface is within the orthographic projection area of the gate on the substrate surface. The material of the active layer is a photosensitive semiconductor material. A source electrode and a drain electrode are disposed on the surface of the active layer facing away from the first insulating layer and are separated from each other. The source electrode is disposed opposite to the first region of the gate, the drain electrode is disposed opposite to the second region of the gate, and the orthographic projection of the source electrode on the substrate surface is within the orthographic projection area of the first region of the gate on the substrate surface, and the orthographic projection of the drain electrode on the substrate surface is within the orthographic projection area of the second region of the gate on the substrate surface. The active layer is defined as including a first part, a second part and a third part. The first part is sandwiched between the first region of the gate and the source electrode, the second part is sandwiched between the second region of the gate and the drain electrode, and the third part is disposed in the separation region between the source electrode and the drain electrode. The gate receives an alternating voltage signal, the source electrode receives a low-potential signal, and the drain electrode is left open.

10. A liquid crystal display panel, characterized in that, It includes the anti-static array substrate according to any one of claims 1-9.

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