A display panel and its driving method

Abstract

This invention discloses a display panel and its driving method. The display panel includes multiple pixel circuits, multiple first scan lines, multiple data lines, and multiple light-emitting control lines. The data lines are used to transmit data voltage to the pixel circuits row by row during the data writing phase of each row of pixel circuits within one frame period. The pixel circuits are used to write the data voltage to the pixel circuits in response to the first scan signal during the corresponding data writing phase. Within one frame period, the light-emitting control signal includes at least one pulse. Within one frame period, the level transition of at least one pulse of the light-emitting control signal of the m-th row pixel circuit occurs outside the data writing phase of the n-th row pixel circuit. Within one frame period, the data writing phase of the n-th row pixel circuit occurs after the data writing phase of the m-th row pixel circuit, where m and n are different positive integers. The technical solution provided by this embodiment solves the problem of flickering when the display panel displays an image.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and its driving method. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for display panels. Existing display panels have flickering issues when displaying images, which affects the display effect. Summary of the Invention

[0003] This invention provides a display panel and its driving method to solve the problem of flickering when the display panel displays images, which affects the display effect of the display panel.

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution:

[0005] This invention provides a display panel, comprising:

[0006] Multiple pixel circuits arranged in an array;

[0007] Multiple first scan lines, each first scan line is used to transmit a first scan signal to the pixel circuit of the corresponding row;

[0008] Multiple data lines are used to transmit data voltage to the pixel circuit row by row during the data writing phase of each row of pixel circuits within one frame period; the pixel circuits are used to write data voltage to the pixel circuits in response to the first scan signal during the corresponding data writing phase.

[0009] Multiple light-emitting control lines are used to transmit light-emitting control signals to the pixel circuits of the corresponding rows. Within one frame period, the light-emitting control signal includes at least one pulse. Within one frame period, the level transition time of at least one pulse of the light-emitting control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit. Within one frame period, the data writing phase of the n-th row pixel circuit is after the data writing phase of the m-th row pixel circuit. m and n are different positive integers.

[0010] Optionally, within a frame period, the light emission control signal includes a first pulse and at least one second pulse following the first pulse; the data writing phase of the pixel circuit is located during the duration of the extinguishing level of the first pulse of the light emission control signal corresponding to the pixel circuit.

[0011] Specifically, within one frame period, the level transition time of the second pulse of the light emission control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit.

[0012] Optionally, within a frame period, the moment when the second pulse of the light emission control signal of the m-th row pixel circuit changes to the off level is outside the data writing phase of the n-th row pixel circuit, and / or, the moment when the second pulse of the light emission control signal of the m-th row pixel circuit changes to the on level is outside the data writing phase of the n-th row pixel circuit.

[0013] Optionally, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to at least one row of pixel circuits is outside the data writing phase corresponding to the other rows of pixel circuits;

[0014] Optionally, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to each row of pixel circuits is outside the data writing phase corresponding to the other rows of pixel circuits.

[0015] Optionally, within a frame period, the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the off level before the data writing phase of the n-th row pixel circuit; the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the off level after the data writing phase of the (n-1)-th row pixel circuit, where n is an integer greater than 2.

[0016] Optionally, within one frame period, the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on-level before the data writing phase of the n+k-th row pixel circuit; the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on-level after the data writing phase of the n+k-1-th row pixel circuit, where k is an integer greater than or equal to 1.

[0017] Optionally, within a frame period, the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on-level after the data writing phase of the n-th row pixel circuit; the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on-level after the data writing phase of the (n+1)-th row pixel circuit.

[0018] Optionally, the display panel may also include:

[0019] Multiple second scan lines are used to transmit second scan signals to the corresponding pixel circuits during the initialization phase of the pixel circuits in the corresponding rows; the second scan signals are used to control the pixel circuits to write initialization voltages.

[0020] Within one frame period, the level transition time of the second pulse of the light emission control signal of the m-th row pixel circuit is outside the initialization phase of the n-th row pixel circuit, and the initialization phase of the n-th row pixel circuit is after the initialization phase of the m-th row pixel circuit.

[0021] Optionally, the initialization phase of the (n+1)th row pixel circuit coincides with the data writing phase of the nth row pixel circuit;

[0022] Optionally, the second scan line electrically connected to the pixel circuit of the (n+1)th row is electrically connected to the first scan line electrically connected to the pixel circuit of the nth row, or they are the same scan signal line.

[0023] Optionally, the pixel circuit includes a driving transistor, a light-emitting element, and a data writing module;

[0024] The data writing module is connected between the data line and the gate of the driving transistor. The control terminal of the data writing module is connected to the first scan line. The data writing module is used to transmit data voltage to the gate of the driving transistor in response to the first scan signal during the data writing stage.

[0025] Optionally, the effective level of the first scan signal is the on-state level that controls the data writing module to turn on;

[0026] Optionally, the data writing module includes a data writing transistor and a threshold compensation transistor, wherein the gate of the data writing transistor is electrically connected to the first scan line; the data writing transistor is connected between the data line and the first terminal of the driving transistor, and the threshold compensation transistor is connected between the gate and the second terminal of the driving transistor.

[0027] Optionally, the gate of the threshold compensation transistor is electrically connected to the first scan line;

[0028] Optional, multiple data lines and multiple light control lines can be cross-insulated;

[0029] Optionally, multiple data lines extend along a first direction and are arranged along a second direction; multiple light-emitting control lines extend along a second direction and are arranged along a first direction; the first and second directions intersect.

[0030] Multiple first scan lines extend along the second direction and are arranged along the first direction.

[0031] Optionally, the display panel may also include:

[0032] Initialization lines are used to transmit initialization voltage to the pixel circuit.

[0033] The pixel circuit also includes:

[0034] An initialization module is connected to the gate of the driving transistor and / or the first electrode of the light-emitting element, and the control terminal of the initialization module is connected to the second scan line; the initialization module is used to transmit an initialization voltage to the gate of the driving transistor and / or the first electrode of the light-emitting element during the initialization phase.

[0035] Optionally, the effective level of the second scan signal on the second scan line is the on-state level that controls the initialization module to turn on.

[0036] Optionally, the pixel circuit further includes: a first light-emitting control module and / or a second light-emitting control module, wherein the first light-emitting control module is connected between the first power supply line and the first electrode of the driving transistor, the second light-emitting control module is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element, and the second electrode of the light-emitting element is connected to the second power supply line;

[0037] The control terminals of the first and second light-emitting control modules are connected to the light-emitting control line. The first and second light-emitting modules are used to control the light-emitting element to emit light in response to the light-emitting control signal during the light-emitting stage.

[0038] Optionally, the off level is the off level that controls the first light-emitting control module and / or the second light-emitting control module to turn off; the on level is the on level that controls the first light-emitting control module and / or the second light-emitting control module to turn on.

[0039] According to another aspect of the present invention, this embodiment provides a driving method for a display panel, comprising:

[0040] Within a frame period, during the data writing phase of each row of pixel circuits, data voltage on the data line is transmitted to the pixel circuit row by row; the pixel circuit responds to the first scan signal on the corresponding first scan line during the corresponding data writing phase and writes the data voltage on the data line into the pixel circuit.

[0041] During the light-emitting phase, the pixel circuit emits light in response to the illumination level of the light-emitting control signal on the light-emitting control line; wherein, within one frame period, the light-emitting control signal on the light-emitting control line includes at least one pulse; within one frame period, the level transition time of at least one pulse of the light-emitting control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit, and within one frame period, the data writing phase of the n-th row pixel circuit is after the data writing phase of the m-th row pixel circuit, where m and n are different positive integers.

[0042] Optionally, within a frame period, the light emission control signal on the light emission control line includes a first pulse and at least one second pulse following the first pulse; the data writing phase of the pixel circuit is located during the duration of the extinguishing level of the first pulse of the light emission control signal corresponding to the pixel circuit; wherein, within a frame period, the level transition time of the second pulse of the light emission control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit.

[0043] According to another aspect of the present invention, this embodiment provides a display device including the display panel proposed in any of the first aspects.

[0044] The display panel provided in this embodiment of the invention transmits data voltage to the pixel circuit row by row during the data writing stage of each row of pixel circuits within one frame period. The level transition of at least one pulse of the light emission control signal of the m-th row pixel circuit occurs outside the data writing stage of the n-th row pixel circuit. This ensures that when data voltage is written to the n-th row pixel circuit, the level transition of at least one pulse of the light emission control signal of the m-th row pixel circuit cannot couple to the data voltage transmitted via the data line. This ensures that within one frame period, the data voltage charged into the storage capacitor of the n-th row pixel circuit via the data line is always the correct data voltage, guaranteeing the accuracy of the light emission brightness of the light-emitting element. This effectively solves the flicker problem of the display panel and improves the display effect. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the driving timing of a display panel provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0049] Figure 4 This is a flowchart of a driving method for a display panel provided in an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0052] Based on the above-mentioned technical problems, this embodiment proposes the following solutions:

[0053] Figure 1This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the driving timing of a display panel provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. (Combined with...) Figures 1 to 3 The display panel 100 provided in this embodiment of the invention includes multiple pixel circuits 10 arranged in an array, multiple first scan lines s2, multiple data lines d, and multiple light emission control lines em.

[0054] The first scan line s2 is used to transmit the first scan signal S2 to the pixel circuit 10 of the corresponding row; the data line d is used to transmit the data voltage Vdata to the pixel circuit 10 row by row during the data writing phase of each row of pixel circuit 10 within one frame period (equivalent to one screen refresh period, which can be one frame period or each frame period of multiple frame periods). The pixel circuit 10 is used to write the data voltage Vdata to the pixel circuit 10 in response to the first scan signal S2 during the corresponding data writing phase. The light emission control line em is used to transmit the light emission control signal EM to the pixel circuit 10 of the corresponding row; within one frame period, the light emission control signal EM includes at least one pulse; wherein, within one frame period, the level transition time of at least one pulse of the light emission control signal of the m-th row pixel circuit 10 is outside the data writing phase of the n-th row pixel circuit 10 (which can be equivalent to the period when the first scan signal S2-n on the first scan line s2 electrically connected to the n-th row pixel circuit 10 is at an effective level). Within one frame period, the data writing phase of the n-th row pixel circuit 10 is after the data writing phase of the m-th row pixel circuit 10, where m and n are different positive integers.

[0055] Optionally, within a frame period, the light emission control signal EM includes a first pulse and at least one second pulse following the first pulse; the data writing phase of the pixel circuit 10 is located during the duration of the extinguishing level (or black insertion level) of the first pulse of the light emission control signal EM corresponding to the pixel circuit 10; wherein, the level transition time of the second pulse of the light emission control signal of the m-th row pixel circuit 10 is outside the data writing phase of the n-th row pixel circuit 10 (which may be equivalent to the period when the first scan signal S2-n on the first scan line s2 electrically connected to the n-th row pixel circuit 10 is at an effective level).

[0056] The first scan line S2 can be electrically connected to the pixel circuit 10 of the corresponding row. The data line d can be electrically connected to the pixel circuit of the corresponding column. The light emission control line em can be electrically connected to the pixel circuit of the corresponding row. Multiple light emission control lines em can be intersected and insulated from multiple data lines d. Multiple first scan lines s2 can be intersected and insulated from multiple data lines d. The light emission control line em can have the same extension direction as the first scan line s2. Optionally, multiple data lines d extend along a first direction Y and are arranged along a second direction X; multiple light emission control lines em extend along a second direction X and are arranged along a first direction Y; the first direction X and the second direction Y intersect; optionally, the first direction X and the second direction Y are perpendicular. Multiple first scan lines s2 can extend along a second direction X and are arranged along a first direction Y. (Continue to see...) Figure 1 The first scan line s2 and the light emission control line em extend along the first direction X, and the data line d extends along the second direction Y.

[0057] Specifically, the pixel circuit 10 may include a light-emitting element D1, a driving transistor M7, at least one switching transistor, and a storage capacitor C1. During the initialization phase, the pixel circuit 10 initializes the first electrode (e.g., anode) of the light-emitting element D1 and / or the gate of the driving transistor M7 using an initialization voltage transmitted via an initialization line. During the data writing phase, the pixel circuit transmits the data voltage Vdata on the data line d to the gate of the driving transistor according to the first scan signal S2 transmitted on the first scan line S2, thereby charging the storage capacitor C1. During the light-emitting phase, the illumination level of the light-emitting control signal EM controls the light-emitting control module to turn on, transmitting the first power signal VDD transmitted via the first power line to the first electrode (e.g., source) of the driving transistor M7, thereby driving the transistor M7 to generate a driving current based on its gate-source voltage difference, driving the light-emitting element D1 to emit light. A second power line is connected to the second electrode of the light-emitting element D1, and the second power line is used to transmit a second power signal VSS to the second electrode of the light-emitting element D1. One of the first power signal VDD and the second power signal VSS is a high-level signal, and the other is a low-level signal. The first power supply signal VDD can be a high-level signal, and the second power supply signal VSS can be a low-level signal. The storage capacitor C1 can be connected between the first power supply line and the gate of the driving transistor M7.

[0058] Within one frame period, during the data writing phase of each row of pixel circuits 10, data voltage is written to the pixel circuits 10 row by row, so that within one frame period, the pixel circuits 10 of the display panel 100 are charged row by row from top to bottom. Within one frame period, the data writing phases corresponding to pixel circuits in different rows do not overlap, that is, data voltage is transmitted to each row of pixel circuits in a time-division manner. The data writing phase can be equated to the period when the first scan signal S2 is at an active level.

[0059] Optionally, within one frame period, the light emission control signal EM includes a first pulse pulse1 and one or more second pulses pulse2 following the first pulse pulse1. Each pulse may include the moment of transition from the on level to the off level, the period of holding the off level, and the moment of transition from the off level to the on level. Within one frame period, the light emission control signal EM may include multiple off levels.

[0060] In related technologies, during the data writing phase of the nth pixel circuit 10, if the second pulse pulse2 of the light emission control signal EM of the mth row pixel circuit 10 undergoes a level jump, since the data line electrically connected to the nth pixel circuit 10 and the light emission control line electrically connected to the mth row pixel circuit 10 are cross-insulated, there is capacitive coupling between them, which causes the data voltage on the data line electrically connected to the nth pixel circuit 10 to be interfered with, and the data voltage written by the nth pixel circuit 10 is incorrect, which will cause the display panel 100 to have a flickering problem.

[0061] In this embodiment, the level transition time of at least one pulse (e.g., a first pulse and / or a second pulse) of the light emission control signal EMm on the light emission control line em electrically connected to the m-th row pixel circuit 10 before the data writing phase occurs outside the data writing phase of the n-th row pixel circuit 10 (which may correspond to the period when the first scan signal S2-n on the first scan line s2 electrically connected to the n-th row pixel circuit 10 is at an effective level). The level transition time of at least one pulse (e.g., a first pulse and / or a second pulse) of the light emission control signal of the m-th row pixel circuit does not overlap with the data writing phase of the n-th row pixel circuit (which corresponds to the period when the first scan signal of the n-th row pixel circuit is at an effective level). When the n-th row pixel circuit is writing data voltage (which corresponds to the period when the first scan signal of the n-th row pixel circuit is at an effective level), the level of at least one pulse (e.g., a first pulse and / or a second pulse) of the light emission control signal of the m-th row pixel circuit will not transition. This configuration ensures that the level transition of at least one pulse (e.g., the first pulse and / or the second pulse) of the light emission control signal EMm of the m-th row pixel circuit 10, which precedes the data writing phase, is time-staggered with the data writing phase of the n-th row pixel circuit (corresponding to the period when the first scan signal S2-n on the first scan line s electrically connected to the n-th row pixel circuit is at an effective level). This configuration prevents the level transition of at least one pulse (e.g., the first pulse and / or the second pulse) of the light emission control signal EMm of the m-th row pixel circuit 10 from coupling to the data voltage transmitted on the data line d during the writing of data voltage in the n-th row pixel circuit 10. This ensures that within one frame period, the data voltage charged into the storage capacitor of the n-th row pixel circuit 10 by the data line d is always the correct data voltage, effectively solving the flickering problem of the display panel 100 and improving the display effect of the display panel 100.

[0062] The display panel 100 provided in this embodiment transmits data voltage to the pixel circuit 10 row by row during the data writing phase of each row of pixel circuit 10 in one frame period. The level transition of at least one pulse of the light emission control signal EMm of the m-th row pixel circuit 10 occurs outside the data writing phase of the n-th row pixel circuit 10. This ensures that when the n-th row pixel circuit 10 is writing data voltage, the level transition of at least one pulse of the light emission control signal EMm of the m-th row pixel circuit 10 cannot be coupled to the data voltage transmitted by the data line d. This ensures that the data voltage charged into the storage capacitor of the n-th row pixel circuit 10 by the data line d is the correct data voltage in one frame period, guaranteeing the accuracy of the light emission brightness of the light-emitting element D1. This effectively solves the flickering problem of the display panel 100 and improves the display effect of the display panel 100.

[0063] Optionally, based on the above embodiments, combined with Figures 1 to 3 Within a frame period, the moment when the first pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the off level is outside the data writing phase of the n-th row pixel circuit 10, and / or the moment when the first pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the on level is outside the data writing phase of the n-th row pixel circuit 10.

[0064] Optionally, based on the above embodiments, combined with Figures 1 to 3 Within one frame period, the moment when the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the off level (e.g.) Figure 2 At time t1 in the nth row of pixel circuit 10, during the data writing phase (e.g., time t1) Figure 2 Outside of the T1 time period in the middle, and / or, the moment when the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the on-level (e.g., during the T1 time period), Figure 2 (at time t2) outside the data writing phase of the nth row pixel circuit 10.

[0065] In one optional implementation, within a frame period, the moment when the first pulse and / or the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to an off level is outside the data writing phase of the n-th row pixel circuit 10. This is equivalent to the moment when the first pulse and / or the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to an off level not being within the data writing phase of the n-th row pixel circuit 10, meaning that during the data writing phase of the n-th row pixel circuit 10, the first pulse and / or the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 will not transition to an off level.

[0066] Specifically, this configuration ensures that the timing of the first pulse and / or second pulse of the light-emitting control signal EMm of the m-th row pixel circuit 10, which precedes the data writing phase, transitions to an off level at a time that is different from the data writing phase of the n-th row pixel circuit 10, which follows the data writing phase. This effectively prevents the first pulse and / or second pulse of the light-emitting control signal EMm of the m-th row pixel circuit 10, which precedes the data writing phase, from transitioning to an off level and affecting the data writing of the n-th row pixel circuit 10. This configuration also ensures that during the data writing phase of the n-th row pixel circuit 10, the data line charges the storage capacitor of the n-th row pixel circuit 10 with a more accurate data voltage, effectively solving the flickering problem of the display panel 100 and further improving the display effect of the display panel 100.

[0067] In another optional implementation, within a frame period, the moment when the first pulse and / or the second pulse of the light emission control signal EMn of the m-th row pixel circuit 10 transitions to the on-state is outside the data writing phase of the n-th row pixel circuit 10. This is equivalent to the moment when the first pulse and / or the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the on-state being outside the data writing phase of the n-th row pixel circuit 10; in other words, during the data writing phase of the n-th row pixel circuit 10, the first pulse and / or the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 will not transition to the on-state.

[0068] Specifically, this configuration ensures that the timing of the first pulse and / or second pulse of the light-emitting control signal EMm of the m-th row pixel circuit 10, which precedes the data writing phase, transitions to the on-state level at a time different from the data writing phase of the n-th row pixel circuit 10, which follows the data writing phase. This effectively prevents the first pulse and / or second pulse of the light-emitting control signal EMm of the m-th row pixel circuit 10, which precedes the data writing phase, from affecting the data writing of the n-th row pixel circuit 10. This configuration also ensures that during the data writing phase of the n-th row pixel circuit 10, the data line charges the storage capacitor of the n-th row pixel circuit 10 with the correct data voltage Vdata, effectively solving the flickering problem of the display panel 100 and further improving the display effect of the display panel 100.

[0069] In another optional implementation, within a frame period, the moment when the first pulse and / or the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the off level is outside the data writing phase of the n-th row pixel circuit 10; and the moment when the first pulse and / or the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the on level is outside the data writing phase of the n-th row pixel circuit 10.

[0070] Based on the above embodiments, see below. Figure 2 Optionally, the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to an off level before the data writing phase of the n-th row pixel circuit 10; equivalent to the second pulse pulse2 of the light emission control signal EMm of the m-th row pixel circuit 10 transitioning to an off level before the start of the data writing phase of the n-th row pixel circuit 10 (which may be equivalent to the start of the effective level of the first scan signal S2-n on the first scan line s2 electrically connected to the n-th row pixel circuit 10). The second pulse pulse2 of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to an off level before the data writing phase of the (n-1)-th row pixel circuit 10 (e.g., Figure 2 After the T2 time period, the moment when the second pulse pulse2 of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the off level is after the end of the data writing phase of the n-1 row pixel circuit 10 (which can be equivalent to the end of the effective level of the first scan signal S2-n-1 on the first scan line s2 electrically connected to the n-th row pixel circuit 10). For example, m = 1.

[0071] For example, within one frame period, the emission control signal EM may include one first pulse and 15 second pulses. During the duration of the off-level of the first pulse of the emission control signal EM corresponding to each row of pixel circuits 10, a data writing phase may be set, and data writing may be performed on that row of pixel circuits 10. During the duration of the off-level of the second pulse of the emission control signal EM corresponding to each row of pixel circuits 10, no data writing phase is set, and data writing may not be performed on that row of pixel circuits 10. See also... Figure 2 The first second pulse of the m-th row pixel circuit 10 is also the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10.

[0072] Optionally, within a frame period, the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on level before the data writing phase of the n+k-th row pixel circuit (equivalent to the period when the first scan signal on the first scan line electrically connected to the n+k-th row pixel circuit is at an effective level); the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on level after the data writing phase of the n+k-1-th row pixel circuit (equivalent to the period when the first scan signal on the first scan line electrically connected to the n+k-1-th row pixel circuit is at an effective level), where k is an integer greater than or equal to 1. Figure 2 An example is drawn for the case where k=2. Within one frame period, the second pulse of the illumination control signal for the m-th row pixel circuit transitions to the on level at the data writing phase of the (n+2)-th row pixel circuit (equivalent to...). Figure 2Before the T4 time period; the moment when the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on level is during the data writing phase of the n+1-th row pixel circuit (equivalent to...). Figure 2 (After the T3 time period in the middle).

[0073] Based on the above embodiments, see below. Figure 2 Optionally, within a frame period, the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the on-level after the data writing phase of the n-th row pixel circuit 10; the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the on-level during the data writing phase of the (n+1)-th row pixel circuit 10 (e.g., ...). Figure 2 After the T3 time period.

[0074] For example, see [link to example]. Figure 2 and Figure 3 Taking a P-type transistor as an example, the illumination level of the light-emitting control signal EMn is a low-level signal, and the extinguishing level of the light-emitting control signal EMn is a high-level signal. The first pulse and the second pulse of the light-emitting control signal EMn both correspond to the extinguishing level of the light-emitting control signal EMn. That is to say, when the pulses of the light-emitting control signal EMn (including the first pulse and the second pulse) arrive, the light-emitting element D1 of the row pixel circuit 10 does not emit light, and the row pixel circuit 10 enters the data writing stage according to the arrival of the first scan signal S2-n.

[0075] For example, see [link to example]. Figure 2 and Figure 3Within one frame period, the number of pulses for the light emission control signal EMn can be set to 16. Within one frame period, the first row of pixel circuit 10 corresponds to the first scan signal S2-1, the second scan signal S1-1, and the light emission control signal EM1. The second row of pixel circuit 10 corresponds to the second scan signal S2-2, the second scan signal S1-2, and the light emission control signal EM2. And so on, the m-th row of pixel circuit 10 corresponds to the first scan signal S2-m, the second scan signal S1-m, and the light emission control signal EMm. The (m+1)-th row of pixel circuit 10 corresponds to the second scan signal S2-m+1, the second scan signal S1-m+1, and the light emission control signal EMm+1. The (n-1)-th row of pixel circuit 10 corresponds to the first scan signal S2-n, the second scan signal S1-n, and the light emission control signal EMn-1. The n-th row of pixel circuit 10 corresponds to the first scan signal S2-n, the second scan signal S1-n, and the light emission control signal EMn. The corresponding first scan signal S2-n+1, ​​second scan signal S1-n+1, ​​and light emission control signal EMn+1 for the (n+1)th row pixel circuit 10. The corresponding first scan signal S2-n+2, second scan signal S1-n+2, and light emission control signal EMn+2 for the (n+2)th row pixel circuit 10.

[0076] Optionally, within a frame period, the level transition time of at least one pulse (e.g., a first pulse and / or a second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits occurs outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row). For example, within a frame period, the level transition time of at least one pulse (e.g., a first pulse and / or a second pulse) of the light emission control signal corresponding to the m-th row of pixel circuits occurs outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0077] Optionally, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to at least one row of pixel circuits is outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row). For example, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to the m-th row of pixel circuits is outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0078] Optionally, within a frame period, the level transition time of at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits is outside the data writing phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0079] Optionally, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to each row of pixel circuits is outside the data writing phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0080] Optionally, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits transitions to the off level occurs outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits transitions to the on level occurs outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0081] Optionally, within a frame period, the moment when the second pulse of the light emission control signal corresponding to at least one row of pixel circuits transitions to the off level is outside the data writing phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when the second pulse of the light emission control signal corresponding to at least one row of pixel circuits transitions to the on level is outside the data writing phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0082] Optionally, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the off level occurs outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the on level occurs outside the data writing phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0083] Optionally, within a frame period, the moment when the second pulse of the light emission control signal corresponding to each row of pixel circuits transitions to the off level occurs outside the data writing phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when the second pulse of the light emission control signal corresponding to each row of pixel circuits transitions to the on level occurs outside the data writing phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0084] Optionally, based on the above embodiments, further combinations can be made... Figures 1 to 3The display panel 100 provided in this embodiment may further include: multiple second scan lines s1, the second scan lines s1 being used to transmit second scan signals S1-n to the corresponding pixel circuit 10 during the initialization phase of the corresponding pixel circuit; the second scan signals S1-n being used to control the pixel circuit 10 to write an initialization voltage. Within one frame period, the initialization phase of the nth row pixel circuit 10 is after the initialization phase of the mth row pixel circuit 10.

[0085] Optionally, within a frame period, the level transition time of at least one pulse of the light emission control signal EMm of the m-th row pixel circuit 10 is outside the initialization phase of the n-th row pixel circuit 10 (equivalent to the period when the second scan signal S1-n on the second scan line s1 electrically connected to the n-th row pixel circuit 10 is at an effective level).

[0086] Optionally, within a frame period, the level transition time of the first pulse of the light emission control signal EMm of the m-th row pixel circuit 10 is outside the initialization phase of the n-th row pixel circuit 10 (equivalent to the period when the second scan signal S1-n on the second scan line s1 electrically connected to the n-th row pixel circuit 10 is at an effective level).

[0087] Optionally, within a frame period, the level transition time of the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 is outside the initialization phase of the n-th row pixel circuit 10 (equivalent to the period when the second scan signal S1-n on the second scan line s1 electrically connected to the n-th row pixel circuit 10 is at an effective level).

[0088] Specifically, during the initialization phase, the initialization module of the pixel circuit 10 responds to the second scan signal S1-n, causing the initialization module to turn on. The initialization voltage transmitted on the initialization line is then transmitted through the initialization module to the first electrode of the light-emitting element D1 and / or the gate of the driving transistor. The initialization line can be configured to be insulated from the light-emitting control signal line. Since the initialization voltage is written to the first electrode of the light-emitting element D1 and / or the gate of the driving transistor during the initialization phase, by setting the level transition time of the first pulse and / or the second pulse of the light-emitting control signal EMm of the m-th row pixel circuit 10 to be outside the initialization phase of the n-th row pixel circuit 10, the initialization voltage written to the first electrode of the light-emitting element D1 and / or the gate of the driving transistor during the initialization phase of the n-th row pixel circuit 10 can be made more accurate, further improving the display effect of the display panel 100.

[0089] Optionally, the initialization phase of the (n+1)th row pixel circuit 10 coincides with the data writing phase of the nth row pixel circuit 10, which is equivalent to the period when the second scan signal S2-n+1 of the (n+1)th row pixel circuit 10 is at an effective level coinciding with the period when the first scan signal S2-n of the nth row pixel circuit 10 is at an effective level. Optionally, the first scan line s2 of the nth row pixel circuit 10 and the second scan line s1 of the (n+1)th row pixel circuit 10 are electrically connected, or are the same scan signal line, to reduce the area occupied by the scan driving circuit.

[0090] Optionally, within a frame period, the level transition time of at least one pulse (e.g., a first pulse and / or a second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row). For example, within a frame period, the level transition time of at least one pulse (e.g., a first pulse and / or a second pulse, or all pulses) of the light emission control signal corresponding to the m-th row of pixel circuits is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0091] Optionally, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to at least one row of pixel circuits is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row). For example, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to the m-th row of pixel circuits is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0092] Optionally, within a frame period, the level transition time of at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits is outside the initialization phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0093] Optionally, within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to each row of pixel circuits is outside the initialization phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0094] Optionally, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits transitions to the off level is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits transitions to the on level is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0095] Optionally, within a frame period, the moment when the second pulse of the light emission control signal corresponding to at least one row of pixel circuits transitions to the off level is outside the initialization phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when the second pulse of the light emission control signal corresponding to at least one row of pixel circuits transitions to the on level is outside the initialization phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0096] Optionally, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the off level is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when at least one pulse (e.g., the first pulse and / or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the on level is outside the initialization phase corresponding to the remaining row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0097] Optionally, within a frame period, the moment when the second pulse of the light emission control signal corresponding to each row of pixel circuits transitions to the off level is outside the initialization phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row), and / or, within a frame period, the moment when the second pulse of the light emission control signal corresponding to each row of pixel circuits transitions to the on level is outside the initialization phase corresponding to the other row of pixel circuits (or all row of pixel circuits, including the pixel circuit of this row).

[0098] For example, in combination Figures 1 to 3 The extinguishing level of the light emission control signal EMn corresponds to the beginning of the pulse of the light emission control signal EMn, and the extinguishing level of the light emission control signal EMn is high; the effective level of the first scan signal S2-n is low; the effective level of the second scan signal S1-n is low.

[0099] Optionally, based on the above embodiments, see also... Figure 3 The pixel circuit 10 provided in this embodiment includes a driving transistor M7, a light-emitting element D1, and a data writing module 1. The data writing module 1 is connected between the data line d and the gate of the driving transistor M7. The control terminal of the data writing module 1 is connected to the first scan line S2. The data writing module 1 is used to transmit a data voltage Vdata to the gate of the driving transistor M7 in response to the first scan signal S2 during the data writing stage.

[0100] Optionally, the effective level of the first scan signal S2 is the conduction level that controls the data writing module to turn on. During the data writing stage, the data writing module 1 turns on in response to the effective level of the first scan signal S2, transmitting a data voltage to the gate of the driving transistor M7. Before the light-emitting stage, the gate of the driving transistor M7 of the pixel circuit 10 writes the data voltage, so that the voltage of the gate of the driving transistor M7 of the pixel circuit 10 is stored in the storage capacitor. This setting allows the pixel circuit 10 to maintain the gate voltage of the driving transistor M7 better during the light-emitting stage, improving the display effect of the display panel 100. Optionally, the data writing module 1 may include a data writing transistor M2 and a threshold compensation transistor M1. The data writing transistor M2 is connected between the data line and the first terminal of the driving transistor M7. The threshold compensation transistor M1 is connected between the gate and the second terminal of the driving transistor M7. The gate of the data writing transistor M2 is electrically connected to the first scan line. Optionally, the gate of the threshold compensation transistor M1 is electrically connected to the first scan line. The gates of the data writing transistor M2 and the threshold compensation transistor M1 may be connected to the same scan line or different scan lines.

[0101] Optionally, based on the above embodiments, see also... Figure 3 The display panel 100 provided in this embodiment may further include: an initialization line, which is used to transmit an initialization voltage Vinit to the pixel circuit 10. The pixel circuit 10 may further include: an initialization module 3, which is connected to the gate of the driving transistor M7 and / or the first electrode of the light-emitting element D1, and the control terminal of the initialization module 3 is connected to the second scan line s1; the initialization module 3 is used to transmit an initialization voltage to the gate of the driving transistor M7 and / or the first electrode of the light-emitting element D1 during the initialization phase.

[0102] Specifically, this configuration ensures that during the initialization phase, the pixel circuit 10 transmits a second scan signal S1 to the control terminal of the initialization module 3 via the second scan line S1. The initialization module 3 is activated in response to the effective level of the second scan signal S1, transmitting the initialization voltage transmitted on the initialization line to the gate of the driving transistor M7 and / or the first electrode (e.g., the anode) of the light-emitting element D1, thus initializing the gate of the driving transistor M7 and / or the first electrode of the light-emitting element D1. This configuration ensures that the initial states of each row of pixel circuits 10 are as consistent as possible, and that the potential of the first electrode of the light-emitting element D1 of each pixel circuit 10 is as consistent as possible after the initialization phase. The consistent potential of the gates of the driving transistors M7 of each row of pixel circuits ensures that when each row of pixel circuits enters the light-emitting phase after writing the data voltage, the brightness of each pixel circuit 10 is as consistent as possible with the required brightness, further improving the display effect of the display panel 100.

[0103] Optionally, the initialization module 3 may include a first initialization transistor M5 and / or a second initialization transistor M4. The first initialization transistor M5 is connected between the initialization line and the gate of the driving transistor M7, and is used to initialize the gate of the driving transistor M7 during the initialization phase. The second initialization transistor M4 is connected between the initialization line and the first electrode of the light-emitting element D1. The second initialization transistor M4 is used to initialize the first electrode of the light-emitting element D1 during the initialization phase. Optionally, the effective level of the second scan signal S1 is the conduction level that controls the initialization module 3 to be turned on. The gate of the first initialization transistor M5 is electrically connected to the second scan line. Optionally, the gate of the second initialization transistor M4 is electrically connected to the second scan line. The gates of the first initialization transistor M5 and the second initialization transistor M4 may be connected to the same scan line or different scan lines.

[0104] Optionally, based on the above embodiments, see also... Figure 3The pixel circuit 10 provided in this embodiment may further include at least one light-emitting control module. The at least one light-emitting control module includes a first light-emitting control module 21 and / or a second light-emitting control module 22. The first light-emitting control module 21 is connected between the first power line and the first electrode of the driving transistor M7. The second light-emitting control module 22 is connected between the second electrode (e.g., drain) of the driving transistor M7 and the first electrode (e.g., anode) of the light-emitting element D1. The second electrode (e.g., cathode) of the light-emitting element D1 is connected to the second power line. The control terminals of the first light-emitting control module 21 and the second light-emitting control module 22 are connected to the light-emitting control line EM. The first light-emitting control module 21 and the second light-emitting control module 22 are used to control the light-emitting element D1 to emit light in response to the light-emitting control signal EM during the light-emitting phase. The first light-emitting control module 21 may include a first light-emitting control transistor M3. The second light-emitting control module 22 may include a second light-emitting control transistor M6.

[0105] Specifically, during the light-emitting phase, the stored energy in the storage capacitor maintains the gate potential of the driving transistor M7, thus stabilizing the driving current generated by the driving transistor M7 during the light-emitting phase. The control terminals of the first light-emitting control module 21 and / or the second light-emitting control module 22 are turned on in response to the lighting level of the light-emitting control signal EM, so as to transmit the first power signal VDD transmitted from the first power line to the first terminal (e.g., the source terminal) of the driving transistor M7, thereby driving the transistor M7 to generate a driving current according to its gate-source voltage difference, driving the light-emitting element D1 to emit light.

[0106] Optionally, the off level is the off level that controls the first light-emitting control module and / or the second light-emitting control module to turn off; the on level is the on level that controls the first light-emitting control module and / or the second light-emitting control module to turn on. One of the off level and the on level can be a high level, and the other can be a low level.

[0107] Optionally, within a frame period, the initialization phase of the same pixel circuit can be before the data writing phase; the emission phase of the same pixel circuit can be after the data writing phase.

[0108] Optionally, the data driving circuit is electrically connected to the pixel circuit via a data line. Optionally, the scan driving circuit is electrically connected to the pixel circuit via a first scan line and / or a second scan line. Optionally, the light-emitting driving circuit is electrically connected to the pixel circuit via a light-emitting control line. Optionally, the timing controller is electrically connected to the data driving circuit, the scan driving circuit, and the light-emitting driving circuit. Optionally, the timing controller and the data driving circuit can be integrated into the driver chip. The light-emitting control signal EM can be adjusted (e.g., shifted forward or backward) so that the level transition time of at least one pulse (e.g., the first pulse and / or the second pulse) of the light-emitting control signal EM is staggered from the data writing stage and does not overlap. The display panel includes a display area AA. The pixel circuit may be located in the display area AA.

[0109] Figure 4 This is a flowchart of a driving method for a display panel according to an embodiment of the present invention. This driving method for the display panel can be used to drive the display panel in the above embodiment. See also... Figure 4 The display panel driving method provided in this embodiment includes:

[0110] S101. During a frame period, in the data writing stage of each row of pixel circuits, data voltage on the data line is transmitted to the pixel circuit row by row; in the corresponding data writing stage, the pixel circuit responds to the first scan signal on the corresponding first scan line and writes the data voltage into the pixel circuit.

[0111] S102. During the light-emitting phase, the pixel circuit emits light in response to the illumination level of the light-emitting control signal on the light-emitting control line, wherein, within one frame period, the light-emitting control signal on the light-emitting control line includes at least one pulse; within one frame period, the level transition time of at least one pulse of the light-emitting control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit, and within one frame period, the data writing phase of the n-th row pixel circuit is after the data writing phase of the m-th row pixel circuit, where m and n are different positive integers.

[0112] Optionally, within a frame period, the light emission control signal on the light emission control line includes a first pulse and at least one second pulse following the first pulse; the data writing phase of the pixel circuit is located during the duration of the extinguishing level of the first pulse of the light emission control signal corresponding to the pixel circuit; wherein, the level transition time of the second pulse of the light emission control signal of the m-th row pixel circuit is outside the duration of the effective level of the first scan signal of the n-th row pixel circuit.

[0113] The display panel driving method provided in this embodiment transmits data voltage to the pixel circuit row by row during the data writing stage of each row of pixel circuits within one frame period. The level transition of the second pulse of the light emission control signal of the m-th row pixel circuit occurs outside the data writing stage of the n-th row pixel circuit. This ensures that when data voltage is written to the n-th row pixel circuit, the level transition of the second pulse of the light emission control signal of the m-th row pixel circuit cannot couple to the data voltage transmitted via the data line. This ensures that within one frame period, the data voltage charged into the storage capacitor of the n-th row pixel circuit via the data line is always the correct data voltage, guaranteeing the accuracy of the light emission brightness of the light-emitting element, effectively solving the flicker problem of the display panel, and improving the display effect of the display panel.

[0114] The driving method for this display panel can be used to drive the display panel in the above embodiments, and has the beneficial effects of the above embodiments, which will not be repeated here.

[0115] Optionally, within a frame period, the data writing phase of the same row of pixel circuits precedes the light emission phase.

[0116] Optionally, within a frame period, before the data writing phase of the same row of pixel circuits, the method further includes: during the initialization phase, the pixel circuit responds to a second scan signal on the second scan line by writing an initialization voltage on the initialization line into the pixel circuit.

[0117] Figure 5 This is a schematic diagram of a display device provided in an embodiment of the present invention. Based on the above embodiment, see... Figure 5 The display device 200 provided in this embodiment includes the display panel 100 provided in any of the above embodiments, and has the beneficial effects of the display panel 100 proposed in any of the above embodiments, which will not be described again here. The display device 200 provided in this embodiment of the invention may include terminals such as mobile phones, tablet computers, and wearable devices.

[0118] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Multiple pixel circuits arranged in an array; Multiple first scan lines, the first scan lines being used to transmit first scan signals to the pixel circuits of the corresponding rows; Multiple data lines are provided, which are used to transmit data voltage to the pixel circuit row by row during the data writing phase of each row of the pixel circuit within a frame period; the pixel circuit is used to write the data voltage to the pixel circuit in response to the first scan signal during the corresponding data writing phase. Multiple light-emitting control lines are used to transmit light-emitting control signals to the pixel circuits of the corresponding rows. Within one frame period, the light-emitting control signal includes at least one pulse. Within one frame period, the level transition time of at least one pulse of the light-emitting control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit. Within one frame period, the data writing phase of the n-th row pixel circuit is after the data writing phase of the m-th row pixel circuit. m and n are different positive integers. Within one frame period, the light emission control signal includes a first pulse and at least one second pulse following the first pulse; the data writing phase of the pixel circuit is located during the duration of the extinguishing level of the first pulse of the light emission control signal corresponding to the pixel circuit; Among them, within one frame period, the level transition time of the second pulse of the light emission control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit; Within one frame period, the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the off level before the data writing phase of the n-th row pixel circuit; the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the off level after the data writing phase of the (n-1)-th row pixel circuit, where n is an integer greater than 2. And / or, Within a frame period, the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on level before the data writing stage of the n+k-th row pixel circuit; the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on level after the data writing stage of the n+k-1-th row pixel circuit, where k is an integer greater than or equal to 1.

2. The display panel according to claim 1, characterized in that, Within a frame period, the moment when the second pulse of the light emission control signal of the m-th row pixel circuit changes to the off level is outside the data writing phase of the n-th row pixel circuit, and / or the moment when the second pulse of the light emission control signal of the m-th row pixel circuit changes to the on level is outside the data writing phase of the n-th row pixel circuit.

3. The display panel according to claim 1, characterized in that, Within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to at least one row of pixel circuits is outside the data writing phase corresponding to the other rows of pixel circuits.

4. The display panel according to claim 1, characterized in that, Within a frame period, the level transition time of the second pulse of the light emission control signal corresponding to each row of pixel circuits is outside the data writing phase corresponding to the other rows of pixel circuits.

5. The display panel according to claim 1, characterized in that, Within one frame period, the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on level after the data writing phase of the n-th row pixel circuit; the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the on level after the data writing phase of the (n+1)-th row pixel circuit.

6. The display panel according to claim 1, characterized in that, The display panel also includes: Multiple second scan lines are provided, which are used to transmit a second scan signal to the corresponding pixel circuit during the initialization phase of the pixel circuit in the corresponding row; the second scan signal is used to control the pixel circuit to write an initialization voltage. Within one frame period, the level transition of the second pulse of the light emission control signal of the m-th row pixel circuit occurs outside the initialization phase of the n-th row pixel circuit, and the initialization phase of the n-th row pixel circuit occurs after the initialization phase of the m-th row pixel circuit.

7. The display panel according to claim 6, characterized in that, The initialization phase of the (n+1)th row pixel circuit coincides with the data writing phase of the nth row pixel circuit.

8. The display panel according to claim 6, characterized in that, The second scan line electrically connected to the pixel circuit in the (n+1)th row is electrically connected to the first scan line electrically connected to the pixel circuit in the nth row, or they are the same scan signal line.

9. The display panel according to any one of claims 1-5, characterized in that, The pixel circuit includes a driving transistor, a light-emitting element, and a data writing module; The data writing module is connected between the data line and the gate of the driving transistor. The control terminal of the data writing module is connected to the first scan line. The data writing module is used to transmit data voltage to the gate of the driving transistor in response to the first scan signal during the data writing stage.

10. The display panel according to claim 9, characterized in that, The effective level of the first scanning signal is the conduction level that controls the data writing module to turn on.

11. The display panel according to claim 9, characterized in that, The data writing module includes a data writing transistor and a threshold compensation transistor. The gate of the data writing transistor is electrically connected to the first scan line. The data writing transistor is connected between the data line and the first terminal of the driving transistor, and the threshold compensation transistor is connected between the gate and the second terminal of the driving transistor.

12. The display panel according to claim 11, characterized in that, The gate of the threshold compensation transistor is electrically connected to the first scan line.

13. The display panel according to claim 12, characterized in that, The multiple data lines and the multiple light-emitting control lines are cross-insulated.

14. The display panel according to claim 13, characterized in that, The plurality of data lines extend along a first direction and are arranged along a second direction; the plurality of light-emitting control lines extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect; The plurality of first scan lines extend along the second direction and are arranged along the first direction.

15. The display panel according to any one of claims 10-14, characterized in that, The display panel also includes: An initialization line, which is used to transmit an initialization voltage to the pixel circuit; The pixel circuit also includes: An initialization module is provided, which is connected to the gate of the driving transistor and / or the first electrode of the light-emitting element, and the control terminal of the initialization module is connected to a second scan line; the initialization module is used to transmit an initialization voltage to the gate of the driving transistor and / or the first electrode of the light-emitting element during the initialization phase.

16. The display panel according to claim 15, characterized in that, The effective level of the second scan signal on the second scan line is the conduction level that controls the initialization module to be turned on.

17. The display panel according to any one of claims 10-14, characterized in that, The pixel circuit further includes: a first light-emitting control module and / or a second light-emitting control module, wherein the first light-emitting control module is connected between the first power line and the first electrode of the driving transistor, and the second light-emitting control module is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element, and the second electrode of the light-emitting element is connected to the second power line; The control terminals of the first light-emitting control module and the second light-emitting control module are connected to the light-emitting control line. The first light-emitting control module and the second light-emitting control module are used to control the light-emitting element to emit light in response to the light-emitting control signal during the light-emitting stage.

18. The display panel according to claim 17, characterized in that, The off level is the off level that controls the first light-emitting control module and / or the second light-emitting control module to turn off; the on level is the on level that controls the first light-emitting control module and / or the second light-emitting control module to turn on.

19. A driving method for a display panel, used to control the display panel as described in any one of claims 1-18, characterized in that, include: Within one frame period, during the data writing phase of each row of pixel circuits, data voltages on the data lines are transmitted to the pixel circuits row by row. In the corresponding data writing phase, the pixel circuit responds to the first scan signal on the corresponding first scan line and writes the data voltage on the data line into the pixel circuit. During the light-emitting phase, the pixel circuit emits light in response to the illumination level of the light-emitting control signal on the light-emitting control line; wherein, within one frame period, the light-emitting control signal on the light-emitting control line includes at least one pulse; within one frame period, the level transition time of at least one pulse of the light-emitting control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit, and within one frame period, the data writing phase of the n-th row pixel circuit is after the data writing phase of the m-th row pixel circuit, where m and n are different positive integers.

20. The driving method for a display panel according to claim 19, characterized in that, Within one frame period, the light emission control signal on the light emission control line includes a first pulse and at least one second pulse following the first pulse; the data writing phase of the pixel circuit is located during the duration of the extinguishing level of the first pulse of the light emission control signal corresponding to the pixel circuit; wherein, within one frame period, the level transition time of the second pulse of the light emission control signal of the m-th row pixel circuit is outside the data writing phase of the n-th row pixel circuit.

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