Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure has an array region and a peripheral region, and includes a substrate and a first dielectric layer on the substrate, the substrate and the first dielectric layer cross the array region and the peripheral region; a capacitor contact structure is located in the first dielectric layer of the array region and is exposed by the first dielectric layer; a first conductive structure is located on the first dielectric layer of the peripheral region; a dielectric stack includes a second dielectric layer and a third dielectric layer on the second dielectric layer, the second dielectric layer is located between adjacent first conductive structures and covers the surface of the first conductive structure; wherein the material of the second dielectric layer is the same as the material of the first dielectric layer, and is different from the material of the third dielectric layer; a second conductive structure includes a second part located on part of the third dielectric layer and a first part connected with the second part, the first part penetrates the dielectric stack and contacts the first conductive structure. Embodiments of the present disclosure can at least simplify the process steps of manufacturing the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] As the integration density of Dynamic Random Access Memory (DRAM) continues to increase, the density of components such as transistors in DRAM array structures is also trending towards higher densities, leading to a continuous reduction in the feature size of these components. However, this reduction in feature size results in shorter contact plugs used to connect two different components, or necessitates multiple deposition and etching processes to form the contact plugs.

[0003] Therefore, how to simplify the process steps for manufacturing semiconductor structures while improving the yield of the formed semiconductor structures is a problem that urgently needs to be considered by those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure, which at least helps to simplify the manufacturing process steps of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate and a first dielectric layer located on the substrate, the substrate including an array region and a peripheral region located around the array region, the first dielectric layer being located on the array region and the peripheral region; a capacitive contact structure located in the first dielectric layer on the array region, wherein the first dielectric layer exposes the top surface of the capacitive contact structure; a first conductive structure located on the first dielectric layer on the peripheral region; a dielectric stack, the dielectric stack including at least a second dielectric layer and a third dielectric layer, the second dielectric layer covering the first dielectric layer on the peripheral region and located between adjacent first conductive structures, the third dielectric layer covering a portion of the second dielectric layer; wherein the material of the first dielectric layer is the same as the material of the second dielectric layer, and the material of the second dielectric layer is different from the material of the third dielectric layer; a second conductive structure located on the peripheral region, the second conductive structure including a first portion and a second portion connected to each other, the first portion penetrating the dielectric stack and electrically contacting the top surface of the first conductive structure, the second portion being located on a portion of the third dielectric layer.

[0006] In some embodiments, the bottom surface of the third dielectric layer is higher than the top surface of the second dielectric layer that is not covered by the second part.

[0007] In some embodiments, the bottom surface of the third dielectric layer is flush with the top surface of the second dielectric layer not covered by the second part; the material of the second dielectric layer includes nitrides.

[0008] In some embodiments, the third dielectric layer covers the entire top surface of the second dielectric layer, wherein the top surface of the third dielectric layer not covered by the second part is lower than the bottom surface of the second part.

[0009] In some embodiments, the dielectric stack further includes a fourth dielectric layer located between the third dielectric layer and the second portion, wherein the material of the fourth dielectric layer is different from the material of the third dielectric layer.

[0010] In some embodiments, the device further includes a capacitor that contacts the top surface of the capacitor contact structure.

[0011] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including an array region and a peripheral region located around the array region, a first dielectric layer formed on the substrate, a capacitive contact structure formed in the first dielectric layer on the array region, and the first dielectric layer exposing the top surface of the capacitive contact structure, and a first conductive structure formed on the first dielectric layer on the peripheral region; forming a dielectric stack, the dielectric stack including at least a second dielectric layer and a third dielectric layer, the second dielectric layer being located between the first dielectric layer and the third dielectric layer, and filling the gaps between adjacent first conductive structures; wherein, the material of the second dielectric layer is the same as that of the first conductive structure. The dielectric layers are made of the same material, while the material of the second dielectric layer is different from that of the third dielectric layer. The dielectric stack on the peripheral region is patterned to form a first groove, the bottom of which exposes the first conductive structure. A conductive layer is formed, covering the top surface of the dielectric stack and filling the first groove. The conductive layer and the third dielectric layer on the peripheral region are patterned, and the conductive layer and the dielectric stack on the array region are removed to form a second groove in the third dielectric layer. The conductive layer in the first groove is retained as a first part, and the conductive layer on the top surface of the remaining dielectric stack is retained as a second part. The first part and the second part are connected to form a second conductive structure.

[0012] In some embodiments, the step of patterning the conductive layer and the third dielectric layer on the peripheral region further includes: patterning the second dielectric layer on the peripheral region, wherein the bottom surface of the second groove is located in the second dielectric layer, and the bottom surface of the second groove is higher than the top surface of the first conductive structure.

[0013] In some embodiments, the material of the second dielectric layer includes nitride; the step of forming the second groove and the second conductive structure includes: patterning the conductive layer and the third dielectric layer on the peripheral region, and removing the conductive layer and the third dielectric layer on the array region; and removing the second dielectric layer on the array region using phosphoric acid.

[0014] In some embodiments, the dielectric stack further includes a fourth dielectric layer covering the top surface of the third dielectric layer, the fourth dielectric layer being made of a different material than the third dielectric layer; the step of forming the second groove and the second conductive structure further includes: patterning the fourth dielectric layer on the peripheral region and removing the fourth dielectric layer on the array region.

[0015] In some embodiments, the method further includes forming a capacitor that contacts the top surface of the capacitor contact structure.

[0016] The technical solutions provided in this disclosure have at least the following advantages:

[0017] The semiconductor structure provided in this disclosure includes a dielectric stack between a first conductive structure and a second conductive structure. The dielectric stack includes a second dielectric layer on a first dielectric layer located on a peripheral region and a third dielectric layer on a portion of the second dielectric layer. The first dielectric layer is made of the same material as the second dielectric layer, resulting in good adhesion between them. The second dielectric layer is also made of the same material as the third dielectric layer, allowing for different etching rates for the second and third dielectric layers in the same etching process, which helps control the etching stop time. Furthermore, in related technologies, the removal of the dielectric layer on the capacitor contact structure and the patterning of the dielectric layer on the first conductive structure to form the second conductive structure are performed in steps. In this disclosure, by providing a dielectric stack, the different materials of the different layers in the dielectric stack result in different etching rates for the layers composed of different materials. Based on the etching load effect, the removal of the dielectric stack on the array region and the patterning of the dielectric stack on the peripheral region can be performed in the same process, thus reducing process complexity. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0020] Figure 2 for Figure 1 A schematic diagram of a first cross-sectional structure of a semiconductor structure is provided;

[0021] Figure 3 for Figure 1 A schematic diagram of a second cross-sectional structure of the provided semiconductor structure;

[0022] Figure 4 for Figure 1 A schematic diagram of a third cross-sectional structure of the provided semiconductor structure;

[0023] Figure 5 A top view of the layer containing the capacitor and the second conductive structure in another semiconductor structure provided in an embodiment of this disclosure;

[0024] Figure 6 for Figure 5 A schematic diagram of the first cross-sectional structure of another semiconductor structure provided;

[0025] Figure 7 for Figure 5 A schematic diagram of a second cross-sectional structure of another semiconductor structure is provided;

[0026] Figure 8 for Figure 5 A schematic diagram of a third cross-sectional structure of another semiconductor structure is provided.

[0027] Figures 9 to 23 This is a schematic diagram of the semiconductor structure corresponding to each step of the semiconductor structure preparation method provided in another embodiment of the present disclosure. Detailed Implementation

[0028] As can be seen from the background technology, the current process steps for manufacturing semiconductor structures are quite complicated.

[0029] This disclosure provides a semiconductor structure in which a dielectric stack is located between a first conductive structure and a second conductive structure, and covers a first dielectric layer in the peripheral region. The dielectric stack includes a second dielectric layer on the first dielectric layer in the peripheral region and a third dielectric layer on a portion of the second dielectric layer. The material of the first dielectric layer is the same as that of the second dielectric layer, thus improving the adhesion between the first and second dielectric layers. The fact that the materials of the second and third dielectric layers are the same allows for different etching rates for the second and third dielectric layers in the same etching process, which is beneficial for controlling the etching stop time. Furthermore, in related technologies, the dielectric layer on the capacitor contact structure is removed and the dielectric layer on the first conductive structure is patterned to form the second conductive structure through different steps. In this disclosure, by providing a dielectric stack and utilizing the different materials of the different layers in the dielectric stack, based on the etching load effect, the removal of the dielectric stack on the array region and the patterning of the dielectric stack on the peripheral region can be performed in the same process, thus reducing the process complexity.

[0030] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] Figure 1 A top view of a semiconductor structure provided in an embodiment of this disclosure; Figure 2 for Figure 1 A schematic diagram of a first cross-sectional structure of a semiconductor structure is provided; Figure 3 for Figure 1 A schematic diagram of a second cross-sectional structure of the provided semiconductor structure; Figure 4 for Figure 1 A schematic diagram of a third cross-sectional structure of the provided semiconductor structure; Figure 5 A top view of the layer containing the capacitor and the second conductive structure in another semiconductor structure provided in an embodiment of this disclosure; Figure 6 for Figure 5 A schematic diagram of the first cross-sectional structure of another semiconductor structure provided; Figure 7 for Figure 5 A schematic diagram of a second cross-sectional structure of another semiconductor structure is provided; Figure 8 for Figure 5 A schematic diagram of a third cross-sectional structure of another semiconductor structure is provided.

[0032] refer to Figures 1 to 4 ,in, Figure 2 The middle left image is along Figure 1 A sectional view of section AA1. Figure 2 The middle right figure is along Figure 1 Cross-sectional view of section BB in the middle. Figure 3 The middle left image is along Figure 1 A sectional view of section AA1. Figure 3 The middle right figure is along Figure 1 Sectional view of section BB in the middle. Figure 4 The middle left image is along Figure 1 A sectional view of section AA1. Figure 4 The middle right image shows along Figure 1 A cross-sectional view of section BB. The semiconductor structure includes a substrate 100 and a first dielectric layer 101 on the substrate 100. The substrate 100 includes an array region 10 and a peripheral region 20 surrounding the array region 10. The first dielectric layer 101 is located on the array region 10 and the peripheral region 20. The semiconductor structure includes a capacitor contact structure 102 located in the first dielectric layer 101 on the array region 10, with the first dielectric layer 101 exposed on the top surface of the capacitor contact structure 102. The semiconductor structure includes a first conductive structure 103 located on the first dielectric layer 101 on the peripheral region 20. The semiconductor structure includes a dielectric stack 104, which may include at least a second dielectric layer 204 and a third dielectric layer 304. The second dielectric layer 204 covers the first dielectric layer 101 on the peripheral region 20 and is located between adjacent first conductive structures 103. The third dielectric layer 304 covers a portion of the second dielectric layer 204. The material of the first dielectric layer 101 is the same as that of the second dielectric layer 204, while the material of the second dielectric layer 204 is different from that of the third dielectric layer 304. The semiconductor structure also includes a second conductive structure 105 located on the peripheral region 20. The second conductive structure 105 includes a first portion 205 and a second portion 305 connected together. The first portion 205 penetrates the second dielectric layer 204 and the third dielectric layer 304 and makes electrical contact with the top surface of the first conductive structure 103. The second portion 305 is located on a portion of the third dielectric layer 304.

[0033] Thus, the peripheral region 20 has two stacked plug structures: a first conductive structure 103 and a second conductive structure 105. By constructing the peripheral region 20 with a dual conductive plug structure, the problem of short circuits easily occurring between adjacent first conductive structures 103 when the peripheral region only has the first conductive structure can be avoided. Furthermore, by making the materials of the first dielectric layer 101 and the second dielectric layer 204 the same, the adhesion between the first dielectric layer 101 and the second dielectric layer 204 can be improved, ensuring the structural stability of the second conductive structure 105.

[0034] Understandably, in related technologies, the removal of the dielectric layer on the array region 10 and the patterning of the dielectric layer on the peripheral region 20 are performed in steps, which is quite complicated. Furthermore, the entire dielectric layer on the array region 10 is removed, while only a portion of the dielectric layer on the peripheral region 20 is removed. In other words, in the direction from the capacitor contact structure 102 toward the first conductive structure 103, the width of the dielectric layer removed on the array region 10, i.e., the width of the array region 10, is greater than the width of the dielectric layer removed between adjacent first conductive structures 103. Based on the etching load effect, in the same process step, the etching depth of the dielectric layer on the array region 10 is greater than the etching depth of the dielectric layer on the peripheral region 20.

[0035] This embodiment of the disclosure includes a dielectric stack 104, in which the film layers are composed of different materials. In the same process step, the different materials are etched at different rates, which is beneficial for controlling the etching time. Furthermore, by utilizing the etching complexity effect, the patterning processing of the dielectric stack 104 on the peripheral region 20 and the removal of the dielectric stack 104 on the array region 10 can be performed in the same process step, thereby reducing the process complexity of forming the semiconductor structure. Moreover, based on the etching load effect, when the dielectric stack 104 on the array region 10 is completely removed in the same process step, there is still a portion of the second dielectric layer 204 between adjacent first conductive structures 103. The top surface of this portion of the second dielectric layer 204 is higher than the top surface of the first conductive structure 103, thus protecting the first conductive structure 103 from erosion and improving the yield of the formed semiconductor structure.

[0036] In some embodiments, the substrate 100 may include a substrate 107 and an active layer 106 located on the substrate 107. The substrate 107 is made of a semiconductor material, including silicon, silicon germanium, or germanium; the active layer 106 is made of a semiconductor material, for example, the active layer 106 may be made of silicon, silicon germanium, or germanium; wherein, the substrate 107 and the active layer 106 may also be prepared from the same original substrate as the substrate 107.

[0037] The active layer 106 may include a channel region and a first source / drain region and a second source / drain region located at both ends of the channel region. The capacitive contact structure 102 and the first conductive structure 103 are both electrically connected to the first source / drain region or the second source / drain region of the active layer 106.

[0038] In some embodiments, an isolation structure 108 may be provided between adjacent active layers 106. The isolation structure 108 is used to isolate adjacent active layers 106 and define the region of each transistor. Specified transistors are selected through bit lines and word lines for writing and reading data. The isolation structure 108 may be a shallow trench isolation (STI) structure made of an isolation material.

[0039] The material of the capacitor contact structure 102 can be conductive materials such as tungsten, tantalum, titanium, tantalum nitride, or titanium nitride. In some embodiments, the arrangement of the capacitor contact structure 102 can be... Figure 1 The capacitor contacts 102 are arranged in a hexagonal, densest configuration. In some embodiments, the capacitor contact structures 102 may also be arranged in a square configuration with equal intervals.

[0040] In some embodiments, a connection layer 115 may be provided between the capacitor contact structure 102 and the active layer 106. The connection layer 115 may be a metal silicide layer and / or a polysilicon layer. The metal silicide layer can reduce the contact resistance between the capacitor contact structure 102 and the active layer 106.

[0041] In some embodiments, the material of the first conductive structure 103 may be conductive materials such as tungsten, tantalum, titanium, tantalum nitride, or titanium nitride. The first conductive structure 103 is in contact with the first source / drain region or the second source / drain region in the peripheral region 20. In some embodiments, the first conductive structure 103 may be formed in the same process step as the capacitor contact structure 102, that is, the material of the first conductive structure 103 is the same as the material of the capacitor contact structure 102.

[0042] In some embodiments, the semiconductor structure may further include an isolation layer 120 located on the surface of the active layer 106, a capacitive contact structure 102 and a first conductive structure 103 located within the isolation layer 120 and protruding from the surface of the isolation layer 120, and a first dielectric layer 101 located on the side of the isolation layer 120 away from the substrate 100. The material of the isolation layer 120 may be silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant.

[0043] The first dielectric layer 101 is used to isolate the portion of the adjacent capacitor contact structure 102 that protrudes from the isolation layer 120 and is located on the bottom surface of the first conductive structure 103. In some embodiments, the material of the first dielectric layer 101 can be a dielectric material such as silicon oxide, silicon nitride, or silicon carbonitride. For example, if the material of the first dielectric layer 101 is silicon nitride, silicon nitride has high dielectric properties and high hardness, which can ensure that the capacitor contact structure 102 and the first conductive structure 103 located in the first dielectric layer 101 are less likely to undergo contour deformation, which is beneficial to improving the yield of the semiconductor structure.

[0044] In some embodiments, the second conductive structure 105 can be a contact plug that functions the same as the first conductive structure 103, that is, the second conductive structure 105 can make electrical contact with the first conductive structure 103. The material of the second conductive structure 105 can be conductive materials such as tungsten, tantalum, tungsten nitride, or tantalum nitride.

[0045] In some embodiments, the semiconductor structure includes a bit line 109 located in the array region 10, and the bit line 109 is electrically connected to either a first source / drain region or a second source / drain region in the active layer 106. The bit line 109 may be made of conductive materials such as tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0046] In some embodiments, an insulating layer 110 is further provided on the side of the bit line 109 away from the active layer 106. The insulating layer 110 is used to isolate the bit line 109 from the capacitor contact structure 102. The material of the insulating layer 110 can be silicon oxide, silicon nitride, or silicon oxynitride.

[0047] In some embodiments, the semiconductor structure includes a gate structure located on the peripheral region 20 and covered by an isolation layer 120. The gate structure includes a gate dielectric layer 111, a first film layer 112, and a second film layer 113 sequentially stacked in a direction away from the substrate 100; and a third film layer 114 covering the surfaces of the gate dielectric layer, the first film layer 112, and the second film layer 113. The isolation layer 120 is also located in the peripheral region 20 and covers the gate structure.

[0048] The gate dielectric layer 111 is made of materials including silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), hafnium silicate oxide (HfSiO4), hafnium dioxide (HfO2), lanthanum oxide (La2O3), zirconium dioxide (ZrO2), strontium titanate (SrTiO3), or zirconium silicate oxide (ZrSiO4), etc.

[0049] In some embodiments, the gate structure is a high-k metal-gate (HKMG) or a doped polysilicon gate. The first film layer 112 is a barrier layer or a work function layer. When the first film layer 112 is a barrier layer, its material can be titanium nitride or other metal nitrides, which can be used to improve the polysilicon depletion problem of the gate and to mitigate the performance issues of the gate dielectric layer caused by the diffusion of the top metal gate material into the gate dielectric layer. When the first film layer 112 is a work function layer, its material can include aluminum oxide or lanthanum oxide, etc.

[0050] The material of the second film layer 113 can be metal or doped polycrystalline silicon. The material of the third film layer 114 can be silicon nitride, silicon oxide, or silicon oxynitride.

[0051] In some embodiments, the material of the second dielectric layer 204 may be a dielectric material such as silicon oxide or a nitride. The material of the third dielectric layer 304 may also be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The fact that the material of the second dielectric layer 204 is different from the material of the first dielectric layer 101 facilitates the control of the etching stop time by monitoring the etching rates of the second dielectric layer 204 and the first dielectric layer 101 in the same process step.

[0052] Based on the etching load effect, after the removal of the dielectric stack 104 on the patterned peripheral region 20 and the dielectric stack 104 on the array region 10 in the same process step, the dielectric stack 104 on the array region 10 is completely removed. The depth of the removed dielectric stack 104 on the peripheral region 20 is less than the depth of the removed dielectric stack 104 on the array region 10, that is, referring to... Figure 2 The bottom surface of the third dielectric layer can be higher than the top surface of the second dielectric layer 204 not covered by the second part 305, and the top surface of the second dielectric layer 204 not covered by the second part 305 is higher than the top surface of the first conductive structure 103. The second dielectric layer 204 not covered by the second part 305 can protect the first conductive structure 103 in the dielectric stack 104 step on the patterned peripheral region 20, reduce the possibility of the first conductive structure 103 being eroded, and help improve the yield of the semiconductor structure.

[0053] It is understandable that the etching of each layer in the dielectric stack 104 can be performed in stages. For example, the patterning of the third dielectric layer 304 on the peripheral region 20 and the removal of the third dielectric stack 104 on the array region 10 can be performed simultaneously. In this step, the second dielectric layer 204 can be used as an etching stop layer. Then, a wet etching process is used to remove the second dielectric layer 204 on the array region 10. The second dielectric layer 204 on the peripheral region 20 is not etched and is used to protect the first conductive structure 103. That is, refer to Figure 3 The bottom surface of the third dielectric layer 304 can be flush with the top surface of the second dielectric layer 204 that is not covered by the second part 305. The material of the second dielectric layer 204 may include nitrides. Nitrides have high hardness and are difficult to be etched or etched through. They can be used as an etch stop layer or a protective layer to protect the first conductive structure 103, reduce the possibility of the first conductive structure 103 being eroded, and help improve the yield of the semiconductor structure.

[0054] It is also understandable that, based on the etching load effect, during the simultaneous patterning of the third dielectric layer 304 on the peripheral region 20 and the removal of the third dielectric layer 304 on the array region 10, when the third dielectric layer 304 on the array region 10 is completely removed, there is still a third dielectric layer 304 with a partial thickness at the position directly opposite to the removed third dielectric layer 304 on the peripheral region 20. That is, the third dielectric layer covers the entire top surface of the second dielectric layer 204, wherein the top surface of the third dielectric layer 304 not covered by the second part 305 is lower than the bottom surface of the second part 305.

[0055] In some embodiments, the dielectric stack 104 may also include two or more dielectric layers. By setting the dielectric layers of adjacent layers to be of different materials, the etching rates of films composed of different materials are different in the same process step. This is beneficial for controlling the etching stop time, reducing the possibility of over-etching, and improving the yield of the formed semiconductor structure. For example, refer to Figure 4 The dielectric stack 104 may also include a fourth dielectric layer 404 located between the third dielectric layer 304 and the second part 305, wherein the material of the fourth dielectric layer 404 is different from the material of the third dielectric layer 304.

[0056] refer to Figures 5 to 8 ,in, Figure 6 The middle left image is along Figure 5 A sectional view of section AA1. Figure 6 The middle right image shows along Figure 5 Sectional view of section BB in the middle. Figure 7 The middle left image is along Figure 5 A sectional view of section AA1. Figure 7 The middle right image shows along Figure 5 Sectional view of section BB in the middle. Figure 8 The middle left image is along Figure 5 A sectional view of section AA1. Figure 8 The middle right image shows along Figure 5 A cross-sectional view of section BB. The semiconductor structure may also include a capacitor 116, which is in contact with the top surface of the capacitor contact structure 102. A support layer 118 is also disposed between adjacent capacitors to support the capacitors. The capacitor 116 may include an upper plate, a lower plate, and a dielectric layer located between the upper and lower plates. Adjacent transistors may share the upper plate, thereby increasing the area of ​​the storage structure and thus improving the charge storage capacity of the semiconductor structure.

[0057] The lower electrode can be made of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten. The dielectric layer can be made of silicon oxide, silicon nitride, or any combination of high-dielectric-constant materials, including hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate. The upper electrode can be made of titanium, titanium nitride, ruthenium, cobalt, nickel, tungsten, doped polycrystalline silicon, germanium silicon, etc. The support layer 118 can be made of silicon nitride, silicon oxynitride, silicon carbonitride, or silicon boron nitride, etc.

[0058] refer to Figures 6 to 8 In some embodiments, the semiconductor structure may further include a planarization layer 119 and a first plug 117. The planarization layer 119 is located on the array region 10 and the peripheral region 20, and covers the capacitor and the second conductive structure 105. The first plug 117 is located within the planarization layer 119, on the array region 10 and the peripheral region 20. The first plug 117 located on the array region 10 is electrically connected to the capacitor, a portion of the first plug 117 located on the peripheral region 20 is electrically in contact with the second conductive structure 105, and a portion of the first plug 117 located on the peripheral region 20 is electrically in contact with the first conductive structure 103. It is understood that... Figures 6 to 8 The contact relationship between the first plug and the capacitor contact structure 102, the first conductive structure 103, and the second conductive structure is merely an example. In some embodiments, the first plug 117 may only contact the second conductive structure 105, or the first plug 117 may only contact the first conductive structure 103.

[0059] By providing two stacked plug structures, a first conductive structure 103 and a second conductive structure 105, on the peripheral area 20, the first plug 117 can make electrical contact with the second conductive structure 105, so that the first plug 117 can be electrically connected to the first conductive structure 103 through the second conductive structure. In this way, the length of the first plug 117 can be reduced, thereby ensuring that the height difference between the first plug 117 synchronously formed on the array area 10 and the first plug 117 on the peripheral area 20 is small, and improving the yield of forming the first plug 117.

[0060] The planarization layer can be a single film layer, or the planarization layer 119 can be a stacked structure of multiple film layers. By setting the planarization layer 119 to have multiple film layers, it is beneficial to control the etching time of the planarization layer 119 to prepare the groove to accommodate the first plug 117, thereby improving the groove accuracy. The material of the planarization layer 119 can be one or more of the following materials: silicon nitride, silicon oxynitride, silicon carbide, or hard mask. The material of the first plug 117 can be at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0061] The semiconductor structure provided in this embodiment includes a dielectric stack 104. The materials of adjacent layers in the dielectric stack 104 are different. Based on the etching load effect, the patterning of the dielectric stack 104 on the peripheral region 20 and the removal of the dielectric stack 104 on the array region 10 can be performed in the same process step. This simplifies the process steps for manufacturing the semiconductor structure and reduces process complexity. Furthermore, after the dielectric stack 104 on the array region 10 is completely removed, a portion of the dielectric stack 104 remains opposite the removed dielectric stack 104 on the peripheral region 20. The top surface of this portion of the dielectric stack 104 is higher than the top surface of the first conductive structure 103, protecting the first conductive structure 103 from erosion, thereby improving the yield of the formed semiconductor structure. In addition, the material of the second dielectric layer 204, which is the bottom layer of the dielectric stack 104, is the same as the material of the first dielectric layer 101. This improves the adhesion between the first dielectric layer 101 and the second dielectric layer 204, ensuring the structural stability of the second conductive structure 105.

[0062] In addition, by providing two stacked plug structures, a first conductive structure 103 and a second conductive structure 105, on the outer perimeter 20, the first plug 117 can contact the capacitor contact structure 102, the first conductive structure 103, and the second conductive structure 105. In this way, the problem of short circuits easily occurring between adjacent first conductive structures 103 when only the first conductive structure 103 is provided on the outer perimeter 20 can be avoided. It can also avoid the problem of small contact size between the first conductive structure 103 and the first plug 117, resulting in large contact resistance.

[0063] Accordingly, according to some embodiments of this disclosure, another aspect of this disclosure also provides a method for preparing a semiconductor structure, used to prepare the semiconductor structure provided in the above embodiments. The same components as in the above embodiments will not be described again here.

[0064] Figures 9 to 23 This is a schematic diagram of the semiconductor structure corresponding to each step of the semiconductor structure preparation method provided in another embodiment of the present disclosure.

[0065] refer to Figure 9 and Figure 10 ,in, Figure 9 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 10 for Figure 9A cross-sectional view of the provided semiconductor structure. A substrate 100 is provided, the substrate 100 including an array region 10 and a peripheral region 20 located around the array region. A first dielectric layer 101 is formed on the array region 10 and the peripheral region 20. A capacitor contact structure 102 is formed in the first dielectric layer 101 on the array region 10, and the top surface of the first dielectric layer 101 is exposed. A first conductive structure 103 is formed on the first dielectric layer 101 on the peripheral region 20.

[0066] In some embodiments, the substrate 100 may include a substrate 107 and an active layer 106 located on the substrate 107. The substrate 107 is made of a semiconductor material, including silicon, silicon germanium, or germanium; the active layer 106 is made of a semiconductor material, for example, the active layer 106 may be made of silicon, silicon germanium, or germanium; wherein, the substrate 107 and the active layer 106 may also be prepared from the same original substrate as the substrate 107.

[0067] The active layer 106 may include a channel region and a first source / drain region and a second source / drain region located at both ends of the channel region. The capacitive contact structure 102 and the first conductive structure 103 are both electrically connected to the first source / drain region or the second source / drain region of the active layer 106.

[0068] In some embodiments, an isolation structure 108 may be provided between adjacent active layers 106. The isolation structure 108 is used to isolate adjacent active layers 106 and define the region of each transistor. The specified transistor is selected by bit lines and word lines and data is written and read.

[0069] In some embodiments, a plurality of spaced-apart capacitive contact structures 102 are provided on the array region 10. In some embodiments, the arrangement of the capacitive contact structures 102 can be... Figure 9 The capacitor contacts 102 are arranged in a hexagonal, densest configuration. In some embodiments, the capacitor contacts 102 can also be arranged in a tetragonal configuration with equal spacing. The material of the capacitor contacts 102 can be conductive materials such as tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0070] In some embodiments, a connection layer 115 may be provided between the capacitor contact structure 102 and the active layer 106. The connection layer 115 may be a metal silicide layer or a polysilicon layer. The metal silicide layer can reduce the contact resistance between the capacitor contact structure 102 and the active layer 106.

[0071] In some embodiments, the material of the first conductive structure 103 may be conductive materials such as tungsten, tantalum, titanium, tantalum nitride, or titanium nitride. The first conductive structure 103 is in contact with the first source / drain region or the second source / drain region in the peripheral region 20. In some embodiments, the first conductive structure 103 may be formed in the same process step as the capacitor contact structure 102, that is, the material of the first conductive structure 103 is the same as the material of the capacitor contact structure 102.

[0072] In some embodiments, the semiconductor structure may further include an isolation layer 120 located on the surface of the active layer 106, a capacitive contact structure 102 and a first conductive structure 103 located within the isolation layer 120 and protruding from the surface of the isolation layer 120, and a first dielectric layer 101 located on the side of the isolation layer 120 away from the substrate 100.

[0073] The first dielectric layer 101 is used to isolate the portion of the adjacent capacitor contact structure 102 that protrudes from the isolation layer 120, and is located on the bottom surface of the first conductive structure 103. The material of the first dielectric layer 101 can be a dielectric material such as silicon oxide, silicon nitride, or silicon carbonitride.

[0074] In some embodiments, a bit line 109 may also be provided in the array region 10, and the bit line 109 is electrically connected to either the first source / drain region or the second source / drain region in the active layer 106.

[0075] In some embodiments, a gate structure may also be disposed on the peripheral region 20, and the gate structure is covered by an isolation layer 120. The gate structure includes a stacked gate dielectric layer 111, a first film layer 112, and a second film layer 113; and a third film layer 114, which covers the surfaces of the gate dielectric layer 111, the first film layer 112, and the second film layer 113.

[0076] refer to Figure 11 A dielectric stack 104 is formed, which may include at least a second dielectric layer 204 and a third dielectric layer 304. The second dielectric layer 204 is located between the first dielectric layer 101 and the third dielectric layer 304 and fills the gap between adjacent first conductive structures 103. The material of the second dielectric layer 204 is the same as that of the first dielectric layer 101, and the material of the second dielectric layer 204 is different from that of the third dielectric layer 304.

[0077] Thus, by setting the material of the first dielectric layer 101 and the second dielectric layer 204 to be the same, the adhesion between the first dielectric layer 101 and the second dielectric layer 204 can be improved, ensuring the structural stability of the first conductive structure 103.

[0078] The material of the second dielectric layer 204 can be a dielectric material such as silicon oxide or nitride. For example, the material of the second dielectric layer can be silicon nitride, which has high dielectric properties and high hardness, making it difficult to be etched or etched through. The material of the third dielectric layer 304 can be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0079] Subsequent steps include forming a conductive layer covering the dielectric stack 104, then removing the dielectric stack 104 and conductive layer on the array region 10, and patterning the dielectric stack 104 and conductive layer on the peripheral region 20 to form a second conductive structure on the peripheral region 20, exposing the top surface of the capacitive contact structure 102 on the array region 10. By providing a dielectric stack 104 with different materials for adjacent film layers in the dielectric stack 104, the removal of the dielectric stack 104 on the array region 10 and the patterning of the dielectric stack 104 on the peripheral region 20 can be performed in the same process step, simplifying the process steps and reducing process complexity.

[0080] In some embodiments, the dielectric stack 104 may also include two or more dielectric stacks 104, with adjacent dielectric layers made of different materials. For example, refer to Figure 19 The dielectric stack 104 may also include a fourth dielectric layer 404, which covers the top surface of the third dielectric layer 304. The material of the fourth dielectric layer 404 is different from that of the third dielectric layer 304, so that the etching rates of the fourth dielectric layer 404 and the third dielectric layer 304 are different in the same process step, which makes it easier to control the etching dielectric stack time and improve the etching accuracy.

[0081] refer to Figure 12 The dielectric stack 104 on the patterned peripheral area is used to form a first groove 200. The bottom of the first groove 200 exposes a first conductive structure 103. The first groove 121 is used to form a second conductive structure in subsequent steps. By providing a dielectric stack 104, the materials of adjacent dielectric layers in the dielectric stack 104 are different, which helps to improve the etching accuracy of the first groove 200. Thus, the morphology of the first part formed in the first groove 121 is better.

[0082] The first groove 200 penetrates the second dielectric layer 204 and the third dielectric layer 304.

[0083] refer to Figure 20 In some embodiments, the dielectric stack 104 may further include a fourth dielectric layer 404, and during the formation of the first groove 200, the first groove 200 also penetrates the fourth dielectric layer 404.

[0084] refer to Figure 13 and Figure 21A conductive layer 201 is formed, which covers the top surface of the dielectric stack 104 and fills the first groove 200. The conductive layer 201 is used to form a second conductive structure in subsequent steps.

[0085] The conductive layer 201 can be made of conductive materials such as tungsten, tantalum, tungsten nitride, or tantalum nitride.

[0086] refer to Figure 14 , Figures 16 to 17 ,and Figure 22 The conductive layer 201 and the third dielectric layer 304 on the peripheral region 20 are patterned, and the conductive layer 201 and the dielectric stack 104 on the array region 10 are removed to form a second groove 202 in the third dielectric layer 304. The conductive layer 201 in the first groove 200 is retained as the first part 205, and the conductive layer 201 on the top surface of the remaining dielectric stack 104 is retained as the second part 305. The first part 205 and the second part 305 are connected to form a second conductive structure 105.

[0087] In some embodiments, the second conductive structure 105 can be a contact plug that functions the same as the first conductive structure 103, that is, the second conductive structure 105 can make electrical contact with the first conductive structure 103. The material of the second conductive structure 105 can be conductive materials such as tungsten, tantalum, tungsten nitride, or tantalum nitride.

[0088] refer to Figure 14 In some embodiments, the step of patterning the conductive layer 201 and the third dielectric layer 304 on the patterned peripheral region 20 further includes: patterning the second dielectric layer 204 on the patterned peripheral region 20, wherein the bottom surface of the second groove 202 is located in the second dielectric layer 204, and the bottom surface of the second groove 202 is higher than the top surface of the first conductive structure 103. In other words, in the same process step, the etching process of each dielectric layer in conductive layer 201 and dielectric stack 104 is performed. Since the width of the dielectric stack 104 removed from the array region 10 in the direction from the capacitor contact structure 102 toward the first conductive structure 103, that is, the width of the array region 10 is greater than the width of the dielectric stack 104 removed between adjacent first conductive structures 103 in the peripheral region 20, based on the etching load effect, in the same process step, the etching depth of the dielectric stack 104 on the array region 10 is greater than the etching depth of the dielectric stack 104 on the peripheral region 20. When the dielectric stack 104 on the array region 10 is completely removed, the second dielectric layer 204 at the bottom of the dielectric stack 104 on the peripheral region 20 is not completely removed, and the top surface of the unremoved second dielectric layer 204 is higher than the top surface of the first conductive structure 103, which can protect the first conductive structure 103 covered by the second dielectric layer 204 from being eroded, which is beneficial to improving the yield of the formed semiconductor structure.

[0089] In some embodiments, the hardness of the second dielectric layer 204 may be set to be greater than that of the third dielectric layer 304, so that when the third dielectric layer 304 is etched, the second dielectric layer 204 can act as an etching stop and protect the first conductive structure 103 covered by the second dielectric layer 204 from being eroded. For example, refer to Figures 16 to 17 The material of the second dielectric layer may include nitrides, such as silicon nitride and silicon oxynitride, which have high hardness. The steps of forming the second groove 202 and the second conductive structure 105 may include: patterning the conductive layer 201 and the third dielectric layer 304 on the peripheral region 20, and removing the conductive layer 201 and the third dielectric layer 304 in the array region 10. In this step, the second dielectric layer 204 acts as an etching stop and protects the first conductive structure 103 covered by the second dielectric layer 204 from being eroded. The second dielectric layer 204 on the array region 10 is removed with phosphoric acid to expose the top surface of the capacitor contact structure 102.

[0090] It is understandable that in the steps of patterning the conductive layer 201 and the third dielectric layer 304 on the peripheral region 20 and removing the conductive layer 201 and the third dielectric layer 304 on the array region 10, based on the etching load effect, after the third dielectric layer 304 on the array region 10 is completely removed, there is still a portion of the thickness of the third dielectric layer 304 at the position directly opposite to the removed third dielectric layer 304 on the peripheral region 20. This portion of the unremoved third dielectric layer 304 can further reduce the possibility of the first conductive structure 103 being etched.

[0091] In some embodiments, the dielectric stack 104 may also include two or more dielectric layers, with adjacent layers made of different dielectric materials. For example, see reference... Figure 22 The dielectric stack 104 may further include a fourth dielectric layer 404; the step of forming the second groove and the second conductive structure may further include: patterning the fourth dielectric layer 404 on the peripheral region 20 and removing the fourth dielectric layer 404 on the array region 10.

[0092] refer to Figure 15 , Figure 18 and Figure 23 Subsequent steps may further include forming a capacitor 116, which contacts the top surface of the capacitor contact structure 102. A support layer 118 is also provided between adjacent capacitors to support the capacitors. The capacitor 116 may include an upper plate, a lower plate, and a dielectric layer located between the upper and lower plates. Adjacent transistors may share the upper plate, thereby increasing the area of ​​the storage structure and thus improving the charge storage capacity of the semiconductor structure.

[0093] Continue to refer to Figure 15 , Figure 18 and Figure 23After forming the capacitor 116, a planarization layer 119 can be formed on the array region 10 and the peripheral region 20. The planarization layer 119 covers the capacitor and the second conductive structure 105. The first plug 117 is located in the planarization layer 119. The first plug 117 is located on the array region 10 and the peripheral region 20. The first plug 117 located on the array region 10 is electrically connected to the capacitor. The portion of the first plug 117 located on the peripheral region 20 is electrically contacted with the second conductive structure 105. The portion of the first plug 117 located on the peripheral region 20 is electrically contacted with the first conductive structure 103.

[0094] By providing two stacked plug structures, a first conductive structure 103 and a second conductive structure 105, on the outer perimeter region 20, the first plug 117 can make electrical contact with the second conductive structure 105, so as to be electrically connected to the first conductive structure 103 through the second conductive structure. In this way, the length of the first plug 117 can be reduced, thereby ensuring that the height difference between the first plug 117 synchronously formed on the array region 10 and the first plug 117 on the outer perimeter region 20 is small, and improving the yield of forming the first plug 117.

[0095] The planarization layer 119 can be a single film layer or a stacked structure of multiple film layers. By setting the planarization layer 119 to have multiple film layers, it is beneficial to control the etching time of the planarization layer 119 to prepare the groove to accommodate the first plug 117, thereby improving the groove accuracy. The material of the planarization layer 119 can be one or more of the following materials: silicon nitride, silicon oxynitride, silicon carbide, or hard mask. The material of the first plug 117 can be at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0096] The semiconductor structure manufacturing method provided in the above-disclosed embodiments, by forming a dielectric stack 104, wherein the materials of adjacent films in the dielectric stack 104 are different, is beneficial to improving the etching accuracy of the first groove 200 formed by etching. Thus, the first portion 205 formed in the first groove 200 has a better morphology. Furthermore, based on the etching load effect, the patterning of the dielectric stack 104 on the peripheral region 20 and the removal of the dielectric stack 104 on the array region 10 can be performed in the same process step. This simplifies the process steps for manufacturing the semiconductor structure, reduces process complexity, and improves the dielectric stack on the array region 10. After 104 is completely removed, at least a portion of the dielectric stack 104 remains on the outer region 20 opposite the removed dielectric stack 104. The top surface of this portion of the dielectric stack 104 is higher than the top surface of the first conductive structure 103, which can protect the first conductive structure 103 from corrosion, thereby improving the yield of the formed semiconductor structure. Furthermore, the material of the second dielectric layer 204, which is the bottom layer of the dielectric stack 104, is the same as the material of the first dielectric layer 101, which helps to improve the adhesion between the first dielectric layer 101 and the second dielectric layer 204 and ensures the structural stability of the second conductive structure 105.

[0097] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and a first dielectric layer located on the substrate, the substrate including an array region and a peripheral region located around the array region, the first dielectric layer being located on the array region and the peripheral region; A capacitive contact structure is located in the first dielectric layer on the array region, and the first dielectric layer exposes the top surface of the capacitive contact structure. A first conductive structure is located on the first dielectric layer on the peripheral region; A dielectric stack, comprising at least a second dielectric layer and a third dielectric layer, wherein the second dielectric layer covers the first dielectric layer on the peripheral region and is located between adjacent first conductive structures, and the third dielectric layer covers a portion of the second dielectric layer; wherein the material of the first dielectric layer is the same as the material of the second dielectric layer, and the material of the second dielectric layer is different from the material of the third dielectric layer; The second conductive structure is located on the peripheral region. The second conductive structure includes a first part and a second part connected to each other. The first part penetrates the dielectric stack and is in electrical contact with the top surface of the first conductive structure. The second part is located on a portion of the third dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the third dielectric layer is higher than the top surface of the second dielectric layer not covered by the second part, and the top surface of the second dielectric layer not covered by the second part is higher than the top surface of the first conductive structure.

3. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the third dielectric layer is flush with the top surface of the second dielectric layer that is not covered by the second part; the material of the second dielectric layer includes nitrides.

4. The semiconductor structure according to claim 3, characterized in that, The third dielectric layer covers the entire top surface of the second dielectric layer, wherein the top surface of the third dielectric layer not covered by the second part is lower than the bottom surface of the second part.

5. The semiconductor structure according to claim 1, characterized in that, The dielectric stack further includes a fourth dielectric layer located between the third dielectric layer and the second part, wherein the material of the fourth dielectric layer is different from that of the third dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: A capacitor that is in contact with the top surface of the capacitor contact structure.

7. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region located around the array region, a first dielectric layer is formed on the array region and the peripheral region, a capacitive contact structure is formed in the first dielectric layer on the array region, and the first dielectric layer exposes the top surface of the capacitive contact structure, and a first conductive structure is formed on the first dielectric layer on the peripheral region. A dielectric stack is formed, the dielectric stack including at least a second dielectric layer and a third dielectric layer, the second dielectric layer being located between the first dielectric layer and the third dielectric layer and filling the gap between adjacent first conductive structures; wherein, the material of the second dielectric layer is the same as the material of the first dielectric layer, and the material of the second dielectric layer is different from the material of the third dielectric layer; The dielectric stack on the peripheral region is graphically represented to form a first groove, the bottom of which exposes the first conductive structure. A conductive layer is formed, which covers the top surface of the dielectric stack and fills the first groove; The conductive layer and the third dielectric layer on the peripheral region are graphically represented, and the conductive layer and the dielectric stack on the array region are removed to form a second groove in the third dielectric layer. The conductive layer in the first groove is retained as a first part, and the conductive layer on the top surface of the remaining dielectric stack is retained as a second part. The first part and the second part are connected to form a second conductive structure.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The step of graphically representing the conductive layer and the third dielectric layer on the peripheral region further includes: graphically representing the second dielectric layer on the peripheral region, wherein the bottom surface of the second groove is located in the second dielectric layer, and the bottom surface of the second groove is higher than the top surface of the first conductive structure.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The material of the second dielectric layer includes nitride; the steps of forming the second groove and the second conductive structure include: patterning the conductive layer and the third dielectric layer on the peripheral region, and removing the conductive layer and the third dielectric layer on the array region; The second dielectric layer on the array region is removed using phosphoric acid.

10. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The dielectric stack further includes a fourth dielectric layer, which covers the top surface of the third dielectric layer, and the material of the fourth dielectric layer is different from that of the third dielectric layer. The steps of forming the second groove and the second conductive structure further include: patterning the fourth dielectric layer on the peripheral region and removing the fourth dielectric layer on the array region.

11. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, Also includes: A capacitor is formed, and the capacitor is in contact with the top surface of the capacitor contact structure.

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