A field effect transistor device and a manufacturing method thereof

Abstract

A field-effect transistor device and a manufacturing method thereof. The present invention relates to power semiconductor devices. To overcome existing problems, the present invention provides a first region and a second region in the device. The first region includes a second-conductivity-type doped body region, a first source region, a second-conductivity-type heavily doped contact doping region, a first doping region, and a contact hole trench; the second region includes a second-conductivity-type doped body region and a first-conductivity-type heavily doped second doping source region. The present invention proposes a shielded gate trench-type field-effect transistor device structure and a manufacturing process flow, which can achieve a smaller cell size, have a lower on-resistance, and better switching threshold uniformity.

Description

Technical Field

[0001] The present invention relates to power semiconductor devices, and particularly to a shielded gate trench field effect transistor device with a small cell size and a manufacturing method thereof. Background Art

[0002] The shielded gate trench field effect transistor has the characteristics of low on-resistance and fast switching speed. An existing shielded gate trench field effect transistor structure is as shown in Figure 1 and Figure 2 shown. Figure 1 FIG. is a schematic structural diagram of a conventional N-type shielded gate trench field effect transistor. The device structure includes: an N-type semiconductor 100; a series of cell trenches 101 located in the N-type semiconductor 100. The cell trenches 101 are filled with a gate electrode 110 located above and a shielded gate electrode 120 located below. Among them, the gate electrode 110 and the corresponding trench sidewall are isolated by a gate oxide layer; the shielded gate electrode 120 and the corresponding trench sidewall are isolated by a trench oxide layer; the gate electrode 110 and the shielded gate electrode 120 are isolated by an inter-pole isolation oxide layer. The structure further includes a P-doped body region 103 and an N+-doped source region 104 located on the upper surface of the semiconductor between the cell trenches 101; in addition, between the cell trenches 101, there are also a series of contact hole trenches 102, and a P+-contact doped region 105 located below the source contact hole trenches 102. The source contact hole trenches 102 are covered with an upper surface metal layer, which is not shown in the figure.

[0003] In order to further reduce the on-resistance of the shielded gate trench field effect transistor, it is necessary to reduce the cell size of the device and increase the cell density of the device. However, in the manufacturing process of the above-mentioned shielded gate trench field effect transistor, the cell size is limited by the lithography process. As shown in Figure 1 shown, the cell trenches 101 and the source contact hole trenches 102 are formed by two successive lithographies respectively. Limited by the accuracy of the lithography process and the alignment deviation of the two lithographies, the distance between the cell trenches 101 and the source contact hole trenches 102 is likely to be too close, resulting in the P+-contact doped region 105 formed below the source contact trench affecting the doping concentration of the channel region of the corresponding cell trench, and further affecting the on-resistance and switching threshold of the device. Therefore, an appropriate safety distance needs to be left between the cell trenches 101 and the source contact hole trenches 102 in the above structure, and this safety distance limits the further reduction of the cell size. Figure 2 FIG. is a schematic structural diagram of an existing improved N-type shielded gate trench field effect transistor. And Figure 1Compared with the structure, the source contact hole trench 102 is formed in a self-aligned manner by using a pre-formed hard mask insulating layer 111. This structure can solve the limitation of lithography accuracy on the cell size. However, there are still the following problems in this structure: the morphology of the N+ doped source region 104 results in a relatively large contact resistance formed with the metal in the contact hole; in addition, Figure 2 In the device structure, the distance from the P+ contact doped region 105 to the adjacent cell trench can be adjusted by increasing the etching angle and depth of the contact hole trench 102 to avoid affecting the doping concentration in the channel region. However, as the cell size is reduced, the corresponding contact hole trench opening becomes narrower, making the above method difficult to implement. Therefore, it is difficult to avoid the P+ contact doped region 105 from affecting the doping concentration in the channel region, resulting in an increase in the on-resistance of the device (especially the on-resistance at a low switching threshold) and a deterioration in the uniformity of the switching threshold. Summary of the Invention

[0004] One object of the present invention is to provide a field effect transistor device, which includes a first conductive type epitaxial layer, a series of cell trenches located in the first conductive type epitaxial layer, a shielding gate electrode isolated from each other in the cell trenches, a gate electrode located above the shielding gate electrode, and an upper surface metal located at the top of the device; a first region and a second region alternately arranged above the semiconductor between the cell trenches, the first region including a second conductive type doped body region, a first conductive type heavily doped first source region located on both sides of the cell trench and deeper than the gate electrode above the second conductive type doped body region, a second conductive type heavily doped contact doped region located between the left and right first conductive type heavily doped first source regions, and a contact hole trench located above the first conductive type heavily doped first doped region and the second conductive type heavily doped contact doped region; the second region includes a second conductive type doped body region and a first conductive type heavily doped second doped source region located on both sides of the cell trench and deeper than the gate electrode above the second conductive type doped body region; the first conductive type heavily doped first source region and the first conductive type heavily doped second source region are connected, and the second conductive type heavily doped contact doped region, the first conductive type heavily doped first source region, and the first conductive type heavily doped second source region are connected to the upper surface metal through ohmic contacts.

[0005] Preferably, the first conductive type heavily doped second source region is in a "gate" shape, and adjacent contact hole trenches are separated by the upper part of the "gate" shape of the first conductive type heavily doped second source region.

[0006] Preferably, the contact hole trench is an inverted trapezoid with a larger upper part and a smaller lower part.

[0007] Preferably, a depth h1 of the discontinuous contact hole trench from the upper surface of the semiconductor is shallower than a height h2 of the upper surface of the gate electrode.

[0008] Preferably, the length L1 of the contact hole trench along the cell trench direction is between 0.1um and 1um, and the distance between adjacent contact hole trenches is between 0.05um and 0.5um.

[0009] Preferably, the concentration of the first source region heavily doped with the first conductivity type decreases with the distance away from the cell trench and the lowest concentration is not less than 10 18 cm -3 .

[0010] Preferably, the depth of the heavily doped contact region of the second conductivity type is shallower than that of the heavily doped first source region of the first conductivity type.

[0011] Preferably, a first conductivity type channel stop region is provided below the second conductivity type doped body region and close to the trench sidewall, and the doping concentration of the first conductivity type channel stop region is higher than the doping concentration of the first conductivity type epitaxial layer.

[0012] Another object of the present invention is to provide a method for manufacturing a field effect transistor device, the method comprising the following steps:

[0013] The first step is to form a series of cell trenches and a shielding gate insulating layer, a shielding gate electrode, an electrode isolation layer in the trenches, and a gate oxide layer located on the sidewalls above the cell trenches on the first conductive type semiconductor;

[0014] The second step is to fill the trench with gate material and etch it back into the cell trench to form a gate electrode;

[0015] The third step is to form a second conductivity type doped body region and a first conductivity type heavily doped source region in a gate shape on the upper surface of the semiconductor and between the cell trenches;

[0016] Step 4: forming an insulating filling layer material in the trench;

[0017] Step 5: etching back the insulating filling layer material to the upper surface of the semiconductor and exposing the first conductivity type heavily doped source region;

[0018] Step 6: Etching a discontinuous contact hole trench and forming a second conductivity type heavily doped contact doped region in the contact hole trench. After etching, the upper surface of the gate-shaped first conductivity type heavily doped source region is partially etched, leaving a small section on both sides of the cell trench. After etching the contact hole trench, the second conductivity type doped body region located between the first conductivity type heavily doped source regions is exposed.

[0019] The seventh step is to form surface metal and finally form the device.

[0020] Preferably, in the first step, a channel cutoff region of the first conductivity type is formed on the semiconductor near the electrode isolation layer.

[0021] Preferably, in the third step, before performing ion implantation to form the dopant region of the second conductivity type and the heavily doped source region of the first conductivity type, thermal oxidation is performed and the oxide layer is etched back to form an enlarged trench opening.

[0022] Another object of the present invention is to provide a method for manufacturing a field effect transistor device, and the manufacturing method includes the following steps:

[0023] In the first step, a series of cell trenches, a shielding gate insulating layer, a shielding gate electrode, an electrode isolation layer in the trenches, and a gate oxide layer on the sidewalls above the cell trenches are respectively formed on the semiconductor of the first conductivity type; a polishing stop layer is formed on the upper surface of the semiconductor;

[0024] In the second step, the trench is filled with gate material and etched back into the cell trench to form a gate electrode;

[0025] In the third step, a dopant region of the second conductivity type is formed on the upper surface of the semiconductor, and a heavily doped first source region of the first conductivity type is formed on the sidewalls of the cell trenches;

[0026] In the fourth step, an insulating filling layer material is formed in the trench and chemical mechanical polishing is performed until reaching the polishing stop layer;

[0027] In the fifth step, the polishing stop layer is removed, and a heavily doped ion implantation of the first conductivity type in the vertical direction is performed to form a heavily doped second source region of the first conductivity type in a gate shape;

[0028] In the sixth step, photolithography is performed, and discontinuous contact hole trenches are etched under the protection of the photoresist, and a contact doping region of the second conductivity type is formed in the contact hole trenches;

[0029] In the seventh step, surface metal is formed, and finally the device is formed.

[0030] Preferably, when etching the discontinuous contact hole trenches in the sixth step, discontinuous contact hole trenches with a larger upper part and a smaller lower part are etched.

[0031] Preferably, the depth of the heavily doped source region of the first conductivity type is adjusted by adjusting the height of the gate electrode in the cell trench.

[0032] The present invention provides a shielding gate trench type field effect transistor device structure and manufacturing process flow, which can achieve a smaller cell size, have a lower on-resistance, and better switching threshold uniformity. Description of the Drawings

[0033] Figure 1It is a schematic structural diagram of a traditional shield-gate trench MOSFET device after removing the surface metal.

[0034] Figure 2 It is a schematic structural diagram of an existing shield-gate trench MOSFET device after removing the surface metal.

[0035] Figure 3 It is a schematic structural diagram of the first embodiment of the device of the present invention.

[0036] Figure 4 and 5 It is a schematic structural diagram of the first embodiment of the device of the present invention after removing the surface metal.

[0037] Figure 6 It is a schematic diagram of setting a channel cutoff region in the device.

[0038] Figures 7-13 It is a cross-sectional schematic diagram of the key steps of the manufacturing process of an embodiment of the device of the present invention above. Figures 14-18 It is a cross-sectional schematic diagram of the key steps of the manufacturing process of another embodiment of the device of the present invention.

[0039] Figure 19 It is a cross-sectional schematic diagram after non-continuous contact hole trench etching in the key steps of the manufacturing process of an embodiment of the device of the present invention above.

[0040] Figure 20 It is a cross-sectional schematic diagram of different N+ doped source region structures formed corresponding to different gate electrode heights in the key steps of the manufacturing process of an embodiment of the device of the present invention above. Detailed implementation manners

[0041] The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that in the following description of the shielded gate trench type field effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench type field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for manufacturing the shielded gate trench type field effect transistor, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into a second conductivity type (such as P-type) and a first conductivity type (such as N-type). A semiconductor region with a P-type conductivity type can be formed by doping one or several impurities into the original semiconductor region, and these impurities can be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), etc.; a semiconductor region with an N-type conductivity can also be formed by doping one or several impurities into the original semiconductor region, and these impurities can be, but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H+), etc. In the following description, the heavily doped P-type conductive semiconductor region is marked as the P+ region, and the heavily doped N-type conductive semiconductor region is marked as the N+ region. For example, in a silicon material substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally between 1×10 19 cm -3 and 1×10 22 cm -3 . Those skilled in the art should know that the P-type (second conductivity type) and N-type (first conductivity type) described in the present invention can be interchanged.

[0042] The corresponding position words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "vertical" described in this document are relative positions corresponding to the reference drawings. The specific implementation does not limit the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to scale, and the straight lines shown by the boundaries of the doped regions and trenches in the drawings, as well as the sharp corners formed by the boundaries, are generally not straight lines and precise angles in practical applications.

[0043] Figure 3 is a schematic structural diagram of the first embodiment of the device of the present invention. Among them, Figure 4 and 5 are respectively Figure 3 schematic structural diagrams of different cross-sections of the device after removing the surface metal.

[0044] As Figure 3 shown, the semiconductor field effect transistor device includes: a series of mutually parallel cell trenches 201 located on the N-type semiconductor 200; a P-doped body region 203 on the upper surface of the semiconductor between the cell trenches;

[0045] Among them, in the cell trench 201, there are a gate electrode 210 and a shield gate electrode 220 that are isolated from each other, and an insulating filling layer 211 is provided above the gate electrode 210 in the cell trench 201;

[0046] The device further includes a series of discontinuous contact hole trenches 202 located between the series of cell trenches 201. Marked by the presence or absence of the contact hole trenches 202, it is divided into two regions:

[0047] In the first region, below the discontinuous contact hole trenches 202, there are N+ doped source regions 204 (first) located on both sides of the cell trench 201, and a P+ contact doped region 205 located between the left and right N+ doped source regions 204, as Figure 4 shown.

[0048] In addition, in the second region, on the upper surface of the semiconductor between the cell trenches 201 between two adjacent discontinuous segments of the contact hole trenches 202, there is a gate-shaped N+ doped source region 204 (second), as Figure 5 shown. Among them, the depth h3 of the gate-shaped N+ doped source region 204 near the cell trench 201 is deeper than the upper surface depth h2 of the gate electrode 210 (h3 > h2).

[0049] The first N+ doped source region 204, the P+ contact doped region 205 below the contact hole trenches 202, and the gate-shaped second N+ doped source region 204 at the discontinuous part of the contact hole trenches are all connected to the upper surface metal through ohmic contacts.

[0050] In an actual embodiment, the width of the discontinuous contact hole trenches 202 is usually the width between the cell trenches 201 and is perpendicular to the upper surface of the semiconductor. In some embodiments, the discontinuous contact hole trenches 202 may also be trapezoidal with a larger upper part and a smaller lower part. The depth h1 of the discontinuous contact hole trenches 202 from the upper surface of the semiconductor is usually shallower than the upper surface height h2 of the gate electrode 210 (h1 < h2), and is between 0.1 and 1 um (h1) from the upper surface of the semiconductor.

[0051] The length L1 of the discontinuous contact hole trenches 202 in the direction of the cell trench is usually between 0.1 um and 1 um. The length L2 of the discontinuous part between two adjacent contact hole trenches 202 is usually between 0.05 um and 0.5 um, as Figure 5 .

[0052] The doping concentration of the first N+ doped source region 204 located on both sides of the cell trench 201 below the contact hole trenches 202 near the cell trench 201 may be 10 21 cm -3Above. In one embodiment, the concentration of the first N+ doped source region 204 decreases with the distance away from the cell trench 201, and the lowest concentration is not less than 10 18 cm -3 .

[0053] The P+ contact doped region 205 located below the contact hole trench 202 has a doping source region concentration of not less than 10 18 cm -3 . The depth of the P+ contact doped region 205 is usually shallower than that of the N+ doped source region 204, but in some embodiments, it can also be deeper than the N+ doped source region 204.

[0054] When the above device conducts forward, at the Figure 5 cross-section, the N+ doped source region 204 forms a large-area contact with the metal on the upper surface of the semiconductor, which can effectively reduce the ohmic contact resistance and current diffusion resistance of the N+ doped source region 204. The N+ doped source region 204 on the sidewall of the cell trench 201 forms a channel under a positive gate voltage, and the channel is not affected by the P+ contact doped region 205 in the horizontal direction. At the Figure 4 cross-section, the distance from the P+ contact doped region 205 under the discontinuous contact hole trench 202 to the adjacent channel can be adjusted by adjusting the distance L2 of the discontinuous segment of the discontinuous contact hole trench and the width of the N+ doped source region 204 on the sidewall of the cell trench. The influence of the P+ contact doped region 205 on the doping concentration of the channel can be well controlled. Therefore, the switching threshold uniformity of the above device is better than that of the traditional structure, and a lower on-resistance can be effectively achieved.

[0055] In one embodiment, an N-type channel cutoff region 223 may be provided directly below the P-doped body region 203 or near the trench sidewall below the P-doped body region 203, as Figure 6 shown. The doping concentration of the N-type channel cutoff region 223 is higher than that of the N-type epitaxial layer 200, which can reduce the channel length, reduce the on-resistance of the device, and enhance the UIS performance of the device.

[0056] The following shows the key steps of a manufacturing method of the device in the Figures 3-5 embodiment, as Figures 7 to 13 shown.

[0057] First step, a series of cell trenches 201 are formed on the N-type semiconductor, and then a shield gate insulating layer 218, a shield gate electrode 220, an electrode isolation layer 217 located above the shield gate electrode, and a gate oxide layer 219 located at the upper sidewall of the cell trench are formed. As Figure 7 shown.

[0058] Generally, the above-mentioned cell trenches 201 are arranged in parallel, and the trench width may be between 0.3 um and 0.8 um. The width between trenches is between 0.1 um and 0.6 um.

[0059] The shielding gate insulating layer 218 may be composed of an oxide or a combined layer of an oxide and a nitride, and is formed by thermal oxidation or chemical vapor deposition.

[0060] The shielding gate electrode 220 may be composed of polysilicon or other easily fillable metals such as titanium, tungsten or their alloys.

[0061] The electrode isolation layer 217 may be formed by thermal oxidation or may be formed by multiple steps of thermal oxidation and chemical vapor deposition. In one embodiment, the thickness of the electrode isolation layer 217 is between 0.1 um and 0.4 um. In one embodiment, the formation step of the electrode isolation layer 217 includes at least one step of high-density plasma chemical vapor deposition (HDP CVD) of an oxide.

[0062] The gate oxide layer 219 is usually formed by thermal oxidation, and the thickness of the gate oxide layer is usually determined by the switching threshold of the device. In an embodiment of a device with a switching threshold of 3V, the thickness of the gate oxide layer is between 450 Å and 1000 Å.

[0063] In a variant embodiment, an N-type channel cutoff region 223 may be formed on the semiconductor near the electrode isolation layer 217. The formation method may be dopant diffusion or N+ ion implantation with an inclined angle. The N-type channel cutoff region 223 can limit and shorten the depth of the P-doped body region 203 formed in subsequent processes.

[0064] In the second step, the trench is filled with gate material and etched back into the cell trench to form the gate electrode 210. As Figure 8 shown.

[0065] The etch-back depth of the gate material is between 0.1 um and 0.5 um. A series of shallow trenches are formed above the cell trench after etch-back.

[0066] The gate material is usually polysilicon and is etched back by dry etching. This dry etching may be carried out in a Cl2 + HBr or SF6 + O2 environment.

[0067] The gate material may also be other easily fillable metals such as titanium, tungsten or their alloys.

[0068] In the third step, a P-doped body region 203 and an N+-doped source region 204 with a gate shape are formed on the upper surface of the semiconductor, as Figure 9 shown.

[0069] The P-doped body region 203 is formed by P-type ion implantation with an implantation energy between 50 keV and 300 keV. After ion implantation, thermal diffusion at 800 - 1100 °C may be carried out to adjust the depth of the P-doped body region.

[0070] The N+-doped source region 204 may be formed by N+ ion implantation with an inclined angle, and the implantation energy is between 10 keV - 80 keV. The inclined angle depends on the topography of the shallow trench during ion implantation and is usually between 20 degrees and 70 degrees. The dopant for N+ ion implantation is usually As. In some embodiments, the ion implantation dopant may also be Sb to reduce the diffusion depth of the N+-doped source region during subsequent thermal processes.

[0071] In one embodiment, before ion implantation, the gate oxide layer on the surface may be further etched to reduce its thickness.

[0072] After N+ ion implantation, a rapid thermal annealing process may be carried out in one step.

[0073] In a variant embodiment, first, N+ ion implantation with an inclined angle is carried out to form a gate-shaped N+-doped source region 204, and then an additional N+ ion implantation with a vertical angle is carried out. The above process can deepen the doping region of the N+-doped source region near the upper surface of the semiconductor, which is beneficial to reducing the on-resistance.

[0074] In a variant embodiment, before ion implantation to form the P-doped body region and the N+-doped source region, first, a thermal oxidation is carried out, and then the oxide layer is etched back to form an enlarged trench opening. The above process is beneficial to adjusting the width 202 of the contact hole trench in the subsequent process.

[0075] In the fourth step, an insulating filling layer material 211 is formed in the trench, such as Figure 10 shown.

[0076] The insulating filling layer material may be an oxide layer, a nitride, BPSG, or a combination layer.

[0077] In the fifth step, the insulating filling layer material 211 is etched back to the upper surface of the semiconductor, and the N+-doped source region 204 is exposed, such as Figure 11 shown.

[0078] The etching-back method may be wet etching, dry etching, or chemical mechanical polishing (CMP). In an actual embodiment, the insulating filling layer material 211 is an oxide, and the etching-back process first performs CMP and then wet etching.

[0079] In the sixth step, photolithography is carried out to etch out discontinuous contact hole trenches 202 under the protection of the photoresist 230, and P+ contact doping regions 205 are formed in the contact hole trenches. As Figure 12, as shown in FIG. 13, wherein Figure 12 is the cross-section of the etched contact hole trench, Figure 13 is the cross-section at the photoresist 230 protection layer.

[0080] The etching method of the discontinuous contact hole trench 202 is usually dry etching, but wet etching can also be used. The etching depth is higher than the upper surface height of the gate electrode. After etching, the upper surface part of the N+-doped source region 204 in the shape of a Chinese character 'door' is etched, and a small section remaining on both sides of the cell trench is left. After the contact hole trench is etched, the P-type body region 203 located between the N+-doped source regions is exposed.

[0081] In one embodiment, the photoresist is a series of long strips located on the upper surface, and is arranged in a direction perpendicular to the cell trench.

[0082] The P+-contact doped region 205 is usually formed by one or more ion implantations at a vertical angle on the P-type body region 203 exposed in the contact hole trench. The dopant for this ion implantation is usually BF2.

[0083] In a variant embodiment, the etching of the discontinuous contact hole trench 202 does not rely on the photoresist as the etching protection layer, but uses a photolithography method to pre-form a hard mask layer, and then performs trench etching under this hard mask layer. The hard mask layer may be an oxide layer or a nitride layer.

[0084] The seventh step is to form the surface metal and finally form the device.

[0085] The device of the present invention is not limited to the above manufacturing process. The following introduces the key steps of another manufacturing method of the device of the present invention, as Figures 14 to 18 shown.

[0086] The first step is as in the above Figure 7 steps. On the N-type semiconductor, a series of cell trenches 201 are respectively formed, and then a shielding gate insulating layer 218, a shielding gate electrode 220, an electrode isolation layer 217 located above the shielding gate electrode, and a gate oxide layer 219 located at the upper sidewall of the cell trench are formed. In addition, a polishing stop layer 224 is formed on the upper surface of the semiconductor.

[0087] The polishing stop layer 224 may be formed before the cell trenches 201 are formed, as a hard mask for the cell trench etching, and remains on the upper surface of the semiconductor. A feasible method is as shown in the process flow of patent CN113990755B.

[0088] The polishing stop layer 224 may also be formed by deposition, photolithography and other methods before and after the shielding gate electrode 220 is formed. A feasible method is as shown in the process flow of patent CN111415992B.

[0089] The polishing stop layer 224 may be a nitride layer with a thickness between 500 Å and 4000 Å.

[0090] In some embodiments, there may be an oxide layer between the polishing stop layer 224 and the upper surface of the semiconductor.

[0091] In the second step, the gate material is filled in the trench and then etched back into the cell trench to form the gate electrode 210. Figure 15 shown.

[0092] In some embodiments, before filling the gate material, the grinding barrier layer 224 may be etched in advance to adjust the length of the grinding barrier layer 224 to expand the trench opening and prevent voids from occurring during filling.

[0093] In the third step, a P-doped body region 203 and an N+-doped source region 204 are formed on the upper surface of the semiconductor. Figure 16 shown.

[0094] The above steps and Figure 9 The steps are the same as those in FIG. 2 , but because the polishing barrier layer 224 on the semiconductor surface blocks some of the vertical ion implantation, an ion implantation process with an inclined angle is usually required. Under the protection of the polishing barrier layer 224, the N+ doped source region 204 formed by ion implantation is located on the sidewalls of the cell trench.

[0095] In some embodiments, before ion implantation, the polishing stop layer 224 may be etched in advance to adjust the length of the polishing stop layer 224 so as to adjust the ion implantation area.

[0096] In some embodiments, etching may be performed before ion implantation to adjust the length of the polishing stop layer 224 and thus adjust the ion implantation area.

[0097] In the fourth step, an insulating filling layer material 211 is formed in the trench and chemical mechanical polishing is performed until the insulating filling layer 211 is polished onto the polishing barrier layer 224. Figure 17 shown.

[0098] In one embodiment, the insulating filling layer material 211 is oxide and is formed by a high density plasma chemical vapor deposition (HDP CVD) process.

[0099] The fifth step is to remove the grinding barrier layer 224 and perform vertical N+ ion implantation to form a gate-shaped N+ doped source region. Figure 18 shown.

[0100] This N+ ion implantation may have a higher energy and a deeper implantation depth than the ion implantation for forming the N+ doped source region in the third step. In some embodiments, the dopant of this N+ ion implantation may be different from that of the ion implantation for forming the N+ doped source region in the third step. For example, the dopant of the N+ ion implantation in the third step is Sb, and the dopant of the N+ ion implantation in the fifth step is As.

[0101] In some embodiments, before removing the polishing stop layer 224, the insulating fill layer material 211 may be etched first to the height of the semiconductor upper surface.

[0102] In some embodiments, before removing the polishing stop layer 224 and performing ion implantation, a thin oxide layer may be pre-formed on the semiconductor surface.

[0103] The sixth step is to perform photolithography to etch out discontinuous contact hole trenches 202 under the protection of the photoresist 230, and form P+ contact doped regions 205 in the contact hole trenches.

[0104] The seventh step is to form the surface metal and finally form the device.

[0105] The above process flow forms a gate-shaped N+ doped source region in two steps, which can independently adjust the N+ doping concentration and depth at the semiconductor upper surface and near the channel, facilitating better adjustment of the ohmic resistance formed between the N+ doped source region upper surface and the metal, the current diffusion resistance in the N+ doped source region, and the channel resistance, so as to optimize the on-resistance of the device. Moreover, the method of chemical mechanical polishing in the fourth step can ensure that the depth of the subsequent contact hole trenches is more uniform, which is beneficial to process control.

[0106] In the process flow of the embodiments of the present invention, when etching the discontinuous contact hole trenches 202 in the sixth step, it is possible to etch out a series of trenches with a larger upper part and a smaller lower part. For example, in Figure 18 's structure, after ion implantation, using the insulating fill layer material 211 as a hard mask and using photoresist, discontinuous contact hole trenches with a larger upper part and a smaller lower part are etched out, as shown in Figure 19 . For the trenches with a larger upper part and a smaller lower part, the sidewall etching angle is usually between 70 degrees and 90 degrees, which is beneficial to forming deeper trenches and enhancing the UIS ability of the device.

[0107] In the process flow of the embodiments of the present invention, the N+ doped source region 204 is usually formed by ion implantation with an inclined angle, and its depth is related to the height of the upper surface of the adjacent gate electrode 210. In some embodiments, different-height gate electrode morphologies may be formed in the cell trenches by etching or other means to adjust the depth of the N+ doped source region 204 in different regions of the chip, such as Figure 20Cross-sections of different locations are shown, where the gate electrode 210 in the cross-section of the left figure is higher than that in the cross-section of the right figure. In the schematic diagram of the cross-section of the left figure, the gate electrode 210 is located slightly below the upper surface of the semiconductor. After the inclined-angle ion implantation, a shallower N+ doped source region 204 is formed. In some embodiments, there is a polishing stop layer 224 at the upper surface of the semiconductor to block ion implantation. Cooperating with the higher gate electrode 210, it can further limit the N+ ion implantation. The above-mentioned shallower N+ doped source region 204 may be completely removed in subsequent oxidation or etching processes. The shallower or completely removed N+ doped source region 204 can reduce the possibility of the parasitic triode conduction, which is beneficial to enhancing the UIS capability of the non-active region of the chip. In some embodiments, the higher gate electrode 210 may be connected to the gate metal located on the upper surface.

[0108] Those skilled in the art should know that the structural features and process step details mentioned in the above embodiments of the present invention can be combined with each other to form more device structures and manufacturing processes of embodiments.

Claims

1. A field effect transistor device, the device comprising an epitaxial layer of a first conductivity type, a series of cell trenches located within the epitaxial layer of the first conductivity type, a shield gate electrode isolated from each other within the cell trenches, a gate electrode located above the shield gate electrode, and an upper surface metal located at the top of the device; characterized in that, A first region and a second region which are alternately arranged above the semiconductor between the cell trenches. The first region includes a second-conductivity-type dopant region, a first-conductivity-type heavily doped first source region which is located above the second-conductivity-type dopant region on both sides of the cell trench and has a depth exceeding that of the gate electrode, a second-conductivity-type heavily doped contact doping region located between the two left and right first-conductivity-type heavily doped first source regions, and a contact hole trench located above the first-conductivity-type heavily doped first doping region and the second-conductivity-type heavily doped contact doping region; the second region includes a second-conductivity-type dopant region and a first-conductivity-type heavily doped second doping source region which is located above the second-conductivity-type dopant region on both sides of the cell trench and has a depth exceeding that of the gate electrode; the first-conductivity-type heavily doped first source region and the first-conductivity-type heavily doped second source region are connected, and the second-conductivity-type heavily doped contact doping region, the first-conductivity-type heavily doped first source region, and the first-conductivity-type heavily doped second source region are connected to the upper surface metal through an ohmic contact. The first-conductivity-type heavily doped second source region is in a "gate" shape, and adjacent contact hole trenches are separated by the upper part of the "gate" shape of the first-conductivity-type heavily doped second source region.

2. The field effect transistor device according to claim 1, wherein The contact hole trench is an inverted trapezoid with a larger upper part and a smaller lower part.

3. The field effect transistor device according to claim 1, wherein The depth h1 of the discontinuous contact hole trench from the upper surface of the semiconductor is shallower than the upper surface height h2 of the gate electrode.

4. The field effect transistor device according to claim 1, wherein, The length L1 of the contact hole trench in the direction of the cell trench is between 0.1 um and 1 um, and the separation distance between adjacent contact hole trenches is between 0.05 um and 0.5 um.

5. The field effect transistor device according to claim 1, characterized in that, The concentration of the heavily doped first source region of the first conductivity type decreases with the distance from the cell trench, and the lowest concentration is not less than 10 18 cm -3 .

6. The field effect transistor device according to claim 1, wherein The depth of the second-conductivity-type heavily doped contact doping region is shallower than that of the first-conductivity-type heavily doped first source region.

7. The field effect transistor device according to claim 1, wherein A first-conductivity-type channel cutoff region is provided near the trench sidewall below the second-conductivity-type dopant region, and the doping concentration of the first-conductivity-type channel cutoff region is higher than that of the first-conductivity-type epitaxial layer.

8. The method for manufacturing a field effect transistor device according to any one of claims 1-7, characterized in that, The manufacturing method includes the following steps: In the first step, a series of cell trenches, a shielding gate insulating layer, a shielding gate electrode, an electrode isolation layer in the trenches, and a gate oxide layer at the upper sidewall above the cell trenches are respectively formed on the first-conductivity-type semiconductor. In the second step, a gate material is filled in the trenches and etched back into the cell trenches to form gate electrodes. In the third step, a second-conductivity-type dopant region and a first-conductivity-type heavily doped source region with a gate shape are formed on the upper surface of the semiconductor between the cell trenches. In the fourth step, an insulating filling layer material is formed in the trenches. In the fifth step, the insulating filling layer material is etched back to the upper surface of the semiconductor, and the first-conductivity-type heavily doped source region is exposed. In the sixth step, discontinuous contact hole trenches are etched, and a second-conductivity-type heavily doped contact doping region is formed in the contact hole trenches. After etching, the upper surface part of the first-conductivity-type heavily doped source region in the "gate" shape is etched, and a small section on both sides of the cell trench remains. After the contact hole trenches are etched, the second-conductivity-type dopant region located between the first-conductivity-type heavily doped source regions is exposed. In the seventh step, surface metal is formed, and finally a device is formed.

9. The method for manufacturing a field effect transistor device according to claim 8, characterized in that, In the first step, a channel cut-off region of a first conductivity type is formed on the semiconductor near the electrode isolation layer.

10. The method for manufacturing a field effect transistor device according to claim 8, characterized in that, In the third step, before ion implantation is performed to form a dopant region of a second conductivity type and a heavily doped source region of a first conductivity type, thermal oxidation is carried out and the oxide layer is etched back to form an enlarged trench opening.

11. The method for manufacturing a field effect transistor device according to any one of claims 1-7, characterized in that, The manufacturing method described above includes the following steps: In the first step, a series of cell trenches are respectively formed on a semiconductor of a first conductivity type, and a shield gate insulating layer, a shield gate electrode, an electrode isolation layer in the trenches, and a gate oxide layer on the sidewalls above the cell trenches are formed; a polishing stop layer is formed on the upper surface of the semiconductor; In the second step, a gate material is filled in the trenches and etched back into the cell trenches to form gate electrodes; In the third step, a dopant region of a second conductivity type is formed on the upper surface of the semiconductor, and a heavily doped first source region of a first conductivity type is formed on the sidewalls of the cell trenches; In the fourth step, an insulating filling layer material is formed in the trenches and chemical mechanical polishing is carried out until reaching the polishing stop layer; In the fifth step, the polishing stop layer is removed, and a first conductivity type heavy doping ion implantation in the vertical direction is carried out to form a second source region of a first conductivity type in a gate shape; In the sixth step, photolithography is carried out, and discontinuous contact hole trenches are etched under the protection of a photoresist, and a contact doping region of a second conductivity type heavy doping is formed in the contact hole trenches; In the seventh step, a surface metal is formed and finally a device is formed.

12. The method for manufacturing a field effect transistor device according to claim 11, wherein, When etching the discontinuous contact hole trenches in the sixth step, discontinuous contact hole trenches with a larger upper part and a smaller lower part are etched.

13. For the method of manufacturing a field effect transistor device as described in claim 11, the depth of the heavily doped source region of the first conductivity type in the cell trenches is adjusted by adjusting the height of the gate electrode.

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