Voltage monitoring circuit and chip

Abstract

The application relates to a voltage monitoring circuit and chip, and relates to the chip field and is used for realizing higher-precision measurement of the voltage of a monitored power supply. The voltage monitoring circuit comprises a first delay sub-circuit (31), a second delay sub-circuit (32) and an encoding sub-circuit (33). The first delay sub-circuit (31) is used for delaying an inputted periodic flip reference signal by at least one period of the reference signal to obtain a first signal. The second delay sub-circuit (32) comprises a plurality of groups of delay devices (321) connected in series, the plurality of groups of delay devices (321) are powered by the monitored power supply, the first group of delay devices is used for inputting the periodic flip reference signal, and each group of delay devices (321) is used for delaying the inputted signal to output a second signal. The encoding sub-circuit (33) is used for performing exclusive OR operation on the first signal and a plurality of second signals outputted by the plurality of groups of delay devices (321) respectively to output an encoding value corresponding to the voltage of the monitored power supply.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chips, in particular to a voltage monitoring circuit and method. BACKGROUND

[0002] The voltage monitoring circuit in the chip can be used to detect whether the power supply voltage is safe. The voltage monitoring circuit in the chip can only determine whether the voltage of the monitored power supply is higher or lower than the threshold, and cannot provide a higher precision voltage value. SUMMARY

[0003] The embodiment of the present application provides a voltage monitoring circuit and a chip, which are used to realize higher precision measurement of the voltage of the monitored power supply.

[0004] To achieve the above object, the embodiment of the present application adopts the following technical scheme:

[0005] In a first aspect, a voltage monitoring circuit is provided, comprising: a first delay sub-circuit, a second delay sub-circuit and an encoding sub-circuit; the first delay sub-circuit is used to delay an input periodic flip reference signal by at least one period of the reference signal to obtain a first signal; the second delay sub-circuit comprises a plurality of groups of delay devices connected in series, the plurality of groups of delay devices are powered by a monitored power supply, the first group of delay devices is used to input the periodic flip reference signal, and each group of delay devices is used to delay the input signal to output a second signal; and the encoding sub-circuit is used to perform exclusive OR operation on the first signal and a plurality of second signals output by the plurality of groups of delay devices respectively, to output an encoding value corresponding to the voltage of the monitored power supply.

[0006] The voltage monitoring circuit provided by the embodiment of the present application comprises: a first delay sub-circuit, a second delay sub-circuit and an encoding sub-circuit; the first delay sub-circuit is used to delay an input periodic flip reference signal by at least one period of the reference signal to obtain a first signal; the second delay sub-circuit comprises a plurality of groups of delay devices connected in series, the plurality of groups of delay devices are powered by a monitored power supply, the first group of delay devices is used to input the periodic flip reference signal, and each group of delay devices is used to delay the input signal to output a second signal; and the encoding sub-circuit is used to perform exclusive OR operation on the first signal and a plurality of second signals output by the plurality of groups of delay devices respectively, to output an encoding value corresponding to the voltage of the monitored power supply. The distance of the periodic flip reference signal transmitted in the delay chain is different under the condition of different monitored power supply, and the voltage of the monitored power supply is encoded, so that higher precision measurement of the voltage of the monitored power supply can be realized.

[0007] In a possible implementation, the first delay sub-circuit comprises 2N first flip-flops in series, a data input terminal of a first first flip-flop is configured to input the periodic flip reference signal, a data output terminal of a previous first flip-flop is coupled to a data input terminal of a next first flip-flop, a data output terminal of a last first flip-flop is configured to output the first signal, and N is a positive integer. This implementation provides a possible form of the first delay sub-circuit.

[0008] In a possible implementation, the second delay sub-circuit further comprises a plurality of second flip-flops corresponding to the plurality of groups of delay devices respectively, a data input terminal of each second flip-flop is coupled to an output terminal of a corresponding delay device, and a data output terminal of each second flip-flop is configured to output a second signal. The second flip-flop can sample the signal input to the data input terminal D, so as to output a stable signal through the data output terminal Q, thereby preventing the output signal from being metastable, i.e., preventing the output of an indeterminate signal.

[0009] In a possible implementation, the encoding sub-circuit comprises a plurality of coupled groups of exclusive-OR gates and third flip-flops, and for a group of exclusive-OR gates and third flip-flop: one input terminal of the exclusive-OR gate is configured to input the first signal, another input terminal of the exclusive-OR gate is configured to input the second signal, an output terminal of the exclusive-OR gate is coupled to a data input terminal of the third flip-flop, and a data output terminal of the third flip-flop is configured to output one bit of the encoding value. This implementation provides a possible form of the encoding sub-circuit.

[0010] In a possible implementation, the voltage monitoring circuit further comprises a frequency division circuit configured to divide the clock signal to obtain the periodic flip reference signal. This implementation provides a simple way to obtain the periodic flip reference signal without adding extra circuits.

[0011] In a possible implementation, the frequency division circuit comprises a fourth flip-flop and a NOT gate, a clock signal terminal of the fourth flip-flop is configured to input the clock signal, a data output terminal of the fourth flip-flop is coupled to an input terminal of the NOT gate, an output terminal of the NOT gate is coupled to a data input terminal of the fourth flip-flop, and an output terminal of the NOT gate is configured to output the periodic flip reference signal. This implementation provides a possible form of the frequency division circuit.

[0012] In a second aspect, a chip is provided, comprising the voltage monitoring circuit and the working circuit as described in the first aspect and any implementation thereof, and the voltage monitoring circuit is configured to monitor the working voltage of the working circuit. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 FIG. 1 shows a structure of a voltage monitoring circuit based on a BandGap circuit according to an embodiment of the present application;

[0014] Figure 2A structure diagram of a voltage monitoring circuit based on a ring oscillator provided by an embodiment of the present application is shown in the figure.

[0015] Figure 3 A structure diagram of a voltage monitoring circuit based on a delay chain provided by an embodiment of the present application is shown in the figure.

[0016] Figure 4 A structure diagram of another voltage monitoring circuit based on a delay chain provided by an embodiment of the present application is shown in the figure.

[0017] Figure 5 A simulation result of a TT Corner of a delay device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0018] As shown in the figure, another voltage monitoring circuit provided by an embodiment of the present application includes a BandGap circuit 11 and an analog to digital converter (ADC) 12. The BandGap circuit 11 generates a reference voltage, and the voltage of a monitored power supply is converted into a digital code by the ADC 12, and the high and low of the voltage of the monitored power supply can be determined by the code. Figure 1 However, in an advanced chip manufacturing process of 5nm and below, the input voltage is too low, so that the BandGap circuit cannot be used in a poor power supply quality scenario.

[0019] As shown in the figure, another voltage monitoring circuit provided by an embodiment of the present application includes a Process, voltage, temperature (PVT) sensor 21, a reference counter 22, an or gate 23, and an advanced peripheral bus (APB) 24. The PVT sensor 21 includes a ring oscillator (Ring Oscillator) 211, a multiplexer (MUX) 212, a counter 213, and a synchronizer 214.

[0020] Figure 2

[0021] ​​Reference counter 22 receives control and feedback from other devices in the chip via APB 24. Reference counter 22 outputs a fixed-frequency reference clock to counter 213, and controls MUX 212 to select either the self-test clock or the output of ring oscillator 211 via a selection signal. An enable signal controls whether ring oscillator 211 operates. Synchronizer 214 synchronizes the output of counter 213. Specifically, when testing the overall circuit's normal operation, MUX 212 selects the self-test clock to test the normal operation of counter 213; during normal operation (monitoring the voltage of the monitored power supply), MUX 212 selects the output of ring oscillator 211.

[0022] Ring oscillator 211 is a closed-loop self-oscillating circuit that outputs different oscillation frequencies depending on the voltage of the monitored power supply. If the voltage of the monitored power supply increases, the output frequency of ring oscillator 211 will increase; if the voltage decreases, the output frequency will decrease. Counter 213 counts the reference signal output at a fixed frequency from reference counter 22 and also counts the oscillation frequency output by ring oscillator 211. By comparing these two count values, it determines whether the voltage of the monitored power supply is higher or lower than the reference voltage corresponding to the reference clock. This circuit cannot accurately measure the voltage of the monitored power supply; it can only compare it with a reference voltage, resulting in low accuracy.

[0023] like Figure 3 As shown, this application embodiment provides another voltage monitoring circuit, including a first delay sub-circuit 31, a second delay sub-circuit 32, and an encoding sub-circuit 33.

[0024] The first delay sub-circuit 31 is used to delay the input period-inverted reference signal by at least one period of a reference signal to obtain the first signal. The reason is that the reference signal is delayed by a delay chain, and the shortest delay chain supports a delay of one period of a reference signal. Within at least one period of a reference signal, a transition of the reference signal can occur (e.g., from high level to low level, or from low level to high level).

[0025] In one possible implementation, the first delay sub-circuit 31 includes 2N first flip-flops 311 connected in series, where N is a positive integer. The data input terminal D of the first first flip-flop 311 is used to input a reference signal for periodic switching, the data output terminal Q of the preceding first flip-flop 311 is coupled to the data input terminal D of the following flip-flop 311, and the data output terminal Q of the last first flip-flop 311 is coupled to the encoding sub-circuit 33 for outputting a first signal.

[0026] The reason for using 2N first flip-flops 311 is that each flip-flop flips the reference signal once, and the reference signal is flipped back by the flip-flops in pairs, so as to be compared with the output of the second delay sub-circuit.

[0027] In the embodiment of the application, the flip-flop can sample the signal input to the data input end D, so as to output a stable signal through the data output end Q, thereby preventing the output signal from being in a metastable state, i.e., preventing the output signal from being an uncertain signal.

[0028] The second delay sub-circuit 32 includes a plurality of groups of delay devices 321 connected in series, and the plurality of groups of delay devices 321 are powered by the monitored power supply. Exemplary delay devices can be buffers (BUF), inverters, etc. The delay of each group of delay devices 321 can be the same or different. The first group of delay devices 321 is used to input the periodically flipped reference signal, each group of delay devices is used to delay the input signal to output a second signal through a tap, i.e., the next group of delay devices 321 is used to delay the second signal output by the previous group of delay devices 321 and output another second signal.

[0029] Optionally, the second delay sub-circuit 32 further includes a plurality of second flip-flops 322 corresponding to the plurality of groups of delay devices 321 respectively. The data input end D of the second flip-flop 322 is coupled to the output end of a group of delay devices 321, and the data output end Q of the second flip-flop 322 is used to output a second signal.

[0030] Optionally, as shown in Figure 4 The voltage monitoring circuit further includes a frequency division circuit 41, which is used to divide the clock signal to obtain the periodically flipped reference signal.

[0031] In a possible implementation, the frequency division circuit 41 includes a fourth flip-flop 411 and a NOT gate 412. The clock signal end CLK of the fourth flip-flop 411 is used to input the clock signal, the data output end Q of the fourth flip-flop 411 is coupled to the input end of the NOT gate 412, the output end of the NOT gate 412 is coupled to the data input end D of the fourth flip-flop 411, and the output end of the NOT gate 412 is used to output the periodically flipped reference signal.

[0032] The encoding sub-circuit 33 is used to perform exclusive OR operation on the first signal and the second signals output by the plurality of groups of delay devices 321 respectively, so as to output an encoding value corresponding to the voltage of the monitored power supply.

[0033] In a possible implementation, the encoding sub-circuit 33 comprises a plurality of groups of coupled XOR gates 331 and third flip-flops 332, and for a group of XOR gates 331 and third flip-flops 332: one input of the XOR gate 331 is configured to input the first signal, the other input of the XOR gate 331 is configured to input the second signal, the output of the XOR gate 331 is coupled to the data input D of the third flip-flop 332, and the data output Q of the third flip-flop 332 is configured to output one bit of the encoding value.

[0034] Since the first delay sub-circuit 31 and the second delay sub-circuit 32 delay the same periodically-inverted reference signal, and the delay time of the first delay sub-circuit 31 is fixed, the first signal output by the first delay sub-circuit 31 is taken as a reference. When the periodically-inverted reference signal is sequentially transmitted in the plurality of groups of delay devices 321, if the second signal output by a certain group of delay devices 321 is the same as the first signal, it indicates that the periodically-inverted reference signal has been transmitted to the group of delay devices 321, and thus the result of the XOR operation between the first signal and the second signal is 0, i.e., the corresponding bit value of the encoding value of the group of delay devices 321 is 0; if the second signal output by a certain group of delay devices 321 is different from the first signal, it indicates that the periodically-inverted reference signal has not been transmitted to the group of delay devices 321, and thus the result of the XOR operation between the first signal and the second signal is 1, i.e., the corresponding bit value of the encoding value of the group of delay devices 321 is 1.

[0035] The size of the encoding value can be used to determine the size of the voltage of the monitored power supply (or the frequency of the reference signal) accessed by the second delay sub-circuit. When the voltage of the monitored power supply is larger (or the frequency of the reference signal is faster), the delay of each group of delay devices will be relatively smaller, and in the same time, the periodically-inverted reference signal will be transmitted in the delay devices for a longer distance, and the number of bits of the encoding value starting to appear 1 will be later. Taking the low bit as the front position of the encoding value and the high bit as the rear position of the encoding value as an example, the smaller the encoding value is. Similarly, when the voltage of the monitored power supply is smaller (or the frequency of the reference signal is slower), the delay of each group of delay devices will be relatively larger, and in the same time, the periodically-inverted reference signal will be transmitted in the delay devices for a shorter distance, and the number of bits of the encoding value starting to appear 1 will be earlier. Taking the low bit as the front position of the encoding value and the high bit as the rear position of the encoding value as an example, the larger the encoding value is.

[0036] For example, an encoding value is shown in Table 1.

[0037] Table 1

[0038] Value of the tap position OUT[n-1:0] Description Encoded value ’b0***** Delay knee at nth tap position n ’b10**** Delay knee at n-1th tap position n-1 ’b110** Delay knee at n-2th tap position n-2 ’b1110*** Delay knee at n-3th tap position n-3 ’b11110*** Delay knee at n-4th tap position n-4 ’b111110*** Delay knee at n-5th tap position n-5 ’b1111110*** Delay knee at n-6th tap position n-6 ’b11111110*** Delay knee at n-7th tap position n-7 ’b111111110*** Delay knee at n-8th tap position n-8 ’b1111111110*** Delay knee at n-9th tap position n-7 …… …… {n-1{1},1'bo} Delay knee at 1st tap position 1 {n{1}} Delay knee at 0th tap position 0

[0039] In Table 1, * indicates that the value is not concerned and is set to 0 by default. The delay turning point indicates the tap position at which the result of the XOR operation between the first signal and the second signal starts to be 1.

[0040] For example, using a 5nm process fixed length delay chain, the TTCorner simulation of the delay device at different temperatures is shown in Table 2 and Figure 5 As can be seen from Table 2 and

[0041] Table 2

[0042]

[0043] Tables 3-5 below show the encoding values at different frequencies of the reference signal, where Table 3 is 160Mhz, Table 4 is 240Mhz, and Table 5 is 300MHz. As can be seen, the faster the frequency of the reference signal, the smaller the encoding value.

[0044] Table 3

[0045]

[0046] Table 4

[0047]

[0048] Table 5

[0049]

[0050] The voltage monitoring circuit provided by the embodiments of the present application comprises a first delay sub-circuit, a second delay sub-circuit and an encoding sub-circuit. The first delay sub-circuit is configured to delay an input periodic flip reference signal by at least one period of the reference signal to obtain a first signal. The second delay sub-circuit comprises a plurality of groups of delay devices connected in series, the plurality of groups of delay devices are powered by a monitored power supply, the first group of delay devices is configured to input the periodic flip reference signal, and each group of delay devices is configured to delay the input signal to output a second signal. The encoding sub-circuit is configured to perform exclusive OR operation on the first signal and a plurality of second signals output by the plurality of groups of delay devices respectively to output an encoding value corresponding to the voltage of the monitored power supply. By using different monitored power supplies, the distance of the periodic flip reference signal passing through the delay chain is different, and the voltage of the monitored power supply is encoded, so that higher precision measurement of the voltage of the monitored power supply can be achieved.

[0051] By decoupling the power supply voltage detection inside the chip from the production process, the functional index range that cannot be achieved by traditional analog circuits can be solved. Under the advanced production process, the area of the chip occupied by the power supply detection circuit can be effectively reduced, and the area of the relative analog circuit can be reduced by at least 50%. In addition, the traditional analog circuit must be placed in a reasonable position, and the scheme of the present application has basically no constraint in the layout and wiring link, and can be more flexible. Moreover, the relative analog circuit is more concealed at the layout identification level, and has no obvious boundary and dispersed power supply network. The analog circuit has obvious boundary, which is relatively easy to find in the field of secure chips, and can be attacked or focused ion beam (FIB) attack.

[0052] In addition, the above-mentioned voltage monitoring circuit can be used as power supply voltage detection, clock frequency detection (i.e. the function of a digital voltage sensor) in the field of secure chips. The output encoded value is compared with the threshold value. If the encoded value is greater than the high alarm threshold value, it means that the power supply voltage is too high. If the encoded value is less than the low alarm threshold, it means that the power supply voltage is too low. On this basis, an interrupt or reset signal can be output to remind or reset safely.

[0053] The above-mentioned voltage monitoring circuit can also be used for power supply voltage detection, time-frequency detection, etc. inside the chip in the non-secure field.

[0054] The above-mentioned voltage monitoring circuit can also be used for detecting the device process speed in the chip production process, and can also realize the management of the working clock speed and the power supply voltage inside the chip, and realize the power consumption control.

[0055] The embodiment of the present application also provides a chip comprising the above-mentioned voltage monitoring circuit and a working circuit, and the voltage monitoring circuit is used for monitoring the working voltage of the working circuit. The technical effects are referred to the description of the voltage monitoring circuit.

[0056] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software mode depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0057] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the above-mentioned system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0058] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the embodiments of the device described above are merely schematic, and the division of the units is merely logical function division. There can be other division manners in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0059] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0060] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically independent unit, or two or more units can be integrated into one unit.

[0061] The above is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A voltage monitoring circuit, characterized in that, include: Frequency divider circuit, first delay sub-circuit, second delay sub-circuit and encoding sub-circuit; The frequency divider circuit is used to divide the clock signal to obtain a reference signal for periodic switching; The first delay sub-circuit includes 2N first flip-flops connected in series. The 2N first flip-flops are used to delay the input reference signal with the inverted period by at least one period of the reference signal to obtain a first signal, where N is a positive integer. The second delay sub-circuit includes multiple sets of delay devices connected in series. The multiple sets of delay devices are powered by the monitored power supply. The first set of delay devices is used to input the reference signal of the periodic reversal. Each set of delay devices is used to delay the input signal to output a second signal. The encoding sub-circuit is used to XOR the first signal with a plurality of second signals output by the plurality of delay devices to output the encoded value corresponding to the voltage of the monitored power supply.

2. The voltage monitoring circuit according to claim 1, characterized in that, The data input terminal of the first first flip-flop is used to input the reference signal for the periodic switching, the data output terminal of the previous first flip-flop is coupled to the data input terminal of the next first flip-flop, and the data output terminal of the last first flip-flop is used to output the first signal.

3. The voltage monitoring circuit according to any one of claims 1-2, characterized in that, The second delay sub-circuit also includes a plurality of second flip-flops corresponding to the plurality of delay devices respectively. The data input terminal of the second flip-flop is coupled to the output terminal of the corresponding delay device, and the data output terminal of the second flip-flop is used to output a second signal.

4. The voltage monitoring circuit according to any one of claims 1-3, characterized in that, The encoding sub-circuit includes multiple sets of coupled XOR gates and third flip-flops. For each set of XOR gates and third flip-flops: one input terminal of the XOR gate is used to input the first signal, the other input terminal of the XOR gate is used to input the second signal, the output terminal of the XOR gate is coupled to the data input terminal of the third flip-flop, and the data output terminal of the third flip-flop is used to output one bit of the encoded value.

5. The voltage monitoring circuit according to any one of claims 1-4, characterized in that, The frequency divider circuit includes a fourth flip-flop and an NOT gate. The clock signal terminal of the fourth flip-flop is used to input the clock signal. The data output terminal of the fourth flip-flop is coupled to the input terminal of the NOT gate. The output terminal of the NOT gate is coupled to the data input terminal of the fourth flip-flop. The output terminal of the NOT gate is used to output the reference signal for the period flipping.

6. A chip, characterized in that, It includes a voltage monitoring circuit and a working circuit as described in any one of claims 1-5, wherein the voltage monitoring circuit is used to monitor the working voltage of the working circuit.

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