Memory system

Abstract

A memory system according to an embodiment of the present invention includes: a first chip including a first plane and a first input / output circuit; and a controller capable of issuing an instruction for controlling the first chip. The first plane includes: a first memory cell array; and a first latch circuit capable of storing first read data read from the first memory cell array. The first input / output circuit includes a first FIFO circuit capable of taking in the first read data from the first latch circuit. The controller can send a first instruction to the first chip during a read operation being performed in the first plane, and the first instruction commands the first read data to be taken in from the first latch circuit to the first FIFO circuit.

Description

Technical Field

[0001] The embodiment relates to a memory system and a semiconductor memory device included in the memory system. Background Art

[0002] As a semiconductor memory device, a memory system including a NAND type flash memory is known.

[0003] [Background Art Document]

[0004] [Patent Document]

[0005] Patent Document 1: US Patent Application Publication No. 2019 / 0080763 Summary of the Invention

[0006] [Problems to be Solved by the Invention]

[0007] Provide a memory system capable of accelerating the operation.

[0008] [Technical Means for Solving the Problems]

[0009] A memory system according to an embodiment includes: a first chip including a first plane and a first input / output circuit; and a controller capable of issuing an instruction for controlling the first chip. The first plane includes: a first memory cell array having a plurality of first memory cell transistors; and a first latch circuit capable of storing first read data read from the first memory cell array. The first input / output circuit includes a first FIFO circuit capable of taking in the first read data from the first latch circuit. The controller can send a first instruction to the first chip during a read operation in the first plane, and the first instruction commands the first read data to be taken in from the first latch circuit to the first FIFO circuit. Brief Description of the Drawings

[0010] Figure 1 is a block diagram of the memory system according to the first embodiment.

[0011] Figure 2 is a block diagram of the semiconductor memory device included in the memory system according to the first embodiment.

[0012] Figure 3 is a block diagram of a NAND chip in the semiconductor memory device included in the memory system according to the first embodiment.

[0013] Figure 4 is a block diagram showing the configuration of the NAND chip included in the memory system according to the first embodiment from the perspective of the plane.

[0014] Figure 5It is a circuit diagram of a memory cell array in a plane included in the memory system of the first embodiment.

[0015] Figure 6 It is a block diagram showing the configuration of a NAND chip included in the memory system of the first embodiment, focusing on the input / output circuit and the buffer.

[0016] Figure 7 It is a block diagram showing an example of a FIFO (First In First Out) circuit in the input / output circuit included in the memory system of the first embodiment.

[0017] Figure 8 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0018] Figure 9 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0019] Figure 10 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0020] Figure 11 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0021] Figure 12 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0022] Figure 13 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0023] Figure 14 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0024] Figure 15 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0025] Figure 16 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0026] Figure 17 It is a diagram showing an example of an instruction sequence for the read operation of the memory system of the first embodiment.

[0027] Figure 18It is a block diagram showing the configuration of the NAND chip included in the memory system of the second embodiment, focusing on the input / output circuit and the buffer.

[0028] Figure 19 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the second embodiment.

[0029] Figure 20 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the second embodiment.

[0030] Figure 21 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the second embodiment.

[0031] Figure 22 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the second embodiment.

[0032] Figure 23 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the second embodiment.

[0033] Figure 24 It is a block diagram showing the configuration of the NAND chip included in the memory system of the third embodiment, focusing on the input / output circuit and the buffer.

[0034] Figure 25 It is a diagram explaining the outline of the data flow for the read operation of the memory system of the third embodiment.

[0035] Figure 26 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the third embodiment.

[0036] Figure 27 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the third embodiment.

[0037] Figure 28 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the third embodiment.

[0038] Figure 29 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the third embodiment.

[0039] Figure 30 It is a block diagram showing the configuration of the NAND chip included in the memory system of the fourth embodiment, focusing on the input / output circuit and the buffer.

[0040] Figure 31 It is a diagram showing an example of the instruction sequence for the read operation of the memory system of the fourth embodiment.

[0041] Figure 32 It is a diagram showing an example of an instruction sequence for a read operation of a memory system according to the fourth embodiment.

[0042] Figure 33 It is a diagram showing an example of an instruction sequence for a read operation of a memory system according to the fourth embodiment.

[0043] Figure 34 It is a diagram showing an example of an instruction sequence for a read operation of a memory system according to the fourth embodiment.

[0044] Figure 35 It is a diagram showing an example of an instruction sequence for a read operation of a memory system according to the fourth embodiment.

[0045] Figure 36 It is a diagram showing an example of an instruction sequence for a read operation of a memory system according to the fifth embodiment.

[0046] Figure 37 It is a diagram showing an example of an instruction sequence for a read operation of a memory system according to the fifth embodiment.

[0047] Figure 38 It is a diagram showing an example of an instruction sequence for a read operation of a memory system according to the fifth embodiment.

[0048] Figure 39 It is a diagram showing the operation of a NAND chip of a comparative example.

[0049] Figure 40 It is a diagram showing the operation of a NAND chip included in the memory system according to the first embodiment. Detailed Embodiment

[0050] Hereinafter, the embodiments will be described with reference to the drawings. In this description, in all the drawings, common reference numerals are assigned to common parts.

[0051] 1. First Embodiment

[0052] The memory system according to the first embodiment will be described. Hereinafter, as a semiconductor memory device, a memory system including a NAND-type flash memory (hereinafter described as "NAND chip") will be described as an example.

[0053] 1.1 Configuration

[0054] 1.1.1 Overall Configuration of the Memory System

[0055] Regarding the overall configuration of the memory system of this embodiment, use Figure 1 to describe. Figure 1 It is a block diagram of the memory system of this embodiment.

[0056] The memory system 100 includes a semiconductor memory device 200 and a memory controller 300. The memory system 100 is controlled by a host device (hereinafter simply referred to as "host") 400. The memory system 100 processes based on a request signal received from the host 400. The memory system 100 is, for example, an SSD (Solid State Drive), a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD TM card. The host 400 is, for example, a digital camera or a personal computer.

[0057] The semiconductor memory device 200 includes, for example, an I / F chip and NAND chips, and stores data non-volatilely. A plurality of NAND chips may be provided in the semiconductor memory device 200. In addition, the I / F chip may be omitted. In this case, the NAND chip functions as a semiconductor memory device. The semiconductor memory device 200 is controlled by the memory controller 300. In addition, a plurality of semiconductor memory devices 200 may be provided in the memory system 100. In this case, under the control of the memory controller 300, the plurality of semiconductor memory devices 200 can operate independently.

[0058] The memory controller 300 receives a request signal from the host 400 via a main bus. The type of the main bus and the request signal transmitted via the main bus depend on the application program applied to the memory system 100. When the memory system 100 is an SSD, for example, a SAS (Serial Attached SCSI), SATA (Serial ATA), PCIe TM (Programmable Communications Interface Express), or UFS (Universal Flash Storage) specification interface is used as the main bus. When the memory system 100 is a USB memory, USB is used as the main bus. When the memory system 100 is an MMC, an eMMC specification interface is used as the main bus. When the memory system 100 is an SD TM card, an SD TM specification interface is used as the main bus.

[0059] The memory controller 300 controls the semiconductor memory device 200 based on a request signal received from the host 400. Thus, the memory controller 300 is connected to the semiconductor memory device 200 via the NAND bus. The NAND bus performs signal transmission and reception according to the NAND interface. Specific examples of such signals include the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signals REn and RE, the write protect signal WPn, the data strobe signals DQS and DQSn, the input / output signal DQ, and the ready / busy signal RBn.

[0060] The signal CEn is a signal for enabling the NAND chip within the semiconductor memory device 200 and is asserted, for example, at a low (“L”) level. Additionally, “asserted” means that the signal (or logic) is set to an active state. The signal CLE is a signal indicating that the signal DQ is a command and is asserted, for example, at a high (“H”) level. The signal ALE is a signal indicating that the signal DQ is an address and is asserted, for example, at the “H” level. The signal WEn is a signal for taking in the received signal into the semiconductor memory device 200 and is asserted, for example, at the “L” level. Whenever WEn is triggered, the semiconductor memory device 200 takes in the signal DQ. The signals REn and RE are signals for the memory controller 300 to read data from the semiconductor memory device 200. The signal REn is the inverted signal of the signal RE. Whenever the signals REn and RE are triggered, the semiconductor memory device 200 outputs the signal DQ to the memory controller 300. The signal WPn is a signal for prohibiting writing or erasing in the semiconductor memory device 200 and is asserted, for example, at the “L” level. The signals CEn, CLE, ALE, WEn, REn, RE, and WPn are sent from the memory controller 300 to the semiconductor memory device 200.

[0061] The signals DQS and DQSn are used to control the timing of signal transmission and reception of the signal DQ. The signal DQSn is the inverted signal of the signal DQS. For example, during data writing, the signals DQS and DQSn are sent from the memory controller 300 to the semiconductor memory device 200 together with the write data DQ. The semiconductor memory device 200 receives the write data DQ synchronously with the signals DQS and DQSn. Additionally, during data reading, the signals DQS and DQSn are sent from the semiconductor memory device 200 to the memory controller 300 together with the read data DQ. The signals DQS and DQSn are generated based on the aforementioned signal REn. The memory controller 300 receives the read data DQ synchronously with the signals DQS and DQSn.

[0062] The input / output signal DQ is, for example, an 8-bit signal (hereinafter, when differentiating the eight signals DQ, they are respectively described as DQ0 to DQ7, and when not differentiating, simply described as the signal DQ). The input / output signal DQ is the entity of the data transceived between the semiconductor memory device 200 and the memory controller 300, and is, for example, an instruction CMD, an address ADD, write data or read data DAT, and status information STS.

[0063] The signal RBn is a signal indicating whether the NAND chip in the semiconductor memory device 200 is in a busy state or a ready state. For example, it is set to the "L" level when the NAND chip is in a busy state. When the signal RBn is in a ready state, the NAND chip can receive an instruction from the memory controller 300, and when the signal RBn is in a busy state, the NAND chip cannot receive an instruction from the memory controller 300. The signal RBn is sent from the semiconductor memory device 200 to the memory controller 300.

[0064] The memory controller 300 includes: a host interface circuit (host I / F) 310, a memory interface circuit (memory I / F) 320, a ROM (read only memory) 330, a CPU (central processing unit) 340, and a RAM (random access memory) 350.

[0065] The host interface circuit 310 is connected to the host 400 via a main bus and is in charge of the communication between the memory controller 300 and the host 400.

[0066] The memory interface circuit 320 is connected to the semiconductor memory device 200 via a NAND bus and is in charge of the communication between the memory controller 300 and the semiconductor memory device 200.

[0067] The ROM 330 stores firmware (programs) for the memory controller 300 to perform various operations and for a part of the functions of the host interface circuit 310 and the memory interface circuit 320. The firmware is configured to enable the memory controller 300 to perform the operations described in the respective embodiments.

[0068] The CPU 340 controls the overall operation of the memory controller 300. For example, when the CPU 340 receives a read-related request signal from the host 400, based on this, it issues a read instruction to the semiconductor memory device 200 to the memory interface circuit 320. When the CPU 340 receives a write-related request signal from the host 400, it performs the same operation.

[0069] The RAM 350 is used as a working area for the CPU 340. The RAM 350 is a semiconductor memory such as a DRAM or an SRAM. The RAM 350 stores, for example, the firmware described above. The firmware is loaded into the RAM 350 by the memory controller 300 immediately after the power of the memory system 100 is turned on, for example.

[0070] 1.1.2 Configuration of the semiconductor storage device 200

[0071] Regarding the configuration of the semiconductor storage device 200, Figure 2 an explanation will be given. Figure 2 is a block diagram of the semiconductor storage device 200 included in the memory system 100 of the present embodiment.

[0072] The semiconductor storage device 200 includes an I / F chip 210, a NAND chip 0 (CP0), and a NAND chip 1 (CP1). The I / F chip 210 is connected to the memory controller 300 via a NAND bus and manages communication between the memory controller 300 and the NAND chip 0 (CP0) and the NAND chip 1 (CP1). The NAND chip 0 (CP0) and the NAND chip 1 (CP1) are NAND-type flash memories. Hereinafter, the "NAND chip 0" may be simply described as "chip 0", and the "NAND chip 1" may be simply described as "chip 1". In addition, the number of NAND chips provided in the semiconductor storage device 200 is not limited to 2, and may be 1 or more than 2. The NAND chip 0 (CP0) and the NAND chip 1 (CP1) are controlled by the memory controller 300. The NAND chip 0 (CP0) and the NAND chip 1 (CP1) are connected to a common data bus DB. In addition, the NAND chips do not necessarily have to be connected via the common data bus DB, and a configuration in which a plurality of NAND chips are connected to one data bus DB is sufficient.

[0073] The memory controller 300 may send different signals CEn for each NAND chip, or may send a common signal CEn to a plurality of NAND chips. For example, when different signals CEn are sent for each NAND chip, the signal CEn includes signals CEn1 and CEn2 corresponding to the NAND chip 0 (CP0) and the NAND chip 1 (CP1), respectively. In addition, when a common signal CEn is sent to a plurality of NAND chips, the NAND chips are selected based on the signal CEn and the address specifying the NAND chip. The signal RBn includes signals RBn1 and RBn2 corresponding to the NAND chip 0 (CP0) and the NAND chip 1 (CP1), respectively. In addition, the number of signals RBn may be set to the same number as the number of NAND chips provided in the semiconductor storage device 200.

[0074] The I / F chip 210 receives signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, WPn, DQS, DQSn, and DQ from the memory controller 300. The I / F chip 210 sends the received signals CLE, ALE, WEn, REn, RE, WPn, DQS, DQSn, and DQ to the NAND chip 0 (CP0) and the NAND chip 1 (CP1) via the data bus DB. The I / F chip 210 sends the received signal CEn1 to the NAND chip 0 (CP0). The I / F chip 210 sends the received signal CEn2 to the NAND chip 1 (CP1).

[0075] The I / F chip 210 receives signals DQS, DQSn, and DQ from the NAND chip 0 (CP0) and the NAND chip 1 (CP1). The I / F chip 210 sends the received signals DQS, DQSn, and DQ to the memory controller 300.

[0076] The NAND chip 0 (CP0) sends the signal RBn1 to the memory controller 300. The NAND chip 1 (CP1) sends the signal RBn2 to the memory controller 300.

[0077] Data is written to one of the selected NAND chip 0 (CP0) and the NAND chip 1 (CP1). In addition, data is read from one of the selected NAND chip 0 (CP0) and the NAND chip 1 (CP1).

[0078] 1.1.3 Structure of NAND chip 0 (CP0)

[0079] Regarding the structure of the NAND chip 0 (CP0), use Figure 3 is used for explanation. Figure 3 is a block diagram of the NAND chip 0 (CP0) in the semiconductor memory device 200 included in the memory system 100 of the present embodiment. In addition, although in Figure 3 a part of the connection between each block is represented by an arrow line, the connection between the blocks is not limited thereto. Hereinafter, the NAND chip 0 (CP0) will be described, but the NAND chip 1 (CP1) has the same structure.

[0080] The NAND chip 0 (CP0) includes: an input / output circuit 10, a buffer 20, a sequencer 30, a voltage generation circuit 40, and planes 0 to 3 (PL0 to PL3).

[0081] The input / output circuit 10 receives signals CEn1, CLE, ALE, WEn, REn, RE, and WPn from the memory controller 300. The input / output circuit 10 transceives signals DQS, DQSn, and DQ with the memory controller 300 in between. The input / output circuit 10 sends a signal RBn1 to the memory controller 300.

[0082] The buffer 20 includes a status buffer 21, an address buffer 22, and an instruction buffer 23. The status buffer 21 temporarily stores status information STS such as the status of data write, read, and erase operations. The address buffer 22 temporarily stores the address ADD received from the memory controller 300 via the input / output circuit 10. The row address RA and the column address CA are included in the address ADD. The instruction buffer 23 temporarily stores the instruction CMD received from the memory controller 300 via the input / output circuit 10.

[0083] The sequencer 30 controls the overall operation of the NAND chip 0 (CP0). The sequencer 30 receives the instruction CMD from the instruction buffer 23. Based on the received instruction CMD, the sequencer 30 controls the input / output circuit 10, the status buffer 21, the voltage generation circuit 40, and planes 0 to 3 (PL0 to PL3) to perform write, read, and erase operations, etc.

[0084] The voltage generation circuit 40 receives a power supply voltage from the outside of the NAND chip 0 (CP0) and generates various voltages from the power supply voltage based on the control of the sequencer 30. The voltage generation circuit 40 applies the generated voltages to planes 0 to 3 (PL0 to PL3).

[0085] Planes 0 to 3 (PL0 to PL3) are independently controlled by the sequencer 30. Planes 0 to 3 (PL0 to PL3) are units for writing the following data to the memory cell transistors and reading the following data from the memory cell transistors. When writing data, planes 0 to 3 (PL0 to PL3) receive the write data DAT from the memory controller 300 via the input / output circuit 10. In addition, when reading data, planes 0 to 3 (PL0 to PL3) send the read data DAT to the memory controller 300 via the input / output circuit 10.

[0086] Regarding the configuration of plane 0 (PL0), use Figure 4 is described. Figure 4 is a block diagram showing the configuration of the NAND chip 0 (CP0) included in the memory system 100 of the present embodiment focusing on plane 0 (PL0). Hereinafter, plane 0 (PL0) will be described, but planes 1 (PL1), 2 (PL2), and 3 (PL3) also have the same configuration. In addition, inFigure 4 In this case, the status buffer 21, instruction buffer 23, and planes 1 to 3 (PL1 to PL3) are omitted.

[0087] Plane 0 (PL0) includes a memory cell array 51A, a row decoder 52A, a sense amplifier 53A, a data buffer 54A, and a column decoder 55A.

[0088] The memory cell array 51A has a plurality of blocks BLK (BLK0 to BLKn, where n is a natural number of 1 or more) including non-volatile memory cell transistors that establish a correspondence with rows and columns. In addition, the number of blocks BLK in the memory cell array 51A is arbitrary. Details of the memory cell array 51A are described later. A voltage is applied to the memory cell array 51A from a voltage generation circuit 40.

[0089] The row decoder 52A is controlled by an ordinal generator 30. The row decoder 52A receives a row address RA from an address buffer 22. The row decoder 52A decodes the received row address RA, and based on the decoding result, applies a voltage supplied from the voltage generation circuit 40 to the selected memory cell transistors.

[0090] The sense amplifier 53A is controlled by an ordinal generator 30. A voltage is applied to the sense amplifier 53A from a voltage generation circuit 40. When reading data, the sense amplifier 53A senses data DAT read from the memory cell array 51A. The sense amplifier 53A sends the sensed data DAT to the data buffer 54A. In addition, when writing data, the sense amplifier 53A sends the write data DAT to the memory cell array 51A.

[0091] The data buffer 54A is controlled by an ordinal generator 30. A voltage is applied to the data buffer 54A from a voltage generation circuit 40. The data buffer 54A includes a plurality of latch circuits (not shown). The latch circuits store write data and read data DAT. For example, when writing data, the data buffer 54A temporarily stores the write data DAT received from the input / output circuit 10 and sends it to the sense amplifier 53A. In addition, when reading data, the data buffer 54A temporarily stores the read data DAT received from the sense amplifier 53A and sends it to the input / output circuit 10.

[0092] The column decoder 55A is controlled by an ordinal generator 30. A voltage is applied to the column decoder 55A from a voltage generation circuit 40. The column decoder 55A receives a column address CA from the address buffer 22. The column decoder 55A decodes the column address CA during, for example, write, read, and erase operations, and selects a latch circuit in the data buffer 54A according to the decoding result.

[0093] 1.1.4 Circuit Configuration of Memory Cell Array 51A

[0094] Regarding the circuit configuration of the memory cell array 51A, use Figure 5 to describe. Figure 5 It is a circuit diagram of the memory cell array 51A in the plane 0 (PL0) included in the memory system 100 of the present embodiment.

[0095] Figure 5 Extract one block BLK from the multiple blocks BLK included in the memory cell array 51A and display an example of the circuit configuration of the memory cell array 51A. All other blocks BLK also have Figure 5 the configuration shown.

[0096] The block BLK includes, for example, four string units SU0 to SU3. In addition, the number of string units SU in the block BLK is arbitrary. Each string unit SU includes a plurality of NAND strings NS. The plurality of NAND strings NS are respectively associated with bit lines BL0 to BLm (m is a natural number of 1 or more). Each NAND string NS includes, for example, memory cell transistors MC0 to MC7, and selection transistors ST1 and ST2. The memory cell transistor MC includes a control gate and a charge storage layer, and stores data non-volatilely. The selection transistors ST1 and ST2 are respectively used for selecting the string unit SU during various operations.

[0097] In each NAND string NS, the memory cell transistors MC0 to MC7 are connected in series. In the same block BLK, the control gates of the memory cell transistors MC0 to MC7 are commonly connected to word lines WL0 to WL7 respectively.

[0098] In each NAND string NS, the drain of the selection transistor ST1 is connected to the associated bit line BL, and the source of the selection transistor ST1 is connected to one end of the series-connected memory cell transistors MC0 to MC7. In the same block BLK, the gates of the selection transistors ST1 in the string units SU0 to SU3 are commonly connected to selection gate lines SGD0 to SGD3 respectively.

[0099] In each NAND string NS, the drain of the selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC7. In the same block BLK, the source of the selection transistor ST2 is connected to the source line SL, and the gate of the selection transistor ST2 is commonly connected to the selection gate line SGS.

[0100] In the circuit configuration of the memory cell array 51A described above, the bit line BL is shared among, for example, a plurality of NAND strings NS corresponding to each block BLK. The source line SL is shared among, for example, a plurality of blocks BLK.

[0101] 1.1.5 Configuration of the input / output circuit 10

[0102] The configuration of the input / output circuit 10 will be described using Figure 6 as follows. Figure 6 FIG. is a block diagram showing the configuration of the NAND chip 0 (CP0) included in the memory system 100 of the present embodiment, focusing on the input / output circuit 10 and the buffer 20. In addition, in Figure 6 the status buffer 21 and the voltage generation circuit 40 are omitted.

[0103] Similar to plane 0 (PL0), plane 1 (PL1) includes: a memory cell array 51B, a row decoder 52B, a sense amplifier 53B, a data buffer 54B, and a column decoder 55B. Plane 2 (PL2) includes: a memory cell array 51C, a row decoder 52C, a sense amplifier 53C, a data buffer 54C, and a column decoder 55C. Plane 3 (PL3) includes: a memory cell array 51D, a row decoder 52D, a sense amplifier 53D, a data buffer 54D, and a column decoder 55D. Hereinafter, without distinguishing the memory cell arrays 51A to 51D, they will be simply described as the memory cell array 51, and without distinguishing the data buffers 54A to 54D, they will be simply described as the data buffer 54.

[0104] The input / output circuit 10 includes a DQ pad 11 and a FIFO circuit 12. The DQ pad 11 connects the input / output circuit 10 to the NAND bus. In addition, the DQ pad 11 is connected to the data buffers 54A to 54D via the FIFO circuit 12. The DQ pad 11 can be recognized from the outside of the NAND chip 0 (CP0) as one output terminal having a certain output impedance.

[0105] The FIFO circuit 12 takes in the data DAT read from planes 0 to 3 (PL0 to PL3) based on the following write clock Wclk. In addition, the FIFO circuit 12 sends the stored signal to the DQ pad 11 based on the following read clock Rclk. Details of the FIFO circuit 12 will be described later.

[0106] 1.1.6 Configuration of Buffer 20

[0107] The configuration of the buffer 20 will be described using Figure 6 as follows.

[0108] The address buffer 22 includes: row address buffers 0 (RR0) to 3 (RR3), row address buffers 0' (RR0') to 3' (RR3'), column address buffer 0 (CR0), and column address buffer 0' (CR0').

[0109] The row address buffer 0 (RR0) is connected to the input / output circuit 10 and the plane 0 (PL0), and stores the row address RA of the plane 0 (PL0) received from the input / output circuit 10. The row address buffer 0 (RR0) sends the row address RA to the row decoder 52A. The row address buffer 1 (RR1) is connected to the input / output circuit 10 and the plane 1 (PL1), and stores the row address RA of the plane 1 (PL1) received from the input / output circuit 10. The row address buffer 1 (RR1) sends the row address RA to the row decoder 52B. The row address buffer 2 (RR2) is connected to the input / output circuit 10 and the plane 2 (PL2), and stores the row address RA of the plane 2 (PL2) received from the input / output circuit 10. The row address buffer 2 (RR2) sends the row address RA to the row decoder 52C. The row address buffer 3 (RR3) is connected to the input / output circuit 10 and the plane 3 (PL3), and stores the row address RA of the plane 3 (PL3) received from the input / output circuit 10. The row address buffer 3 (RR3) sends the row address RA to the row decoder 52D.

[0110] The row address buffer 0’ (RR0’) is connected to the row address buffer 0 (RR0) and the plane 0 (PL0), and stores the (duplicated) row address RA received from the row address buffer 0 (RR0). The row address buffer 0’ (RR0’) sends the row address RA to the row decoder 52A. The row address buffer 1’ (RR1’) is connected to the row address buffer 1 (RR1) and the plane 1 (PL1), and stores the (duplicated) row address RA received from the row address buffer 1 (RR1). The row address buffer 1’ (RR1’) sends the row address RA to the row decoder 52B. The row address buffer 2’ (RR2’) is connected to the row address buffer 2 (RR2) and the plane 2 (PL2), and stores the (duplicated) row address RA received from the row address buffer 2 (RR2). The row address buffer 2’ (RR2’) sends the row address RA to the row decoder 52C. The row address buffer 3’ (RR3’) is connected to the row address buffer 3 (RR3) and the plane 3 (PL3), and stores the (duplicated) row address RA received from the row address buffer 3 (RR3). The row address buffer 3’ (RR3’) sends the row address RA to the row decoder 52D.

[0111] The column address buffer 0 (CR0) is connected to the input / output circuit 10 and the planes 0 to 3 (PL0 to PL3), and stores the column address CA of the planes 0 to 3 (PL0 to PL3) received from the input / output circuit 10. The column address buffer 0’ (CR0’) is connected to the column address buffer 0 (CR0) and the planes 0 to 3 (PL0 to PL3), and stores the (duplicated) column address CA received from the column address buffer 0 (CR0).

[0112] Column address buffer 0 (CR0) includes column address counter circuit CC0, and column address buffer 0' (CR0') includes column address counter circuit CC0'. Column address counter circuits CC0 and CC0' increment column address CA by 1 successively.

[0113] Column address buffer 0 (CR0) sends column address CA to column decoders 55A to 55D. More specifically, column address buffer 0 (CR0) sends the initial column address CA of the plane specified by column address CA to column decoders 55A to 55D. When sending the initial column address CA to column decoders 55A to 55D, column address counter circuit CC0 increments column address CA by only 1, and column address buffer 0 (CR0) sends the next column address CA of the initial column address CA to column decoders 55A to 55D. When sending the last column address CA to column decoders 55A to 55D, the transmission of column address CA to column decoders 55A to 55D ends. Column address buffer 0' (CR0') sends column address CA to column decoders 55A to 55D in the same manner as column address buffer 0 (CR0).

[0114] Instruction buffer 23 includes instruction buffers 0 (MR0) to 3 (MR3), and instruction buffers 0' (MR0') to 3' (MR3').

[0115] Instruction buffer 0 (MR0) is connected to input / output circuit 10 and sequencer 30, and stores instruction CMD related to plane 0 (PL0) received from input / output circuit 10. Instruction buffer 0 (MR0) sends instruction CMD to sequencer 30. Instruction buffer 1 (MR1) is connected to input / output circuit 10 and sequencer 30, and stores instruction CMD related to plane 1 (PL1) received from input / output circuit 10. Instruction buffer 1 (MR1) sends instruction CMD to sequencer 30. Instruction buffer 2 (MR2) is connected to input / output circuit 10 and sequencer 30, and stores instruction CMD related to plane 2 (PL2) received from input / output circuit 10. Instruction buffer 2 (MR2) sends instruction CMD to sequencer 30. Instruction buffer 3 (MR3) is connected to input / output circuit 10 and sequencer 30, and stores instruction CMD related to plane 3 (PL3) received from input / output circuit 10. Instruction buffer 3 (MR3) sends instruction CMD to sequencer 30.

[0116] The instruction buffer 0’ (MR0’) is connected to the instruction buffer 0 (MR0) and the sequencer 30, and stores the (copied) instruction CMD received from the instruction buffer 0 (MR0). The instruction buffer 0’ (MR0’) sends the instruction CMD to the sequencer 30. The instruction buffer 1’ (MR1’) is connected to the instruction buffer 1 (MR1) and the sequencer 30, and stores the (copied) instruction CMD received from the instruction buffer 1 (MR1). The instruction buffer 1’ (MR1’) sends the instruction CMD to the sequencer 30. The instruction buffer 2’ (MR2’) is connected to the instruction buffer 2 (MR2) and the sequencer 30, and stores the (copied) instruction CMD received from the instruction buffer 2 (MR2). The instruction buffer 2’ (MR2’) sends the instruction CMD to the sequencer 30. The instruction buffer 3’ (MR3’) is connected to the instruction buffer 3 (MR3) and the sequencer 30, and stores the (copied) instruction CMD received from the instruction buffer 3 (MR3). The instruction buffer 3’ (MR3’) sends the instruction CMD to the sequencer 30.

[0117] 1.1.7 Constitution of the FIFO circuit 12

[0118] Regarding the constitution of the FIFO circuit 12, use Figure 7 is used for explanation. Figure 7 is a block diagram showing an example of the FIFO circuit 12 in the input / output circuit 10 included in the memory system 100 of the present embodiment.

[0119] The FIFO circuit 12 includes: a multiplexer (hereinafter referred to as “MUX”) 60, flip-flops (hereinafter referred to as “FFs”) 61 to 63, a MUX 64, a write clock generation circuit 65, a write pointer generation circuit 66, a read clock generation circuit 67, and a read pointer generation circuit 68.

[0120] The MUX 60 selects any one of the FFs 61 to 63 based on the write pointer Wptr received from the write pointer generation circuit 66. The signal received from the data buffer 54A is sent to the FF selected by the MUX 60. Details of the write pointer Wptr are described later.

[0121] The FFs 61 to 63 receive signals from the MUX 60. The FFs 61 to 63 take in the signals received from the MUX 60 at the timing when the write clock Wclk rises from the “L” level to the “H” level, and store the taken-in signals.

[0122] The MUX 64 selects any one of the FFs 61 to 63 based on the read pointer Rptr received from the read pointer generation circuit 68. Details of the read pointer Rptr are described later.

[0123] The write clock generation circuit 65 generates a write clock Wclk that specifies the timing for taking in signals to the FFs 61 to 63. The write clock generation circuit 65 sends the generated write clock Wclk to the write pointer generation circuit 66.

[0124] The write pointer generation circuit 66 generates a write pointer Wptr that specifies which one of the FFs 61 to 63 the signal received from the data buffer 54A is to be taken into. The write pointer Wptr is incremented at the timing when the write clock Wclk rises from the "L" level to the "H" level, thereby generating the write pointer Wptr.

[0125] The read clock generation circuit 67 generates a read clock Rclk that specifies the timing for switching the connection of any one of the FFs 61 to 63 to the MUX 64. The read clock generation circuit 67 sends the generated read clock Rclk to the read pointer generation circuit 68.

[0126] The read pointer generation circuit 68 generates a read pointer Rptr that specifies which one of the FFs 61 to 63 the signal received from is to be output. The read pointer Rptr is incremented at the timing when the read clock Rclk rises from the "L" level to the "H" level, thereby generating the read pointer Rptr.

[0127] In addition, the FFs 61 to 63 can be set in multiple stages between the MUX 60 and the MUX 64.

[0128] 1.2 Operation

[0129] Regarding the operation of the memory system 100 of the present embodiment, it is described using Figures 8 - 17 for illustration. Figures 8 - 17 is a diagram showing an example of an instruction sequence for the read operation of the memory system 100 of the present embodiment. Hereinafter, taking the case where the signals CEn1 and CEn2 are the same signal (CEn1 = CEn2 = CEn) and reading data is repeated in the sequence of plane 0 of chip 0, plane 0 of chip 1, plane 1 of chip 0, plane 1 of chip 1, plane 2 of chip 0, plane 2 of chip 1, plane 3 of chip 0, plane 3 of chip 1 as an example, the description is given.

[0130] At Figures 8 - 17It also represents the cache busy signal CB for each plane of chip 0 (CP0) and chip 1 (CP1). Additionally, in this specification, the "cache busy signal CB" means a signal indicating whether the target plane is in a busy state or a ready state. The signal CB is set for each plane and is set to the "L" level when the corresponding plane is in a busy state, for example. When the signal CB is in the busy state, it is a state where access to the data buffer 54 (data DAT) of the corresponding plane is not possible. When the signal CB is in the ready state, it is a state where access to the data buffer 54 (data DAT) of the corresponding plane is possible. The signal CB is stored in the status register 21. The memory controller 300 confirms the status of the signal CB for each plane by reading the status information STS from the status register 21. Hereinafter, the signal CB for planes 0 to 3 (PL0 to PL3) of chip 0 (CP0) will be described as signal CB00, signal CB01, signal CB02, and signal CB03 respectively, and the signal CB for planes 0 to 3 (PL0 to PL3) of chip 1 (CP1) will be described as signal CB10, signal CB11, signal CB12, and signal CB13 respectively. Additionally, the signal RB is the result of the sequencer 30 performing an AND operation on the signal CB for each plane within the chip. For example, in chip 0 (CP0), when the signal CB of any one of planes 0 to 3 (PL0 to PL3) is at the "L" level, the signal RB is at the "L" level, and when the signal CB of all planes 0 to 3 (PL0 to PL3) is at the "H" level, the signal RB is at the "H" level. Thus, the signal RB indicates whether all planes are in the ready state in each chip.

[0131] The read operation of this embodiment is single-plane reading. Additionally, in this specification, "single-plane reading" means an operation of independently reading the data DAT from each plane.

[0132] First, as Figures 8 - 9 shown, the memory controller 300 performs a normal read of plane 0 (PL0) of chip 0 (CP0). Additionally, in this specification, "normal read" means that in the target plane, until the read data DAT is stored in the data buffer 54 from the memory cell array 51 (until the signal CB is in the ready state), the read operation of the next instruction for the target plane is not accepted.

[0133] More specifically, after setting the signal CEn to the "L" level, the memory controller 300 issues the instruction <00h>, the address <Ad00>, and the instruction <30h> to perform a normal read of plane 0 (PL0) of chip 0 (CP0). The instruction "00h" is an instruction for commanding a readout. The address "Ad00" specifies the address of plane 0 of chip 0. The instruction "30h" is an instruction for performing a normal read in a single-plane read.

[0134] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad00>, and the instruction <30h> issued by the memory controller 300. Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 0 (MR0) of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad00> to the row address buffer 0 (RR0) of chip 0 (CP0), and sends the column address CA of the received address <Ad00> to the column address buffer 0 (CR0) of chip 0 (CP0). Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 0 (MR0) of chip 0 (CP0).

[0135] If the row address RA of the address <Ad00> is stored in the row address buffer 0 (RR0), then the row address buffer 0 (RR0) sends the row address RA to the row decoder 52A.

[0136] When receiving the instruction <30h> from the instruction buffer 0 (MR0), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 0 (PL0). The sequencer 30 sets the signal CB00 to the busy state. The signal CB00 is stored in the status buffer 21. When the normal read in plane 0 (PL0) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB00 to the ready state. Plane 0 (PL0) of chip 0 (CP0) can accept the next instruction.

[0137] Next, the memory controller 300 performs a normal read of plane 0 (PL0) of chip 1 (CP1).

[0138] More specifically, after issuing the instruction <00h>, the address <Ad00>, and the instruction <30h>, the memory controller 300 issues the instruction <00h>, the address <Ad10>, and the instruction <30h> to perform a normal read of plane 0 (PL0) of chip 1 (CP1). The address "Ad10" specifies the address of plane 0 of chip 1.

[0139] In chip 1 (CP1), the input / output circuit 10 receives the instruction <00h>, the address <Ad10>, and the instruction <30h> issued by the memory controller 300. Then, similar to the normal read of plane 0 (PL0) of chip 0 (CP0), the normal read of plane 0 (PL0) of chip 1 (CP1) is started. The sequencer 30 of chip 1 (CP1) sets the signal CB10 to the busy state. The signal CB10 is stored in the status buffer 21. When the normal read in plane 0 (PL0) of chip 1 (CP1) ends, the sequencer 30 sets the signal CB10 to the ready state. Plane 0 (PL0) of chip 1 (CP1) can accept the next instruction.

[0140] Next, the memory controller 300 performs a normal read of plane 1 (PL1) of chip 0 (CP0).

[0141] More specifically, after issuing the instruction <00h>, the address <Ad10>, and the instruction <30h>, the memory controller 300 issues the instruction <00h>, the address <Ad01>, and the instruction <30h> to perform a normal read of plane 1 (PL1) of chip 0 (CP0). The address "Ad01" specifies the address of plane 1 of chip 0.

[0142] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad01>, and the instruction <30h> issued by the memory controller 300. Based on the address <Ad01>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 1 (MR1) of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad01> to the row address buffer 1 (RR1) of chip 0 (CP0), and sends the column address CA of the received address <Ad01> to the column address buffer 0 (CR0) of chip 0 (CP0). Based on the address <Ad01>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 1 (MR1) of chip 0 (CP0).

[0143] If the row address RA of the address <Ad01> is stored in the row address buffer 1 (RR1), then the row address buffer 1 (RR1) sends the row address RA to the row decoder 52B.

[0144] When receiving the instruction <30h> from the instruction buffer 1 (MR1), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 1 (PL1). The sequencer 30 sets the signal CB01 to the busy state. The signal CB01 is stored in the status buffer 21. When the normal read in plane 1 (PL1) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB01 to the ready state. Plane 1 (PL1) of chip 0 (CP0) can accept the next instruction.

[0145] Next, the memory controller 300 performs a normal read of plane 1 (PL1) of chip 1 (CP1).

[0146] More specifically, after issuing the instruction <00h>, the address <Ad01>, and the instruction <30h>, the memory controller 300 issues the instruction <00h>, the address <Ad11>, and the instruction <30h> in order to perform a normal read of plane 1 (PL1) of chip 1 (CP1). The address "Ad11" specifies the address of plane 1 of chip 1.

[0147] In chip 1 (CP1), the input / output circuit 10 receives the instruction <00h>, the address <Ad11>, and the instruction <30h> issued by the memory controller 300. Then, in the same way as the normal read of plane 1 (PL1) of chip 0 (CP0) described above, a normal read of plane 1 (PL1) of chip 1 (CP1) is started. The sequencer 30 of chip 1 (CP1) sets the signal CB11 to the busy state. The signal CB11 is stored in the status buffer 21. When the normal read in plane 1 (PL1) of chip 1 (CP1) ends, the sequencer 30 sets the signal CB11 to the ready state. Plane 1 (PL1) of chip 1 (CP1) can accept the next instruction.

[0148] Next, the memory controller 300 performs a normal read of plane 2 (PL2) of chip 0 (CP0).

[0149] More specifically, after issuing the instruction <00h>, the address <Ad11>, and the instruction <30h>, the memory controller 300 issues the instruction <00h>, the address <Ad02>, and the instruction <30h> in order to perform a normal read of plane 2 (PL2) of chip 0 (CP0). The address "Ad02" specifies the address of plane 2 of chip 0.

[0150] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad02>, and instruction <30h> issued by the memory controller 300. Based on address <Ad02>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 2 (MR2) of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad02> to the row address buffer 2 (RR2) of chip 0 (CP0), and sends the column address CA of the received address <Ad02> to the column address buffer 0 (CR0) of chip 0 (CP0). Based on address <Ad02>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 2 (MR2) of chip 0 (CP0).

[0151] If the row address RA of address <Ad02> is stored in the row address buffer 2 (RR2), then the row address buffer 2 (RR2) sends the row address RA to the row decoder 52C.

[0152] When receiving instruction <30h> from the instruction buffer 2 (MR2), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 2 (PL2). The sequencer 30 sets the signal CB02 to the busy state. The signal CB02 is stored in the status buffer 21. When the normal read in plane 2 (PL2) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB02 to the ready state. Plane 2 (PL2) of chip 0 (CP0) can accept the next instruction.

[0153] Next, the memory controller 300 performs a normal read of plane 2 (PL2) of chip 1 (CP1).

[0154] More specifically, after issuing instruction <00h>, address <Ad02>, and instruction <30h>, the memory controller 300 issues instruction <00h>, address <Ad12>, and instruction <30h> to perform a normal read of plane 2 (PL2) of chip 1 (CP1). The address "Ad12" specifies the address of plane 2 of chip 1.

[0155] In chip 1 (CP1), the input / output circuit 10 receives the instruction <00h>, the address <Ad12>, and the instruction <30h> issued by the memory controller 300. Then, in the same manner as the normal read of plane 2 (PL2) of chip 0 (CP0), the normal read of plane 2 (PL2) of chip 1 (CP1) is started. The sequencer 30 of chip 1 (CP1) sets the signal CB12 to the busy state. The signal CB12 is stored in the status buffer 21. When the normal read in plane 2 (PL2) of chip 1 (CP1) ends, the sequencer 30 sets the signal CB12 to the ready state. Plane 2 (PL2) of chip 1 (CP1) can accept the next instruction.

[0156] Next, the memory controller 300 performs a normal read of plane 3 (PL3) of chip 0 (CP0).

[0157] More specifically, after issuing the instruction <00h>, the address <Ad12>, and the instruction <30h>, the memory controller 300 issues the instruction <00h>, the address <Ad03>, and the instruction <30h> in order to perform a normal read of plane 3 (PL3) of chip 0 (CP0). The address "Ad03" specifies the address of plane 3 of chip 0.

[0158] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad03>, and the instruction <30h> issued by the memory controller 300. Based on the address <Ad03>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 3 (MR3) of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad03> to the row address buffer 3 (RR3) of chip 0 (CP0), and sends the column address CA of the received address <Ad03> to the column address buffer 0 (CR0) of chip 0 (CP0). Based on the address <Ad03>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 3 (MR3) of chip 0 (CP0).

[0159] If the row address RA of the address <Ad03> is stored in the row address buffer 3 (RR3), then the row address buffer 3 (RR3) sends the row address RA to the row decoder 52D.

[0160] When receiving the instruction <30h> from the instruction buffer 3 (MR3), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 3 (PL3). The sequencer 30 sets the signal CB03 to the busy state. The signal CB03 is stored in the status buffer 21. When the normal read in plane 3 (PL3) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB03 to the ready state. Plane 3 (PL3) of chip 0 (CP0) can accept the next instruction.

[0161] Next, the memory controller 300 performs a normal read of plane 3 (PL3) of chip 1 (CP1).

[0162] More specifically, after issuing the instruction <00h>, the address <Ad03>, and the instruction <30h>, the memory controller 300 issues the instruction <00h>, the address <Ad13>, and the instruction <30h> to perform a normal read of plane 3 (PL3) of chip 1 (CP1). The address "Ad13" specifies the address of plane 3 of chip 1.

[0163] In chip 1 (CP1), the input / output circuit 10 receives the instruction <00h>, the address <Ad13>, and the instruction <30h> issued by the memory controller 300. Then, similar to the normal read of plane 3 (PL3) of chip 0 (CP0) described above, a normal read of plane 3 (PL3) of chip 1 (CP1) starts. The sequencer 30 of chip 1 (CP1) sets the signal CB13 to the busy state. The signal CB13 is stored in the status buffer 21. When the normal read in plane 3 (PL3) of chip 1 (CP1) ends, the sequencer 30 sets the signal CB13 to the ready state. Plane 3 (PL3) of chip 1 (CP1) can accept the next instruction.

[0164] Next, as Figure 10 shown, the memory controller 300 performs a status read of plane 0 (PL0) of chip 0 (CP0).

[0165] More specifically, after issuing the instruction <00h>, the address <Ad13>, and the instruction <30h>, the memory controller 300 issues the instruction <78h> and the address <Ad00> to perform a status read of plane 0 (PL0) of chip 0 (CP0). The instruction "78h" is an instruction to read the status information STS from the status buffer 21.

[0166] The sequencer 30 of chip 0 (CP0) sends the status information STS of the signal CB00 corresponding to the address <Ad00> to the memory controller 300.

[0167] Next, when receiving the signal CB00 indicating the ready state from the status register 21, the memory controller 300 performs a cache read of plane 0 (PL0) of chip 0 (CP0). Additionally, in this specification, "cache read" means that in the target plane, even if the storage of the read data DAT from the memory cell array 51 to the data buffer 54 is not completed (even if the signal CB is in the busy state), the read operation for the next instruction of the target plane is accepted.

[0168] More specifically, in order to perform a cache read of plane 0 (PL0) of chip 0 (CP0), the memory controller 300 issues an instruction <00h>, an address <Ad00>, and an instruction <31h>. The instruction "31h" is an instruction for performing a cache read in a single-plane read.

[0169] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad00>, and the instruction <31h> issued by the memory controller 300. Then, in the same manner as the normal read of plane 0 (PL0) of chip 0 (CP0), the cache read of plane 0 (PL0) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets the signal CB00 to the busy state. When the cache transfer (the transfer of the read data DAT from the memory cell array 51 to the corresponding data buffer 54 during the execution of the cache read) in plane 0 (PL0) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB00 to the ready state. However, when the sequencer 30 receives an instruction indicating the execution of the following prefetch, after continuing the cache transfer and performing the prefetch, it is set to the ready state.

[0170] Next, the memory controller 300 reserves the prefetch of the read data of the normal read to be performed in plane 0 (PL0) of chip 0 (CP0). Additionally, in this specification, "prefetch" means the operation of taking the data DAT read from the memory cell array 51 into the FIFO circuit 12 from the data buffer 54. Additionally, "reserving prefetch" means preparing for the execution of the prefetch and entering the standby state for the prefetch execution.

[0171] More specifically, by issuing an instruction <00h>, an address <Ad00>, and an instruction <31h>, during the period of performing the cache read (i.e., the period when the signal CB00 is in the busy state), the memory controller 300 issues an instruction <05h>, an address <Ad00>, and an instruction <E0h> in order to reserve the prefetch of plane 0 (PL0) of chip 0 (CP0). The instruction "05h" is an instruction for commanding the prefetch. The instruction "E0h" is an instruction indicating the execution of the prefetch.

[0172] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad00>, and instruction <E0h> sent by the memory controller 300. Based on address <Ad00>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 0 (MR0) of chip 0 (CP0), and copies instruction <05h> to the instruction buffer 0' (MR0') of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad00> to the row address buffer 0 (RR0) of chip 0 (CP0), and copies the row address RA of address <Ad00> to the row address buffer 0' (RR0') of chip 0 (CP0). The input / output circuit 10 sends the column address CA of the received address <Ad00> to the column address buffer 0 (CR0) of chip 0 (CP0), and copies the column address CA of address <Ad00> to the column address buffer 0' (CR0') of chip 0 (CP0). Based on address <Ad00>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 0 (MR0) of chip 0 (CP0), and copies instruction <E0h> to the instruction buffer 0' (MR0') of chip 0 (CP0).

[0173] If the row address RA of address <Ad00> is copied to the row address buffer 0' (RR0'), then the row address buffer 0' (RR0') sends the row address RA to the row decoder 52A.

[0174] When receiving instruction <E0h> from the instruction buffer 0' (MR0'), the sequencer 30 of chip 0 (CP0) reserves prefetch in plane 0 (PL0). Then, the sequencer 30 starts prefetching. If instruction <E0h> is received when signal CB00 is in the busy state, then the sequencer 30 performs prefetching of plane 0 (PL0) of chip 0 (CP0) during the period when signal CB00 is in the busy state. More specifically, if the sequencer 30 of chip 0 (CP0) receives instruction <E0h> when signal CB00 is in the busy state, then following the cache transfer, it performs prefetching, and after completing the prefetching, sets signal CB00 to the ready state.

[0175] When starting prefetching, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0' to 0. The column address buffer 0' (CR0') sends the initial column address CA to the last column address CA to the column decoders 55A - 55D. In column decoder 55A, based on the result of decoding the column address CA of address <Ad00>, the corresponding latch circuit within the data buffer 54A is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12.

[0176] Next, as Figure 10 shown, the memory controller 300 reads the status of plane 0 (PL0) of chip 1 (CP1).

[0177] More specifically, after sending instruction <05h>, address <Ad00>, and instruction <E0h>, the memory controller 300 issues instruction <78h> and address <Ad10> to perform the status read of plane 0 (PL0) of chip 1 (CP1).

[0178] The sequencer 30 of chip 1 (CP1) sends the status information STS of signal CB10 corresponding to address <Ad10> to the memory controller 300.

[0179] Next, when receiving signal CB10 indicating the ready state from the status buffer 21, the memory controller 300 performs the cache read of plane 0 (PL0) of chip 1 (CP1).

[0180] More specifically, the memory controller 300 issues instruction <00h>, address <Ad10>, and instruction <31h> to perform the cache read of plane 0 (PL0) of chip 1 (CP1).

[0181] In chip 1 (CP1), the input / output circuit 10 receives instruction <00h>, address <Ad10>, and instruction <31h> issued by the memory controller 300. Then, similar to the cache read of plane 0 (PL0) of chip 0 (CP0), the cache read of plane 0 (PL0) of chip 1 (CP1) is started. The sequencer 30 of chip 1 (CP1) sets signal CB10 to the busy state. When the cache transfer in plane 0 (PL0) of chip 1 (CP1) ends, the sequencer 30 sets signal CB10 to the ready state. However, when the sequencer 30 receives an instruction indicating the execution of prefetch, after continuing the cache transfer and performing the prefetch, it is set to the ready state.

[0182] Next, the memory controller 300 reserves the prefetch of the read data for the normal read performed in plane 0 (PL0) of chip 1 (CP1).

[0183] More specifically, by issuing instruction <00h>, address <Ad10>, and instruction <31h>, during the period of performing the cache read (i.e., the period when signal CB10 is in the busy state), the memory controller 300 issues instruction <05h>, address <Ad10>, and instruction <E0h> to reserve the prefetch of plane 0 (PL0) of chip 1 (CP1).

[0184] In chip 1 (CP1), the input / output circuit 10 receives the instruction <05h>, the address <Ad10>, and the instruction <E0h> issued by the memory controller 300. Then, similar to the prefetch reservation and execution of plane 0 (PL0) of chip 0 (CP0), the prefetch of plane 0 (PL0) of chip 1 (CP1) is reserved and the prefetch is started. If the instruction <E0h> is received while the signal CB10 is in the busy state, then the sequencer 30 of chip 1 (CP1) performs the prefetch of plane 0 (PL0) of chip 1 (CP1) during the period when the signal CB10 is in the busy state. More specifically, if the sequencer 30 of chip 1 (CP1) receives the instruction <E0h> while the signal CB10 is in the busy state, then following the cache transfer, the prefetch is performed, and after the prefetch is completed, the signal CB10 is set to the ready state.

[0185] Next, as Figure 10 shown, the memory controller 300 performs a status read of plane 1 (PL1) of chip 0 (CP0).

[0186] More specifically, after issuing the instruction <05h>, the address <Ad10>, and the instruction <E0h>, the memory controller 300 issues the instruction <78h> and the address <Ad01> in order to perform a status read of plane 1 (PL1) of chip 0 (CP0).

[0187] The sequencer 30 of chip 0 (CP0) sends the status information STS of the signal CB01 corresponding to the address <Ad01> to the memory controller 300.

[0188] Next, when receiving the signal CB01 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 0 (CP0).

[0189] More specifically, the memory controller 300 issues the instruction <00h>, the address <Ad01>, and the instruction <31h> in order to perform a cache read of plane 1 (PL1) of chip 0 (CP0).

[0190] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad01>, and the instruction <31h> issued by the memory controller 300. Then, similar to the normal read of plane 1 (PL1) of chip 0 (CP0), the cache read of plane 1 (PL1) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets the signal CB01 to the busy state. When the cache transfer in plane 1 (PL1) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB01 to the ready state.

[0191] Next, as Figure 11 shown, the memory controller 300 performs a status read of plane 1 (PL1) of chip 1 (CP1).

[0192] More specifically, after issuing instruction <00h>, address <Ad01>, and instruction <31h>, the memory controller 300 issues instruction <78h> and address <Ad11> to perform a status read of plane 1 (PL1) of chip 1 (CP1).

[0193] The sequencer 30 of chip 1 (CP1) sends the status information STS of signal CB11 corresponding to address <Ad11> to the memory controller 300.

[0194] Next, when receiving signal CB11 indicating a ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 1 (CP1).

[0195] More specifically, the memory controller 300 issues instruction <00h>, address <Ad11>, and instruction <31h> to perform a cache read of plane 1 (PL1) of chip 1 (CP1).

[0196] In chip 1 (CP1), the input / output circuit 10 receives instruction <00h>, address <Ad11>, and instruction <31h> issued by the memory controller 300. Then, similar to the cache read of plane 1 (PL1) of chip 0 (CP0) described above, the cache read of plane 1 (PL1) of chip 1 (CP1) is started. The sequencer 30 of chip 1 (CP1) sets signal CB11 to the busy state. When the cache transfer in plane 1 (PL1) of chip 1 (CP1) ends, the sequencer 30 sets signal CB11 to the ready state.

[0197] Next, as Figure 11 shown, the memory controller 300 performs a status read of plane 2 (PL2) of chip 0 (CP0).

[0198] More specifically, after issuing instruction <00h>, address <Ad11>, and instruction <31h>, the memory controller 300 issues instruction <78h> and address <Ad02> to perform a status read of plane 2 (PL2) of chip 0 (CP0).

[0199] The sequencer 30 of chip 0 (CP0) sends the status information STS of signal CB02 corresponding to address <Ad02> to the memory controller 300.

[0200] Next, when receiving the signal CB02 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 2 (PL2) of chip 0 (CP0).

[0201] More specifically, in order to perform a cache read of plane 2 (PL2) of chip 0 (CP0), the memory controller 300 issues an instruction <00h>, an address <Ad02>, and an instruction <31h>.

[0202] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad02>, and the instruction <31h> issued by the memory controller 300. Then, in the same manner as the normal read of plane 2 (PL2) of chip 0 (CP0), a cache read of plane 2 (PL2) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets the signal CB02 to the busy state. When the cache transfer in plane 2 (PL2) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB02 to the ready state.

[0203] Next, as Figure 11 shown, the memory controller 300 performs a status read of plane 2 (PL2) of chip 1 (CP1).

[0204] More specifically, after issuing the instruction <00h>, the address <Ad02>, and the instruction <31h>, the memory controller 300 issues an instruction <78h> and an address <Ad12> in order to perform a status read of plane 2 (PL2) of chip 1 (CP1).

[0205] The sequencer 30 of chip 1 (CP1) sends the status information STS of the signal CB12 corresponding to the address <Ad12> to the memory controller 300.

[0206] Next, when receiving the signal CB12 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 2 (PL2) of chip 1 (CP1).

[0207] More specifically, in order to perform a cache read of plane 2 (PL2) of chip 1 (CP1), the memory controller 300 issues an instruction <00h>, an address <Ad12>, and an instruction <31h>.

[0208] In chip 1 (CP1), the input / output circuit 10 receives instruction <00h>, address <Ad12>, and instruction <31h> issued by the memory controller 300. Then, similar to the cache read of plane 2 (PL2) of chip 0 (CP0), the cache read of plane 2 (PL2) of chip 1 (CP1) is started. The sequencer 30 of chip 1 (CP1) sets signal CB12 to the busy state. When the cache transfer in plane 2 (PL2) of chip 1 (CP1) ends, the sequencer 30 sets signal CB12 to the ready state.

[0209] Next, as Figure 11 shown, the memory controller 300 performs a status read of plane 3 (PL3) of chip 0 (CP0).

[0210] More specifically, after issuing instruction <00h>, address <Ad12>, and instruction <31h>, the memory controller 300 issues instruction <78h> and address <Ad03> to perform a status read of plane 3 (PL3) of chip 0 (CP0).

[0211] The sequencer 30 of chip 0 (CP0) sends the status information STS of signal CB03 corresponding to address <Ad03> to the memory controller 300.

[0212] Next, when receiving signal CB03 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 0 (CP0).

[0213] More specifically, the memory controller 300 issues instruction <00h>, address <Ad03>, and instruction <31h> to perform a cache read of plane 3 (PL3) of chip 0 (CP0).

[0214] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad03>, and instruction <31h> issued by the memory controller 300. Then, similar to the normal read of plane 3 (PL3) of chip 0 (CP0), the cache read of plane 3 (PL3) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets signal CB03 to the busy state. When the cache transfer in plane 3 (PL3) of chip 0 (CP0) ends, the sequencer 30 sets signal CB03 to the ready state.

[0215] Next, as Figure 12 shown, the memory controller 300 performs a status read of plane 3 (PL3) of chip 1 (CP1).

[0216] More specifically, after sending instruction <00h>, address <Ad03>, and instruction <31h>, the memory controller 300 issues instruction <78h> and address <Ad13> to perform a status read of plane 3 (PL3) of chip 1 (CP1).

[0217] Sequencer 30 of chip 1 (CP1) sends the status information STS of signal CB13 corresponding to address <Ad13> to the memory controller 300.

[0218] Next, when receiving signal CB13 indicating a ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 1 (CP1).

[0219] More specifically, the memory controller 300 issues instruction <00h>, address <Ad13>, and instruction <31h> to perform a cache read of plane 3 (PL3) of chip 1 (CP1).

[0220] In chip 1 (CP1), the input / output circuit 10 receives instruction <00h>, address <Ad13>, and instruction <31h> issued by the memory controller 300. Then, similar to the cache read of plane 3 (PL3) of chip 0 (CP0), the cache read of plane 3 (PL3) of chip 1 (CP1) is started. Sequencer 30 of chip 1 (CP1) sets signal CB13 to the busy state. When the cache transfer in plane 3 (PL3) of chip 1 (CP1) ends, sequencer 30 sets signal CB13 to the ready state.

[0221] Next, as Figure 12 shown, the memory controller 300 performs a status read of plane 0 (PL0) of chip 0 (CP0). The details of this status read performed by issuing instruction <78h> and address <Ad00> after issuing instruction <00h>, address <Ad13>, and instruction <31h> are the same as the status read of plane 0 (PL0) of chip 0 (CP0) described above.

[0222] Next, when receiving signal CB00 indicating a ready state from the status buffer 21, the memory controller 300 performs data output of plane 0 (PL0) of chip 0 (CP0). Additionally, in this specification, "data output" means the action of outputting data DAT taken into the FIFO circuit 12 from the data buffer 54 through the DQ pad 11 to the memory controller 300 from the FIFO circuit 12.

[0223] More specifically, the memory controller 300 issues an instruction <XXh> to execute the data output of plane 0 (PL0) of chip 0 (CP0). The instruction "XXh" is an instruction for selecting a chip and a plane and executing data output.

[0224] In chip 0 (CP0), the input / output circuit 10 receives the instruction <XXh> issued by the memory controller 300. The input / output circuit 10 sends the received instruction <XXh> to the instruction buffer 0 (MR0) of chip 0 (CP0).

[0225] When receiving the instruction <XXh> from the instruction buffer 0 (MR0), the sequencer 30 of chip 0 (CP0) starts to execute the data output of the prefetched plane 0 (PL0).

[0226] Next, as Figure 12 shown, the memory controller 300 reserves the prefetch of the readout data of the normal read to be executed in plane 1 (PL1) of chip 0 (CP0).

[0227] More specifically, when the data output in plane 0 (PL0) of chip 0 (CP0) ends, the memory controller 300 issues an instruction <05h>, an address <Ad01>, and an instruction <E0h> to reserve the prefetch of plane 1 (PL1) of chip 0 (CP0).

[0228] In chip 0 (CP0), the input / output circuit 10 receives the instruction <05h>, the address <Ad01>, and the instruction <E0h> issued by the memory controller 300. Based on the address <Ad01>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 1 (MR1) of chip 0 (CP0) and copies the instruction <05h> to the instruction buffer 1' (MR1') of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad01> to the row address buffer 1 (RR1) of chip 0 (CP0) and copies the row address RA of the address <Ad01> to the row address buffer 1' (RR1') of chip 0 (CP0). The input / output circuit 10 sends the column address CA of the received address <Ad01> to the column address buffer 0 (CR0) of chip 0 (CP0) and copies the column address CA of the address <Ad01> to the column address buffer 0' (CR0') of chip 0 (CP0). Based on the address <Ad01>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 1 (MR1) of chip 0 (CP0) and copies the instruction <E0h> to the instruction buffer 1' (MR1') of chip 0 (CP0).

[0229] When the row address RA at address <Ad01> is copied to the row address buffer 1' (RR1'), the row address buffer 1' (RR1') sends the row address RA to the row decoder 52B.

[0230] When receiving the instruction <E0h> from the instruction buffer 1' (MR1'), the sequencer 30 of chip 0 (CP0) reserves a prefetch in plane 1 (PL1). Then, the sequencer 30 starts the prefetch. When receiving the instruction <E0h> while the signal CB01 is in the ready state, the sequencer 30 immediately performs the prefetch of plane 1 (PL1) of chip 0 (CP0).

[0231] When starting the prefetch, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0' to 0. The column address buffer 0' (CR0') sends the initial column address CA to the last column address CA to the column decoders 55A - 55D. In the column decoder 55B, based on the result of decoding the column address CA of address <Ad01>, the corresponding latch circuit in the data buffer 54B is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12.

[0232] Next, as Figure 12 shown, the memory controller 300 performs a cache read of plane 0 (PL0) of chip 0 (CP0). After issuing the instruction <05h>, address <Ad01>, and instruction <E0h>, the details of this cache read executed by issuing the instruction <00h>, address <Ad00>, and instruction <31h> are the same as the cache read of plane 0 (PL0) of chip 0 (CP0) described above. When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB00 to the busy state. When the cache transfer ends in plane 0 (PL0) of chip 0 (CP0), the sequencer 30 sets the signal CB00 to the ready state.

[0233] Next, as Figure 13 shown, the memory controller 300 performs a status read of plane 0 (PL0) of chip 1 (CP1). After issuing the instruction <00h>, address <Ad00>, and instruction <31h>, the details of this status read executed by issuing the instruction <78h> and address <Ad10> are the same as the status read of plane 0 (PL0) of chip 1 (CP1) described above.

[0234] Next, when receiving the signal CB10 indicating the ready state from the status buffer 21, the memory controller 300 performs the data output of plane 0 (PL0) of chip 1 (CP1).

[0235] More specifically, the memory controller 300 issues an instruction <XXh> to perform data output of plane 0 (PL0) of chip 1 (CP1).

[0236] In chip 1 (CP1), the input / output circuit 10 receives the instruction <XXh> issued by the memory controller 300. Then, similar to the data output of plane 0 (PL0) of chip 0 (CP0), it starts to perform the data output of the prefetched plane 0 (PL0).

[0237] Next, as Figure 13 shown, the memory controller 300 reserves the prefetch of the readout data of the normal read to be performed on plane 1 (PL1) of chip 1 (CP1).

[0238] More specifically, when the data output in plane 0 (PL0) of chip 1 (CP1) ends, the memory controller 300 issues an instruction <05h>, an address <Ad11>, and an instruction <E0h> to reserve the prefetch of plane 1 (PL1) of chip 1 (CP1).

[0239] In chip 1 (CP1), the input / output circuit 10 receives the instruction <05h>, the address <Ad11>, and the instruction <E0h> issued by the memory controller 300. Then, similar to the reservation and execution of the prefetch of plane 1 (PL1) of chip 0 (CP0), it reserves the prefetch of plane 1 (PL1) of chip 1 (CP1) and starts the prefetch. When the instruction <E0h> is received while the signal CB11 is in the ready state, the sequencer 30 of chip 1 (CP1) immediately performs the prefetch of plane 1 (PL1) of chip 1 (CP1).

[0240] Next, the memory controller 300 performs a cache read of plane 0 (PL0) of chip 1 (CP1). The details of this cache read, which is performed by issuing an instruction <00h>, an address <Ad10>, and an instruction <31h> after issuing the instruction <05h>, the address <Ad11>, and the instruction <E0h>, are the same as the cache read of plane 0 (PL0) of chip 1 (CP1) described above. When starting this cache read, the sequencer 30 of chip 1 (CP1) sets the signal CB10 to the busy state. When the cache transfer in plane 0 (PL0) of chip 1 (CP1) ends, the sequencer 30 sets the signal CB10 to the ready state.

[0241] Next, as Figure 13As shown, the memory controller 300 performs a status read of plane 1 (PL1) of chip 0 (CP0). After issuing instruction <00h>, address <Ad10>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad01> are the same as the status read of plane 1 (PL1) of chip 0 (CP0) described above.

[0242] Next, when receiving the signal CB01 indicating a ready state from the status buffer 21, the memory controller 300 performs data output of plane 1 (PL1) of chip 0 (CP0).

[0243] More specifically, the memory controller 300 issues instruction <XXh> to perform data output of plane 1 (PL1) of chip 0 (CP0).

[0244] In chip 0 (CP0), the input / output circuit 10 receives instruction <XXh> issued by the memory controller 300. The input / output circuit 10 sends the received instruction <XXh> to the instruction buffer 1 (MR1) of chip 0 (CP0).

[0245] When receiving instruction <XXh> from the instruction buffer 1 (MR1), the sequencer 30 of chip 0 (CP0) starts to execute the pre-fetched data output of plane 1 (PL1).

[0246] Next, as Figure 14 shown, the memory controller 300 reserves the pre-fetch of the readout data of the normal read performed in plane 2 (PL2) of chip 0 (CP0).

[0247] More specifically, when the data output in plane 1 (PL1) of chip 0 (CP0) ends, the memory controller 300 issues instruction <05h>, address <Ad02>, and instruction <E0h> to reserve the pre-fetch of plane 2 (PL2) of chip 0 (CP0).

[0248] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad02>, and instruction <E0h> issued by the memory controller 300. Based on the address <Ad02>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 2 (MR2) of chip 0 (CP0), and copies the instruction <05h> to the instruction buffer 2' (MR2') of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad02> to the row address buffer 2 (RR2) of chip 0 (CP0), and copies the row address RA of the address <Ad02> to the row address buffer 2' (RR2') of chip 0 (CP0). The input / output circuit 10 sends the column address CA of the received address <Ad02> to the column address buffer 0 (CR0) of chip 0 (CP0), and copies the column address CA of the address <Ad02> to the column address buffer 0' (CR0') of chip 0 (CP0). Based on the address <Ad02>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 2 (MR2) of chip 0 (CP0), and copies the instruction <E0h> to the instruction buffer 2' (MR2') of chip 0 (CP0).

[0249] When the row address RA of the address <Ad02> is copied to the row address buffer 2' (RR2'), the row address buffer 2' (RR2') sends the row address RA to the row decoder 52C.

[0250] When receiving the instruction <E0h> from the instruction buffer 2' (MR2'), the sequencer 30 of chip 0 (CP0) reserves prefetch in plane 2 (PL2). Then, the sequencer 30 starts prefetch. When receiving the instruction <E0h> while the signal CB02 is in the ready state, the sequencer 30 immediately performs prefetch of plane 2 (PL2) of chip 0 (CP0).

[0251] When starting prefetch, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0' to 0. The column address buffer 0' (CR0') sends the initial column address CA to the last column address CA to the column decoders 55A - 55D. In the column decoder 55C, based on the result of decoding the column address CA of the address <Ad02>, the corresponding latch circuit in the data buffer 54C is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12.

[0252] Next, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 0 (CP0). After issuing instruction <05h>, address <Ad02>, and instruction <E0h>, the details of this cache read performed by issuing instruction <00h>, address <Ad01>, and instruction <31h> are the same as the aforementioned cache read of plane 1 (PL1) of chip 0 (CP0). When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB01 to the busy state. When the cache transfer ends in plane 1 (PL1) of chip 0 (CP0), sequencer 30 sets signal CB01 to the ready state.

[0253] Next, as Figure 14 shown, the memory controller 300 performs a status read of plane 1 (PL1) of chip 1 (CP1). After issuing instruction <00h>, address <Ad01>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad11> are the same as the aforementioned status read of plane 1 (PL1) of chip 1 (CP1).

[0254] Next, when receiving signal CB11 indicating the ready state from status buffer 21, the memory controller 300 performs data output of plane 1 (PL1) of chip 1 (CP1).

[0255] More specifically, the memory controller 300 issues instruction <XXh> in order to perform data output of plane 1 (PL1) of chip 1 (CP1).

[0256] In chip 1 (CP1), input / output circuit 10 receives instruction <XXh> issued by the memory controller 300. Then, similar to the data output of plane 1 (PL1) of chip 0 (CP0), the data output of the prefetched plane 1 (PL1) starts to be executed.

[0257] Next, as Figure 14 shown, the memory controller 300 reserves the prefetch of the readout data of the normal read to be performed in plane 2 (PL2) of chip 1 (CP1).

[0258] More specifically, when the data output ends in plane 1 (PL1) of chip 1 (CP1), the memory controller 300 issues instruction <05h>, address <Ad12>, and instruction <E0h> in order to reserve the prefetch of plane 2 (PL2) of chip 1 (CP1).

[0259] In chip 1 (CP1), the input / output circuit 10 receives the instruction <05h>, the address <Ad12>, and the instruction <E0h> issued by the memory controller 300. Then, similar to the prefetch reservation and execution of plane 2 (PL2) of chip 0 (CP0), the prefetch of plane 2 (PL2) of chip 1 (CP1) is reserved and prefetching is started. When the instruction <E0h> is received while the signal CB12 is in the ready state, the sequencer 30 of chip 1 (CP1) immediately executes the prefetch of plane 2 (PL2) of chip 1 (CP1).

[0260] Next, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 1 (CP1). After issuing the instruction <05h>, the address <Ad12>, and the instruction <E0h>, the details of this cache read performed by issuing the instruction <00h>, the address <Ad11>, and the instruction <31h> are the same as the aforementioned cache read of plane 1 (PL1) of chip 1 (CP1). When starting this cache read, the sequencer 30 of chip 1 (CP1) sets the signal CB11 to the busy state. When the cache transfer ends in plane 1 (PL1) of chip 1 (CP1), the sequencer 30 sets the signal CB11 to the ready state.

[0261] Next, as Figure 15 shown, the memory controller 300 performs a status read of plane 2 (PL2) of chip 0 (CP0). After issuing the instruction <00h>, the address <Ad11>, and the instruction <31h>, the details of this status read performed by issuing the instruction <78h> and the address <Ad02> are the same as the aforementioned status read of plane 2 (PL2) of chip 0 (CP0).

[0262] Next, when receiving the signal CB02 indicating the ready state from the status buffer 21, the memory controller 300 performs the data output of plane 2 (PL2) of chip 0 (CP0).

[0263] More specifically, the memory controller 300 issues the instruction <XXh> in order to perform the data output of plane 2 (PL2) of chip 0 (CP0).

[0264] In chip 0 (CP0), the input / output circuit 10 receives the instruction <XXh> issued by the memory controller 300. The input / output circuit 10 sends the received instruction <XXh> to the instruction buffer 2 (MR2) of chip 0 (CP0).

[0265] When receiving the instruction <XXh> from the instruction buffer 2 (MR2), the sequencer 30 of chip 0 (CP0) starts the data output of plane 2 (PL2) after completing the prefetch.

[0266] Next, as Figure 15 shown, the memory controller 300 reserves the prefetch of the readout data of the normal read to be executed on plane 3 (PL3) of chip 0 (CP0).

[0267] More specifically, when the data output in plane 2 (PL2) of chip 0 (CP0) ends, the memory controller 300 issues instruction <05h>, address <Ad03>, and instruction <E0h> to reserve the prefetch of plane 3 (PL3) of chip 0 (CP0).

[0268] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad03>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad03>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 3 (MR3) of chip 0 (CP0), and copies instruction <05h> to the instruction buffer 3' (MR3') of chip 0 (CP0). The input / output circuit 10 sends the row address RA of the received address <Ad03> to the row address buffer 3 (RR3) of chip 0 (CP0), and copies the row address RA of address <Ad03> to the row address buffer 3' (RR3') of chip 0 (CP0). The input / output circuit 10 sends the column address CA of the received address <Ad03> to the column address buffer 0 (CR0) of chip 0 (CP0), and copies the column address CA of address <Ad03> to the column address buffer 0' (CR0') of chip 0 (CP0). Based on address <Ad03>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 3 (MR3) of chip 0 (CP0), and copies instruction <E0h> to the instruction buffer 3' (MR3') of chip 0 (CP0).

[0269] When the row address RA of address <Ad03> is copied to the row address buffer 3' (RR3'), the row address buffer 3' (RR3') sends the row address RA to the row decoder 52D.

[0270] When receiving instruction <E0h> from the instruction buffer 3' (MR3'), the sequencer 30 of chip 0 (CP0) reserves the prefetch in plane 3 (PL3). Then, the sequencer 30 starts the prefetch. When receiving instruction <E0h> when the signal CB03 is in the ready state, the sequencer 30 immediately executes the prefetch of plane 3 (PL3) of chip 0 (CP0).

[0271] When starting prefetching, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0’ to 0. The column address buffer 0’ (CR0’) sends the initial column address CA to the final column address CA to the column decoders 55A to 55D. In the column decoder 55D, based on the result of decoding the column address CA of the address <Ad03>, the corresponding latch circuit in the data buffer 54D is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12.

[0272] Next, the memory controller 300 performs a cache read of plane 2 (PL2) of chip 0 (CP0). After issuing the instruction <05h>, the address <Ad03>, and the instruction <E0h>, the details of this cache read performed by issuing the instruction <00h>, the address <Ad02>, and the instruction <31h> are the same as the aforementioned cache read of plane 2 (PL2) of chip 0 (CP0). When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB02 to the busy state. When the cache transfer ends in plane 2 (PL2) of chip 0 (CP0), the sequencer 30 sets the signal CB02 to the ready state.

[0273] Next, as Figure 15 shown, the memory controller 300 performs a status read of plane 2 (PL2) of chip 1 (CP1). After issuing the instruction <00h>, the address <Ad02>, and the instruction <31h>, the details of this status read performed by issuing the instruction <78h> and the address <Ad12> are the same as the aforementioned status read of plane 2 (PL2) of chip 1 (CP1).

[0274] Next, when receiving the signal CB12 indicating the ready state from the status buffer 21, the memory controller 300 performs a data output of plane 2 (PL2) of chip 1 (CP1).

[0275] More specifically, the memory controller 300 issues the instruction <XXh> in order to perform the data output of plane 2 (PL2) of chip 1 (CP1).

[0276] In chip 1 (CP1), the input / output circuit 10 receives the instruction <XXh> issued by the memory controller 300. Then, similar to the data output of plane 2 (PL2) of chip 0 (CP0), the data output of plane 2 (PL2) after the prefetch is completed starts to be executed.

[0277] Next, as Figure 16 shown, the memory controller 300 reserves the prefetch of the readout data of the normal read to be performed in plane 3 (PL3) of chip 1 (CP1).

[0278] More specifically, when the data output in plane 2 (PL2) of chip 1 (CP1) ends, the memory controller 300 issues instruction <05h>, address <Ad13>, and instruction <E0h> to reserve the prefetch of plane 3 (PL3) of chip 1 (CP1).

[0279] In chip 1 (CP1), the input / output circuit 10 receives instruction <05h>, address <Ad13>, and instruction <E0h> issued by the memory controller 300. Then, similar to the reservation and execution of the prefetch of plane 3 (PL3) of chip 0 (CP0), the prefetch of plane 3 (PL3) of chip 1 (CP1) is reserved and the prefetch is started. When instruction <E0h> is received while signal CB13 is in the ready state, sequencer 30 of chip 1 (CP1) immediately executes the prefetch of plane 3 (PL3) of chip 1 (CP1).

[0280] Next, the memory controller 300 performs the cache read of plane 2 (PL2) of chip 1 (CP1). The details of this cache read, which is performed by issuing instruction <00h>, address <Ad12>, and instruction <31h> after issuing instruction <05h>, address <Ad13>, and instruction <E0h>, are the same as the aforementioned cache read of plane 2 (PL2) of chip 1 (CP1). When starting this cache read, sequencer 30 of chip 1 (CP1) sets signal CB12 to the busy state. When the cache transfer in plane 2 (PL2) of chip 1 (CP1) ends, sequencer 30 sets signal CB12 to the ready state.

[0281] Next, as Figure 16 shown, the memory controller 300 performs the status read of plane 3 (PL3) of chip 0 (CP0). The details of this status read, which is performed by issuing instruction <78h> and address <Ad03> after issuing instruction <00h>, address <Ad12>, and instruction <31h>, are the same as the aforementioned status read of plane 3 (PL3) of chip 0 (CP0).

[0282] Next, when receiving the signal CB03 indicating the ready state from the status buffer 21, the memory controller 300 performs the data output of plane 3 (PL3) of chip 0 (CP0).

[0283] More specifically, the memory controller 300 issues instruction <XXh> to perform the data output of plane 3 (PL3) of chip 0 (CP0).

[0284] In chip 0 (CP0), the input / output circuit 10 receives the instruction <XXh> issued by the memory controller 300. The input / output circuit 10 sends the received instruction <XXh> to the instruction buffer 3 (MR3) of chip 0 (CP0).

[0285] When receiving the instruction <XXh> from the instruction buffer 3 (MR3), the sequencer 30 of chip 0 (CP0) starts to execute the data output of the prefetched plane 3 (PL3).

[0286] Next, as Figure 16 shown, the memory controller 300 reserves the prefetch of the readout data of the cache read performed in plane 0 (PL0) of chip 0 (CP0).

[0287] More specifically, when the data output in plane 3 (PL3) of chip 0 (CP0) ends, the memory controller 300 issues the instruction <05h>, the address <Ad00>, and the instruction <E0h> to reserve the prefetch of plane 0 (PL0) of chip 0 (CP0).

[0288] In chip 0 (CP0), the input / output circuit 10 receives the instruction <05h>, the address <Ad00>, and the instruction <E0h> issued by the memory controller 300. Then, in the same way as the reservation and execution of the prefetch of plane 0 (PL0) of chip 0 (CP0), the prefetch of plane 0 (PL0) of chip 0 (CP0) is reserved and the prefetch is started. When receiving the instruction <E0h> while the signal CB00 is in the busy state, the sequencer 30 of chip 0 (CP0) performs the prefetch of plane 0 (PL0) of chip 0 (CP0) during the period when the signal CB00 is in the busy state.

[0289] Next, the memory controller 300 performs the cache read of plane 3 (PL3) of chip 0 (CP0). The details of this cache read performed by issuing the instruction <00h>, the address <Ad03>, and the instruction <31h> after issuing the instruction <05h>, the address <Ad00>, and the instruction <E0h> are the same as the cache read of plane 3 (PL3) of chip 0 (CP0) described above. When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB03 to the busy state. When the cache transfer in plane 3 (PL3) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB03 to the ready state.

[0290] Next, as Figure 17As shown, the memory controller 300 performs a status read of plane 3 (PL3) of chip 1 (CP1). After issuing instruction <00h>, address <Ad03>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad13> are the same as the status read of plane 3 (PL3) of chip 1 (CP1) described above.

[0291] Next, when receiving the signal CB13 indicating the ready state from the status buffer 21, the memory controller 300 performs data output of plane 3 (PL3) of chip 1 (CP1).

[0292] More specifically, the memory controller 300 issues instruction <XXh> to perform data output of plane 3 (PL3) of chip 1 (CP1).

[0293] In chip 1 (CP1), the input / output circuit 10 receives instruction <XXh> issued by the memory controller 300. Then, similar to the data output of plane 3 (PL3) of chip 0 (CP0), it starts to perform the data output of the prefetched plane 3 (PL3).

[0294] Next, as Figure 17 shown, the memory controller 300 reserves the prefetch of the readout data of the cache read to be performed in plane 0 (PL0) of chip 1 (CP1).

[0295] More specifically, when the data output in plane 3 (PL3) of chip 1 (CP1) ends, the memory controller 300 issues instruction <05h>, address <Ad10>, and instruction <E0h> to reserve the prefetch of plane 0 (PL0) of chip 1 (CP1).

[0296] In chip 1 (CP1), the input / output circuit 10 receives instruction <05h>, address <Ad10>, and instruction <E0h> issued by the memory controller 300. Then, similar to the reservation and execution of the prefetch of plane 0 (PL0) of chip 1 (CP1) described above, it reserves the prefetch of plane 0 (PL0) of chip 1 (CP1) and starts the prefetch. When receiving instruction <E0h> while the signal CB10 is in the busy state, the sequencer 30 of chip 1 (CP1) performs the prefetch of plane 0 (PL0) of chip 1 (CP1) during the period when the signal CB10 is in the busy state.

[0297] Next, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 1 (CP1). After issuing instruction <05h>, address <Ad10>, and instruction <E0h>, the details of this cache read performed by issuing instruction <00h>, address <Ad13>, and instruction <31h> are the same as the described cache read of plane 3 (PL3) of chip 1 (CP1). When starting this cache read, sequencer 30 of chip 1 (CP1) sets signal CB13 to the busy state. When the cache transfer ends in plane 3 (PL3) of chip 1 (CP1), sequencer 30 sets signal CB13 to the ready state.

[0298] Thereafter, the instruction sequence during E to K is repeated until all the data to be read out in planes 0 to 3 (PL0 to PL3) of chip 0 (CP0) and planes 0 to 3 (PL0 to PL3) of chip 1 (CP1) are output as data.

[0299] 1.3 Effects

[0300] In Figure 39 shows the operation of the NAND chip of the comparative example. After the NAND chip of the comparative example receives instruction <00h>, address <Ad00>, and instruction <31h> for performing a cache read from the memory controller 300, it receives instruction <05h>, address <Ad00>, and instruction <E0h> for performing data output. Moreover, when the signal CB becomes the ready state after the NAND chip of the comparative example receives the instruction "31h" issued from the memory controller 300, it performs prefetch and data output by receiving the instruction "05h".

[0301] In contrast, in the memory system 100 of the present embodiment, the memory controller 300 issues instruction <05h>, address <Ad00>, and instruction <E0h> for reserving prefetch in the middle between issuing instruction <00h>, address <Ad00>, and instruction <31h> for performing a cache read from the semiconductor memory device 200 and issuing instruction "XXh" for performing data output. The NAND chip of the present embodiment can receive the instruction "05h" regardless of whether the signal CB is in the busy state or the ready state. Thus, when the NAND chip of the present embodiment receives the instruction "05h" in the middle between receiving the instruction "31h" issued from the memory controller 300 and receiving the instruction "XXh", it can reserve prefetch.

[0302] In Figure 40This shows the operation when the instruction "05h" is accepted while the signal CB is in the busy state in the NAND chip of the present embodiment. In this case, the sequencer 30 continues the cache transfer and performs prefetch, and after the prefetch is completed, the signal CB is set to the ready state. As a result, before the signal CB becomes the ready state, the data DAT read from the memory cell array 51 into the data buffer 54 is fetched from the data buffer 54 into the FIFO circuit 12. Therefore, data output can be immediately executed after the signal CB becomes the ready state.

[0303] According to the configuration of the present embodiment, the memory controller 300 can issue the instruction "05h" to each plane in the chip regardless of whether the signal CB is in the busy state or the ready state during the period from issuing the instruction "31h" to issuing the instruction "XXh". That is, since prefetch can be reserved during the read operation, the period until data output starts can be shortened compared to the case where prefetch is reserved after the read operation ends. Therefore, the operation of the memory system can be speeded up.

[0304] In addition, as Figures 8 - 17 shown, in the memory system 100 of the present embodiment, after the memory controller 300 issues the instruction <05h> for reserving prefetch, the address <Ad00>, and the instruction <E0h> for any one of the multiple NAND chips included in the semiconductor memory device 200, and during the prefetch execution in the NAND chip, for other NAND chips, for example, an instruction for instructing cache read can be issued. Therefore, in the configuration where multiple NAND chips are connected to one data bus DB, the time when the data bus DB is not used can be suppressed, and the usage efficiency of the data bus DB can be improved.

[0305] 2. Second Embodiment

[0306] The memory system 100 of the second embodiment will be described. The memory system 100 of the present embodiment has two FIFO circuits provided in the input / output circuit 10 and four row address buffers provided in the address buffer 22 in the memory system 100 of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0307] 2.1 Configuration of Input / Output Circuit 10

[0308] Regarding the configuration of the input / output circuit 10, Figure 18 is used for the description. Figure 18 is a block diagram showing the configuration of the NAND chip 0 (CP0) included in the memory system 100 of the present embodiment, focusing on the input / output circuit 10 and the buffer 20. In addition, in Figure 18 the status buffer 21 and the voltage generation circuit 40 are omitted.

[0309] The input / output circuit 10 includes DQ pads 11, and FIFO circuits 12A and 12B. The DQ pad 11 is connected to data buffers 54A and 54C via the FIFO circuit 12A. Additionally, the DQ pad 11 is connected to data buffers 54B and 54D via the FIFO circuit 12B. The FIFO circuits 12A and 12B have the same configuration as the FIFO circuit 12 described in the Figure 6 first embodiment.

[0310] 2.2 Configuration of Buffer 20

[0311] The configuration of buffer 20 will be described using Figure 18 the following.

[0312] The address buffer 22 in the address buffer 22 described in the first embodiment Figure 6 further includes a column address buffer 1 (CR1) and a column address buffer 1' (CR1'). The column address buffer 1 (CR1) has the same configuration as the column address buffer 0 (CR0) described in the Figure 6 first embodiment. The column address buffer 1' (CR1') has the same configuration as the column address buffer 0' (CR0') described in the Figure 6 first embodiment.

[0313] The column address buffer 0 (CR0) is connected to the input / output circuit 10, and planes 0 and 2 (PL0 and PL2), and stores the column addresses CA of planes 0 and 2 (PL0 and PL2) received from the input / output circuit 10. The column address buffer 0' (CR0') is connected to the column address buffer 0 (CR0), and planes 0 and 2 (PL0 and PL2), and stores the (duplicated) column addresses CA received from the column address buffer 0 (CR0).

[0314] The column address buffer 1 (CR1) is connected to the input / output circuit 10, and planes 1 and 3 (PL1 and PL3), and stores the column addresses CA of planes 1 and 3 (PL1 and PL3) received from the input / output circuit 10. The column address buffer 1' (CR1') is connected to the column address buffer 1 (CR1), and planes 1 and 3 (PL1 and PL3), and stores the (duplicated) column addresses CA received from the column address buffer 1 (CR1).

[0315] Column address buffer 0 (CR0) sends column address CA to column decoders 55A and 55C. More specifically, column address buffer 0 (CR0) sends the initial column address CA of the plane specified by column address CA to column decoders 55A and 55C. When sending the initial column address CA to column decoders 55A and 55C, column address counter circuit CC0 increments column address CA by only 1, and column address buffer 0 (CR0) sends the next column address CA of the initial column address CA to column decoders 55A and 55C. When sending the last column address CA to column decoders 55A and 55C, the transmission of column address CA to column decoders 55A and 55C ends. Column address buffer 0' (CR0') sends column address CA to column decoders 55A and 55C in the same manner as column address buffer 0 (CR0).

[0316] Column address buffer 1 (CR1) sends column address CA to column decoders 55B and 55D. More specifically, column address buffer 1 (CR1) sends the initial column address CA of the plane specified by column address CA to column decoders 55B and 55D. When sending the initial column address CA to column decoders 55B and 55D, column address counter circuit CC1 increments column address CA by only 1, and column address buffer 1 (CR1) sends the next column address CA of the initial column address CA to column decoders 55B and 55D. When sending the last column address CA to column decoders 55B and 55D, the transmission of column address CA to column decoders 55B and 55D ends. Column address buffer 1' (CR1') sends column address CA to column decoders 55B and 55D in the same manner as column address buffer 1 (CR1).

[0317] 2.3 Operations

[0318] For the operation of the memory system 100 of this embodiment, it is described using Figures 19 - 23 as follows. Figures 19 - 23 FIG. is an example of an instruction sequence showing the read operation of the memory system 100 of this embodiment. Hereinafter, an example is given in which signals CEn1 and CEn2 are the same signal (CEn1 = CEn2 = CEn), and in chip 0 (CP0), data is read repeatedly in the order of planes 0 to 3 (PL0 to PL3). In Figures 19 - 23 the signals CB00 to CB03 of each plane of chip 0 (CP0) are also shown. The same applies to the case of reading data from chip 1 (CP1). The read operation of this embodiment is single-plane reading.

[0319] First, as Figure 19 shown, memory controller 300 performs normal reading of plane 0 (PL0) of chip 0 (CP0).

[0320] More specifically, after setting the signal CEn to the "L" level, the memory controller 300 issues an instruction <00h>, an address <Ad00>, and an instruction <30h> to perform a normal read of plane 0 (PL0) of chip 0 (CP0).

[0321] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad00>, and the instruction <30h> issued by the memory controller 300. Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 0 (MR0). The input / output circuit 10 sends the row address RA of the received address <Ad00> to the row address buffer 0 (RR0), and sends the column address CA of the received address <Ad00> to the column address buffer 0 (CR0). Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 0 (MR0).

[0322] When the row address RA of the address <Ad00> is stored in the row address buffer 0 (RR0), the row address buffer 0 (RR0) sends the row address RA to the row decoder 52A.

[0323] When receiving the instruction <30h> from the instruction buffer 0 (MR0), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 0 (PL0). The sequencer 30 sets the signal CB00 to the busy state. The signal CB00 is stored in the status buffer 21. When the normal read in plane 0 (PL0) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB00 to the ready state. Plane 0 (PL0) of chip 0 (CP0) can accept the next instruction.

[0324] Next, the memory controller 300 performs a normal read of plane 1 (PL1) of chip 0 (CP0).

[0325] More specifically, after issuing the instruction <00h>, the address <Ad00>, and the instruction <30h>, the memory controller 300 issues an instruction <00h>, an address <Ad01>, and an instruction <30h> to perform a normal read of plane 1 (PL1) of chip 0 (CP0).

[0326] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad01>, and the instruction <30h> issued by the memory controller 300. Based on the address <Ad01>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 1 (MR1). The input / output circuit 10 sends the row address RA of the received address <Ad01> to the row address buffer 1 (RR1), and sends the column address CA of the received address <Ad01> to the column address buffer 1 (CR1). Based on the address <Ad01>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 1 (MR1).

[0327] When the row address RA of the address <Ad01> is stored in the row address buffer 1 (RR1), the row address buffer 1 (RR1) sends the row address RA to the row decoder 52B.

[0328] When receiving the instruction <30h> from the instruction buffer 1 (MR1), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 1 (PL1). The sequencer 30 sets the signal CB01 to the busy state. The signal CB01 is stored in the status buffer 21. When the normal read in plane 1 (PL1) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB01 to the ready state. Plane 1 (PL1) of chip 0 (CP0) can accept the next instruction.

[0329] Next, the memory controller 300 performs a normal read of plane 2 (PL2) of chip 0 (CP0).

[0330] More specifically, after issuing the instruction <00h>, the address <Ad01>, and the instruction <30h>, the memory controller 300 issues the instruction <00h>, the address <Ad02>, and the instruction <30h> to perform a normal read of plane 2 (PL2) of chip 0 (CP0).

[0331] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad02>, and the instruction <30h> issued by the memory controller 300. Based on the address <Ad02>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 2 (MR2). The input / output circuit 10 sends the row address RA of the received address <Ad02> to the row address buffer 2 (RR2), and sends the column address CA of the received address <Ad02> to the column address buffer 0 (CR0). Based on the address <Ad02>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 2 (MR2).

[0332] When the row address RA at address <Ad02> is stored in the row address buffer 2 (RR2), the row address buffer 2 (RR2) sends the row address RA to the row decoder 52C.

[0333] When receiving the instruction <30h> from the instruction buffer 2 (MR2), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 2 (PL2). The sequencer 30 sets the signal CB02 to the busy state. The signal CB02 is stored in the status buffer 21. When the normal read in plane 2 (PL2) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB02 to the ready state. Plane 2 (PL2) of chip 0 (CP0) can accept the next instruction.

[0334] Next, the memory controller 300 performs a normal read of plane 3 (PL3) of chip 0 (CP0).

[0335] More specifically, after issuing the instruction <00h>, address <Ad02>, and instruction <30h>, the memory controller 300 issues the instruction <00h>, address <Ad03>, and instruction <30h> to perform a normal read of plane 3 (PL3) of chip 0 (CP0).

[0336] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, address <Ad03>, and instruction <30h> issued by the memory controller 300. Based on the address <Ad03>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 3 (MR3). The input / output circuit 10 sends the row address RA of the received address <Ad03> to the row address buffer 3 (RR3), and sends the column address CA of the received address <Ad03> to the column address buffer 1 (CR1). Based on the address <Ad03>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 3 (MR3).

[0337] When the row address RA at address <Ad03> is stored in the row address buffer 3 (RR3), the row address buffer 3 (RR3) sends the row address RA to the row decoder 52D.

[0338] When receiving the instruction <30h> from the instruction buffer 3 (MR3), the sequencer 30 of chip 0 (CP0) starts a normal read in plane 3 (PL3). The sequencer 30 sets the signal CB03 to the busy state. The signal CB03 is stored in the status buffer 21. When the normal read in plane 3 (PL3) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB03 to the ready state. Plane 3 (PL3) of chip 0 (CP0) can accept the next instruction.

[0339] Next, as Figure 20 shown, the memory controller 300 reads the state of plane 0 (PL0) of chip 0 (CP0). After issuing instruction <00h>, address <Ad03>, and instruction <30h>, the details of this state read performed by issuing instruction <78h> and address <Ad00> are the same as those in the first embodiment.

[0340] Next, when receiving the signal CB00 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 0 (PL0) of chip 0 (CP0).

[0341] More specifically, the memory controller 300 issues instruction <00h>, address <Ad00>, and instruction <31h> to perform a cache read of plane 0 (PL0) of chip 0 (CP0).

[0342] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad00>, and instruction <31h> issued by the memory controller 300. Then, similar to the normal read of plane 0 (PL0) of chip 0 (CP0), the cache read of plane 0 (PL0) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets the signal CB00 to the busy state.

[0343] Next, the memory controller 300 reserves the prefetch of the read data of the normal read performed on plane 0 (PL0) of chip 0 (CP0).

[0344] More specifically, instruction <00h>, address <Ad00>, and instruction <31h> are issued. During the period of performing the cache read (i.e., the period when the signal CB00 is in the busy state), the memory controller 300 issues instruction <05h>, address <Ad00>, and instruction <E0h> to reserve the prefetch of plane 0 (PL0) of chip 0 (CP0).

[0345] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad00>, and instruction <E0h> issued by the memory controller 300. Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 0 (MR0), and copies the instruction <05h> to the instruction buffer 0' (MR0'). The input / output circuit 10 sends the row address RA of the received address <Ad00> to the row address buffer 0 (RR0), and copies the row address RA of the address <Ad00> to the row address buffer 0' (RR0'). The input / output circuit 10 sends the column address CA of the received address <Ad00> to the column address buffer 0 (CR0), and copies the column address CA of the address <Ad00> to the column address buffer 0' (CR0'). Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 0 (MR0), and copies the instruction <E0h> to the instruction buffer 0' (MR0').

[0346] When the row address RA of the address <Ad00> is copied to the row address buffer 0' (RR0'), the row address buffer 0' (RR0') sends the row address RA to the row decoder 52A.

[0347] When receiving the instruction <E0h> from the instruction buffer 0' (MR0'), the sequencer 30 of chip 0 (CP0) reserves prefetch in plane 0 (PL0). Then, the sequencer 30 starts prefetching. When receiving the instruction <E0h> while the signal CB00 is in the busy state, the sequencer 30 performs prefetching of plane 0 (PL0) of chip 0 (CP0) during the period when the signal CB00 is in the busy state. More specifically, when receiving the instruction <E0h> while the signal CB00 is in the busy state, the sequencer 30 continues the cache transfer and performs prefetching.

[0348] When starting prefetching, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0' to 0. The column address buffer 0' (CR0') sends the initial column address CA to the last column address CA to the column decoders 55A and 55C. In the column decoder 55A, based on the result of decoding the column address CA of the address <Ad00>, the corresponding latch circuit in the data buffer 54A is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12A. When prefetching is completed, the sequencer 30 sets the signal CB00 to the ready state.

[0349] Next, as Figure 20As shown, the memory controller 300 performs a status read of plane 1 (PL1) of chip 0 (CP0). After issuing instruction <05h>, address <Ad00>, and instruction <E0h>, the details of this status read performed by issuing instruction <78h> and address <Ad01> are the same as those of the first embodiment.

[0350] Next, when receiving the signal CB01 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 0 (CP0).

[0351] More specifically, the memory controller 300 issues instruction <00h>, address <Ad01>, and instruction <31h> to perform a cache read of plane 1 (PL1) of chip 0 (CP0).

[0352] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad01>, and instruction <31h> issued by the memory controller 300. Then, similar to the normal read of plane 1 (PL1) of chip 0 (CP0), a cache read of plane 1 (PL1) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets the signal CB01 to the busy state.

[0353] Next, the memory controller 300 reserves the prefetch of the read data of the normal read performed on plane 1 (PL1) of chip 0 (CP0).

[0354] More specifically, instruction <00h>, address <Ad01>, and instruction <31h> are issued. During the period of performing the cache read (i.e., the period when the signal CB01 is in the busy state), the memory controller 300 issues instruction <05h>, address <Ad01>, and instruction <E0h> to reserve the prefetch of plane 1 (PL1) of chip 0 (CP0).

[0355] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad01>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad01>, the input / output circuit 10 sends the received instruction <05h> to instruction buffer 1 (MR1), and copies instruction <05h> to instruction buffer 1' (MR1'). The input / output circuit 10 sends the row address RA of the received address <Ad01> to row address buffer 1 (RR1), and copies the row address RA of address <Ad01> to row address buffer 1' (RR1'). The input / output circuit 10 sends the column address CA of the received address <Ad01> to column address buffer 1 (CR1), and copies the column address CA of address <Ad01> to column address buffer 1' (CR1'). Based on address <Ad01>, the input / output circuit 10 sends the received instruction <E0h> to instruction buffer 1 (MR1), and copies instruction <E0h> to instruction buffer 1' (MR1').

[0356] When the row address RA of address <Ad01> is copied to row address buffer 1' (RR1'), row address buffer 1' (RR1') sends row address RA to row decoder 52B.

[0357] When receiving instruction <E0h> from instruction buffer 1' (MR1'), sequencer 30 of chip 0 (CP0) reserves prefetch in plane 1 (PL1). Then, sequencer 30 starts prefetching. When receiving instruction <E0h> while signal CB01 is in the busy state, sequencer 30 performs prefetching of plane 1 (PL1) of chip 0 (CP0) during the period when signal CB00 is in the busy state. More specifically, when receiving instruction <E0h> while signal CB01 is in the busy state, sequencer 30 continues cache transfer and performs prefetching.

[0358] When starting prefetching, sequencer 30 of chip 0 (CP0) resets the counter value CNT of column address counter circuit CC1' to 0. Column address buffer 1' (CR1') sends the initial column address CA to the last column address CA to column decoders 55B and 55D. In column decoder 55B, based on the result of decoding the column address CA of address <Ad01>, the corresponding latch circuit in data buffer 54B is selected. The data of the sequentially selected latch circuits is sent to FIFO circuit 12B. When prefetching is completed, sequencer 30 sets signal CB01 to the ready state.

[0359] Next, as Figure 20As shown, the memory controller 300 performs a status read of plane 2 (PL2) of chip 0 (CP0). After issuing instruction <05h>, address <Ad01>, and instruction <E0h>, the details of this status read performed by issuing instruction <78h> and address <Ad02> are the same as those of the first embodiment.

[0360] Next, when receiving the signal CB02 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 2 (PL2) of chip 0 (CP0).

[0361] More specifically, the memory controller 300 issues instruction <00h>, address <Ad02>, and instruction <31h> to perform a cache read of plane 2 (PL2) of chip 0 (CP0).

[0362] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad02>, and instruction <31h> issued by the memory controller 300. Then, similar to the normal read of plane 2 (PL2) of chip 0 (CP0), a cache read of plane 2 (PL2) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets the signal CB02 to the busy state. When the cache transfer in plane 2 (PL2) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB02 to the ready state.

[0363] Next, as Figure 21 shown, the memory controller 300 performs a status read of plane 3 (PL3) of chip 0 (CP0). After issuing instruction <00h>, address <Ad02>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad03> are the same as those of the first embodiment.

[0364] Next, when receiving the signal CB03 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 0 (CP0).

[0365] More specifically, the memory controller 300 issues instruction <00h>, address <Ad03>, and instruction <31h> to perform a cache read of plane 3 (PL3) of chip 0 (CP0).

[0366] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad03>, and instruction <31h> issued by the memory controller 300. Then, in the same manner as the normal read of plane 3 (PL3) of chip 0 (CP0), cache read of plane 3 (PL3) of chip 0 (CP0) is started. The sequencer 30 of chip 0 (CP0) sets the signal CB03 to the busy state. When the cache transfer ends in plane 3 (PL3) of chip 0 (CP0), the sequencer 30 sets the signal CB03 to the ready state.

[0367] Next, as Figure 21 shown, the memory controller 300 performs a status read of plane 0 (PL0) of chip 0 (CP0). After issuing instruction <00h>, address <Ad03>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad00> are the same as those in the first embodiment.

[0368] Next, when the memory controller 300 receives the signal CB00 indicating the ready state from the status buffer 21, the memory controller 300 performs data output of plane 0 (PL0) of chip 0 (CP0). After the memory controller 300 receives the signal CB00 indicating the ready state from the status buffer 21, the details of the data output (performing the data output of the prefetched plane 0 (PL0)) performed by issuing instruction <XXh> are the same as those in the first embodiment.

[0369] Next, the memory controller 300 reserves the prefetch of the readout data of the normal read to be performed in plane 2 (PL2) of chip 0 (CP0).

[0370] More specifically, when the data output ends in plane 0 (PL0) of chip 0 (CP0), the memory controller 300 issues instruction <05h>, address <Ad02>, and instruction <E0h> to reserve the prefetch of plane 2 (PL2) of chip 0 (CP0).

[0371] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad02>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad02>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 2 (MR2), and copies the instruction <05h> to the instruction buffer 2' (MR2'). The input / output circuit 10 sends the row address RA of the received address <Ad02> to the row address buffer 2 (RR2), and copies the row address RA of address <Ad02> to the row address buffer 2' (RR2'). The input / output circuit 10 sends the column address CA of the received address <Ad02> to the column address buffer 0 (CR0), and copies the column address CA of address <Ad02> to the column address buffer 0' (CR0'). Based on address <Ad02>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 2 (MR2), and copies the instruction <E0h> to the instruction buffer 2' (MR2').

[0372] When the row address RA of address <Ad02> is copied to the row address buffer 2' (RR2'), the row address buffer 2' (RR2') sends the row address RA to the row decoder 52C.

[0373] When receiving instruction <E0h> from the instruction buffer 2' (MR2'), the sequencer 30 of chip 0 (CP0) reserves prefetch in plane 2 (PL2). Then, the sequencer 30 starts prefetching. When receiving instruction <E0h> while the signal CB02 is in the ready state, the sequencer 30 immediately performs prefetching of plane 2 (PL2) of chip 0 (CP0).

[0374] When starting prefetching, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0' to 0. The column address buffer 0' (CR0') sends the initial column address CA to the last column address CA to the column decoders 55A and 55C. In the column decoder 55C, based on the result of decoding the column address CA of address <Ad02>, the corresponding latch circuit in the data buffer 54C is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12A.

[0375] Next, the memory controller 300 performs a cache read of plane 0 (PL0) of chip 0 (CP0). After issuing instruction <05h>, address <Ad02>, and instruction <E0h>, the details of this cache read performed by issuing instruction <00h>, address <Ad00>, and instruction <31h> are the same as the aforementioned cache read of plane 0 (PL0) of chip 0 (CP0). When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB00 to the busy state. When the cache transfer ends in plane 0 (PL0) of chip 0 (CP0), sequencer 30 sets signal CB00 to the ready state.

[0376] Next, as Figure 22 shown, the memory controller 300 performs a status read of plane 1 (PL1) of chip 0 (CP0). After issuing instruction <00h>, address <Ad00>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad01> are the same as those of the first embodiment.

[0377] Next, when the memory controller 300 receives signal CB01 indicating the ready state from status buffer 21, it performs data output for plane 1 (PL1) of chip 0 (CP0). After the memory controller 300 receives signal CB01 indicating the ready state from status buffer 21, the details of this data output (performing the data output of prefetched plane 1 (PL1)) performed by issuing instruction <XXh> are the same as those of the first embodiment.

[0378] Next, the memory controller 300 reserves the prefetch of the readout data of the normal read to be performed on plane 3 (PL3) of chip 0 (CP0).

[0379] More specifically, when the data output ends in plane 1 (PL1) of chip 0 (CP0), the memory controller 300 issues instruction <05h>, address <Ad03>, and instruction <E0h> to reserve the prefetch for plane 3 (PL3) of chip 0 (CP0).

[0380] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad03>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad03>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 3 (MR3), and copies the instruction <05h> to the instruction buffer 3' (MR3'). The input / output circuit 10 sends the row address RA of the received address <Ad03> to the row address buffer 3 (RR3), and copies the row address RA of the address <Ad03> to the row address buffer 3' (RR3'). The input / output circuit 10 sends the column address CA of the received address <Ad03> to the column address buffer 1 (CR1), and copies the column address CA of the address <Ad03> to the column address buffer 1' (CR1'). Based on address <Ad03>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 3 (MR3), and copies the instruction <E0h> to the instruction buffer 3' (MR3').

[0381] When the row address RA of address <Ad03> is copied to the row address buffer 3' (RR3'), the row address buffer 3' (RR3') sends the row address RA to the row decoder 52D.

[0382] When receiving instruction <E0h> from the instruction buffer 3' (MR3'), the sequencer 30 of chip 0 (CP0) reserves prefetch in plane 3 (PL3). Then, the sequencer 30 starts prefetch. When receiving instruction <E0h> while the signal CB03 is in the ready state, the sequencer 30 immediately executes the prefetch of plane 3 (PL3) of chip 0 (CP0).

[0383] When starting prefetch, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC1' to 0. The column address buffer 1' (CR1') sends the initial column address CA to the last column address CA to the column decoders 55B and 55D. In the column decoder 55D, based on the result of decoding the column address CA of address <Ad03>, the corresponding latch circuit in the data buffer 54D is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12B.

[0384] Next, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 0 (CP0). After issuing instruction <05h>, address <Ad03>, and instruction <E0h>, the details of this cache read performed by issuing instruction <00h>, address <Ad01>, and instruction <31h> are the same as the aforementioned cache read of plane 1 (PL1) of chip 0 (CP0). When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB01 to the busy state. When the cache transfer in plane 1 (PL1) of chip 0 (CP0) ends, sequencer 30 sets signal CB01 to the ready state.

[0385] Next, as Figure 22 shown, the memory controller 300 performs a status read of plane 2 (PL2) of chip 0 (CP0). After issuing instruction <00h>, address <Ad01>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad02> are the same as those of the first embodiment.

[0386] Next, when the memory controller 300 receives signal CB02 indicating the ready state from status buffer 21, it performs a data output of plane 2 (PL2) of chip 0 (CP0). After the memory controller 300 receives signal CB02 indicating the ready state from status buffer 21, the details of this data output (performing the data output of prefetched plane 2 (PL2)) performed by issuing instruction <XXh> are the same as those of the first embodiment.

[0387] Next, as Figure 23 shown, the memory controller 300 reserves the prefetch of the readout data of the cache read to be performed in plane 0 (PL0) of chip 0 (CP0).

[0388] More specifically, when the data output in plane 2 (PL2) of chip 0 (CP0) ends, the memory controller 300 issues instruction <05h>, address <Ad00>, and instruction <E0h> to reserve the prefetch of plane 0 (PL0) of chip 0 (CP0).

[0389] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad00>, and instruction <E0h> issued by the memory controller 300. Then, in the same way as the prefetch reservation and execution in plane 0 (PL0) of chip 0 (CP0), the prefetch of plane 0 (PL0) of chip 0 (CP0) is reserved and prefetch is started. When instruction <E0h> is received while signal CB00 is in the busy state, the sequencer 30 of chip 0 (CP0) performs the prefetch of plane 0 (PL0) of chip 0 (CP0) during the period when signal CB00 is in the busy state.

[0390] Next, the memory controller 300 performs a cache read of plane 2 (PL2) of chip 0 (CP0). After issuing instruction <05h>, address <Ad00>, and instruction <E0h>, the details of this cache read performed by issuing instruction <00h>, address <Ad02>, and instruction <31h> are the same as the cache read in plane 2 (PL2) of chip 0 (CP0). When starting this cache read, the sequencer 30 of chip 0 (CP0) sets signal CB02 to the busy state. When the cache transfer ends in plane 2 (PL2) of chip 0 (CP0), the sequencer 30 sets signal CB02 to the ready state.

[0391] Next, as Figure 23 shown, the memory controller 300 performs a status read of plane 3 (PL3) of chip 0 (CP0). After issuing instruction <00h>, address <Ad02>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad03> are the same as those in the first embodiment.

[0392] Next, when the memory controller 300 receives signal CB03 indicating the ready state from the status buffer 21, it performs data output of plane 3 (PL3) of chip 0 (CP0). After the memory controller 300 receives signal CB03 indicating the ready state from the status buffer 21, the details of this data output (performing the data output of the prefetch-completed plane 3 (PL3)) performed by issuing instruction <XXh> are the same as those in the first embodiment.

[0393] Next, the memory controller 300 reserves the prefetch of the readout data of the cache read to be performed in plane 1 (PL1) of chip 0 (CP0).

[0394] More specifically, when the data output ends in plane 3 (PL3) of chip 0 (CP0), the memory controller 300 issues instruction <05h>, address <Ad01>, and instruction <E0h> to reserve the prefetch of plane 1 (PL1) of chip 0 (CP0).

[0395] In chip 0 (CP0), the input / output circuit 10 receives the instruction <05h>, the address <Ad01>, and the instruction <E0h> issued by the memory controller 300. Then, similar to the prefetch reservation and execution in plane 1 (PL1) of chip 0 (CP0), it reserves the prefetch of plane 1 (PL1) of chip 0 (CP0) and starts the prefetch. When the instruction <E0h> is received while the signal CB01 is in the busy state, the sequencer 30 of chip 0 (CP0) performs the prefetch of plane 1 (PL1) of chip 0 (CP0) during the period when the signal CB01 is in the busy state.

[0396] Next, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 0 (CP0). After issuing the instruction <05h>, the address <Ad00>, and the instruction <E0h>, the details of this cache read performed by issuing the instruction <01h>, the address <Ad03>, and the instruction <31h> are the same as the cache read in plane 3 (PL3) of chip 0 (CP0) described above. When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB03 to the busy state. When the cache transfer ends in plane 3 (PL3) of chip 0 (CP0), the sequencer 30 sets the signal CB03 to the ready state.

[0397] After that, the instruction sequence during periods C to F is repeated until all the data to be read out in planes 0 to 3 (PL0 to PL3) of chip 0 (CP0) is output as data.

[0398] 2.4 Effects

[0399] According to the configuration of the present embodiment, similar to the first embodiment, since prefetch can be reserved during the read operation, the period until data output starts can be shortened compared to the case where prefetch is reserved after the read operation ends. Therefore, the operation of the memory system can be speeded up.

[0400] 3. Third Embodiment

[0401] The memory system 100 of the third embodiment will be described. In the memory system 100 of the present embodiment, a bus switch BSW is provided in the NAND chip 0 (CP0) of the memory system 100 of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0402] 3.1 Configuration of the Input / Output Circuit 10

[0403] Regarding the configuration of the input / output circuit 10, use Figure 24 for the description. Figure 24FIG. 0 is a block diagram showing the configuration of the NAND chip 0 (CP0) included in the memory system 100 of the present embodiment with an eye to the input / output circuit 10 and the buffer 20. Further, in Figure 24 the status buffer 21 and the voltage generation circuit 40 are omitted.

[0404] The NAND chip 0 (CP0) includes a bus switch BSW. The bus switch BSW is connected to the FIFO circuit 12. The bus switch BSW can be connected to the data buffers 54A to 54D. The bus switch BSW is configured to selectively connect to any one of the data buffers 54A to 54D.

[0405] 3.2 Outline of data flow

[0406] Regarding the outline of the data flow of the read operation of the memory system 100 of the present embodiment, use Figure 25 is used for explanation. Hereinafter, a case where n-bit data DAT is read from the memory cell arrays 51A to 51D to the data buffers 54A to 54D, respectively, will be taken as an example for explanation. Further, in Figure 25 the period in which the instruction CMD and the address ADD issued by the memory controller 300 are transmitted from the memory controller 300 to the DQ pad 11 is omitted.

[0407] First, n-bit data DAT (hereinafter described as bits 1 to n. Figure 25 The 1 to n of

[0408] correspond to bits 1 to n) is stored in the data buffer 54A in plane 0 (PL0). Bits 1 to n sequentially correspond to the upward count of the counter value CNT of the column address counter circuit CC0 starting from bit 1.

[0409] In this state, the bus switch BSW is connected to the data buffer 54A. Then, prefetching is started in plane 0 (PL0). Bits 1 to n are sequentially transferred from the data buffer 54A to the FIFO circuit 12 starting from bit 1.

[0410] The data of bits 1 to n transferred to the FIFO circuit 12 is output through the DQ pad 11 in the order of transfer. Figure 25

[0411] When the transfer of data from the data buffer 54A to the FIFO circuit 12 is completed, the bus switch BSW switches the connection from the data buffer 54A to the data buffer 54B. Then, prefetching is started in plane 1 (PL1). The n-bit data DAT (hereinafter described as bits n + 1 to 2n. Figure 25 The n + 1 to 2n of

[0411] correspond to bits n + 1 to 2n) stored in the data buffer 54B is sequentially transferred from bit n + 1 to the FIFO circuit 12.The data of bits n+1 to bit 2n transmitted to the FIFO circuit 12 is output as data through the DQ pad 11 in the transmitted sequence.

[0412] When the transmission of data from the data buffer 54B to the FIFO circuit 12 ends, the bus switch BSW switches the connection from the data buffer 54B to the data buffer 54C. Then, prefetching starts in plane 2 (PL2). The n-bit data DAT stored in the data buffer 54C (hereinafter described as bits 2n+1 to bit 3n. Figure 25 The 2n+1 to 3n corresponding to bits 2n+1 to bit 3n) are sequentially transmitted from bit 2n+1 from the data buffer 54C to the FIFO circuit 12.

[0413] The data of bits 2n+1 to bit 3n transmitted to the FIFO circuit 12 is output as data through the DQ pad 11 in the transmitted sequence.

[0414] When the transmission of data from the data buffer 54C to the FIFO circuit 12 ends, the bus switch BSW switches the connection from the data buffer 54C to the data buffer 54D. Then, prefetching starts in plane 3 (PL3). The n-bit data DAT stored in the data buffer 54D (hereinafter described as bits 3n+1 to bit 4n. Figure 25 The 3n+1 to 4n corresponding to bits 3n+1 to bit 4n) are sequentially transmitted from bit 3n+1 from the data buffer 54D to the FIFO circuit 12.

[0415] The data of bits 3n+1 to bit 4n transmitted to the FIFO circuit 12 is output as data through the DQ pad 11 in the transmitted sequence.

[0416] In addition, the configuration from the bus switch BSW to the FIFO circuit 12 can be constituted by a waveguide line and the FIFO circuit 12.

[0417] 3.3 Operations

[0418] Regarding the operation of the memory system 100 of the present embodiment, use Figures 26 - 29 will be described. Figures 26 - 29 is a diagram showing an example of an instruction sequence of the read operation of the memory system 100 of the present embodiment. Hereinafter, an example will be described in which the signals CEn1 and CEn2 are the same signal (CEn1 = CEn2 = CEn), and in chip 0 (CP0), data is repeatedly read in the sequence of planes 0 to 3 (PL0 to PL3). In Figures 26 - 29 the signals CB00 to signal CB03 of each plane of chip 0 (CP0) are also shown. The same applies to the case of reading data from chip 1 (CP1).

[0419] The read operation of this embodiment is multi-plane reading. In addition, in this specification, "multi-plane reading" means an operation of simultaneously reading data DAT from each plane in the target chip.

[0420] First, as Figure 26 shown, the memory controller 300 performs a normal read of plane 0 (PL0) of chip 0 (CP0).

[0421] More specifically, after setting the signal CEn to the "L" level, the memory controller 300 issues instruction <00h>, address <Ad00>, and instruction <32h> to perform a normal read of plane 0 (PL0) of chip 0 (CP0). Instruction "32h" is an instruction for performing a normal read in multi-plane reading.

[0422] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad00>, and instruction <32h> issued by the memory controller 300. Based on address <Ad00>, the input / output circuit 10 sends the received instruction <00h> to instruction buffer 0 (MR0). The input / output circuit 10 sends the row address RA of the received address <Ad00> to row address buffer 0 (RR0), and sends the column address CA of the received address <Ad00> to column address buffer 0 (CR0). Based on address <Ad00>, the input / output circuit 10 sends the received instruction <32h> to instruction buffer 0 (MR0).

[0423] When the row address RA of address <Ad00> is stored in row address buffer 0 (RR0), row address buffer 0 (RR0) sends the row address RA to row decoder 52A.

[0424] Next, the memory controller 300 performs a normal read of plane 1 (PL1) of chip 0 (CP0).

[0425] More specifically, after issuing instruction <00h>, address <Ad00>, and instruction <32h>, the memory controller 300 issues instruction <00h>, address <Ad01>, and instruction <32h> to perform a normal read of plane 1 (PL1) of chip 0 (CP0).

[0426] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad01>, and instruction <32h> issued by the memory controller 300. Based on address <Ad01>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 1 (MR1). The input / output circuit 10 sends the row address RA of the received address <Ad01> to the row address buffer 1 (RR1), and sends the column address CA of the received address <Ad01> to the column address buffer 0 (CR0). Based on address <Ad01>, the input / output circuit 10 sends the received instruction <32h> to the instruction buffer 1 (MR1).

[0427] When the row address RA of address <Ad01> is stored in the row address buffer 1 (RR1), the row address buffer 1 (RR1) sends the row address RA to the row decoder 52B.

[0428] Next, the memory controller 300 performs a normal read of plane 2 (PL2) of chip 0 (CP0).

[0429] More specifically, after issuing instruction <00h>, address <Ad01>, and instruction <32h>, the memory controller 300 issues instruction <00h>, address <Ad02>, and instruction <32h> to perform a normal read of plane 2 (PL2) of chip 0 (CP0).

[0430] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad02>, and instruction <32h> issued by the memory controller 300. Based on address <Ad02>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 2 (MR2). The input / output circuit 10 sends the row address RA of the received address <Ad02> to the row address buffer 2 (RR2), and sends the column address CA of the received address <Ad02> to the column address buffer 0 (CR0). Based on address <Ad02>, the input / output circuit 10 sends the received instruction <32h> to the instruction buffer 2 (MR2).

[0431] When the row address RA of address <Ad02> is stored in the row address buffer 2 (RR2), the row address buffer 2 (RR2) sends the row address RA to the row decoder 52C.

[0432] Next, the memory controller 300 performs a normal read of plane 3 (PL3) of chip 0 (CP0).

[0433] More specifically, after issuing instruction <00h>, address <Ad02>, and instruction <32h>, the memory controller 300 issues instruction <00h>, address <Ad03>, and instruction <30h> to perform a normal read of plane 3 (PL3) of chip 0 (CP0).

[0434] In chip 0 (CP0), the input / output circuit 10 receives instruction <00h>, address <Ad03>, and instruction <30h> issued by the memory controller 300. Based on address <Ad03>, the input / output circuit 10 sends the received instruction <00h> to the instruction buffer 3 (MR3). The input / output circuit 10 sends the row address RA of the received address <Ad03> to the row address buffer 3 (RR3), and sends the column address CA of the received address <Ad03> to the column address buffer 0 (CR0). Based on address <Ad03>, the input / output circuit 10 sends the received instruction <30h> to the instruction buffer 3 (MR3).

[0435] When the row address RA of address <Ad03> is stored in the row address buffer 3 (RR3), the row address buffer 3 (RR3) sends the row address RA to the row decoder 52D.

[0436] When receiving instruction <30h> from the instruction buffer 3 (MR3), the sequencer 30 of chip 0 (CP0) starts a normal read in planes 0 to 3 (PL0 to PL3). The sequencer 30 sets signals CB00 to CB03 to the busy state. Signals CB00 to CB03 are stored in the status buffer 21. When the normal read in planes 0 to 3 (PL0 to PL3) of chip 0 (CP0) ends, the sequencer 30 sets signals CB00 to CB03 to the ready state.

[0437] Next, as Figure 27 shown, the memory controller 300 performs a status read of plane 0 (PL0) of chip 0 (CP0).

[0438] More specifically, the memory controller 300 issues instruction <78h> and address <Ad00> to perform a status read of plane 0 (PL0) of chip 0 (CP0).

[0439] The sequencer 30 of chip 0 (CP0) sends the status information STS of signals CB00 to CB03 corresponding to addresses <Ad00> to <Ad03> to the memory controller 300.

[0440] Next, when receiving signals CB00 to CB03 indicating the ready state from the status buffer 21, the memory controller 300 performs a normal read of plane 0 (PL0) of chip 0 (CP0).

[0441] More specifically, in order to perform a normal read of plane 0 (PL0) of chip 0 (CP0), the memory controller 300 issues an instruction <00h>, an address <Ad00>, and an instruction <32h>.

[0442] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad00>, and the instruction <32h> issued by the memory controller 300. Then, in the same manner as the normal read of plane 0 (PL0) of chip 0 (CP0), the instruction <00h> and the instruction <32h> are sent to the instruction buffer 0 (MR0), and the row address RA of the address <Ad00> is sent to the row decoder 52A via the row address buffer 0 (RR0).

[0443] Next, the memory controller 300 performs a normal read of plane 1 (PL1) of chip 0 (CP0).

[0444] More specifically, after issuing the instruction <00h>, the address <Ad00>, and the instruction <32h>, in order to perform a normal read of plane 1 (PL1) of chip 0 (CP0), the memory controller 300 issues an instruction <00h>, an address <Ad01>, and an instruction <32h>.

[0445] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad01>, and the instruction <32h> issued by the memory controller 300. Then, in the same manner as the normal read of plane 1 (PL1) of chip 0 (CP0), the instruction <00h> and the instruction <32h> are sent to the instruction buffer 1 (MR1), and the row address RA of the address <Ad01> is sent to the row decoder 52B via the row address buffer 1 (RR1).

[0446] Next, the memory controller 300 performs a normal read of plane 2 (PL2) of chip 0 (CP0).

[0447] More specifically, after issuing the instruction <00h>, the address <Ad01>, and the instruction <32h>, in order to perform a normal read of plane 2 (PL2) of chip 0 (CP0), the memory controller 300 issues an instruction <00h>, an address <Ad02>, and an instruction <32h>.

[0448] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad02>, and the instruction <32h> issued by the memory controller 300. Then, in the same manner as the normal read of plane 2 (PL2) of chip 0 (CP0), the instruction <00h> and the instruction <32h> are sent to the instruction buffer 2 (MR2), and the row address RA of address <Ad02> is sent to the row decoder 52C through the row address buffer 2 (RR2).

[0449] Next, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 0 (CP0).

[0450] More specifically, after issuing the instruction <00h>, the address <Ad02>, and the instruction <32h>, the memory controller 300 issues the instruction <00h>, the address <Ad03>, and the instruction <31h> in order to perform a cache read of plane 3 (PL3) of chip 0 (CP0).

[0451] In chip 0 (CP0), the input / output circuit 10 receives the instruction <00h>, the address <Ad03>, and the instruction <31h>. Then, in the same manner as the normal read of plane 3 (PL3) of chip 0 (CP0), the instruction <00h> and the instruction <31h> are sent to the instruction buffer 3 (MR3), and the row address RA of address <Ad03> is sent to the row decoder 52D through the row address buffer 3 (RR3).

[0452] When receiving the instruction <31h> from the instruction buffer 3 (MR3), the sequencer 30 of chip 0 (CP0) starts a normal read in planes 0 to 2 (PL0 to PL2) and starts a cache read in plane 3 (PL3) of chip 0 (CP0). The sequencer 30 sets the signals CB00 to CB03 to the busy state.

[0453] Next, as Figure 28 shown, the memory controller 300 reserves the prefetch of the read data of the normal read to be executed in plane 0 (PL0) of chip 0 (CP0).

[0454] More specifically, by issuing the instruction <00h>, the address <Ad03>, and the instruction <31h>, during the period of performing the cache read (i.e., the period when the signal CB00 is in the busy state), the memory controller 300 issues the instruction <05h>, the address <Ad00>, and the instruction <E0h> in order to reserve the prefetch of plane 0 (PL0) of chip 0 (CP0).

[0455] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad00>, and instruction <E0h> issued by the memory controller 300. Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 0 (MR0), and copies the instruction <05h> to the instruction buffer 0' (MR0'). The input / output circuit 10 sends the row address RA of the received address <Ad00> to the row address buffer 0 (RR0), and copies the row address RA of the address <Ad00> to the row address buffer 0' (RR0'). The input / output circuit 10 sends the column address CA of the received address <Ad00> to the column address buffer 0 (CR0), and copies the column address CA of the address <Ad00> to the column address buffer 0' (CR0'). Based on the address <Ad00>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 0 (MR0), and copies the instruction <E0h> to the instruction buffer 0' (MR0').

[0456] When the row address RA of the address <Ad00> is copied to the row address buffer 0' (RR0'), the row address buffer 0' (RR0') sends the row address RA to the row decoder 52A.

[0457] When receiving the instruction <E0h> from the instruction buffer 0' (MR0'), the sequencer 30 of chip 0 (CP0) connects the bus switch BSW to the data buffer 54A and reserves prefetch in plane 0 (PL0). Then, the sequencer 30 starts prefetch. That is, the transfer of data from the data buffer 54A to the FIFO circuit 12 starts. When receiving the instruction <E0h> while the signal CB00 is in the busy state, the sequencer 30 performs prefetch of plane 0 (PL0) of chip 0 (CP0) during the period when the signal CB00 is in the busy state. More specifically, when receiving the instruction <E0h> while the signal CB00 is in the busy state, the sequencer 30 continues the cache transfer and performs prefetch.

[0458] When starting prefetch, the sequencer 30 of chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0' to 0. The column address buffer 0' (CR0') sends the initial column address CA to the last column address CA to the column decoders 55A - 55D. In the column decoder 55A, based on the result of decoding the column address CA of the address <Ad00>, the corresponding latch circuit in the data buffer 54A is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12.

[0459] Next, as Figure 28As shown, the memory controller 300 performs a status read of the plane 0 (PL0) of the chip 0 (CP0). The details of this status read performed by issuing the instruction <78h> and the address <Ad00> after issuing the instruction <05h>, the address <Ad00>, and the instruction <E0h> are the same as the above-mentioned status read of the plane 0 (PL0) of the chip 0 (CP0).

[0460] Next, upon receiving the signals CB00 to CB03 indicating the ready state from the status buffer 21 , the memory controller 300 performs data output of the plane 0 ( PL0 ) of the chip 0 ( CP0 ).

[0461] More specifically, the memory controller 300 issues a command <YYh> to execute data output of plane 0 (PL0) of chip 0 (CP0). The command "YYh" is a command for selecting a chip and a plurality of planes in the chip and executing data output.

[0462] In chip 0 (CP0), the input / output circuit 10 receives the instruction <YYh> issued by the memory controller 300. The input / output circuit 10 sends the received instruction <YYh> to the instruction buffer 0 (MR0).

[0463] Upon receiving instruction <YYh> from instruction buffer 0 (MR0), sequencer 30 of chip 0 (CP0) starts to execute the data output of plane 0 (PL0) that has been pre-fetched.

[0464] When the data transfer from the data buffer 54A to the FIFO circuit 12 is completed in the plane 0 (PL0) of the chip 0 (CP0), as shown in FIG. Figure 24 , Figure 25 and Figure 28 As shown, the sequencer 30 of chip 0 (CP0) connects the bus switch BSW to the data buffer 54B. When the sequencer 30 switches the bus switch BSW to the data buffer 54B in the middle of the data output of plane 0 (PL0) of chip 0 (CP0), prefetching starts in plane 1 (PL1) of chip 0 (CP0). That is, the data is transferred from the data buffer 54B to the FIFO circuit 12.

[0465] Next, the memory controller 300 performs data output of the plane 1 ( PL1 ) of the chip 0 ( CP0 ).

[0466] More specifically, when data output in plane 0 (PL0) of chip 0 (CP0) is finished, the sequencer 30 of chip 0 (CP0) starts to execute data output of plane 1 (PL1) which has been pre-fetched.

[0467] When the transfer of data from the data buffer 54B to the FIFO circuit 12 ends in plane 1 (PL1) of chip 0 (CP0), as Figure 24 , Figure 25 and Figure 29 shown, the sequencer 30 of chip 0 (CP0) connects the bus switch BSW to the data buffer 54C. When the sequencer 30 switches the bus switch BSW to the connection with the data buffer 54C during the data output in plane 1 (PL1) of chip 0 (CP0), prefetching starts in plane 2 (PL2) of chip 0 (CP0). That is, the transfer of data from the data buffer 54C to the FIFO circuit 12 starts.

[0468] Next, the memory controller 300 executes the data output of plane 2 (PL2) of chip 0 (CP0).

[0469] More specifically, when the data output in plane 1 (PL1) of chip 0 (CP0) ends, the sequencer 30 of chip 0 (CP0) starts the data output of plane 2 (PL2) for which prefetching has been completed.

[0470] When the transfer of data from the data buffer 54C to the FIFO circuit 12 ends in plane 2 (PL2) of chip 0 (CP0), as Figure 24 , Figure 25 and Figure 29 shown, the sequencer 30 of chip 0 (CP0) connects the bus switch BSW to the data buffer 54D. When the sequencer 30 switches the bus switch BSW to the connection with the data buffer 54D during the data output in plane 2 (PL2) of chip 0 (CP0), prefetching starts in plane 3 (PL3) of chip 0 (CP0). That is, the transfer of data from the data buffer 54D to the FIFO circuit 12 starts.

[0471] Thus, in this embodiment, prefetching of plane p + 1 can be executed during the data output of plane p (p is an integer from 0 to 2) of chip 0 (CP0).

[0472] Next, the memory controller 300 executes the data output of plane 3 (PL3) of chip 0 (CP0).

[0473] More specifically, when the data output in plane 2 (PL2) of chip 0 (CP0) ends, the sequencer 30 of chip 0 (CP0) starts the data output of plane 3 (PL3) for which prefetching has been completed.

[0474] When the data output in plane 3 (PL3) of chip 0 (CP0) ends, the instruction sequence during periods B to E is repeated until all the data to be read within planes 0 to 3 (PL0 to PL3) of chip 0 (CP0) is output.

[0475] 3.4 Effects

[0476] According to the configuration of this embodiment, as in the first embodiment, since prefetching can be reserved during the read operation, the period until the start of data output can be shortened compared to the case where prefetching is reserved after the read operation ends. In addition, during the data output period of plane p in the chip, prefetching of plane p + 1 can be executed. Therefore, the period until the start of data output of plane p + 1 can be shortened by the period during which the data output of plane p overlaps with the prefetching of plane p + 1. Therefore, the operation of the memory system can be made faster.

[0477] 4. Fourth Embodiment

[0478] The memory system 100 of the fourth embodiment will be described. The memory system 100 of this embodiment has one row address buffer provided in the address buffer 22 in the memory system 100 of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0479] 4.1 Configuration of Buffer 20

[0480] Regarding the configuration of buffer 20, Figure 30 will be used for the description. Figure 30 is a block diagram showing the configuration of the NAND chip 0 (CP0) included in the memory system 100 of this embodiment centered around the input / output circuit 10 and the buffer 20. In addition, in Figure 30 the status buffer 21 and the voltage generation circuit 40 are omitted.

[0481] As Figure 30 shows, the address buffer 22 has the same configuration as the address buffer 22 described in the first embodiment Figure 6 with the column address buffer 0' (CR0') removed.

[0482] 4.2 Operation

[0483] Regarding the operation of the memory system 100 of this embodiment, Figures 31 - 35 will be used for the description. Figures 31 - 35This is a diagram showing an example of an instruction sequence for the read operation of the memory system 100 according to the present embodiment. Hereinafter, an example will be described in which signals CEn1 and CEn2 are the same signal (CEn1 = CEn2 = CEn), and in chip 0 (CP0), data is read repeatedly in the order of planes 0 to 3 (PL0 to PL3). In Figures 31 - 35 signals CB00 to CB03 of each plane of chip 0 (CP0) are also shown. The same applies to the case of reading data from chip 1 (CP1). The read operation of the present embodiment is single-plane reading.

[0484] First, the memory controller 300 performs a normal read in chip 0 (CP0) in the order of planes 0 to 3 (PL0 to PL3). The instruction sequence and signals CB00 to CB03 from when the memory controller 300 sets the signal CEn to the "L" level until a normal read is performed in plane 3 (PL3) of chip 0 (CP0) are the same as those in the second embodiment until Figure 19 A. Also, during this period, the input / output circuit 10 sends the column address CA of the received address <Ad01> to the column address buffer 0 (CR0). The input / output circuit 10 sends the column address CA of the received address <Ad03> to the column address buffer 0 (CR0). Other operations during this period are the same as those in the second embodiment.

[0485] Next, as Figure 31 shown, the memory controller 300 performs a status read of plane 0 (PL0) of chip 0 (CP0). After issuing the instruction <00h>, the address <Ad03>, and the instruction <30h>, the details of this status read performed by issuing the instruction <78h> and the address <Ad00> are the same as those in the first embodiment.

[0486] Next, when the memory controller 300 receives the signal CB00 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 0 (PL0) of chip 0 (CP0). After the memory controller 300 receives the signal CB00 indicating the ready state from the status buffer 21, the details of this cache read performed by issuing the instruction <00h>, the address <Ad00>, and the instruction <31h> are the same as those in the first embodiment. When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB00 to the busy state. When the cache transfer ends in plane 0 (PL0) of chip 0 (CP0), the sequencer 30 sets the signal CB00 to the ready state.

[0487] Next, the memory controller 300 performs a status read of plane 1 (PL1) of chip 0 (CP0). After issuing instruction <00h>, address <Ad00>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad01> are the same as those in the first embodiment.

[0488] Next, when the memory controller 300 receives a signal CB01 indicating a ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 0 (CP0). After the memory controller 300 receives the signal CB01 indicating a ready state from the status buffer 21, the details of this cache read performed by issuing instruction <00h>, address <Ad01>, and instruction <31h> are the same as those in the first embodiment. When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB01 to the busy state. When the cache transfer ends in plane 1 (PL1) of chip 0 (CP0), the sequencer 30 sets the signal CB01 to the ready state.

[0489] Next, the memory controller 300 performs a status read of plane 2 (PL2) of chip 0 (CP0). After issuing instruction <00h>, address <Ad01>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad02> are the same as those in the first embodiment.

[0490] Next, when the memory controller 300 receives a signal CB02 indicating a ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 2 (PL2) of chip 0 (CP0). After the memory controller 300 receives the signal CB02 indicating a ready state from the status buffer 21, the details of this cache read performed by issuing instruction <00h>, address <Ad02>, and instruction <31h> are the same as those in the first embodiment. When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB02 to the busy state. When the cache transfer ends in plane 2 (PL2) of chip 0 (CP0), the sequencer 30 sets the signal CB02 to the ready state.

[0491] Next, the memory controller 300 performs a status read of plane 3 (PL3) of chip 0 (CP0). After issuing instruction <00h>, address <Ad02>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad03> are the same as those in the first embodiment.

[0492] Next, when receiving the signal CB03 indicating the ready state from the status buffer 21, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 0 (CP0). After the memory controller 300 receives the signal CB03 indicating the ready state from the status buffer 21, the details of this cache read performed by issuing instruction <00h>, address <Ad03>, and instruction <31h> are the same as those of the first embodiment. When starting this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB03 to the busy state. When the cache transfer ends in plane 3 (PL3) of chip 0 (CP0), the sequencer 30 sets the signal CB03 to the ready state.

[0493] Next, as Figure 32 shown, the memory controller 300 performs a status read of plane 0 (PL0) of chip 0 (CP0). After issuing instruction <00h>, address <Ad03>, and instruction <31h>, the details of this status read performed by issuing instruction <78h> and address <Ad00> are the same as those of the first embodiment.

[0494] Next, when receiving the signal CB00 indicating the ready state from the status buffer 21, the memory controller 300 performs a prefetch of plane 0 (PL0) of chip 0 (CP0).

[0495] More specifically, the memory controller 300 issues instruction <05h>, address <Ad00>, and instruction <E0h> to perform a prefetch of plane 0 (PL0) of chip 0 (CP0).

[0496] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad00>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad00>, the input / output circuit 10 sends the received instruction <05h> to the instruction buffer 0 (MR0). The input / output circuit 10 sends the row address RA of the received address <Ad00> to the row address buffer 0 (RR0). The input / output circuit 10 sends the column address CA of the received address <Ad00> to the column address buffer 0 (CR0). Based on address <Ad00>, the input / output circuit 10 sends the received instruction <E0h> to the instruction buffer 0 (MR0).

[0497] When the row address RA of address <Ad00> is stored in the row address buffer 0 (RR0), the row address buffer 0 (RR0) sends the row address RA to the row decoder 52A.

[0498] When receiving the instruction <E0h> from the instruction buffer 0 (MR0), the sequencer 30 of chip 0 (CP0) starts prefetching in plane 0 (PL0). When receiving the instruction <E0h> while the signal CB00 is in the ready state, the sequencer 30 immediately performs the prefetch of plane 0 (PL0) of chip 0 (CP0). More specifically, the sequencer 30 resets the counter value CNT of the column address counter circuit CC0 to 0. The column address buffer 0 (CR0) sends the initial column address CA to the final column address CA to the column decoders 55A - 55D. In the column decoder 55A, based on the result of decoding the column address CA of the address <Ad00>, the corresponding latch circuit in the data buffer 54A is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12.

[0499] Next, the memory controller 300 performs the data output of plane 0 (PL0) of chip 0 (CP0).

[0500] More specifically, when the prefetch in plane 0 (PL0) of chip 0 (CP0) ends, the sequencer 30 of chip 0 (CP0) starts the data output of plane 0 (PL0) after the prefetch is completed.

[0501] Next, as Figure 33 shown, the memory controller 300 performs the status reading of plane 1 (PL1) of chip 0 (CP0). After the data output of plane 0 (PL0) of chip 0 (CP0) ends, the details of this status reading performed by issuing the instruction <78h> and the address <Ad01> are the same as those in the first embodiment.

[0502] Next, when receiving the signal CB01 indicating the ready state from the status buffer 21, the memory controller 300 performs the prefetch of plane 1 (PL1) of chip 0 (CP0).

[0503] More specifically, the memory controller 300 issues the instruction <05h>, the address <Ad01>, and the instruction <E0h> in order to perform the prefetch of plane 1 (PL1) of chip 0 (CP0).

[0504] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad01>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad01>, the input / output circuit 10 sends the received instruction <05h> to instruction buffer 1 (MR1). The input / output circuit 10 sends the row address RA of the received address <Ad01> to row address buffer 1 (RR1). The input / output circuit 10 sends the column address CA of the received address <Ad01> to column address buffer 0 (CR0). Based on address <Ad01>, the input / output circuit 10 sends the received instruction <E0h> to instruction buffer 1 (MR1).

[0505] When the row address RA of address <Ad01> is stored in row address buffer 1 (RR1), row address buffer 1 (RR1) sends the row address RA to row decoder 52B.

[0506] When receiving instruction <E0h> from instruction buffer 1 (MR1), sequencer 30 of chip 0 (CP0) starts prefetching in plane 1 (PL1). When receiving instruction <E0h> when signal CB01 is in the ready state, sequencer 30 immediately performs prefetching of plane 1 (PL1) of chip 0 (CP0). More specifically, sequencer 30 resets the counter value CNT of column address counter circuit CC0 to 0. Column address buffer 0 (CR0) sends the initial column address CA to the last column address CA to column decoders 55A - 55D. In column decoder 55B, based on the result of decoding the column address CA of address <Ad01>, the corresponding latch circuit in data buffer 54B is selected. The data of the sequentially selected latch circuits is sent to FIFO circuit 12.

[0507] Next, memory controller 300 performs cache read of plane 0 (PL0) of chip 0 (CP0). The details of this cache read, which is performed by issuing instruction <00h>, address <Ad00>, and instruction <31h> after issuing instruction <05h>, address <Ad01>, and instruction <E0h>, are the same as those in the first embodiment. When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB00 to the busy state. When cache transfer in plane 0 (PL0) of chip 0 (CP0) ends, sequencer 30 sets signal CB00 to the ready state.

[0508] Next, memory controller 300 performs data output of plane 1 (PL1) of chip 0 (CP0).

[0509] More specifically, an instruction <00h>, an address <Ad00>, and an instruction <31h> are issued. When the prefetch in plane 1 (PL1) of chip 0 (CP0) ends, sequencer 30 of chip 0 (CP0) starts to execute the data output of the prefetched plane 1 (PL1).

[0510] Next, as Figure 34 shown, memory controller 300 reads the status of plane 2 (PL2) of chip 0 (CP0). After the data output of plane 1 (PL1) of chip 0 (CP0) ends, the details of this status read executed by issuing an instruction <78h> and an address <Ad02> are the same as those in the first embodiment.

[0511] Next, when receiving a signal CB02 indicating a ready state from status buffer 21, memory controller 300 performs a prefetch of plane 2 (PL2) of chip 0 (CP0).

[0512] More specifically, memory controller 300 issues an instruction <05h>, an address <Ad02>, and an instruction <E0h> to perform a prefetch of plane 2 (PL2) of chip 0 (CP0).

[0513] In chip 0 (CP0), input / output circuit 10 receives the instruction <05h>, the address <Ad02>, and the instruction <E0h> issued by memory controller 300. Based on the address <Ad02>, input / output circuit 10 sends the received instruction <05h> to instruction buffer 2 (MR2). Input / output circuit 10 sends the row address RA of the received address <Ad02> to row address buffer 2 (RR2). Input / output circuit 10 sends the column address CA of the received address <Ad02> to column address buffer 0 (CR0). Based on the address <Ad02>, input / output circuit 10 sends the received instruction <E0h> to instruction buffer 2 (MR2).

[0514] When the row address RA of address <Ad02> is stored in row address buffer 2 (RR2), row address buffer 2 (RR2) sends the row address RA to row decoder 52C.

[0515] When receiving the instruction <E0h> from the instruction buffer 2 (MR2), the sequencer 30 of chip 0 (CP0) starts prefetching in plane 2 (PL2). When receiving the instruction <E0h> while the signal CB02 is in the ready state, the sequencer 30 immediately performs the prefetch of plane 2 (PL2) of chip 0 (CP0). More specifically, at the start of prefetching, the sequencer 30 resets the counter value CNT of the column address counter circuit CC0 to 0. The column address buffer 0 (CR0) sends the initial column address CA to the final column address CA to the column decoders 55A to 55D. In the column decoder 55C, based on the result of decoding the column address CA of the address <Ad02>, the corresponding latch circuit in the data buffer 54C is selected. The data of the sequentially selected latch circuits is sent to the FIFO circuit 12.

[0516] Next, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 0 (CP0). After issuing the instructions <05h>, address <Ad02>, and instruction <E0h>, the details of this cache read performed by issuing the instructions <00h>, address <Ad01>, and instruction <31h> are the same as those in the first embodiment. At the start of this cache read, the sequencer 30 of chip 0 (CP0) sets the signal CB01 to the busy state. When the cache transfer ends in plane 1 (PL1) of chip 0 (CP0), the sequencer 30 sets the signal CB01 to the ready state.

[0517] Next, the memory controller 300 performs a data output of plane 2 (PL2) of chip 0 (CP0).

[0518] More specifically, by issuing the instructions <00h>, address <Ad01>, and instruction <31h>, when the prefetch ends in plane 2 (PL2) of chip 0 (CP0), the sequencer 30 of chip 0 (CP0) starts the data output of plane 2 (PL2) that has completed the prefetch.

[0519] Next, as Figure 35 shown, the memory controller 300 performs a status read of plane 3 (PL3) of chip 0 (CP0). After the data output of plane 2 (PL2) of chip 0 (CP0) ends, the details of this status read performed by issuing the instruction <78h> and address <Ad03> are the same as those in the first embodiment.

[0520] Next, when receiving the signal CB03 indicating the ready state from the status buffer 21, the memory controller 300 performs a prefetch of plane 3 (PL3) of chip 0 (CP0).

[0521] More specifically, the memory controller 300 issues instruction <05h>, address <Ad03>, and instruction <E0h> to perform prefetching for plane 3 (PL3) of chip 0 (CP0).

[0522] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad03>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad03>, the input / output circuit 10 sends the received instruction <05h> to instruction buffer 3 (MR3). The input / output circuit 10 sends the row address RA of the received address <Ad03> to row address buffer 3 (RR3). The input / output circuit 10 sends the column address CA of the received address <Ad03> to column address buffer 0 (CR0). Based on address <Ad03>, the input / output circuit 10 sends the received instruction <E0h> to instruction buffer 3 (MR3).

[0523] When the row address RA of address <Ad03> is stored in row address buffer 3 (RR3), row address buffer 3 (RR3) sends the row address RA to row decoder 52D.

[0524] When receiving instruction <E0h> from instruction buffer 3 (MR3), sequencer 30 of chip 0 (CP0) starts prefetching in plane 3 (PL3). When receiving instruction <E0h> while signal CB03 is in the ready state, sequencer 30 immediately performs prefetching for plane 3 (PL3) of chip 0 (CP0). More specifically, at the start of prefetching, sequencer 30 resets the counter value CNT of column address counter circuit CC0 to 0. Column address buffer 0 (CR0) sends the initial column address CA to the final column address CA to column decoders 55A - 55D. In column decoder 55D, based on the result of decoding the column address CA of address <Ad03>, the corresponding latch circuit in data buffer 54D is selected. The data of the sequentially selected latch circuits is sent to FIFO circuit 12.

[0525] Next, the memory controller 300 performs cache read for plane 2 (PL2) of chip 0 (CP0). The details of this cache read performed by issuing instruction <00h>, address <Ad02>, and instruction <31h> after issuing instruction <05h>, address <Ad03>, and instruction <E0h> are the same as those in the first embodiment. At the start of this cache read, sequencer 30 of chip 0 (CP0) sets signal CB02 to the busy state. When cache transfer ends in plane 2 (PL2) of chip 0 (CP0), sequencer 30 sets signal CB02 to the ready state.

[0526] Thus, in the present embodiment, during the period when the memory controller 300 sends the instruction <00h>, the address <Ad0q>, and the instruction <31h> of plane q (q is an integer from 0 to 2) of chip 0 (CP0), prefetching of plane q + 1 can be executed.

[0527] Next, the memory controller 300 performs data output of plane 3 (PL3) of chip 0 (CP0).

[0528] More specifically, the instruction <00h>, the address <Ad02>, and the instruction <31h> are issued. When the prefetching in plane 3 (PL3) of chip 0 (CP0) ends, the sequencer 30 of chip 0 (CP0) starts to perform data output of the prefetch-completed plane 3 (PL3).

[0529] Next, the memory controller 300 performs cache reading of plane 3 (PL3) of chip 0 (CP0). After the data output of plane 3 (PL3) of chip 0 (CP0) ends, the details of this cache reading performed by issuing the instruction <00h>, the address <Ad03>, and the instruction <31h> are the same as those in the first embodiment. When starting this cache reading, the sequencer 30 of chip 0 (CP0) sets the signal CB03 to the busy state. When the cache transfer in plane 3 (PL3) of chip 0 (CP0) ends, the sequencer 30 sets the signal CB03 to the ready state.

[0530] Thereafter, the instruction sequence of the period from C to G is repeated until all the data to be read out within planes 0 to 3 (PL0 to PL3) of chip 0 (CP0) are output.

[0531] 4.3 Effects

[0532] According to the configuration of the present embodiment, after the memory controller 300 issues the instruction "05h" of plane q + 1 within the chip, before starting the data output of plane q + 1, it can issue the instruction "31h" of plane q. That is, during the period when the memory controller 300 sends the instruction <00h>, the address <Ad0q>, and the instruction <31h> of plane q of chip 0 (CP0), prefetching of plane q + 1 can be executed. Therefore, the period until the start of the data output of plane q + 1 can be shortened by the period of sending the instruction <00h>, the address <Ad0q>, and the instruction <31h> of plane q overlapping with the prefetching of plane q + 1. Thus, the operation of the memory system can be speeded up.

[0533] 5. The Fifth Embodiment

[0534] The memory system 100 of the fifth embodiment will be described. The memory system 100 of this embodiment reads data by single-plane reading in the memory system 100 of the third embodiment. Hereinafter, the description will focus on the differences from the third embodiment.

[0535] 5.1 Operation

[0536] For the operation of the memory system 100 of this embodiment, Figures 36 - 38 is used for the description. Figures 36 - 38 is a diagram showing an example of an instruction sequence of the read operation of the memory system 100 of this embodiment. Hereinafter, an example will be described in which the signals CEn1 and CEn2 are the same signal (CEn1 = CEn2 = CEn), and in chip 0 (CP0), data is read repeatedly in the order of planes 0 to 3 (PL0 to PL3). In Figures 36 - 38 the signals CB00 to CB03 of each plane of the NAND chip 0 (CP0) are also shown. The same applies to the case of reading data from chip 1 (CP1). The read operation of this embodiment is single-plane reading.

[0537] First, the memory controller 300 performs normal reading in chip 0 (CP0) in the order of planes 0 to 3 (PL0 to PL3). The instruction sequence and the signals CB00 to CB03 from when the memory controller 300 sets the signal CEn to the "L" level until normal reading is performed in plane 3 (PL3) of chip 0 (CP0) are the same as those in the second embodiment until Figure 19 A. In addition, the operation during this period is the same as that of the fourth embodiment.

[0538] Next, the memory controller 300 performs status reading and cache reading in chip 0 (CP0) in the order of planes 0 to 3 (PL0 to PL3). The instruction sequence and the signals CB00 to CB03 from when normal reading is performed in plane 3 (PL3) of chip 0 (CP0) until cache reading is performed in plane 3 (PL3) of chip 0 (CP0) are the same as those in the fourth embodiment until Figure 31 A to B. In addition, the operation during this period is the same as that of the fourth embodiment.

[0539] Next, the memory controller 300 reserves prefetching of the read data of the normal reading to be performed in plane 0 (PL0) of chip 0 (CP0).

[0540] More specifically, as shown in Figure 36As shown, the memory controller 300 issues instruction <05h>, address <Ad00>, and instruction <E0h> to reserve prefetch for plane 0 (PL0) of chip 0 (CP0). Additionally, similar to the third embodiment, the memory controller 300 can issue instruction <00h>, address <Ad03>, and instruction <31h>, and issue instruction <05h>, address <Ad00>, and instruction <E0h> during the period of cache read (i.e., the period when signal CB00 is in the busy state).

[0541] In chip 0 (CP0), the input / output circuit 10 receives instruction <05h>, address <Ad00>, and instruction <E0h> issued by the memory controller 300. Based on address <Ad00>, the input / output circuit 10 sends the received instruction <05h> to instruction buffer 0 (MR0), and copies instruction <05h> to instruction buffer 0' (MR0'). The input / output circuit 10 sends the row address RA of the received address <Ad00> to row address buffer 0 (RR0), and copies the row address RA of address <Ad00> to row address buffer 0' (RR0'). The input / output circuit 10 sends the column address CA of the received address <Ad00> to column address buffer 0 (CR0), and copies the column address CA of address <Ad00> to column address buffer 0' (CR0'). Based on address <Ad00>, the input / output circuit 10 sends the received instruction <E0h> to instruction buffer 0 (MR0), and copies instruction <E0h> to instruction buffer 0' (MR0').

[0542] When the row address RA of address <Ad00> is copied to row address buffer 0' (RR0'), row address buffer 0' (RR0') sends row address RA to row decoder 52A.

[0543] When receiving instruction <E0h> from instruction buffer 0' (MR0'), sequencer 30 of chip 0 (CP0) connects bus switch BSW to data buffer 54A to reserve prefetch in plane 0 (PL0). Then, sequencer 30 starts prefetch. That is, it starts the transfer of data from data buffer 54A to FIFO circuit 12. When receiving instruction <E0h> when signal CB00 is in the ready state, sequencer 30 immediately performs prefetch for plane 0 (PL0) of chip 0 (CP0). Additionally, similar to the third embodiment, when receiving instruction <E0h> when signal CB00 is in the busy state, sequencer 30 performs prefetch for plane 0 (PL0) of chip 0 (CP0) during the period when signal CB00 is in the busy state. More specifically, when sequencer 30 receives instruction <E0h> when signal CB00 is in the busy state, it continues the cache transfer and performs prefetch.

[0544] When prefetching starts, the sequencer 30 of the chip 0 (CP0) resets the counter value CNT of the column address counter circuit CC0' to 0. The column address buffer 0' (CR0') sends the first column address CA to the last column address CA to the column decoders 55A to 55D. In the column decoder 55A, based on the result of decoding the column address CA of the address <Ad00>, the corresponding latch circuit in the data buffer 54A is selected. The data of the latch circuits selected in sequence are sent to the FIFO circuit 12.

[0545] Next, the memory controller 300 executes the state read of plane 0 (PL0) of chip 0 (CP0). The details of this state read executed by issuing command <05h>, address <Ad00>, and command <E0h> and then issuing command <78h> and address <Ad00> are the same as those of the first embodiment.

[0546] Next, upon receiving the signal CB00 indicating the ready state from the status buffer 21 , the memory controller 300 performs data output of the plane 0 ( PL0 ) of the chip 0 ( CP0 ).

[0547] More specifically, the memory controller 300 issues a command <YYh> in order to execute data output of the plane 0 ( PL0 ) of the chip 0 ( CP0 ).

[0548] In chip 0 (CP0), the input / output circuit 10 receives the instruction <YYh> issued by the memory controller 300. The input / output circuit 10 sends the received instruction <YYh> to the instruction buffer 0 (MR0).

[0549] Upon receiving instruction <YYh> from instruction buffer 0 (MR0), sequencer 30 of chip 0 (CP0) starts to execute the data output of plane 0 (PL0) that has been pre-fetched.

[0550] When the data transfer from the data buffer 54A to the FIFO circuit 12 is completed in the plane 0 (PL0) of the chip 0 (CP0), as shown in FIG. Figure 24 , Figure 25 and Figure 36 As shown, the sequencer 30 of chip 0 (CP0) connects the bus switch BSW to the data buffer 54B. When the sequencer 30 switches the bus switch BSW to the data buffer 54B in the middle of the data output of plane 0 (PL0) of chip 0 (CP0), prefetching starts in plane 1 (PL1) of chip 0 (CP0). That is, the data is transferred from the data buffer 54B to the FIFO circuit 12.

[0551] Next, the memory controller 300 performs a cache read of plane 0 (PL0) of chip 0 (CP0). After the data output of plane 0 (PL0) of chip 0 (CP0) ends, the details of this cache read performed by issuing instruction <00h>, address <Ad00>, and instruction <31h> are the same as those in the first embodiment. When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB00 to the busy state. When the cache transfer ends in plane 0 (PL0) of chip 0 (CP0), sequencer 30 sets signal CB00 to the ready state.

[0552] Next, as Figure 37 shown, the memory controller 300 performs the data output of plane 1 (PL1) of chip 0 (CP0).

[0553] More specifically, after issuing instruction <00h>, address <Ad00>, and instruction <31h>, the memory controller 300 issues instruction <YYh> to perform the data output of plane 1 (PL1) of chip 0 (CP0).

[0554] In chip 0 (CP0), input / output circuit 10 receives instruction <YYh> issued by the memory controller 300. Input / output circuit 10 sends the received instruction <YYh> to instruction buffer 1 (MR1).

[0555] When receiving instruction <YYh> from instruction buffer 1 (MR1), sequencer 30 of chip 0 (CP0) starts to execute the pre-fetched data output of plane 1 (PL1).

[0556] When the transfer of data from data buffer 54B to FIFO circuit 12 ends in plane 1 (PL1) of chip 0 (CP0), as Figure 24 , Figure 25 and Figure 37 shown, sequencer 30 of chip 0 (CP0) connects bus switch BSW to data buffer 54C. When sequencer 30 switches bus switch BSW to the connection with data buffer 54C during the data output of plane 1 (PL1) of chip 0 (CP0), pre-fetching starts in plane 2 (PL2) of chip 0 (CP0). That is, the transfer of data from data buffer 54C to FIFO circuit 12 starts.

[0557] Next, the memory controller 300 performs a cache read of plane 1 (PL1) of chip 0 (CP0). After the data output of plane 1 (PL1) of chip 0 (CP0) ends, the details of this cache read performed by issuing instruction <00h>, address <Ad01>, and instruction <31h> are the same as those in the first embodiment. When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB01 to the busy state. When the cache transfer ends in plane 1 (PL1) of chip 0 (CP0), sequencer 30 sets signal CB01 to the ready state.

[0558] Next, as Figure 37 shown, the memory controller 300 performs data output of plane 2 (PL2) of chip 0 (CP0).

[0559] More specifically, after issuing instruction <00h>, address <Ad01>, and instruction <31h>, the memory controller 300 issues instruction <YYh> to perform data output of plane 2 (PL2) of chip 0 (CP0).

[0560] In chip 0 (CP0), input / output circuit 10 receives instruction <YYh> issued by the memory controller 300. Input / output circuit 10 sends the received instruction <YYh> to instruction buffer 2 (MR2).

[0561] When receiving instruction <YYh> from instruction buffer 2 (MR2), sequencer 30 of chip 0 (CP0) starts to execute the pre-fetched data output of plane 2 (PL2).

[0562] For plane 2 (PL2) of chip 0 (CP0), when the transfer of data from data buffer 54C to FIFO circuit 12 ends, as Figure 24 , Figure 25 and Figure 37 shown, sequencer 30 of chip 0 (CP0) connects bus switch BSW to data buffer 54D. Sequencer 30 switches bus switch BSW to the connection with data buffer 54D in the middle of the data output of plane 2 (PL2) of chip 0 (CP0), and starts pre-fetching in plane 3 (PL3) of chip 0 (CP0). That is, it starts the transfer of data from data buffer 54D to FIFO circuit 12.

[0563] Next, the memory controller 300 performs a cache read of plane 2 (PL2) of chip 0 (CP0). After the data output of plane 2 (PL2) of chip 0 (CP0) ends, the details of this cache read performed by issuing instruction <00h>, address <Ad02>, and instruction <31h> are the same as those in the first embodiment. When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB02 to the busy state. When the cache transfer ends in plane 2 (PL2) of chip 0 (CP0), sequencer 30 sets signal CB02 to the ready state.

[0564] Next, as Figure 38 shown, the memory controller 300 performs the data output of plane 3 (PL3) of chip 0 (CP0).

[0565] More specifically, after issuing instruction <00h>, address <Ad02>, and instruction <31h>, the memory controller 300 issues instruction <YYh> to perform the data output of plane 3 (PL3) of chip 0 (CP0).

[0566] In chip 0 (CP0), input / output circuit 10 receives instruction <YYh> issued by the memory controller 300. Input / output circuit 10 sends the received instruction <YYh> to instruction buffer 3 (MR3).

[0567] When receiving instruction <YYh> from instruction buffer 3 (MR3), sequencer 30 of chip 0 (CP0) starts to execute the data output of the prefetched plane 3 (PL3).

[0568] Next, the memory controller 300 performs a cache read of plane 3 (PL3) of chip 0 (CP0). After the data output of plane 3 (PL3) of chip 0 (CP0) ends, the details of this cache read performed by issuing instruction <00h>, address <Ad03>, and instruction <31h> are the same as those in the first embodiment. When starting this cache read, sequencer 30 of chip 0 (CP0) sets signal CB03 to the busy state. When the cache transfer ends in plane 3 (PL3) of chip 0 (CP0), sequencer 30 sets signal CB03 to the ready state.

[0569] After that, the instruction sequence during periods B to E is repeated until all the data to be read out within planes 0 to 3 (PL0 to PL3) of chip 0 (CP0) is output.

[0570] 5.2 Effects

[0571] According to the configuration of the present embodiment, similar to the first embodiment, since prefetching can be reserved during the read operation, the period until the start of data output can be shortened compared to the case where prefetching is reserved after the read operation ends. In addition, similar to the third embodiment, since prefetching of plane p+1 can be executed during the data output period of plane p in the chip, the period until the start of data output of plane p+1 can be shortened by the period during which the data output of plane p overlaps with the prefetching of plane p+1. Therefore, the operation of the memory system can be made faster.

[0572] 6. Variations and the like

[0573] As described above, the memory system of the embodiment includes: a first chip (CP0) including a first plane (PL0) and a first input / output circuit (10); and a controller (300) capable of issuing an instruction for controlling the first chip. The first plane includes: a first memory cell array (51A) having a plurality of first memory cell transistors (MC); and a first latch circuit capable of storing first read data read from the first memory cell array. The first input / output circuit includes a first FIFO circuit (12(12A)) capable of taking in the first read data from the first latch circuit. The controller can send a first instruction (05h) to the first chip during the period of performing a read operation in the first plane, and the first instruction (05h) commands taking in the first read data from the first latch circuit into the first FIFO circuit.

[0574] In addition, the embodiment is not limited to the form described above, and various changes can be made.

[0575] The FIFO circuit can be a FILO (First In Last Out) circuit.

[0576] In addition, in the above embodiment, a NAND type flash memory is taken as an example of the semiconductor memory device, but it is not limited to the NAND type flash memory, and can be applied to all other semiconductor memories, and further can be applied to various storage devices other than semiconductor memories.

[0577] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the present invention. These embodiments or their variations are included in the scope or gist of the invention, and are also included in the scope of the invention described in the claims and its equivalents.

Claims

1. A memory system, comprising: A first chip, including a first plane and a first input / output circuit; And A controller capable of issuing instructions for controlling the first chip; and The first plane includes: a first memory cell array having a plurality of first memory cell transistors; And a first latch circuit capable of storing first read data read from the first memory cell array; The first input / output circuit includes a first FIFO circuit capable of fetching the first read data from the first latch circuit; During the period when the controller executes a read operation in the first plane, the controller can send a first instruction to the first chip, and the first instruction is a command: following the operation of storing the first read data in the first latch circuit, execute the operation of fetching the first read data from the first latch circuit into the first FIFO circuit.

2. The memory system according to claim 1, wherein the first read data is fetched from the first latch circuit into the first FIFO circuit during the period when the read operation is executed in the first plane.

3. The memory system according to claim 1, wherein based on the sending of the first instruction, it is reserved to execute the operation of fetching the first read data from the first latch circuit into the first FIFO circuit following the operation of storing the first read data in the first latch circuit.

4. A memory system, comprising: A first chip, including a first plane and a first input / output circuit; And A controller capable of issuing instructions for controlling the first chip; and The first plane includes: a first memory cell array having a plurality of first memory cell transistors; And a first latch circuit capable of storing first read data read from the first memory cell array; The first input / output circuit includes a first FIFO circuit capable of fetching the first read data from the first latch circuit; During the period when the controller executes a read operation in the first plane, the controller can send a first instruction to the first chip, and the first instruction commands the fetching of the first read data from the first latch circuit to the first FIFO circuit; The memory system further includes a second chip, and the second chip includes a second plane and a second input / output circuit; and The second plane includes: a second memory cell array having a plurality of second memory cell transistors; And a second latch circuit capable of storing second read data read from the second memory cell array; The second input / output circuit includes a second FIFO circuit capable of fetching the second read data from the second latch circuit; The controller is capable of issuing instructions for controlling the second chip; After sending the first instruction to the first chip, during the period when the controller executes a read operation in the second plane, the controller can send a second instruction to the second chip, and the second instruction commands the fetching of the second read data from the second latch circuit to the second FIFO circuit.

5. The memory system according to claim 4, wherein the second read data is fetched into the second FIFO circuit from the second latch circuit during a read operation performed in the second plane.

6. The memory system according to claim 4, wherein the first chip further includes a third plane; and the third plane includes: a third memory cell array having a plurality of third memory cell transistors; and a third latch circuit capable of storing third read data read from the third memory cell array; the first FIFO circuit is capable of fetching the third read data from the third latch circuit; after sending the second instruction to the second chip, the controller sends a third instruction to the first chip, the third instruction commanding the output of the first read data from the first FIFO circuit to the controller, and after outputting the first read data from the first FIFO circuit to the controller based on the third instruction, the controller sends a fourth instruction to the first chip, the fourth instruction commanding the fetching of the third read data from the third latch circuit to the first FIFO circuit.

7. A memory system, comprising: a first chip including a first plane and a first input / output circuit; and a controller capable of issuing instructions for controlling the first chip; and the first plane includes: a first memory cell array having a plurality of first memory cell transistors; and a first latch circuit capable of storing first read data read from the first memory cell array; the first input / output circuit includes a first FIFO circuit capable of fetching the first read data from the first latch circuit; the controller is capable of sending a first instruction to the first chip during a read operation performed in the first plane, the first instruction commanding the fetching of the first read data from the first latch circuit to the first FIFO circuit; the first chip further includes a second plane; and the second plane includes: a second memory cell array having a plurality of second memory cell transistors; and a second latch circuit capable of storing second read data read from the second memory cell array; the first input / output circuit further includes a second FIFO circuit capable of fetching the second read data from the second latch circuit; the controller can send a second instruction to the first chip during a read operation performed in the second plane, the second instruction commanding the fetching of the second read data from the second latch circuit to the second FIFO circuit.

8. The memory system according to claim 7, wherein the second read data is fetched into the second FIFO circuit from the second latch circuit during a read operation performed in the second plane.

9. The memory system according to claim 7, wherein the first chip further includes a third plane; and The third plane includes: a third memory cell array having a plurality of third memory cell transistors; and a third latch circuit capable of storing third read data read out from the third memory cell array; The first FIFO circuit is capable of fetching the third read data from the third latch circuit; After sending the second instruction to the first chip, the controller sends a third instruction to the first chip. The third instruction commands the output of the first read data from the first FIFO circuit to the controller. After the first read data is output from the first FIFO circuit to the controller based on the third instruction, the controller sends a fourth instruction to the first chip. The fourth instruction commands the fetching of the third read data from the third latch circuit to the first FIFO circuit.

10. A memory system, comprising: A first chip including a first plane and a first input / output circuit; And A controller capable of issuing instructions for controlling the first chip; and The first plane includes: a first memory cell array having a plurality of first memory cell transistors; And a first latch circuit capable of storing first read data read out from the first memory cell array; The first input / output circuit includes a first FIFO circuit capable of fetching the first read data from the first latch circuit; The controller is capable of sending a first instruction to the first chip during a read operation in the first plane. The first instruction commands the fetching of the first read data from the first latch circuit to the first FIFO circuit; The first chip further includes a second plane; and The second plane includes: a second memory cell array having a plurality of second memory cell transistors; and a second latch circuit capable of storing second read data read out from the second memory cell array; The first FIFO circuit is capable of fetching the second read data from the second latch circuit; The controller is: after sending the first instruction to the first chip, sending a second instruction to the first chip. The second instruction commands the output of the first read data from the first FIFO circuit to the controller, and the second read data is fetched into the first FIFO circuit from the second latch circuit during the output of the first read data from the first FIFO circuit to the controller based on the second instruction.

11. The memory system according to claim 10, wherein the memory system further includes a switch that switches the connection between the first FIFO circuit and the first latch circuit, and the connection between the first FIFO circuit and the second latch circuit; and After the first read data is transferred from the first latch circuit to the first FIFO circuit, the switch switches from the connection between the first FIFO circuit and the first latch circuit to the connection between the first FIFO circuit and the second latch circuit.

12. The memory system according to claim 10, wherein the controller can send the first instruction to the first chip during a period when read operations are performed in the first plane and the second plane.

13. A memory system, comprising: A chip, including a first plane, a second plane, and an input / output circuit; And A controller capable of issuing instructions for controlling the chip; And The first plane includes: a first memory cell array having a plurality of first memory cell transistors; and a first latch circuit capable of storing first read data read from the first memory cell array; The second plane includes: a second memory cell array having a plurality of second memory cell transistors; And a second latch circuit capable of storing second read data read from the second memory cell array; The input / output circuit includes a FIFO circuit that can take in the first read data from the first latch circuit and can take in the second read data from the second latch circuit; The controller sends a first instruction to the chip, and the first instruction commands the taking in of the second read data from the second latch circuit to the FIFO circuit; The controller is: after sending the first instruction to the chip and before starting the output of the second read data from the FIFO circuit to the controller, issues a second instruction to the first plane, and the second instruction performs the reading of the first read data from the first memory cell array to the first latch circuit.

Images