Chip testing method

Abstract

This disclosure provides a chip testing method, relating to the field of semiconductor technology. The method includes: performing at least one set of chip tests on the chip under test; in each command timing test, performing the following steps: writing first test write data to a first target row and a second target row; sequentially sending a first activation command and a first automatic precharge read command to the chip under test; after an interval corresponding to the adjustment duration of this command timing test, sequentially sending a second activation command and a first read command to the chip under test to obtain first test read data for the second target row; determining the first read / write test result of the second target row in this command timing test based on the first test read data and the first test write data; and determining the actual tRTP corresponding to each set of chip tests based on the respective first read / write test results of multiple command timing tests in each set of chip tests. According to the embodiments of this disclosure, the automatic precharge behavior of the chip can be accurately detected.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a chip testing method. Background Technology

[0002] In the development of semiconductor technology, in order to improve the efficiency of instruction bus utilization, automatic precharge behavior has been introduced into chips. Specifically, by using automatic precharge behavior in conjunction with read and write commands, the chip will automatically start the charging behavior after a set timing, without the need to send an additional precharge command.

[0003] However, since the automatic pre-charging behavior is performed automatically inside the chip and cannot be shown to the outside, there is a lack of technical solutions that can accurately detect the chip's automatic pre-charging behavior.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a chip testing method that overcomes, to some extent, the technical problem of the inability to accurately detect the automatic pre-charging behavior of chips in related technologies.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a chip testing method is provided, comprising:

[0008] At least one set of chip tests is performed on the chip under test. Each set of chip tests includes multiple command timing tests. Each set of chip tests corresponds to a preset read-to-precharge time tRTP. Each command timing test corresponds to an adjustable duration.

[0009] In each command timing test, the following steps are performed:

[0010] Write the same first test write data into the first target row and the second target row. The first target row and the second target row belong to the same memory bank of the chip under test.

[0011] The first activation command and the first automatic precharge read command are sent sequentially to the chip under test to perform a read operation on the first target row;

[0012] Starting from the first automatic precharge read command and after the adjustment time corresponding to the timing test of this command, the second activation command and the first read command are sent to the chip under test in sequence to obtain the first test read data of the second target row.

[0013] Based on the first test read data and the first test write data, determine the first read and write test results of the second target row in this command timing test;

[0014] Based on the first read / write test results of multiple command timing tests in each chip group test, the actual tRTP corresponding to each chip group test is determined.

[0015] In one embodiment, the duration to be adjusted for each of the multiple command timing tests in each chip test group changes sequentially.

[0016] Based on the first read / write test results of multiple command timing tests in each chip group test, the actual tRTP corresponding to each chip group test is determined, including:

[0017] For each group of chip tests, among the adjustment durations corresponding to the multiple command timing tests of this group of chip tests, the first benchmark adjustment duration that meets the first preset selection condition is determined.

[0018] The first benchmark adjustment duration is determined as the actual tRTP corresponding to the chip group test.

[0019] In one embodiment, the first read / write test result is a first test result identifier indicating read / write failure, or a second test result identifier indicating read / write success;

[0020] Based on the first read / write test results of multiple command timing tests in each chip group test, the actual tRTP corresponding to each chip group test is determined, including:

[0021] Based on the first read / write test results of multiple command timing tests in at least one set of chip tests, a first shmoo test diagram is generated. The first shmoo test diagram includes at least one image sequence, each image sequence corresponds to a set of chip tests, each image sequence includes multiple image units, each image unit corresponds to one command timing test, and each image unit has a visual identifier, which is either a first test result identifier or a second test result identifier.

[0022] Based on the first Shmoo test chart, a first baseline adjustment duration that meets the first preset selection conditions is selected;

[0023] The first benchmark adjustment duration is determined as the actual tRTP corresponding to the chip group test.

[0024] In one embodiment, the first read / write test result is a first test result identifier indicating read / write failure, or a second test result identifier indicating read / write success;

[0025] The first preset selection condition is:

[0026] The maximum value of the adjustable duration for each command timing test corresponding to the first test result identifier; or,

[0027] The minimum value among the adjustment durations corresponding to the command timing tests identified by the second test result.

[0028] In one embodiment, each command timing test further includes the following steps:

[0029] Write the second test write data and the third test write data into the third target row and the fourth target row respectively. The second test write data and the third test write data are different. The third target row and the fourth target row belong to the same memory bank of the chip under test.

[0030] The third activation command and the second automatic precharge read command are sent sequentially to the chip under test to perform a read operation on the third target row;

[0031] Starting from the second automatic precharge read command and after the adjustment time corresponding to the timing test of this command, the fourth activation command and the second read command are sent to the chip under test in sequence to obtain the second test read data of the fourth target row.

[0032] Based on the second test read data and the third test write data, the second read and write test result of the fourth target row in this command timing test is determined. The second read and write test result is either a third test result identifier indicating read and write failure, or a fourth test result identifier indicating read and write success.

[0033] In addition, the method also includes:

[0034] Based on the second read / write test results of multiple command timing tests in each chip test group, the first delay value corresponding to each chip test group is determined. The first delay value represents the critical value of the adjustment time for the second read / write test result to change from the third test result identifier to the fourth test result identifier.

[0035] The tRP of the chip under test is determined by testing the actual tRTP and the first delay value of each of at least one set of chips.

[0036] In one embodiment, determining the precharge effective time tRP of the chip under test based on the actual tRTP and first delay value corresponding to at least one set of chip tests includes:

[0037] Determine the baseline tRTP by testing the actual tRTP corresponding to each of at least one set of chips.

[0038] A baseline delay value is determined by testing the first delay value corresponding to each of at least one set of chips.

[0039] The tRP is determined based on the difference between the reference delay value and the reference tRTP.

[0040] In one embodiment, based on the results of the second read / write tests of multiple command timing tests in each chip test group, a first latency value corresponding to each chip test group is determined, including:

[0041] For each group of chip tests, determine the second benchmark adjustment duration that meets the second preset selection condition from the adjustment durations corresponding to the multiple command timing tests of this group of chip tests.

[0042] The second benchmark adjustment duration is determined as the first latency value corresponding to the chip test of this group.

[0043] In one embodiment, the second preset selection condition includes:

[0044] The maximum value of the duration to be adjusted for each command timing test corresponding to the third test result identifier; or,

[0045] The minimum value among the durations to be adjusted for each command timing test corresponding to the fourth test result identifier.

[0046] In one embodiment, based on the results of the second read / write tests of multiple command timing tests in each chip test group, a first latency value corresponding to each chip test group is determined, including:

[0047] Based on the second read / write test results of multiple command timing tests in at least one set of chip tests, a second shmoo test graph is generated. The second shmoo test graph includes at least one image sequence, each image sequence corresponds to a set of chip tests, each image sequence includes multiple image units, each image unit corresponds to one command timing test, and each image unit has a visual identifier, which is either a third test result identifier or a fourth test result identifier.

[0048] Based on the second Shmoo test chart, select the second baseline adjustment duration that meets the second preset selection conditions;

[0049] The second benchmark adjustment duration is determined as the first latency value corresponding to the chip test of this group.

[0050] In one embodiment, the method further includes:

[0051] Obtain the preset tRTP for each of at least one group of chip tests. The preset tRTP is set by writing the predefined code corresponding to the chip test in the predefined code bit in the mode register. The predefined code is specified by the preset standard protocol.

[0052] If at least one set of chips tests their respective preset tRTP and at least one set of chips tests their respective actual tRTP and both meet the preset consistency conditions, it is determined that the automatic precharge behavior of the chip under test meets the design expectations.

[0053] In one embodiment, before acquiring at least one set of chips for testing their respective preset tRTPs, the method further includes:

[0054] In each chip test group, the predefined code corresponding to the chip test group is written into the predefined encoding bit of the mode register of the chip under test, so as to set the tRTP of the chip under test to the preset tRTP corresponding to the chip test group.

[0055] In one embodiment, the method further includes:

[0056] In the testing of each chip group, the first read and write test results of each command timing test are used to determine whether there are abnormal read and write test results; if there are abnormal read and write test results, it is determined that the automatic pre-charge behavior of the chip under test is abnormal.

[0057] In one embodiment, the method further includes: determining whether there are abnormal read / write test results in the second read / write test results of multiple command timing tests in each group of chip tests; and determining that the automatic pre-charge behavior of the chip under test is abnormal if there are abnormal read / write test results.

[0058] In one embodiment, in the first read / write test results of multiple command timing tests in each chip test group, determining whether there are abnormal read / write test results includes:

[0059] In each group of chip tests, the first read and write test results of each command timing test are used to determine whether there are any first read and write test results that meet the preset abnormal result judgment conditions.

[0060] If there is a first read / write test result that meets the preset abnormal result judgment conditions, the first read / write test result that meets the preset abnormal result judgment conditions will be determined as an abnormal read / write test result.

[0061] The preset abnormal result judgment conditions include:

[0062] The adjustment duration corresponding to the abnormal read / write test result is not continuous with the adjustment duration corresponding to the first test result identifier of other chips in the same group.

[0063] In one embodiment, in the second read / write test results of multiple command timing tests in each chip test group, determining whether there are abnormal read / write test results includes:

[0064] In each group of chip tests, the second read and write test results of each of the multiple command timing tests are used to determine whether there are second read and write test results that meet the preset abnormal result judgment conditions.

[0065] If there is a second read / write test result that meets the preset abnormal result judgment conditions, the second read / write test result that meets the preset abnormal result judgment conditions will be determined as an abnormal read / write test result.

[0066] The preset abnormal result judgment conditions include:

[0067] The adjustment duration corresponding to the abnormal read / write test result is not continuous with the adjustment duration corresponding to the first test result identifier of other chips in the same group.

[0068] In one embodiment, after determining that the automatic precharge behavior of the chip under test is abnormal, the method further includes:

[0069] Generate abnormal alarm information to characterize the abnormal operation of the automatic precharge behavior of the chip under test;

[0070] Reporting abnormal alarm information. According to another aspect of this disclosure, a chip testing apparatus is provided, comprising:

[0071] The chip testing module is used to perform at least one set of chip tests on the chip under test. Each set of chip tests includes multiple command timing tests. Each set of chip tests corresponds to a preset tRTP. Each command timing test corresponds to an adjustable duration.

[0072] In each command timing test, the following steps are performed:

[0073] Write the same first test write data into the first target row and the second target row. The first target row and the second target row belong to the same memory bank of the chip under test.

[0074] The first activation command and the first automatic precharge read command are sent sequentially to the chip under test to perform a read operation on the first target row;

[0075] Starting from the first automatic precharge read command and after the adjustment time corresponding to the timing test of this command, the second activation command and the first read command are sent to the chip under test in sequence to obtain the first test read data of the second target row.

[0076] Based on the first test read data and the first test write data, determine the first read and write test results of the second target row in this command timing test;

[0077] The processing module is used to determine the actual tRTP corresponding to each chip test group based on the first read / write test results of multiple command timing tests in each chip test group.

[0078] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described chip testing method by executing the executable instructions.

[0079] According to another aspect of this disclosure, a computer-readable storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the chip testing method described above.

[0080] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the chip testing method described above.

[0081] The chip testing method provided in this disclosure provides a timing test with a duration to be adjusted for each command timing test. Accordingly, the interval between the first automatic precharge read command and the second activation command can be changed between multiple command timing tests in each chip test group as the duration to be adjusted for each command timing test changes. Furthermore, when the same test data is written to the first target line and the second target line, if the second activation command is earlier than the automatic precharge action time, a first read / write test result indicating a read / write failure will be obtained; similarly, if the second activation command is later than the automatic precharge action time, the read / write will be successful. Therefore, by changing the duration to be adjusted to change the interval between the first automatic precharge read command and the second activation command in each command timing test, the actual tRTP corresponding to each chip test group, i.e., the time interval between the second activation command and the automatic precharge action time, can be determined based on the changes in the first read / write test results of multiple command timing tests in each chip test group. Moreover, since the actual tRTP can accurately reflect the actual position of the automatic precharge behavior in the command timing, this disclosure embodiment can accurately detect the chip's automatic precharge behavior.

[0082] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0083] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0084] Figure 1 A schematic diagram of the read process of a chip under test provided in an embodiment of this disclosure is shown;

[0085] Figure 2 This diagram illustrates the command timing of a read process for a chip under test according to an embodiment of this disclosure.

[0086] Figure 3 A schematic diagram of an exemplary storage unit provided in an embodiment of this disclosure is shown;

[0087] Figure 4 This diagram illustrates the voltage changes of the chip's bit lines during data reading.

[0088] Figure 5 A schematic diagram of an exemplary test scenario provided by an embodiment of this disclosure is shown;

[0089] Figure 6 A system architecture diagram of a chip testing system provided in an embodiment of this disclosure is shown;

[0090] Figure 7 This illustration shows a schematic diagram of the specification content of an exemplary preset standard protocol mode register provided in an embodiment of this disclosure;

[0091] Figure 8 A schematic flowchart of a chip testing method provided in an embodiment of this disclosure is shown;

[0092] Figure 9 A schematic flowchart of a chip testing method provided in an embodiment of this disclosure is shown;

[0093] Figure 10 This illustration shows a schematic diagram of an exemplary first test data write provided by an embodiment of this disclosure;

[0094] Figure 11 An exemplary first shmoo test diagram provided by an embodiment of this disclosure is shown;

[0095] Figure 12 A flowchart illustrating another chip testing method provided in an embodiment of this disclosure is shown;

[0096] Figure 13This illustration shows a schematic diagram of an exemplary second test write data and a third test write data provided in an embodiment of this disclosure;

[0097] Figure 14 An exemplary second shmoo test pattern provided by an embodiment of this disclosure is shown;

[0098] Figure 15 A schematic diagram of a chip testing apparatus provided in an embodiment of this disclosure is shown;

[0099] Figure 16 A structural block diagram of an electronic device provided in an embodiment of this disclosure is shown; and

[0100] Figure 17 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0101] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0102] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0103] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0104] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0105] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0106] Chips such as Dynamic Random Access Memory (DRAM) can include multiple banks, each containing multiple arrayed cells. For example, a basic cell can consist of a transistor and a storage capacitor. The presence or absence of charge on the storage capacitor corresponds to the data "1" and "0". In one example, one terminal of the transistor is connected to the storage capacitor; when the transistor is turned on, the charge stored in the capacitor can be read or charge can be written to the capacitor.

[0107] Next, in order to facilitate understanding of this disclosure, Figure 1 This diagram illustrates a read flow chart of a chip under test according to an embodiment of this disclosure. Figure 2 This diagram illustrates the command timing of a read process for a chip under test according to an embodiment of this disclosure. The following section will combine... Figure 1 and Figure 2 The reading process for the chip under test is explained.

[0108] like Figure 1As shown, during each read / write operation, the controller can send an activation command (ACT) to the chip to open the word line WL of the memory cell to be read in the first target row (i.e., activate the word line). After opening the word line WL, if the capacitance of the memory cell to be read corresponds to the data "1", some charge flows from the storage capacitor to the bit line BL corresponding to the memory cell to be read, causing the voltage of the bit line BL to rise slightly; and if the memory cell to be read corresponds to the data "0", some charge on the bit line BL will flow into the storage capacitor, causing the voltage of the bit line BL to drop slightly. Furthermore, under the action of the sense amplifier (SA), the higher voltage side of the bit line BL and the supplementary bit line / BL becomes increasingly higher, and the lower voltage side becomes increasingly lower, until a stable output voltage is achieved. At this time, the controller sends a read command (RD) to the chip. Furthermore, after the Read to Precharge Time (tRTP), the controller sends a Precharge command (PRE) to the chip to disable the word line WL and restore the bit line BL and the reference bit line / BL to the same potential. Then, after the Row Precharge Time (tRP), the controller can sequentially send activation and read commands to the chip to read memory cells on the second target row (i.e., the new working row).

[0109] With the development of semiconductor technology, in order to improve the efficiency of instruction bus utilization, automatic precharge behavior can be introduced, allowing the chip to automatically complete precharge without the need for precharge commands from the controller. For details, see [link to relevant documentation]. Figure 1 and Figure 2 After the controller sends the first activation command ACT1 to the chip to open the first target row for a certain period of time, the controller can send an automatic precharge read command (Read with Auto-Precharge, RDA) to the chip so that the first target row can be automatically precharged after data reading, so that the chip can automatically precharge after a predetermined time without the need for a precharge command.

[0110] However, since the automatic pre-charging behavior occurs automatically within the chip, it cannot be observed externally. Therefore, accurately detecting the chip's automatic pre-charging behavior has become a pressing issue.

[0111] Based on this, the inventors conducted research on changes to the chip's data reading process. Combined with... Figure 3 and Figure 4 The findings of this study are illustrated by taking the example of writing the data "1" into two memory cells corresponding to the same bit line on the first and second target rows.

[0112] Figure 3 A schematic diagram of an exemplary storage unit provided in an embodiment of this disclosure is shown. Figure 4 This diagram illustrates the voltage changes on the chip's bit lines during data readout. (Combined with...) Figure 3 and Figure 4 It can be seen that in the first target row (corresponding to Figure 3 When reading or writing to the memory cell 31 on the word line WL1, after the controller sends the first activation command ACT1 to the chip, the charge of the storage capacitor of the memory cell 31 flows to the bit line BL, slightly raising the voltage of the bit line BL. After data reading and automatic pre-charging operations on the first target row, the residual charge of the storage capacitor of the memory cell 31 on the bit line BL gradually flows out, causing the voltage of the bit line BL to gradually decrease.

[0113] When in Figure 4 When the position shown triggers the activation command ACT2 for the second target row, since the data stored in the storage unit 32 of the second target row is also 1, the voltage on the bit line BL has not completely dropped to the reference value, and the data "1" can be read correctly at this time.

[0114] In summary, the inventors have discovered that when the same data is written to the first target line and the second target line, the data can be read normally by the interval tRTP between the first automatic precharge read command RDA of the first target line and the second activation command ACT2 of the second target line.

[0115] For example, Figure 5 A schematic diagram of an exemplary test scenario provided by an embodiment of this disclosure is shown. For example... Figure 5 As shown, when the interval between the first automatic precharge read command RDA and the second activation command ACT2 is greater than tRTP, that is, when the second activation command ACT2 is later than the automatic precharge action time, the correct read data 51 can be read.

[0116] Furthermore, when the interval between the first automatic precharge read command RDA and the second activation command ACT2 is less than tRTP, that is, when the second activation command ACT2 is earlier than the automatic precharge action time, the read operation of the second target line cannot be executed correctly, resulting in incorrect read data 52.

[0117] Based on the above findings, this disclosure provides a chip testing method, apparatus, device, and medium that can be applied to testing scenarios involving the automatic pre-charge operation of chips. In this disclosure, by changing the interval between the first automatic pre-charge read command and the second activation command in each command timing test by altering the adjustment duration, the actual tRTP corresponding to each chip test group can be determined based on the changes in the first read / write test results of multiple command timing sequences in each chip test group. Furthermore, since the actual tRTP accurately reflects the actual position of the automatic pre-charge behavior in the command timing sequence, this disclosure can accurately detect the chip's automatic pre-charge behavior.

[0118] The embodiments of this disclosure will now be described in detail. Before describing the technical solutions provided in the embodiments of this disclosure, the technical terms involved in the embodiments of this disclosure will be explained first.

[0119] (1) Activate command (ACT), which is used to activate the storage cell of the row to be read or written. Specifically, most storage cells are in a dormant state when they are not being read or written. When it is necessary to read or write a certain row, the storage cell of that row can be activated first.

[0120] (2) Read command (Read, RD) is used to read data from a row or column address in memory.

[0121] (3) Read with Auto-Precharge (RDA) command: This command is used to control the chip to automatically perform pre-charge behavior after the read operation is completed.

[0122] (4) Row Precharge Time (tRP). After the precharge command is issued, there is a certain period of time before the Row Validation Command (RAS) can be sent to open a new working row. This period of time is tRP.

[0123] (5) Read to Precharge Time (tRTP), which defines the delay time from when the controller issues a read command to the next precharge command.

[0124] (6) Column Address Strobe Latency (CL) defines the time interval between reading data from the column address to the IO interface after the read command is issued.

[0125] (7) Shmoo test plot, which is a plot that can be obtained using the Shmoo plot tool and can be used to analyze and evaluate the actual capabilities of the memory. The Shmoo plot can include multiple image units, each with a visual label that visually indicates whether a read or write operation was successful or failed.

[0126] After introducing the above technical terms, in order to facilitate a full understanding of the embodiments of this disclosure, the chip testing system involved in the embodiments of this disclosure will be described next.

[0127] Figure 6 A system architecture diagram of a chip testing system provided in an embodiment of this disclosure is shown. Figure 6 As shown, the chip testing system 60 may include a chip to be tested 61 and a testing device 62, which will be described in turn below.

[0128] The term "chip under test" can refer to the chip used for command timing parameter testing. For example, the chip under test can be any one of the following dynamic random access memories: fourth-generation double-data-rate synchronous dynamic random access memory (DDR4 SDRAM), fourth-generation low-power double-data-rate synchronous dynamic random access memory (LPDDR4 SDRAM), fifth-generation double-data-rate synchronous dynamic random access memory (DDR5 SDRAM), and fifth-generation low-power double-data-rate synchronous dynamic random access memory (LPDDR5 SDRAM), without specific limitation. It should be noted that the memory can also be other types of memory besides dynamic random access memory, without specific limitation.

[0129] Specifically, the chip under test may include multiple memory banks and at least one mode register (MR). The mode register is configured with various parameters of the chip under test. For example, each mode register may include multiple encoded bits, and each parameter may correspond to one or more encoded bits. Different codes on the encoded bits corresponding to a parameter correspond to different parameter values.

[0130] For example, Figure 7 This illustration shows a schematic diagram of the specification content of an exemplary preset standard protocol mode register provided in an embodiment of this disclosure. For example... Figure 7 As shown, the mode register can include 8 coded bits OP[7:0]. Among them, the default standard protocol specifies that OP[7:4] is used to configure tRTP, and OP[3:0] is used to configure Write Recovery Time.

[0131] And, see also Figure 7The tRTP can be modified by changing the predefined codes on the predefined coding bits OP[7:4]. For example, the predefined codes "0000" on the predefined coding bits OP[7:4] correspond to tRTP equal to 12nCK (clock cycles), "0001" corresponds to 14nCK, ..., and "1000" corresponds to 24nCK.

[0132] The test device 62 can be a device that can send control commands such as activation command, automatic precharge read command, read command, and write command to the chip under test 61.

[0133] Furthermore, the testing device 62 can also have data analysis functions, such as determining the actual tRTP based on the test data. For example, it can also determine the tRP of the chip 61 under test.

[0134] Optionally, the test device 62 may also have a chip verification function, such as verifying whether the chip 61 under test meets the design expectations.

[0135] Optionally, the test device 62 may also have the function of modifying the configuration parameters on the mode register of the chip under test 61.

[0136] After introducing the chip testing system 60, the following detailed description of the exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0137] This disclosure provides a chip testing method, which can be executed by any electronic device with chip testing capabilities, such as... Figure 6 The test apparatus shown is used for execution, and no specific limitations are imposed on it.

[0138] Figure 8 A schematic flowchart of a chip testing method provided in an embodiment of this disclosure is shown, as follows: Figure 8 As shown, the chip testing method provided in this embodiment includes the following steps S810 and S820.

[0139] S810 performs at least one set of chip tests on the chip under test. Each set of chip tests includes multiple command timing tests, each command timing test corresponding to a duration to be adjusted. Furthermore, each set of chip tests corresponds to a preset tRTP, meaning that each command timing test in that set of chip tests corresponds to a preset tRTP.

[0140] In S810, Figure 9 A schematic flowchart of a chip testing method provided in an embodiment of this disclosure is shown. Figure 9 As shown, in each command timing test, the following steps S811 to S814 are executed.

[0141] S811, write the same first test write data to the first target row and the second target row. The first target row and the second target row belong to the same memory bank of the chip under test. For example, the first target row and the second target row can be different rows of the same memory bank.

[0142] The first target row can refer to the row in the memory bank that needs to be read and written. For example, when it is necessary to perform read and write tests on the memory cells on word line WL1, the row corresponding to word line WL1 can be determined as the first target row.

[0143] The second target row can refer to the row in the memory that needs to be read after the first target row has been read.

[0144] The first test write data can be the test data that needs to be written to the target row during read / write tests. For example, writing the same first test write data to the first target row and the second target row can mean writing the same data to the memory cell corresponding to the same bit line in the first target row and the second target row.

[0145] In one example Figure 10 A schematic diagram illustrating an exemplary first test write data provided in an embodiment of this disclosure is shown. Figure 10 As shown, if the first test write data "10101010" is written to the memory cell of the first target row (corresponding to word line WL1), the same data "10101010" can be written to the memory cell of the second target row (corresponding to word line WL2). Furthermore, the write data corresponding to memory cells on the same bit line is the same; for example, all memory cells on bit line BL4 are written with "1".

[0146] In some embodiments, in S811, the data writing of the first target row and the second target row can be completed before the reading operation of the first target row is performed. This disclosure does not impose specific limitations on the time of data writing in S811.

[0147] S812 sequentially sends a first activation command and a first automatic precharge read command to the chip under test to perform a read operation on the first target row.

[0148] The first activation command can be an activation command used to activate the first target line. For example, the first activation command can be used to activate the word line (e.g., word line WL1) corresponding to the first target line. For instance, it could be... Figure 5 The first activation command shown is ACT1.

[0149] The first automatic precharge read command is used to read data from the first target row and to perform an automatic precharge operation after a preset tRTP interval. For example, the first automatic precharge read command can be used to read data from the storage unit to be read in the first target row and to use the read data as the first test read data for the first target row.

[0150] In some embodiments, in S812, a first automatic precharge read command can be sent to the chip under test after a first preset time interval following the sending of the first activation command ACT1. The first preset time interval can be specified by a preset standard protocol and is not specifically limited thereto.

[0151] S813, starting from the first automatic precharge read command and after the adjustment time corresponding to the timing test of this command, sequentially sends the second activation command and the first read command to the chip under test to obtain the first test read data of the second target row.

[0152] The second activation command can be an activation command used to activate the second target line. For example, the first activation command can be used to activate the word line (e.g., word line WL2) corresponding to the second target line. For instance, it could be... Figure 5 The second activation command shown is ACT2.

[0153] The first read command is used to read data from the storage unit of the second target row. Exemplarily, the first read command can be a read command (RD). It should be noted that, in embodiments of this disclosure, the first read command can also be a first automatic precharge read command (RDA), without specific limitation. For ease of illustration, this document will now describe it using the read command (RD).

[0154] The first test read data can be the test data obtained from the second target row during the test read.

[0155] For a specific implementation of S813, exemplarily, if the timing test corresponds to an adjustment duration t1, then after sending the first automatic precharge read command RDA, the second activation command ACT2 can be sent after an interval of duration t1. Furthermore, after sending the second activation command ACT2, a read command RD can be sent to the chip under test after an interval of a second preset duration. This second preset duration can be defined by a preset standard protocol and is not specifically limited thereto.

[0156] S814, based on the first test read data and the first test write data, determine the first read and write test result of the second target row in this command timing test.

[0157] In some embodiments, the first read / write test result may include a first test result identifier and a second test result identifier. The first test result identifier indicates that the second target row read / write operation failed, and the second test result identifier indicates that the second target row read / write operation succeeded.

[0158] In one example, S814 may include: in each command timing test, obtaining a second test result identifier indicating successful read / write if the data read in the first test and the data written in the first test are consistent; and obtaining a first test result identifier indicating read / write failure if the data read in the first test and the data written in the first test are inconsistent.

[0159] S820 determines the actual tRTP for each chip test group based on the first read / write test results of multiple command timing tests in each chip test group. In one example, the actual tRTP represents the critical value of the adjustment duration for the first read / write test result to change from the first test result identifier to the second test result identifier.

[0160] In some embodiments, S820 may include steps A1 to A3.

[0161] Step A1: Based on the first read / write test results of multiple command timing tests in at least one set of chip tests, a first SHMOO test graph is generated. The first SHMOO test graph includes at least one image sequence, each image sequence corresponding to a set of chip tests. Each image sequence includes multiple image units, each image unit corresponding to one command timing test, and each image unit has a visual identifier. The visual identifier is either a first test result identifier or a second test result identifier.

[0162] The visual identifiers are used to visually identify different read / write status parameters. For example, a first test result identifier indicates a read / write failure, and a first test result identifier indicates a read / write success. In some embodiments, the visual identifiers can be filled patterns, text, colors, icons, or other visual identifiers with an identifying function, without specific limitations. For example, red can be used to indicate a read / write failure, and green can be used to indicate a read / write success.

[0163] In one example Figure 11 An exemplary first shmoo test diagram provided by an embodiment of this disclosure is shown. The horizontal axis represents the value of the predefined encoding bits OP[7:4] (i.e., the preset tRTP), and the vertical axis represents the time interval between the first automatic precharge read command and the second activation command (i.e., the duration to be adjusted). The pattern-filled rectangle is the identifier for the first test result, and the white rectangle is the identifier for the second test result.

[0164] in, Figure 11Each rectangle represents an image unit, corresponding to one command timing test. Multiple rectangles along a column form an image sequence, corresponding to a set of chip tests. Since different encoding values ​​on the predefined encoding bits OP[7:4] correspond to different tRTPs, the encoding values ​​corresponding to image units in different columns are different, and correspondingly, they correspond to different preset tRTPs. Different image units in the same column correspond to different durations to be adjusted.

[0165] Step A2: Based on the first shmoo test chart, select the first baseline adjustment duration that meets the first preset selection conditions.

[0166] Among them, the first benchmark adjustment duration can refer to the critical value of the adjustment duration corresponding to the first read / write test result changing from the first test result identifier to the second test result identifier.

[0167] Among them, the first preset selection condition can refer to the condition that needs to be met when the critical value of the duration to be adjusted is determined when the first read / write test result changes from the first test result identifier to the second test result identifier.

[0168] In one example, the first preset selection criterion is: the maximum value among the adjustable durations corresponding to the command timing tests identified by the first test result. See also, for an example... Figure 11 For the first group of chip tests, the command timing tests corresponding to the first test result identifier (pattern-filled rectangle) have adjustment durations of 8T (clock cycles), 9T, 10T, 11T, and 12T, respectively. Accordingly, the maximum value of 12T can be selected as the first reference adjustment duration.

[0169] In a specific example, to improve calculation accuracy, the first preset selection condition can be the maximum value among the adjustment durations corresponding to multiple consecutive command timing tests corresponding to the first test result identifier. For example, in the shmoo test graph, if a certain first test result identifier is not continuous with other first test result identifiers, it is an isolated scatter point. When calculating the first baseline adjustment duration, the adjustment duration corresponding to the isolated first test result identifier can be ignored, and the maximum value among the adjustment durations of multiple consecutive command timing tests corresponding to the first test result identifier can be selected as the first baseline adjustment duration.

[0170] In another example, the first preset selection condition is: the minimum value among the adjusted durations of multiple command timing tests corresponding to the second test result identifier.

[0171] For example, see [link to previous article] Figure 11For the first group of chip tests, the timing of the remaining command tests, except for the first 5 command timing tests, all correspond to the second test result identifier. Accordingly, the adjustment duration corresponding to the 6th command timing test is determined as the first benchmark adjustment duration.

[0172] In a specific example, to improve calculation accuracy, the first preset selection condition can be: the minimum value among the adjusted durations of each of the consecutive command timing tests corresponding to the second test result identifier.

[0173] It should be noted that the first preset selection condition can also be other conditions that can determine the critical value of the duration to be adjusted when the first test result identifier is changed to the second test result identifier, and there are no specific restrictions on this.

[0174] By using the first preset selection condition provided in this embodiment, the critical value of the adjustment duration corresponding to the transformation of the first test result identifier into the second test result identifier can be accurately selected, improving the detection accuracy of actual tRTP and thus improving the detection accuracy of the chip's automatic pre-charge behavior. Furthermore, when selecting the maximum / minimum value among the adjustment durations corresponding to multiple consecutive command timing tests, the impact of abnormal read / write test results when the chip under test is abnormal on the actual tRTP is avoided, thereby further improving the detection accuracy and reliability of actual tRTP.

[0175] Step A3: Determine the first benchmark adjustment duration as the actual tRTP corresponding to this group of chip tests. Continuing the previous example, we can determine that the actual tRTP corresponding to the first group of chip tests is equal to 12T.

[0176] It should be noted that, in this embodiment of the disclosure, steps A1 to A3 above can be performed for each group of chip tests to determine the actual tRTP corresponding to each group of chip tests.

[0177] Through steps A1 to A3 above, since the shmoo test graph can intuitively show the changes in read and write test results with the duration to be adjusted, the actual tRTP corresponding to each group of chip tests can be accurately determined through image analysis, thereby improving the detection accuracy and orderliness of the chip's automatic pre-charging behavior.

[0178] In other embodiments, the adjustment duration for each of the multiple command timing tests in each chip test group changes sequentially. For example, it can be increased or decreased sequentially.

[0179] Accordingly, S820 may include steps A4 and A5 as follows.

[0180] Step A4: For each group of chip tests, determine the first benchmark adjustment duration that meets the first preset selection condition from the adjustment durations corresponding to the multiple command timing tests of this group of chip tests.

[0181] The specific details of the first benchmark adjustment duration and the first preset selection conditions can be found in the relevant descriptions in the above-mentioned parts of the embodiments of this disclosure, and will not be elaborated further here.

[0182] In one example, data analysis or data processing can be used to select the first baseline adjustment duration from the adjustment durations corresponding to multiple command timing tests. For instance, if the adjustment durations for 5 command timing tests are "8T", "10T", "11T", "12T", and "13T" respectively, and the first read / write test results are "F, F, F, S, S" respectively, then the first baseline adjustment duration can be determined to be 11T.

[0183] Step A5: Determine the first benchmark adjustment duration as the actual tRTP corresponding to the chip test of this group.

[0184] Through steps A4 and A5 above, by controlling the adjustment duration to increase sequentially in multiple command timing tests, the first read / write test results of multiple command timing tests can accurately reflect the process of the first test result identifier gradually changing to the second test result identifier as the adjustment duration gradually changes. Thus, the actual tRTP corresponding to each group of chip tests can be quickly and accurately determined through data analysis and other methods, improving the detection accuracy and orderliness of the chip's automatic pre-charging behavior.

[0185] It should be noted that in S820, other methods can also be used to determine the actual tRTP corresponding to each group of chip tests by determining the threshold value of the adjustment duration corresponding to the first test result identifier gradually converting to the second test result identifier. No specific restrictions are imposed on this.

[0186] The chip testing method provided in this disclosure provides a timing test with a duration to be adjusted for each command timing test. Accordingly, the interval between the first automatic precharge read command and the second activation command can be changed between multiple command timing tests in each chip test group as the duration to be adjusted for each command timing test changes. Furthermore, when the same test data is written to the first target line and the second target line, if the second activation command is earlier than the automatic precharge action time, a first read / write test result indicating a read / write failure will be obtained; similarly, if the second activation command is later than the automatic precharge action time, the read / write will be successful. Therefore, by changing the duration to be adjusted to change the interval between the first automatic precharge read command and the second activation command in each command timing test, the actual tRTP corresponding to each chip test group, i.e., the time interval between the second activation command and the automatic precharge action time, can be determined based on the changes in the first read / write test results of multiple command timing tests in each chip test group. Moreover, since the actual tRTP can accurately reflect the actual position of the automatic precharge behavior in the command timing, this disclosure embodiment can accurately detect the chip's automatic precharge behavior.

[0187] The chip testing method provided in this disclosure can also verify whether the automatic pre-charging behavior meets the expected design function, which will be explained in the following embodiments.

[0188] In some embodiments, the chip testing method may further include steps B1 and B2.

[0189] Step B1: Obtain at least one set of chips for testing their respective preset tRTP.

[0190] The preset tRTP is set by writing the predefined code corresponding to the chip test in the predefined encoding bits of the mode register.

[0191] The predefined encoding is specified by a predefined standard protocol. This predefined specification protocol can be a protocol that specifies the precharge duration tRP for memory reads and writes. For example, the predefined specification protocol can be a Joint Electron Device Engineering Council (JEDEC) standard protocol.

[0192] For example, if a set of chip tests corresponds to the predefined code "0011", then according to Figure 7 It can be seen that the preset tRTP corresponding to this chip test is equal to 17T.

[0193] Step B2, after at least one group of chips has tested their respective preset tRTPs and at least one group of chips has tested their respective actual tRTPs and both meet preset consistency conditions, determines that the automatic precharge behavior of the chip under test meets design expectations. In one embodiment, this can also be described as determining whether the automatic precharge behavior of the chip under test conforms to preset specification protocols such as JEDEC.

[0194] For example, it can be determined whether the actual tRTP value range of at least one set of chip tests is consistent with the preset tRTP value range of at least one set of chip tests. For example, see [link to documentation]. Figure 7 The preset tRTP range corresponding to OP[7:4] = 0000~1000 is [12T, 24T]. And, in Figure 11 In the example, the actual tRTP range corresponding to OP[7:4] = 0000~1000 is [12T, 24T]. The actual tRTP value range is consistent with the preset tRTP value range, and chip 1 meets the design expectations. However, if the actual tRTP range corresponding to OP[7:4] = 0000~1000 is [11T, 22T], and the actual tRTP value range is inconsistent with the preset tRTP value range, then the chip does not meet the design expectations.

[0195] Another example is that the determination can be made based on whether the actual tRTP of each group of chips is consistent with the preset tRTP. For instance, if the actual tRTP of each group of chips is consistent with the preset tRTP, it is determined that the design expectation is met.

[0196] It should be noted that, in the embodiments disclosed herein, other methods can be used to verify whether the actual tRTP is consistent with the preset tRTP in order to verify whether it meets the design expectations, and no specific limitations are imposed on this.

[0197] By using steps B1 and B2 above, we can verify whether the chip meets the design expectations or design specifications by verifying whether the actual tRTP is consistent with the preset tRTP. This allows for accurate verification of whether the automatic pre-charging behavior of chips from different manufacturers and of various models meets the design specifications, improving the comprehensiveness and reliability of the verification and increasing the yield of various types of chips.

[0198] In one embodiment, step B3 is included before step B1.

[0199] Step B3: In each group of chip tests, write the predefined code corresponding to this group of chip tests into the predefined encoding bits of the mode register of the chip under test, so as to set the tRTP of the chip under test to the preset tRTP corresponding to this group of chip tests. For example, the mode register can be mode register 6 (MR6).

[0200] In one example, nine sets of chip tests can be performed. When performing the first set of chip tests, OP[7:4] in the mode register is set to 0000; when performing the second set of chip tests, OP[7:4] is set to 0001; ...; when performing the ninth set of chip tests, OP[7:4] is set to 1000. This allows for a thorough test of whether the automatic pre-charging behavior of the chip under test meets design expectations.

[0201] Through this embodiment, the preset tRTP of each group of chips can be flexibly configured in each group of chip tests by writing predefined codes into predefined encoding bits, thereby enabling flexible testing of whether the automatic pre-charging behavior of the chip under test meets the design expectations.

[0202] After introducing the function of verifying whether the automatic pre-charge behavior meets the design expectations, optionally, the chip testing method provided in this disclosure can also determine whether there are operational anomalies. This will be described below through several embodiments.

[0203] In some embodiments, the chip testing method may further include steps C1 and C2.

[0204] Step C1: In each chip test group, among the first read / write test results of multiple command timing tests, determine whether there are any abnormal read / write test results. For example, an abnormal read / write test result is a first test result identifier, and its corresponding adjustment duration is not continuous with the adjustment durations corresponding to other first test result identifiers in the same chip test group.

[0205] In one example, step C1 may include: among the first read / write test results of multiple command timing tests in each chip test group, determining whether there is a first read / write test result that meets a preset abnormal result determination condition. If there is a first read / write test result that meets the preset abnormal result determination condition, it is determined that an abnormal read / write test result exists. If there is no first read / write test result that meets the preset abnormal result determination condition, it is determined that no abnormal read / write test result exists.

[0206] For example, the preset abnormal result judgment conditions include: the adjustment time corresponding to the abnormal read / write test result is not continuous with the adjustment time corresponding to other first test result identifiers of the same group of chips.

[0207] In one example, data analysis can be used to determine whether there are abnormal read / write test results.

[0208] In another example, the presence of abnormal read / write test results can be determined through image analysis or data analysis using the first shmoo test graph. For instance, an isolated first test result in the shmoo test graph can be identified as an abnormal read / write test result.

[0209] Step C2: If abnormal read / write test results are found, it is determined that the automatic pre-charge behavior of the chip under test is abnormal.

[0210] By using steps C1 and C2 provided in the embodiments of this disclosure, operational abnormalities in the automatic pre-charging behavior of the chip under test can be accurately detected, thereby improving the yield of the chip under test.

[0211] In some embodiments, after step C2, the method may further include steps C3 and C4 as described below.

[0212] Step C3: Generate an abnormal alarm message to characterize the abnormal operation of the automatic precharge behavior of the chip under test.

[0213] Step C4: Report the abnormal alarm information. For example, the abnormal alarm information can be reported to the testing device or other devices with human-computer interaction structures, so that technicians can be informed of the abnormality of the chip under test in a timely manner, so as to repair or remove it in a timely manner.

[0214] This embodiment enables the generation and reporting of abnormal alarm information after an anomaly is detected in the chip under test, thus achieving timely early warning of chip anomalies.

[0215] Based on the same inventive concept, the inventors also discovered that if the data written to the first target row and the second target row are different, for example, if the data stored in the storage unit of the first target row is "1" and the data stored in the storage unit 32 of the second target row is 0, then when in Figure 4 When the indicated position triggers the activation command ACT2 for the second target row, residual charge on the bit line BL of the first target row may cause the second target row data read to fail. In other words, when different data is written to the first and second target rows, after the automatic precharge read command (RDA), an automatic precharge operation will be performed via tRTP. After automatic precharge, tRP will ensure the bit line voltage returns to the reference value before the activation operation of the next row can proceed correctly. That is, at least tRTP + tRP is required between the automatic precharge read command (RDA) for the first target row and the activation command (ACT2) for the second target row to be read normally.

[0216] Based on the above findings, this disclosure also provides a technical solution for testing the tRP of the chip under test, which will be described below with reference to the accompanying drawings.

[0217] Figure 12 This illustration shows a flowchart of another chip testing method provided by an embodiment of the present disclosure. This embodiment is an optimization based on the above embodiments, and can be combined with various optional solutions from one or more of the above embodiments.

[0218] like Figure 12 As shown, the chip testing method includes the following steps S1210 to S1240.

[0219] S1210, perform at least one set of chip tests on the chip under test, wherein each set of chip tests includes multiple command timing tests, each set of chip tests corresponds to a preset tRTP, and each command timing test corresponds to an adjustable duration.

[0220] In each command timing test, the following steps S1211 to S1218 are executed.

[0221] S1211, write the same first test write data to the first target row and the second target row. The first target row and the second target row belong to the same memory bank of the chip under test.

[0222] S1211 is similar to S811, and the details of S811 can be found in the specific content, which will not be repeated here.

[0223] S1212, send the first activation command and the first automatic precharge read command to the chip under test in sequence to perform a read operation on the first target row.

[0224] S1212 is similar to S812, and the details of S812 can be found in the specific content, which will not be repeated here.

[0225] S1213, starting from the first automatic precharge read command and after the adjustment time corresponding to the timing test of this command, the second activation command and the first read command are sent to the chip under test in sequence to obtain the first test read data of the second target row.

[0226] S1213 is similar to S813, and the details of S813 can be found in the specific content, which will not be repeated here.

[0227] S1214, based on the first test read data and the first test write data, determine the first read and write test results of the second target row in this command timing test, and the third target row and the fourth target row belong to the same memory bank of the chip under test.

[0228] S1214 is similar to S814, and the details of S814 can be found in the specific content, which will not be repeated here.

[0229] S1215, write the second test write data and the third test write data to the third target row and the fourth target row, respectively. The third target row and the fourth target row belong to the same memory bank of the chip under test.

[0230] In S1215, the third target row can refer to the row in the memory that needs to be read / write tested. The third target row and the first target row can be the same row or different rows.

[0231] The fourth target row can refer to the row in memory that needs to be read after the third target row has been read. The third target row and the second target row can be the same row or different rows.

[0232] The second test write data can be the test data that needs to be written to the third target row during the read / write test. The third test write data can be the test data that needs to be written to the fourth target row during the read / write test. The second and third test write data are different. For example, this could mean writing different data to the memory cells corresponding to the same bit line in the third and fourth target rows.

[0233] In one example Figure 13 A schematic diagram illustrating an exemplary second test write data and a third test write data provided in an embodiment of this disclosure is shown. Figure 13 As shown, if the first test write data "10101010" is written to the storage cell of the first target row (corresponding to word line WL1), the same data "01010101" can be written to the storage cell of the second target row (corresponding to word line WL2). The write data of the storage cells of different rows on each bit line is different.

[0234] In some embodiments, S1215 may include: writing second test write data to the third target row, and writing third test write data to the third target row. For example, the data writing to the third and fourth target rows may be performed before the read operation on the third target row.

[0235] S1216, sequentially sends a third activation command and a second automatic precharge read command to the chip under test to perform a read operation on the third target row.

[0236] The third activation command can be an activation command used to activate a third target row. For details regarding the third activation command, please refer to the above description of the first activation command in the embodiments of this disclosure; further details will not be repeated here.

[0237] The second automatic precharge read command is used to read data from the third target row and perform an automatic precharge operation after a preset tRTP interval. For details regarding the second automatic precharge read command, please refer to the description of the first automatic precharge read command in the above-mentioned embodiments of this disclosure; further details will not be repeated here.

[0238] In some embodiments, in S1216, a second automatic precharge read command can be sent to the chip under test after a first preset time interval from the time interval between sending the third activation command. The first preset time interval can be specified by a preset standard protocol and is not specifically limited thereto.

[0239] S1217: Starting from the second automatic precharge read command and after the adjustment time corresponding to the timing test of this command, the fourth activation command and the second read command are sent to the chip under test in sequence to obtain the second test read data of the fourth target row.

[0240] The fourth activation command can be an activation command used to activate the fourth target row. For details regarding the fourth activation command, please refer to the description of the second activation command in the preceding sections of this disclosure; further details will not be repeated here.

[0241] The second read command is used to read data from the storage unit of the fourth target row. For details regarding the second read command, please refer to the description of the first read command in the above-mentioned embodiments of this disclosure; further details will not be repeated here.

[0242] The second test data can be the test data read from the fourth target row during the test.

[0243] The specific implementation of S1217 is similar to that of S813. Please refer to the relevant description of S813 in the above part of the embodiments of this disclosure, and it will not be repeated here.

[0244] S1218, based on the second test read data and the third test write data, determine the second read / write test result of the fourth target row in this command timing test. The second read / write test result can be either a third test result identifier indicating read / write failure, or a fourth test result identifier indicating read / write success.

[0245] In one example, S1218 may include: obtaining a fourth test result identifier if, in each command timing test, the data read in the second test and the data written in the third test are consistent; and obtaining a fourth test result identifier if the data read in the second test and the data written in the third test are inconsistent.

[0246] S1220 determines the actual tRTP corresponding to each chip test group based on the first read / write test results of multiple command timing tests in each chip test group.

[0247] S1220 is similar to S820, and the details of S820 can be found in the specific content, which will not be repeated here.

[0248] S1230, based on the second read / write test results of multiple command timing tests in each chip test group, determine the first latency value corresponding to each chip test group. In one example, the first latency value represents the critical value for adjusting the duration when the second read / write test result changes from the third test result identifier to the fourth test result identifier. Exemplarily, the first latency value can characterize the sum of the actual tRTP and the actual tRP.

[0249] In some embodiments, S1230 may include steps D1 to D3.

[0250] Step D1: Generate a second shmoo test graph based on the second read / write test results of multiple command timing tests in at least one set of chip tests.

[0251] The second SHMO test pattern includes at least one image sequence, each image sequence corresponding to a set of chip tests. Each image sequence includes multiple image units, each image unit corresponding to one command timing test, and each image unit has a visual identifier, which is either a third test result identifier or a fourth test result identifier. The relevant content of the second SHMO test pattern is similar to that of the first SHMO test pattern; please refer to the above description of the first SHMO test pattern in the embodiments of this disclosure, which will not be repeated here.

[0252] Step D2: Based on the second shmoo test chart, select the second baseline adjustment duration that meets the second preset selection conditions.

[0253] Among them, the second benchmark adjustment duration can refer to the critical value of the adjustment duration corresponding to the change of the second read / write test result from the third test result identifier to the fourth test result identifier.

[0254] Among them, the second preset selection condition can refer to the condition that needs to be met when the second read / write test result is changed from the third test result identifier to the fourth test result identifier, corresponding to the critical value of the duration to be adjusted.

[0255] In one example, the second preset selection condition is the maximum value among the adjustment durations corresponding to each command timing test for the third test result identifier. For example, the second preset selection condition could be the maximum value among the adjustment durations corresponding to multiple consecutive command timing tests for the third test result identifier.

[0256] In a specific example Figure 14 An exemplary second shmoo test pattern provided by an embodiment of this disclosure is shown. Figure 14 As shown, for the first group of chip tests, the maximum adjustment duration value of 21T corresponding to the third test result identifier can be selected as the second benchmark adjustment duration.

[0257] In another example, the second preset selection condition is the minimum value among the adjustment durations corresponding to each of the command timing tests corresponding to the fourth test result identifier. For example, the second preset selection condition could be the minimum value among the adjustment durations corresponding to multiple consecutive command timing tests corresponding to the fourth test result identifier.

[0258] Step D3: Determine the second benchmark adjustment duration as the first delay value corresponding to the chip test of this group.

[0259] For example, see [link to previous article] Figure 14 21T can be used as the first latency value corresponding to the first group of chips for testing.

[0260] It should be noted that the second preset selection condition can also be other conditions that can determine the critical value of the duration to be adjusted when the third test result identifier changes to the fourth test result identifier, and there are no specific restrictions on this.

[0261] Through steps D1 to D3 above, since the shmoo test graph can intuitively show the changes in read and write test results with the duration to be adjusted, the first delay value corresponding to each group of chip tests can be accurately determined through image analysis, thereby improving the detection accuracy and orderliness of the chip's automatic pre-charging behavior.

[0262] In some embodiments, the duration to be adjusted for each of the multiple command timing tests in each chip test group changes sequentially.

[0263] Accordingly, S1230 may include steps D4 and D5 as follows.

[0264] Step D4: For each group of chip tests, determine the second benchmark adjustment duration that meets the second preset selection condition from the adjustment durations corresponding to the multiple command timing tests of this group of chip tests.

[0265] The specific details of the second benchmark adjustment duration and the second preset selection conditions can be found in the relevant descriptions in the above-mentioned parts of the embodiments of this disclosure, and will not be elaborated further here.

[0266] In one example, data analysis or data processing can be used to select the second benchmark adjustment duration from the adjustment durations corresponding to multiple command timing tests. Step D5: Determine the second benchmark adjustment duration as the first delay value corresponding to the chip group test.

[0267] Through steps D4 and D5 above, by controlling the adjustment duration to increase sequentially in multiple command timing tests, the second read / write test results of multiple command timing tests can accurately reflect the process of the third test result identifier gradually changing to the fourth test result identifier as the adjustment duration gradually changes. Thus, the first delay value corresponding to each group of chip tests can be quickly and accurately determined through data analysis and other methods, improving the detection accuracy and orderliness of the chip's automatic pre-charging behavior.

[0268] It should be noted that in S1230, other methods can also be used to determine the first delay value corresponding to each group of chip tests by determining the critical value of the time to be adjusted corresponding to the third test result identifier gradually converting to the fourth test result identifier. There are no specific restrictions on this.

[0269] S1240, based on at least one set of chip tests, the actual tRTP and first delay value of each chip are used to determine the tRP of the chip under test.

[0270] In S1240, since the first delay value can characterize the sum of the actual tRTP and the actual tRP, the actual tRP can be determined after the first delay value and the actual tRTP are determined.

[0271] In some embodiments, when the adjustment duration is the same, the tRP of the chip under test can be determined based on the difference between the first delay value and the actual tRTP.

[0272] Accordingly, S1240 may include steps E1 to E3.

[0273] Step E1: Determine the baseline tRTP by testing the actual tRTP corresponding to each of at least one set of chips.

[0274] For example, one can be selected as the benchmark tRTP from at least one set of chip tests for their respective actual tRTPs.

[0275] Step E2: Determine the reference delay value based on the first delay value corresponding to each of at least one set of chips.

[0276] For example, a reference latency value can be selected from the first latency values ​​corresponding to at least one set of chip tests. Optionally, the reference latency value and the reference tRTP correspond to the same set of chip tests, that is, they correspond to the same duration to be adjusted.

[0277] Step E3: Determine tRP based on the difference between the reference delay value and the reference tRTP.

[0278] In one example, tRP can be equal to the difference between the baseline delay value and the baseline tRTP. See also, for an example... Figure 11 and Figure 14 The reference tRTP is equal to 12T, the reference delay is equal to 22T, and tRP is equal to 22T-12T, that is, tRP is equal to 10T.

[0279] It should be noted that other methods can also be used to determine the baseline tRTP and baseline delay values, and no specific restrictions are imposed on these methods. Furthermore, after determining the difference between the baseline delay value and the baseline tRTP, the calculation method can be further optimized by multiplying it by a scaling factor and considering the influence of other parameters on the test results, and no specific restrictions are imposed on these methods either.

[0280] Through steps E1 to E3 above, since the first delay value can characterize the sum of the actual tRTP and the actual tRP, the tRP of the chip under test can be accurately calculated based on the first delay value and the actual tRTP, thus realizing the accurate detection of the chip's automatic pre-charging behavior.

[0281] In other embodiments, a reference tRP can be calculated based on the actual tRTP and a first delay value for each group of chip tests. Then, the tRP of the chip under test is determined based on the reference tRPs of at least one group of chip tests.

[0282] For example, the average value of the reference tRP of each of at least one set of chips can be calculated and used as the tRP of the chip under test.

[0283] Alternatively, the frequency of occurrence of each value in the reference tRP of at least one group of chips can be counted, and the reference tRP with the highest frequency can be used as the tRP of the chip to be tested.

[0284] It should be noted that other methods can also be used in S1240 to calculate tRP based on the actual tRTP and the first delay value of each of at least one set of chips, and no specific restrictions are imposed on this.

[0285] The chip testing method provided in this disclosure provides a timing test with a duration to be adjusted for each command timing test. Accordingly, the interval between the first automatic precharge read command and the second activation command can be changed between multiple command timing tests in each chip test group as the duration to be adjusted for each command timing test changes. Furthermore, when the same test data is written to the first target line and the second target line, if the second activation command is earlier than the automatic precharge action time, a first read / write test result indicating a read / write failure will be obtained; similarly, if the second activation command is later than the automatic precharge action time, the read / write will be successful. Therefore, by changing the duration to be adjusted to change the interval between the first automatic precharge read command and the second activation command in each command timing test, the actual tRTP corresponding to each chip test group, i.e., the time interval between the second activation command and the automatic precharge action time, can be determined based on the changes in the first read / write test results of multiple command timing tests in each chip test group. Moreover, since the actual tRTP can accurately reflect the actual position of the automatic precharge behavior in the command timing, this disclosure embodiment can accurately detect the chip's automatic precharge behavior.

[0286] Furthermore, since when different test data is written to the first target row and the second target row, if the time interval between the fourth activation command and the second automatic precharge read command is greater than tRTP+tRP, the read / write operation will succeed; conversely, if the time interval is less than tRTP+tRP, the read / write operation will fail. Therefore, by changing the interval between the second automatic precharge read command and the fourth activation command in each command timing test by changing the duration to be adjusted, the first latency value corresponding to each chip test group can be determined based on the changes in the second read / write test results of multiple command timings in each chip test group. And since the first latency value represents tRTP+tRP, after determining the first latency value and the actual tRTP, the tRP of the chip under test can be accurately detected.

[0287] In some embodiments, the chip testing method may further include steps F1 and F2.

[0288] Step F1: In each group of chip tests, among the second read / write test results of multiple command timing tests, determine whether there are any abnormal read / write test results. For example, an abnormal read / write test result is a first test result identifier, and its corresponding adjustment duration is not continuous with the adjustment durations corresponding to other first test result identifiers in the same group of chip tests.

[0289] Step F1 is similar to step C1. Please refer to the relevant description of step C1 in the above part of the embodiments of this disclosure, and it will not be repeated here.

[0290] Step F2: If abnormal read / write test results are found, it is determined that the automatic pre-charge behavior of the chip under test is abnormal.

[0291] By using steps F1 and F2 provided in the embodiments of this disclosure, operational abnormalities in the automatic pre-charging behavior of the chip under test can be accurately detected, thereby improving the yield of the chip under test.

[0292] In some embodiments, after step F2, the method may further include steps F3 and F4 as described below.

[0293] Step F3 generates an anomaly alarm message to characterize the abnormal operation of the automatic precharge behavior of the chip under test.

[0294] Step F4: Report the abnormal alarm information. For example, the abnormal alarm information can be reported to the testing device or other devices with human-computer interaction structures, so that technicians can be informed of the abnormality of the chip under test in a timely manner, so as to repair or remove it in a timely manner.

[0295] This embodiment enables the generation and reporting of abnormal alarm information after an anomaly is detected in the chip under test, thus achieving timely early warning of chip anomalies.

[0296] Based on the same inventive concept, this disclosure also provides a chip testing device, as shown in the following embodiments.

[0297] Figure 15 A schematic diagram of a chip testing apparatus provided in an embodiment of this disclosure is shown, such as... Figure 15 As shown, the chip testing device 1500 includes a chip testing module 1510 and a first processing module 1520.

[0298] The chip test module 1510 is used to perform at least one set of chip tests on the chip under test. Each set of chip tests includes multiple command timing tests, each set of chip tests corresponds to a preset tRTP, and each command timing test corresponds to an adjustable duration.

[0299] The chip testing module 1510 includes a data writing unit, a data reading unit, and a testing unit.

[0300] The data writing unit is used to write the same first test write data to the first target line and the second target line in each command timing test. The first target line and the second target line belong to the same memory bank of the chip under test.

[0301] The data reading unit is configured to send a first activation command and a first automatic precharge read command to the chip under test in each command timing test to perform a read operation on the first target row; and, in each command timing test, it is also configured to send a second activation command and a first read command to the chip under test in each command timing test, starting from the first automatic precharge read command and after an interval of the adjustment time corresponding to this command timing test, to obtain the first test read data of the second target row.

[0302] The test unit is used to determine the first read / write test result of the second target row in this command timing test based on the first test read data and the first test write data.

[0303] The first processing module 1520 is used to determine the actual tRTP corresponding to each group of chip tests based on the first read and write test results of multiple command timing tests in each group of chip tests.

[0304] The chip testing apparatus provided in this disclosure provides a timing test for each command, corresponding to an adjustable duration. Accordingly, the interval between the first automatic precharge read command and the second activation command between multiple command timing tests in each chip test group can be changed by altering the adjustable duration corresponding to each command timing test. Furthermore, when writing the same test data to the first and second target rows, if the second activation command is earlier than the automatic precharge action time, a first read / write test result indicating a read / write failure will be obtained; similarly, if the second activation command is later than the automatic precharge action time, the read / write will be successful. Therefore, by changing the adjustable duration to alter the interval between the first automatic precharge read command and the second activation command in each command timing test, the actual tRTP corresponding to each chip test group—that is, the time interval between the second activation command and the automatic precharge action time—can be determined based on the changes in the first read / write test results of multiple command timing tests in each chip test group. Moreover, since the actual tRTP accurately reflects the actual position of the automatic precharge behavior in the command timing, this disclosure embodiment can accurately detect the chip's automatic precharge behavior.

[0305] In one embodiment, the duration to be adjusted for each of the multiple command timing tests in each chip test group changes sequentially.

[0306] The first processing module 1520 is specifically configured to: for each group of chip tests, determine the first benchmark adjustment duration that meets the first preset selection condition from the adjustment durations corresponding to the multiple command timing tests of the chip test in this group; and determine the first benchmark adjustment duration as the actual tRTP corresponding to the chip test in this group.

[0307] In one embodiment, the first read / write test result is either a first test result identifier indicating read / write failure or a second test result identifier indicating read / write success.

[0308] The first processing module 1520 includes: a Shmoo graph generation unit and a first time determination unit.

[0309] The Shmoo graph generation unit is used to generate a first Shmoo test graph based on the first read and write test results of multiple command timing tests in at least one set of chip tests. The first Shmoo test graph includes at least one image sequence, each image sequence corresponds to a set of chip tests, each image sequence includes multiple image units, each image unit corresponds to one command timing test, and each image unit has a visual identifier, which is either a first test result identifier or a second test result identifier.

[0310] The first time determination unit is used to select a first reference adjustment duration that meets the first preset selection conditions based on the first shmoo test pattern; the first reference adjustment duration is determined as the actual tRTP corresponding to the chip test of this group.

[0311] In one embodiment, the first read / write test result is either a first test result identifier indicating read / write failure or a second test result identifier indicating read / write success.

[0312] The first preset selection condition is: the maximum value among the adjustment durations corresponding to the command timing tests of the first test result identifier; or the minimum value among the adjustment durations corresponding to the command timing tests of the second test result identifier.

[0313] In one embodiment, during each command timing test, the data writing unit is also used to write second test write data and third test write data to the third target line and the fourth target line, respectively. The second test write data and the third test write data are different, and the third target line and the fourth target line belong to the same memory bank of the chip under test.

[0314] In each command timing test, the data reading unit is also used to send a third activation command and a second automatic precharge read command to the chip under test in sequence to perform a read operation on the third target row; and in each command timing test, it is also used to send a fourth activation command and a second read command to the chip under test in sequence after the second automatic precharge read command starts and after an interval of the adjustment time corresponding to this command timing test, to obtain the second test read data of the fourth target row.

[0315] In each command timing test, the test unit is also used to determine the second read and write test result of the fourth target row in this command timing test based on the second test read data and the third test write data. The second read and write test result is either a third test result identifier indicating read and write failure, or a fourth test result identifier indicating read and write success.

[0316] In addition, the chip testing device 1500 also includes a second processing module and a third processing module.

[0317] The second processing module is used to determine the first delay value corresponding to each group of chip tests based on the second read and write test results of multiple command timing tests in each group of chip tests. The first delay value represents the critical value of the adjustment time for the second read and write test result to change from the third test result identifier to the fourth test result identifier.

[0318] The third processing module is used to determine the tRP of the chip under test by testing the actual tRTP and the first delay value of each of at least one set of chips.

[0319] In one embodiment, the third processing module is specifically configured to: determine a reference tRTP based on the actual tRTP corresponding to at least one set of chips; determine a reference delay value based on the first delay value corresponding to at least one set of chips; and determine tRP based on the difference between the reference delay value and the reference tRTP.

[0320] In one embodiment, the test unit is specifically configured to: for each group of chip tests, determine a second reference adjustment duration that meets the second preset selection condition from the adjustment durations corresponding to the multiple command timing tests of the chip test group; and determine the second reference adjustment duration as the first delay value corresponding to the chip test group.

[0321] In one embodiment, the second preset selection condition includes: the maximum value among the adjustment durations corresponding to the command timing tests corresponding to the third test result identifier; or, the minimum value among the adjustment durations corresponding to the command timing tests corresponding to the fourth test result identifier.

[0322] In one embodiment, the test unit is specifically configured to: generate a second shmoo test graph based on the second read / write test results of multiple command timing tests in at least one set of chip tests, wherein the second shmoo test graph includes at least one image sequence, each image sequence corresponds to a set of chip tests, each image sequence includes multiple image units, each image unit corresponds to one command timing test, and each image unit has a visual identifier, which is a third test result identifier or a fourth test result identifier; based on the second shmoo test graph, select a second benchmark adjustment duration that meets a second preset selection condition; and determine the second benchmark adjustment duration as the first delay value corresponding to this set of chip tests.

[0323] In one embodiment, the chip testing apparatus 1500 further includes a time acquisition module and a verification module.

[0324] The time acquisition module is used to acquire the preset tRTP for at least one group of chip tests. The preset tRTP is set by writing the predefined code corresponding to the chip test in the predefined encoding bit in the mode register. The predefined code is specified by the preset standard protocol.

[0325] The verification module is used to determine whether the automatic precharge behavior of the chip under test meets the design expectations, provided that at least one group of chips tests their respective preset tRTP and at least one group of chips tests their respective actual tRTP and both meet the preset consistency conditions.

[0326] In one embodiment, the chip testing apparatus 1500 further includes a time setting module.

[0327] The time setting module is used to write the predefined code corresponding to the chip test in the predefined encoding bit of the mode register of the chip under test in each chip test group, so as to set the tRTP of the chip under test to the preset tRTP corresponding to the chip test in this group.

[0328] In one embodiment, the chip testing apparatus 1500 further includes an anomaly diagnosis module.

[0329] The anomaly diagnosis module is used to determine whether there are abnormal read / write test results in the first read / write test results of multiple command timing tests in each group of chip tests; if abnormal read / write test results are found, it is determined that the automatic pre-charge behavior of the chip under test is abnormal.

[0330] In one embodiment, the anomaly diagnosis module is further configured to: determine whether there are abnormal read / write test results in the second read / write test results of multiple command timing tests in each group of chip tests; and determine that the automatic pre-charge behavior of the chip under test is abnormal if there are abnormal read / write test results.

[0331] In one embodiment, the anomaly diagnosis module is specifically configured to: determine whether there is a first read / write test result that meets the preset anomaly result judgment condition among the first read / write test results of multiple command timing tests in each group of chip tests; if there is a first read / write test result that meets the preset anomaly result judgment condition, determine the first read / write test result that meets the preset anomaly result judgment condition as an abnormal read / write test result.

[0332] Among them, the preset abnormal result judgment conditions include: the adjustment time corresponding to the abnormal read and write test result is not continuous with the adjustment time corresponding to other first test result identifiers of the same group of chips.

[0333] In one embodiment, the anomaly diagnosis module is specifically configured to: determine whether there is a second read / write test result that meets the preset anomaly result judgment condition among the second read / write test results of multiple command timing tests in each group of chip tests; if there is a second read / write test result that meets the preset anomaly result judgment condition, determine the second read / write test result that meets the preset anomaly result judgment condition as an abnormal read / write test result.

[0334] Among them, the preset abnormal result judgment conditions include: the adjustment time corresponding to the abnormal read and write test result is not continuous with the adjustment time corresponding to other first test result identifiers of the same group of chips.

[0335] In one embodiment, the chip testing apparatus 1500 further includes an alarm information generation module and an alarm information reporting module.

[0336] The alarm information generation module is used to generate abnormal alarm information to indicate that there is an operational abnormality in the automatic pre-charging behavior of the chip under test.

[0337] The alarm information reporting module is used to report abnormal alarm information. It should be noted that... Figure 15 The chip testing device 1500 shown can perform... Figures 8 to 14 The various steps in the method embodiment shown are implemented. Figures 8 to 14 The processes and effects in the method embodiments shown are not described in detail here.

[0338] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0339] The following reference Figure 16To describe an electronic device 1600 according to such an embodiment of the present disclosure. Figure 16 The electronic device 1600 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0340] like Figure 16 As shown, the electronic device 1600 is manifested in the form of a general-purpose computing device. The components of the electronic device 1600 may include, but are not limited to: at least one processing unit 1610, at least one storage unit 1620, and a bus 1630 connecting different system components (including storage unit 1620 and processing unit 1610).

[0341] The storage unit stores program code, which can be executed by the processing unit 1610, causing the processing unit 1610 to perform the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of this disclosure.

[0342] Storage unit 1620 may include readable media in the form of volatile storage units, such as random access memory (RAM) 16201 and / or cache memory 16202, and may further include read-only memory (ROM) 16203.

[0343] Storage unit 1620 may also include a program / utility 16204 having a set (at least one) of program modules 16205, such program modules 16205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0344] Bus 1630 can represent one or more of several types of bus structures, including memory cell bus or memory cell controller, peripheral bus, graphics acceleration port, processing unit, or local bus using any of the multiple bus structures.

[0345] Electronic device 1600 can also communicate with one or more external devices 1640 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 1600, and / or with any device that enables electronic device 1600 to communicate with one or more other computing devices (e.g., router, modem, etc.). Such communication can be performed through input / output (I / O) interface 1650.

[0346] Furthermore, the electronic device 1600 can also communicate with one or more networks (such as local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via the network adapter 1660.

[0347] like Figure 16 As shown, network adapter 1660 communicates with other modules of electronic device 1600 via bus 1630.

[0348] It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 1600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0349] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0350] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. Figure 17 A schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure is shown, such as... Figure 17 As shown, the computer-readable storage medium 1700 stores a program product capable of implementing the methods described above.

[0351] In some possible implementations, various aspects of this disclosure may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the “Exemplary Methods” section of this specification according to various exemplary embodiments of this disclosure.

[0352] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0353] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein readable program code is carried. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0354] A readable signal medium can also be any readable medium other than a readable storage medium, which can send, propagate or transmit a program for use by or in connection with an instruction execution system, apparatus or device.

[0355] In some examples, program code contained on a computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0356] In practice, program code for performing the operations of this disclosure can be written using any combination of one or more programming languages. These programming languages ​​include object-oriented programming languages—such as Java and C++—as well as conventional procedural programming languages—such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0357] In cases involving remote computing devices, the remote computing devices can be connected to user computing devices via any type of network, including local area networks (LANs) or wide area networks (WANs), or they can be connected to external computing devices (e.g., via the Internet using an Internet service provider).

[0358] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the chip testing method provided in various alternative embodiments of this disclosure.

[0359] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0360] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0361] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware.

[0362] Therefore, the technical solution according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the method according to the embodiments of this disclosure.

[0363] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein.

[0364] This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A chip testing method, characterized in that, The method includes: At least one set of chip tests is performed on the chip under test. Each set of chip tests includes multiple command timing tests. Each set of chip tests corresponds to a preset read precharge time tRTP. Each command timing test corresponds to an adjustment duration. The adjustment duration corresponding to each of the multiple command timing tests in each set of chip tests changes sequentially. In each of the command timing tests, the following steps are performed: Write the same first test write data into the first target row and the second target row, where the first target row and the second target row belong to the same memory bank of the chip under test; A first activation command and a first automatic precharge read command are sent sequentially to the chip under test to perform a read operation on the first target row; Starting from the first automatic precharge read command and after the time interval corresponding to the time to be adjusted for this command timing test, the second activation command and the first read command are sent to the chip under test in sequence to obtain the first test read data of the second target row. Based on the first test read data and the first test write data, determine the first read and write test result of the second target row in this command timing test; Based on the first read / write test results of each of the multiple command timing tests in each chip test group, the actual tRTP corresponding to each chip test group is determined, including: for each chip test group, determining a first benchmark adjustment duration that meets the first preset selection condition from the adjustment durations corresponding to the multiple command timing tests in this chip test group; and determining the first benchmark adjustment duration as the actual tRTP corresponding to this chip test group.

2. The method according to claim 1, characterized in that, The first read / write test result is either a first test result identifier indicating read / write failure, or a second test result identifier indicating read / write success; Based on the first read / write test results of multiple command timing tests in each group of chip tests, the actual tRTP corresponding to each group of chip tests is determined, including: generating a first shmoo test graph based on the first read / write test results of multiple command timing tests in at least one group of chip tests, wherein the first shmoo test graph includes at least one image sequence, each image sequence corresponds to a group of chip tests, each image sequence includes multiple image units, each image unit corresponds to one command timing test, and each image unit has a visual identifier, the visual identifier being either the first test result identifier or the second test result identifier; Based on the first shmoo test chart, select the first benchmark adjustment duration that meets the first preset selection conditions; determine the first benchmark adjustment duration as the actual tRTP corresponding to the chip test of this group.

3. The method according to claim 2, characterized in that, The first read / write test result is either a first test result identifier indicating read / write failure, or a second test result identifier indicating read / write success; the first preset selection condition is: The maximum value of the duration to be adjusted for each of the command timing tests corresponding to the first test result identifier; or, The minimum value among the durations to be adjusted for each of the command timing tests corresponding to the second test result identifier.

4. The method according to claim 1, characterized in that, Each command timing test also includes the following steps: Second test write data and third test write data are written in the third target row and the fourth target row respectively. The second test write data and the third test write data are different. The third target row and the fourth target row belong to the same memory bank of the chip under test. A third activation command and a second automatic precharge read command are sequentially sent to the chip under test to perform a read operation on the third target row; Starting from the second automatic precharge read command and after the adjustment time corresponding to the command timing test, the fourth activation command and the second read command are sent to the chip under test in sequence to obtain the second test read data of the fourth target row. Based on the second test read data and the third test write data, the second read and write test result of the fourth target row in this command timing test is determined. The second read and write test result is a third test result identifier that indicates read and write failure, or a fourth test result identifier that indicates read and write success. Furthermore, the method further includes: Based on the second read / write test results of each of the multiple command timing tests in each group of chip tests, a first delay value corresponding to each group of chip tests is determined, wherein the first delay value represents the critical value of the adjustment duration for the second read / write test result to change from the third test result identifier to the fourth test result identifier; Based on the actual tRTP corresponding to each of the at least one set of chip tests and the first delay value, the precharge effective time tRP of the chip under test is determined.

5. The method according to claim 4, characterized in that, Based on the actual tRTP corresponding to each of the at least one set of chip tests and the first delay value, the precharge effective time tRP of the chip under test is determined, including: Based on the actual tRTP corresponding to each of the at least one set of chips, a benchmark tRTP is determined. Based on the first delay value corresponding to each of the at least one group of chips, a reference delay value is determined; The tRP is determined based on the difference between the reference delay value and the reference tRTP.

6. The method according to claim 4, characterized in that, Based on the results of the second read / write tests of each of the multiple command timing tests in each group of chip tests, the first latency value corresponding to each group of chip tests is determined, including: Based on the second read / write test results of each of the multiple command timing tests in the at least one set of chip tests, a second shmoo test graph is generated. The second shmoo test graph includes at least one image sequence, each image sequence corresponds to the set of chip tests, each image sequence includes multiple image units, each image unit corresponds to one command timing test, and each image unit has a visual identifier, which is either the third test result identifier or the fourth test result identifier. Based on the second Shmoo test chart, a second baseline adjustment duration that meets the second preset selection conditions is selected; The second benchmark adjustment duration is determined as the first latency value corresponding to the chip test of this group.

7. The method according to claim 1, characterized in that, The method further includes: Obtain the preset tRTP for each of the at least one group of chip tests. The preset tRTP is set by writing the predefined code corresponding to the chip test in the predefined code bit in the mode register. The predefined code is specified by a preset standard protocol. If the preset tRTP of each of the at least one group of chips and the actual tRTP of each of the at least one group of chips meet the preset consistency conditions, it is determined that the automatic pre-charge behavior of the chip under test meets the design expectations.

8. The method according to claim 7, characterized in that, Before acquiring the preset tRTP for each of the at least one set of chips for testing, the method further includes: In each group of chip tests, the predefined code corresponding to the chip test group is written into the predefined code bit of the mode register of the chip under test, so as to set the tRTP of the chip under test to the preset tRTP corresponding to the chip test group.

9. The method according to claim 4, characterized in that, The method further includes: In each group of chip tests, among the first read / write test results of the multiple command timing tests, it is determined whether there are any abnormal read / write test results; if there are abnormal read / write test results, it is determined that the automatic pre-charge behavior of the chip under test is abnormal; and / or, In each group of chip tests, among the second read / write test results of the multiple command timing tests, it is determined whether there are any abnormal read / write test results; if there are abnormal read / write test results, it is determined that the automatic pre-charge behavior of the chip under test is abnormal.

Images