An array substrate, a display panel, and an electronic device

Abstract

The present disclosure provides an array substrate, a display panel, and an electronic device, including: there are multiple bent portions on the data line, the bent portions are located in the second interval region and are spaced from the first interval region, the first interval region is the interval region between two adjacent main pixel electrodes in the second direction, the second interval region is the interval region between two adjacent sub-pixel electrodes in the second direction, the width of the first interval region in the second direction is greater than the width of the second interval region in the second direction; there are also provided a plurality of first common electrode traces extending along the first direction, corresponding to the data lines and insulated from the data lines, the first common electrode traces are located in the second interval region and are spaced from the first interval region. Through the design of the bent portions and the first common electrode traces, the present disclosure effectively increases the width of the sub-pixel electrodes in the second direction on the basis of ensuring the improvement effect on crosstalk, enabling it to have a larger light-emitting area and achieving an increase in transmittance.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate, a display panel, and an electronic device. Background Art

[0002] The name UV2A comes from the combination of ultraviolet (UV) and the vertical alignment (VA) of liquid crystal molecules in a liquid crystal panel, and refers to a photo-alignment technology. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance. The key to UV2A is to use a special polymer material as the alignment film to precisely control the inclination of liquid crystal molecules along the ultraviolet light direction, with the precision unit being picometers. The advantage of UV2A is that the liquid crystal panel has a simple structure without protrusions or slits. Combined with the 8-domain design of the pixel region, it is more conducive to improving the lateral viewing color shift performance of the display panel.

[0003] However, after adopting the 8-domain design for pixels, although the color shift of the panel is optimized, the formation of a swastika-shaped dark pattern within the pixel aperture will cause a reduction in transmittance. Taking an 85-inch 4K product as an example, the transmittance of the panel is lost by 15% after adopting the 8-domain design. Therefore, how to improve the transmittance of the display panel on the basis of improving the poor color shift of the display panel is the main goal of the existing UV2A mode. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide an array substrate, a display panel, and an electronic device to solve the problem that the transmittance of a large-size high-resolution liquid crystal display panel decreases after the 8-domain design in the prior art.

[0005] Embodiments of the present disclosure adopt the following technical solutions: An array substrate includes: pixel regions arranged in an array, at least one of the pixel regions includes a main pixel region and a sub-pixel region arranged along a first direction, and there are spacer regions between adjacent pixel regions and between the main pixel region and the sub-pixel region; at least a main pixel electrode is provided at the position of the main pixel region, and at least a sub-pixel electrode is provided at the position of the sub-pixel region, and at least a plurality of data lines extending along the first direction and a plurality of gate lines extending along a second direction are provided at the position of the spacer region, and the first direction and the second direction intersect in the plane where the array substrate is located; wherein, there are a plurality of bent portions on at least one of the data lines, the bent portions are located in a second spacer region and are spaced from a first spacer region, the first spacer region is the spacer region between two adjacent main pixel electrodes in the second direction, the second spacer region is the spacer region between two adjacent sub-pixel electrodes in the second direction, and the width of the first spacer region in the second direction is greater than the width of the second spacer region in the second direction; a plurality of first common electrode traces extending along the first direction are further provided in the spacer region, wherein, the first common electrode traces are arranged corresponding to the data lines and are insulated from the data lines, the first common electrode traces are located in the second spacer region and are spaced from the first spacer region.

[0006] In some embodiments, the projection of the first common electrode trace on the array substrate and the projection of the data line on the array substrate are spaced from each other.

[0007] In some embodiments, the first common electrode trace is provided on the same layer as the gate line, and the first common electrode trace is insulated from the gate line.

[0008] In some embodiments, the bent portion at least includes a first portion, a second portion and a third portion connected in sequence, the first portion and the third portion extend along the first direction, the second portion extends along the second direction, the positive projection of the first portion on the array substrate overlaps with the positive projection of a first sub-pixel electrode on the array substrate, the positive projection of the third portion on the array substrate overlaps with the positive projection of a second sub-pixel electrode on the array substrate, and the first sub-pixel electrode and the second sub-pixel electrode are two adjacent sub-pixel electrodes in the second direction.

[0009] In some embodiments, the first common electrode trace includes a first sub-trace and a second sub-trace. The positive projection of the first sub-trace on the array substrate is located between the first main pixel electrode and the data line, and the positive projection of the second sub-trace on the array substrate is located between the second main pixel electrode and the data line. The first main pixel electrode and the second main pixel electrode are two adjacent main pixel electrodes in the second direction.

[0010] In some embodiments, a plurality of second common electrode traces extending along the first direction are further provided in the spacer region. The second common electrode traces are provided on the same layer as the main pixel electrodes and are insulated from the main pixel electrodes. The second common electrode trace at least includes a fourth portion, and the fourth portion is located in the first spacer region.

[0011] In some embodiments, the second common electrode trace further includes a fifth portion, and the fifth portion is located in the second spacer region. The width of the positive projection of the fourth portion on the array substrate in the second direction is greater than the width of the positive projection of the fifth portion on the array substrate in the second direction.

[0012] In some embodiments, the first common electrode trace and the second common electrode trace are connected by a via hole.

[0013] Embodiments of the present disclosure further provide a display panel, at least including: the array substrate as described above; and a packaging substrate disposed opposite to the array substrate.

[0014] In some embodiments, a black matrix layer is provided at a position of the packaging substrate corresponding to the spacer region. The black matrix layer at least includes a first black matrix and a second black matrix. Among them, the positive projection of the first black matrix on the array substrate overlaps with the positive projection of the first spacer region on the array substrate, and the positive projection of the second black matrix on the array substrate overlaps with the positive projection of the second spacer region on the array substrate.

[0015] In some embodiments, when the folded portion of the data line provided in the spacer region of the array substrate includes a first portion, a second portion, and a third portion connected in sequence, the positive projection of the second black matrix on the array substrate overlaps with the positive projection of the second portion on the array substrate, and the positive projection of the second black matrix on the array substrate is spaced apart from the positive projections of the first portion and the third portion on the array substrate.

[0016] Embodiments of the present disclosure further provide an electronic device, at least including the display panel as described above.

[0017] The beneficial effects of the embodiments of the present disclosure are as follows: By arranging a first common electrode trace in the first spacer region corresponding to the main pixel electrode to pull the electric field formed by the coupling between the data line and the pixel electrode, the coupling between the data line and the main pixel electrode is reduced, and the occurrence of crosstalk is avoided; in the second spacer region corresponding to the sub-pixel electrodes, the design of the first common trace is not carried out, and the data line located in the second spacer region is designed with a broken line to block part of the dark pattern, which can effectively increase the width of the sub-pixel electrode in the second direction, enabling it to have a larger light-emitting area and realizing an improvement in the transmittance of the pixel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 is a top view schematic diagram of the array substrate in the first embodiment of the present disclosure;

[0020] Figure 2 is Figure 1 a schematic diagram of the hierarchical structure corresponding to the dashed line PP' in

[0021] Figure 3 is Figure 1 a schematic diagram of the hierarchical structure corresponding to the dashed line QQ' in

[0022] Figure 4 is another top view schematic diagram of the array substrate in the first embodiment of the present disclosure;

[0023] Figure 5 is a schematic diagram of the hierarchical design of the array substrate in the first embodiment of the present disclosure;

[0024] Figure 6 is Figure 5 an enlarged schematic diagram of the dashed line position in

[0025] Figure 7 is a top view schematic diagram of the display panel in the second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Reference is made herein to the accompanying drawings to describe the various aspects and features of the present disclosure.

[0027] It should be understood that various modifications can be made to the embodiments claimed herein. Therefore, the above description should not be construed as limiting, but merely as exemplary of the embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the present disclosure.

[0028] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0029] These and other characteristics of the present disclosure will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0030] It should also be understood that although the present disclosure has been described with reference to certain specific examples, those skilled in the art will be able to realize many other equivalent forms of the present disclosure that have the features of the claims and are therefore within the scope of protection defined thereby.

[0031] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0032] Specific embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant detail. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but rather serve merely as a basis and representative basis for teaching those skilled in the art to variously employ the present disclosure with substantially any suitable detailed structure.

[0033] This description may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," each of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0034] The name UV2A comes from the multiplication of ultraviolet (UV) light and the vertical alignment (VA) method of liquid crystals in liquid crystal panels. It refers to a photo-alignment technology that precisely manipulates the alignment of liquid crystal molecules through ultraviolet light, significantly improving light transmittance. The key to UV2A is the use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light, with an accuracy of picometers. The advantage of UV2A lies in the simple structure of the LCD panel without protrusions or slits. Combined with the 8-domain design of the pixel area, this further helps improve the side-view color skew performance of the display panel.

[0035] However, after adopting the 8-domain design for the pixels, although the color shift of the panel is optimized, the swastika-shaped dark lines formed within the pixel arms will cause a reduction in transmittance. At the same time, during the use of the display panel, crosstalk defects often occur. That is, due to the coupling between the data line and the pixel electrode, when a large jump occurs in the signal applied to the data line, the voltage of the pixel electrode is pulled, resulting in linear display defects in the display screen. To solve the crosstalk problem, the commonly used method at present is to design common electrode traces on both sides of the data line to avoid the coupling between the data line and the pixel electrode. However, the design of the additional common electrode traces will cause a reduction in the area of the pixel electrode region, resulting in a reduction in the transmittance of the liquid crystal display panel. Taking an 85-inch 4K product as an example, after adopting the 8-domain design, the transmittance of the panel is lost by 15%. Therefore, how to improve the transmittance of the display panel on the basis of improving the color shift defect of the display panel is the main goal of the existing UV2A mode.

[0036] To solve the above problems, the first embodiment of the present disclosure provides an array substrate, which mainly refers to the substrate in a liquid crystal display panel for setting levels such as pixel regions and driving circuits. Specifically, Figure 1 shows a top view schematic diagram of the array substrate, which is mainly provided with a plurality of pixel regions arranged in an array. Each pixel region is divided into a main pixel region A1 and a sub-pixel region A2 arranged along the first direction. There are spacer regions B between adjacent pixel regions and between the main pixel region A1 and the sub-pixel region A2 within the same pixel region. The spacer region can be further divided into a first spacer region B1 between adjacent main pixel regions, a second spacer region B2 between adjacent sub-pixel regions, and a third spacer region B3 between the main pixel region and the sub-pixel region within the same pixel region (indicated by a dashed box in Figure 1 ). The setting of the above main and sub-pixel regions combined with the UV2A technology can realize the formation of an 8-domain liquid crystal display panel. It should be noted that for an array substrate, the spacer region should actually be a network region formed in combination with the division of the pixel region. For the network-shaped spacer region, in this embodiment, the overlapping part between the spacer region part extending along the first direction and the spacer region part extending along the second direction is defined as the third spacer region B3, that is, the third spacer region B3 can be a spacer region that penetrates the array substrate along the second direction. In addition, structures such as thin film transistors (TFTs) for driving the main pixel region A1 and the sub-pixel region A2 to emit light are all arranged in the third spacer region B3.

[0037] Figure 2 shows Figure 1 the hierarchical structure schematic diagram corresponding to the dashed line PP' in Figure 3 is Figure 1 the hierarchical structure schematic diagram corresponding to the dashed line QQ' in Figure 2 andFigure 3 As shown, a main pixel electrode 110 is disposed at a position corresponding to the main pixel region A1 on the array substrate 10, and a sub-pixel electrode 120 is disposed at a position corresponding to the sub-pixel region A2. In the interval region, at least a plurality of data lines 40 extending in the first direction and a plurality of gate lines 50 extending in the second direction are provided. Among them, the first direction and the second direction are perpendicular to each other in the plane where the array substrate 10 is located. In this embodiment, the first direction mainly refers to Figure 1 the vertical direction X in Figure 1 and the second direction is Figures 1 to 3 the horizontal direction Y in Figure 2 and Figure 3 is not shown). They are all located in different hierarchical structures. Their corresponding hierarchical positions and setting methods can be carried out according to a conventional liquid crystal display panel, and will not be described in detail in this embodiment. In addition, an insulating layer 200 is provided between the above-mentioned layers to prevent crosstalk between different signals.

[0038] Furthermore, as shown in Figure 1As shown, there are multiple straight portions 41 and multiple folded portions 42 on at least one data line 40. The straight portions 41 are mainly correspondingly arranged in the first interval region B1, and the folded portions 42 are located in the second interval region B2 and are spaced from the first interval region B1, that is, the folded portions 42 are mainly correspondingly arranged for the sub-pixel regions. Specifically, the folded portion 42 at least includes a first portion 421, a second portion 422, and a third portion 423 that are sequentially connected. Among them, the first portion 421 and the third portion 423 extend along the first direction, and the second portion 422 extends along the second direction, so that the folded portion 42 forms a Z-shaped structure. When actually arranged, the first portion 421 and the third portion 423 extending along the first direction will overlap with the sub-pixel electrodes on both sides of the data line 40. For example, the orthographic projection of the first portion 421 on the array substrate 10 overlaps with the orthographic projection of the first sub-pixel electrode 121 on the array substrate 10, and the orthographic projection of the third portion 423 on the array substrate 10 overlaps with the orthographic projection of the second sub-pixel electrode 122 on the array substrate 10. The first sub-pixel electrode 121 and the second sub-pixel electrode 122 are two adjacent sub-pixel electrodes in the second direction. By designing the data line to be folded, the dark lines generated in the sub-pixel regions can be blocked, the overall proportion of the light-emitting region in the pixel region can be increased, and the purpose of improving the transmittance can be achieved. At the same time, the sub-pixel electrodes require a relatively high driving voltage during actual driving. Even if there are overlapping portions between the folded portions of the data line and the sub-pixel electrodes, the voltage coupled between the folded portions and the sub-pixel electrodes will not drive the sub-pixel electrodes to emit light or affect their lighting effect. If the main pixel electrodes are correspondingly provided with folded portions, the crosstalk phenomenon may be more serious. Therefore, in this embodiment, by only providing folded portions in the second interval region, the purpose of avoiding crosstalk and improving the transmittance can be achieved.

[0039] As Figures 1 to 3 shown, in the interval region, there are also multiple first common electrode traces 60 extending along the first direction (corresponding to Figures 1 to 3 the shaded part in), among which, the first common electrode traces 60 are correspondingly arranged for the data lines 40, that is, in the interval region where the data lines 40 are provided, the first common electrode traces 60 are correspondingly arranged, and the data lines 40 and the first common electrode traces 60 are insulated from each other, and there is no overlapping region between their projections on the array substrate 10. Substantially, they are located between different layers on the array substrate 10. Specifically, the first common electrode traces 60 are located in the second interval region B2 and are spaced from the first interval region B1, that is, the first common electrode traces 60 are only provided in the interval region before the main pixel electrodes 110, and the first common electrode traces 60 are not provided in the interval region between the sub-pixel electrodes 120.

[0040] In this embodiment, the first common electrode trace 60 corresponding to the main pixel region can effectively pull the electric field formed by the coupling between the data line 40 and the main pixel electrode 110, so that the voltage jump occurring on the data line 40 is coupled to the first common electrode trace 60, avoiding the influence of the voltage jump of the data line 40 on the actual applied voltage on the main pixel electrode 110 and causing crosstalk defects. For the sub-pixel region, it requires a relatively high voltage for driving when it is lit, and the pulling of the data line 40 on the sub-pixel electrode 120 during the jump results in an insufficient voltage increase to drive the liquid crystal in the sub-pixel region to rotate. Therefore, there is no need to set the first common electrode trace 60 in the corresponding interval region for the sub-pixel region. Then, the width of the sub-pixel electrode 120 in the second direction can be set wider during actual setting, that is, the width of the first interval region B1 in the second direction is greater than the width of the second interval region B2 in the second direction. The sub-pixel region with the expanded width is equivalent to expanding the area of the light-emitting region within a single pixel region, thereby improving the overall transmittance of the liquid crystal display panel.

[0041] In some embodiments, the first common electrode trace 60 can be set on the same layer as the gate line 50 and fabricated using the same metal material as the gate line 50, as long as insulation between the first common electrode trace 60 and the gate line 50 is ensured. At this time, no additional layer needs to be set, and the electric field formed between the first common electrode trace 60 and the data line 40 can be used to weaken the coupling effect of the data line 40 on the pixel electrode without increasing the thickness of the display panel.

[0042] In some embodiments, the first common electrode trace 60 includes a first sub-trace 61 and a second sub-trace 62. Among them, the projection of the first sub-trace 61 on the array substrate 10 is located on one side of the data line 40 in the second direction, and the projection of the second sub-trace 62 on the array substrate 10 is located on the other side of the data line 40 in the second direction. As Figure 1 and Figure 2 shown, the orthographic projection of the first sub-trace 61 on the array substrate 10 is located between the first main pixel electrode 111 and the data line 40, and the orthographic projection of the second sub-trace 62 on the array substrate 10 is located between the second main pixel electrode 112 and the data line 40. The first main pixel electrode 111 and the second main pixel electrode 112 are two adjacent main pixel electrodes in the second direction. By designing the first sub-trace 61 and the second sub-trace 62 on both sides of a data line 40, the pulling effect of the first common electrode trace on the electric field of the data line 40 can be further improved, ensuring an effective improvement in crosstalk defects.

[0043] In some embodiments, as Figures 1 to 3As shown, at the position corresponding to the spacer region on the array substrate 10, a plurality of second common electrode traces 70 extending in the first direction are further provided. The second common electrode traces 70 are provided on the same layer as the main pixel electrode 110 and are insulated from the main pixel electrode 110. Specifically, the second common electrode trace at least includes a fourth portion 71 located within the first spacer region B1. The orthographic projection of the fourth portion 71 on the array substrate 10 completely covers the corresponding data line 40 therebelow. When the voltage of the data line 40 jumps, it is coupled to the data line, avoiding the coupling between the data line and the main pixel electrode. Therefore, the crosstalk prevention effect of the array substrate 10 can be further improved.

[0044] Figure 4 FIG. shows a top view schematic diagram of another array substrate, and the difference between it and Figure 1 is that the second common electrode trace 70 further includes a fifth portion 72 located within the second spacer region B2. And in cooperation with the difference in the widths of the main and sub-pixel electrodes, the width of the orthographic projection of the fourth portion 71 on the array substrate in the second direction is greater than the width of the orthographic projection of the fifth portion 72 on the array substrate in the second direction. Due to the setting of the folded portion 42 within the second spacer region B2, there is only an overlapping region between the orthographic projection of the fifth portion 72 on the array substrate and the orthographic projection of the second portion 422 on the array substrate.

[0045] In actual implementation, both the first common electrode trace 60 and the second common electrode trace 70 can be connected to a rated voltage to ensure their stability. Further, in cooperation with the surface electrode provided on the encapsulation substrate on the opposite side of the array substrate, a stable electric field can be formed between the second common electrode trace 70 and the opposite surface electrode. And the liquid crystal molecules located within this stable electric field will not deflect, which is equivalent to forming a stable non-light-emitting region between adjacent light-emitting regions. Therefore, in the case of setting the second common electrode trace Figure 4 as shown in 70, the implementation of the black matrix layer can be not designed, achieving the purpose of reducing the overall thickness of the display panel.

[0046] In some embodiments, the width of the fourth portion 71 can cover the spacer region between adjacent main pixel regions as much as possible, that is, the projection of the fourth portion 71 on the array substrate covers the projections of the first sub-trace 61, the second sub-trace 62, and the data line 40 on the array substrate at the same time. While pulling the data line 40, it can also fix the liquid crystal molecules at the corresponding position of the spacer region, avoiding defects such as light leakage at the pixel edge.

[0047] Figure 5 is a hierarchical design schematic diagram of the array substrate in this embodiment, Figure 6 is Figure 5 a partial enlarged view of the position of the dashed line in. As Figure 5It can be seen that in actual design, both the first common electrode trace 60 and the second common electrode trace 70 will extend to a certain extent into the third spacer region B3. They can be electrically connected through a via 80 and can be connected to a common signal within the panel at the edge of the display panel or other positions, such as a signal with a stable voltage value like the Vcom signal, to ensure the stability of the voltages applied on the first common electrode trace 60 and the second common electrode trace 70, and achieve a good anti-crosstalk effect.

[0048] In addition, Figure 5 also shows the gate line 50 and TFT-related structures. For example, the data line 40 is actually connected to the source metal SD1 in the same layer of the TFT, and the drain metals of the TFT are SD2 and SD3. SD2 is connected to the main pixel electrode 110, and SD3 is connected to the sub-pixel electrode 120. During driving, the TFT is turned on under the drive of the gate line 50, and the drive voltage applied on the data line 40 is transmitted from SD1 to SD2 and SD3, and then transmitted to the main pixel electrode 110 and the sub-pixel electrode 120 to drive the liquid crystal molecules in the corresponding area.

[0049] In this embodiment, by setting a first common electrode trace in the first spacer region corresponding to the main pixel electrode to pull the electric field formed by the coupling between the data line and the pixel electrode, the coupling between the data line and the main pixel electrode is reduced, and the occurrence of crosstalk is avoided; in the second spacer region corresponding to the sub-pixel electrodes, the design of the first common trace is not carried out, and the data line located in the second spacer region is designed with a broken line to block part of the dark pattern, which can effectively increase the width of the sub-pixel electrode in the second direction, making it have a larger light-emitting area and realizing the improvement of the transmittance of the pixel region.

[0050] When evaluating the characteristic performance of pixels in a display panel in the field, usually the following three parameters are used for description, namely, the crosstalk brightness percentage, the transmittance, and the color shift (CR80 / 20) performance. Taking an 8-domain 4K liquid crystal display panel as an example, the characteristic performance of the current traditional pixel design is: the crosstalk brightness percentage is 1.5%, the transmittance is 100%, and the color shift (CR80 / 20) performance is 40%; while the characteristic performance corresponding to the pixel design shown in Figure 1 this embodiment of the present disclosure is: the crosstalk brightness percentage is 1.5%, the transmittance is 108%, and the color shift (CR80 / 20) performance is 43%. From the above simulation results, it can be seen that the liquid crystal display panel provided by this embodiment of the present disclosure can significantly improve the transmittance performance of the panel while ensuring good crosstalk improvement, and also has a certain degree of improvement effect on the color shift phenomenon.

[0051] A second embodiment of the present disclosure provides a display panel, such as a liquid crystal display panel formed based on the UV2A technology. The display panel at least includes the array substrate provided in the first embodiment of the present disclosure, and a packaging substrate disposed opposite to the array substrate. As Figure 7 shown, the hierarchical structure setting performed on the array substrate has been described in detail in the first embodiment and will not be repeated here. On the side of the packaging substrate close to the array substrate, a black matrix layer 90 (represented by a thick solid line) is usually provided corresponding to the spacer region to implement the division of the pixel region, and the light incident into the spacer region is shielded and absorbed to avoid display defects such as light leakage. Corresponding to Figure 7 the pixel design, the black matrix layer 90 at least includes a first black matrix 91 and a second black matrix 92. The first black matrix 91 is provided corresponding to the first spacer region B1, and its orthographic projection on the array substrate coincides with the first spacer region B1. The second black matrix 92 is designed corresponding to the second spacer region B, and its orthographic projection on the array substrate overlaps with the second spacer region B1.

[0052] Specifically, the orthographic projection of the first black matrix 91 on the array substrate covers the projection of the first common electrode trace 60 on the array substrate. When the first common electrode trace 60 includes a first sub-trace 61 and a second sub-trace 62, it is necessary to cover the projections of both the first sub-trace 61 and the second sub-trace 62 on the array substrate at the same time. The orthographic projection of the second black matrix 92 on the array substrate only overlaps with the orthographic projection of a partial region of the folded portion. For example, when the folded portion includes a first portion 421, a second portion 422, and a third portion 423 connected in sequence, the orthographic projection of the second black matrix 92 on the array substrate overlaps with the orthographic projection of the second portion 422 on the array substrate, and is spaced from the orthographic projections of the first portion 421 and the third portion 423 on the array substrate. Corresponding to the widened design of the sub-pixel electrode 120, the width of the orthographic projection of the first black matrix 91 on the array substrate in the second direction is greater than the width of the orthographic projection of the second black matrix 92 on the array substrate in the second direction, that is, the spacer regions between the sub-pixel regions in the same row are narrower, corresponding to an increase in the overall transmittance of the display panel.

[0053] It should be noted that Figure 7 the black matrix layer 90 extending in the second direction is not shown in

[0054] The third embodiment of the present disclosure provides an electronic device, which is mainly a device such as a television or a display screen with a large size and high resolution. The electronic device should at least include the display panel provided in the second embodiment of the present disclosure. By setting a first common electrode trace in the first interval region corresponding to the main pixel electrode to pull the electric field formed by the coupling between the data line and the pixel electrode, the coupling between the data line and the main pixel electrode is reduced, and the occurrence of crosstalk is avoided; in the second interval region corresponding to the sub-pixel electrodes, the design of the first common trace is not carried out, and the data line located in the second interval region is designed to be folded to block part of the dark pattern, which can effectively increase the width of the sub-pixel electrode in the second direction, making it have a larger light-emitting area, realizing the improvement of the transmittance of the pixel region, and enabling the electronic device to have a better display effect.

[0055] The above has described multiple embodiments of the present disclosure in detail, but the present disclosure is not limited to these specific embodiments. Based on the concept of the present disclosure, those skilled in the art can make various variations and modifications to the embodiments, and these variations and modifications should all fall within the scope required to be protected by the present disclosure.

Claims

1. An array substrate, characterized in that, Comprising: A pixel region arranged in an array, at least one of the pixel regions including a main pixel region and a sub-pixel region arranged along a first direction, and there being a spacing region between adjacent pixel regions and between the main pixel region and the sub-pixel region; At least a main pixel electrode is provided at the position of the main pixel region, and at least a sub-pixel electrode is provided at the position of the sub-pixel region. At least a plurality of data lines extending along the first direction and a plurality of gate lines extending along a second direction are provided at the position of the spacing region. The first direction and the second direction intersect in the plane of the array substrate. Among them, at least one of the data lines has a plurality of bent portions, the bent portions are located in a second spacing region and are spaced from a first spacing region. The first spacing region is the spacing region between two adjacent main pixel electrodes in the second direction, and the second spacing region is the spacing region between two adjacent sub-pixel electrodes in the second direction. The width of the first spacing region in the second direction is greater than the width of the second spacing region in the second direction; A plurality of first common electrode traces extending along the first direction are further provided in the spacing region. Among them, the first common electrode traces are arranged corresponding to the data lines and are insulated from the data lines. The first common electrode traces are located in the first spacing region and are spaced from the second spacing region; The projection of the first common electrode trace on the array substrate and the projection of the data line on the array substrate are spaced from each other.

2. The array substrate according to claim 1, characterized in that The first common electrode trace is provided on the same layer as the gate line, and the first common electrode trace is insulated from the gate line.

3. The array substrate according to claim 1, wherein The bent portion at least includes a first portion, a second portion and a third portion connected in sequence. The first portion and the third portion extend along the first direction, the second portion extends along the second direction. The positive projection of the first portion on the array substrate overlaps with the positive projection of a first sub-pixel electrode on the array substrate, and the positive projection of the third portion on the array substrate overlaps with the positive projection of a second sub-pixel electrode on the array substrate. The first sub-pixel electrode and the second sub-pixel electrode are two adjacent sub-pixel electrodes in the second direction.

4. The array substrate according to claim 1, wherein The first common electrode trace includes a first sub-trace and a second sub-trace. The positive projection of the first sub-trace on the array substrate is located between a first main pixel electrode and the data line, and the positive projection of the second sub-trace on the array substrate is located between a second main pixel electrode and the data line. The first main pixel electrode and the second main pixel electrode are two adjacent main pixel electrodes in the second direction.

5. The array substrate according to any one of claims 1 to 4, characterized in that, A plurality of second common electrode traces extending along the first direction are further provided in the spacing region. The second common electrode traces are provided on the same layer as the main pixel electrode and are insulated from the main pixel electrode. The second common electrode trace at least includes a fourth portion, and the fourth portion is located in the first spacing region.

6. The array substrate according to claim 5, wherein The second common electrode trace further includes a fifth portion located within the second spacer region, and the width of the orthographic projection of the fourth portion on the array substrate in the second direction is greater than the width of the orthographic projection of the fifth portion on the array substrate in the second direction.

7. The array substrate according to claim 5, wherein The first common electrode trace and the second common electrode trace are connected by a via hole.

8. A display panel, characterized in that, At least including: The array substrate according to any one of claims 1 to 7; A packaging substrate disposed opposite to the array substrate.

9. The display panel according to claim 8, wherein, A black matrix layer is provided at a position on the packaging substrate corresponding to the spacer region, and the black matrix layer at least includes a first black matrix and a second black matrix; wherein, the orthographic projection of the first black matrix on the array substrate overlaps with the orthographic projection of the first spacer region on the array substrate, and the orthographic projection of the second black matrix on the array substrate overlaps with the orthographic projection of the second spacer region on the array substrate.

10. The display panel according to claim 9, wherein, When the bent portion of the data line provided in the spacer region of the array substrate includes a first portion, a second portion, and a third portion connected in sequence, the orthographic projection of the second black matrix on the array substrate overlaps with the orthographic projection of the second portion on the array substrate, and the orthographic projection of the second black matrix on the array substrate is spaced apart from the orthographic projections of the first portion and the third portion on the array substrate.

11. An electronic device, characterized in that, At least including the display panel according to any one of claims 8 to 10.

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