A silicon carbide mosfet device and method of manufacture

Abstract

The application relates to the field of semiconductor technology, in particular to a silicon carbide MOSFET device and a manufacturing method thereof. The device comprises a silicon carbide epitaxial layer provided with a doped well region, a same-pattern gate oxide layer and a gate layer which are sequentially arranged on the silicon carbide epitaxial layer, a self-aligned interlayer insulating layer covering the gate oxide layer and the gate layer, and a first conductive layer; the doped well region is provided with a first contact region and a plurality of source junctions, and a surface active region is formed between the source junctions and the silicon carbide epitaxial layer; the silicon carbide epitaxial layer is provided with a second contact region; the gate oxide layer covers the active region, and a gate gap is formed between two adjacent gate layers; the self-aligned interlayer insulating layer has a modified opening corresponding to the first contact region and a gate gap corresponding to the second contact region; based on the modified opening, the first conductive layer covers the first contact region and part of the exposed source junctions, and based on the reduced gate gap, the first conductive layer covers the second contact region.

Description

[0001] The priority basis of this application includes: the invention application with application number CN202211731690.9, application date 2022.12.30, entitled "A silicon carbide MOSFET device and manufacturing method". Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device and a method for manufacturing the same. Background Technology

[0003] Silicon carbide is a promising semiconductor material, and a global industrial chain encompassing materials, devices, and applications has already been established. Silicon carbide possesses a wide bandgap, high thermal conductivity, high breakdown strength, high saturated electron drift velocity, strong physicochemical stability, strong radiation resistance, and excellent electrical and thermal properties, making it an ideal semiconductor material for applications requiring high temperature, high frequency, radiation resistance, and high power.

[0004] Metal-oxide-semiconductor field-effect transistors (MOSFETs) made of silicon carbide are widely used in high-power device applications. Gate oxide reliability is one of the main factors affecting the performance of high-power MOSFETs. In related technologies, the insulating dielectric gate of silicon carbide MOSFETs is made of silicon dioxide obtained through thermal oxidation. However, there are numerous interface states between silicon dioxide and the silicon carbide substrate. This high density of interface states can negatively impact the performance and reliability of silicon carbide MOSFET devices.

[0005] Therefore, silicon carbide MOSFETs of related technologies suffer from excessively high gate oxide interface state density. Summary of the Invention

[0006] To reduce the density of gate oxide interface states in silicon carbide MOSFETs, this application provides a silicon carbide MOSFET device and a method for manufacturing the same.

[0007] This application provides a silicon carbide MOSFET device and its manufacturing method, which adopts the following technical solution: A silicon carbide MOSFET device, comprising: A silicon carbide epitaxial layer, wherein a doped well region is provided in the silicon carbide epitaxial layer and exposed on the upper surface of the silicon carbide epitaxial layer; wherein a plurality of source junctions are provided in the doped well region and exposed on the upper surface of the silicon carbide epitaxial layer; wherein the doped well region forms an active region on the upper surface between the source junctions and the silicon carbide epitaxial layer. A gate oxide layer and a gate layer with the same pattern are disposed on the silicon carbide epitaxial layer to cover the active region; the gate oxide layer covers the upper surface of the doped well region between the silicon carbide epitaxial layer and the source junction, and extends to cover part of the silicon carbide epitaxial layer and part of the source junction, forming a gate gap between two adjacent gate layers; A self-aligned interlayer insulating layer is formed on the silicon carbide epitaxial layer to cover the sides of the gate layer and the gate oxide layer and reduce the gate gap. The self-aligned interlayer insulating layer also extends to cover a portion of the source junction. The self-aligned interlayer insulating layer self-aligns to expose the doped well region between the source junction for forming a first contact region and the region of the silicon carbide epitaxial layer aligned with the gate gap for forming a second contact region. Based on the self-aligned interlayer insulating layer, the first contact region is formed within the doped well region, and the second contact region is formed within the silicon carbide epitaxial layer. The first contact region and the second contact region are exposed on the upper surface of the doped well region. The source junction connects the first contact region and the doped well region. The self-aligned interlayer insulating layer has a correction opening corresponding to the enlargement correction of the first contact region and a reduced gate gap, such that a portion of the upper surface of the source junction is exposed through the correction opening, and the upper surface of the second contact region is exposed through the reduced gate gap. A first conductive layer is formed on the silicon carbide epitaxial layer to cover the self-aligned insulating interlayer; based on the modified opening, the first conductive layer also covers the first contact area and the exposed portion of the source junction, and based on the reduced gate gap, the first conductive layer also covers the second contact area.

[0008] By adopting the above technical solution, a gate gap is formed between two adjacent doped well regions by the gate layer and the gate oxide layer, which reduces the size of the gate and gate oxide, reduces the gate oxide interface state density of the silicon carbide MOSFET device, reduces Qgd and reduces carrier transport scattering, and improves carrier mobility, thereby improving the performance and reliability of the silicon carbide MOSFET device; the interface between the second contact region and the silicon carbide epitaxial layer forms a PN junction, which improves the breakdown resistance and stability of the silicon carbide MOSFET device.

[0009] In one embodiment of this application, the reduced gate gap is smaller than the modified opening.

[0010] By adopting the above technical solution, it is helpful to correct the enlargement of the opening.

[0011] In one embodiment of this application, the silicon carbide MOSFET device further includes a silicon carbide substrate layer and a second conductive layer, wherein the silicon carbide epitaxial layer is disposed on the silicon carbide substrate layer and the second conductive layer is disposed on the back side of the silicon carbide substrate layer.

[0012] In one embodiment of this application, the silicon carbide epitaxial layer and the source junction have the same doping type, and the doping type of the doped well region, the first contact region and the second contact region are the same but different from the doping type of the source junction.

[0013] In one embodiment of this application, the doping concentration of the first contact region is greater than the doping concentration of the doped well region.

[0014] In one embodiment of this application, both the first contact region and the second contact region are doped with aluminum ions activated under an argon atmosphere, wherein the doping amount of aluminum ions is between 1e19cm⁻¹. -3 Up to 1e20cm -3 between.

[0015] In one embodiment of this application, the source junction is doped with nitrogen ions, wherein the nitrogen ion doping amount is between 1e19cm. -3 Up to 1e20cm -3 between.

[0016] In one embodiment of this application, the doped trap region is doped with aluminum ions, wherein the amount of aluminum ions doped is between 0.5e18cm. -3 up to 5e18cm -3 The implantation depth of aluminum ions ranges from 0.5 μm to 0.8 μm.

[0017] In one embodiment of this application, the gate oxide layer is a silicon oxide layer after thermal oxidation, and the thickness of the silicon oxide layer is between 30 nm and 200 nm; the gate layer is a conductive polysilicon layer, and the thickness of the conductive polysilicon layer is between 50 nm and 200 nm.

[0018] This application also provides a method for fabricating a silicon carbide MOSFET device, used to fabricate the silicon carbide MOSFET device described in any embodiment of this application, the fabrication method comprising: S1. Provide a silicon carbide epitaxial layer stacked on a silicon carbide substrate; S3. A doped well region is formed within the silicon carbide epitaxial layer, and the doped well region is exposed on the upper surface of the silicon carbide epitaxial layer. S5. A source junction is formed in the doped well region, the source junction is exposed on the upper surface of the doped well region, and the doped well region forms an active region on the upper surface between the source junction and the silicon carbide epitaxial layer. S71. A gate oxide layer and a gate layer with the same pattern are formed on the silicon carbide epitaxial layer to cover the active region; the gate oxide layer covers the doped well region on the upper surface between the silicon carbide epitaxial layer and the source junction, and extends to cover part of the silicon carbide epitaxial layer and part of the source junction, forming a gate gap between two adjacent gate layers. S72. A self-aligned insulating interlayer is formed on the silicon carbide epitaxial layer to completely cover the sides of the gate layer and the gate oxide layer and reduce the gate gap. The self-aligned insulating interlayer also extends to cover the source junction. The self-aligned insulating interlayer exposes the area of ​​the doped well region between the source junction for forming the first contact region and the area of ​​the silicon carbide epitaxial layer aligned with the gate gap for forming the second contact region. S81. Based on the self-aligned insulating interlayer, a first contact region is formed between the source junctions in the doped well region, and a second contact region is formed in the region of the silicon carbide epitaxial layer aligned with the gate gap. The first contact region is exposed on the upper surface of the silicon carbide epitaxial layer, the source junction is connected to the first contact region and the doped well region, and the second contact region is exposed on the upper surface of the silicon carbide epitaxial layer. S82. Enlarge the correction opening of the self-aligned insulating interlayer corresponding to the first contact area, so that a portion of the upper surface of the source junction is exposed through the correction opening of the self-aligned insulating interlayer. S9. A first conductive layer is formed on the silicon carbide epitaxial layer to cover the self-aligned insulating interlayer. Based on the modified opening, the first conductive layer also covers the first contact area and the exposed portion of the source junction. Based on the reduced gate gap, the first conductive layer also covers the second contact area.

[0019] By adopting the above technical solution, a gate gap is formed between two adjacent doped well regions by the gate layer and the gate oxide layer, which reduces the size of the gate and gate oxide, reduces the gate oxide interface state density of the silicon carbide MOSFET device, reduces Qgd and reduces carrier transport scattering, and improves carrier mobility, thereby improving the performance and reliability of the silicon carbide MOSFET device. While forming the first contact region, a second contact region is also formed. The second contact region forms a PN junction with the silicon carbide epitaxial layer, which improves the breakdown resistance and stability of the silicon carbide MOSFET device. The first contact area is prepared using a self-aligned process, which reduces one photolithography step, simplifies the process flow of silicon carbide MOSFET devices, and lowers the processing cost of silicon carbide MOSFET devices.

[0020] In summary, this application includes at least one of the following beneficial technical effects: 1. By forming a gate gap between two adjacent doped well regions, the size of the gate and gate oxide is reduced, the gate oxide interface state density of the silicon carbide MOSFET device is reduced, Qgd is reduced, and carrier transport scattering is reduced, thereby improving the carrier mobility and thus improving the performance and reliability of the silicon carbide MOSFET device. 2. By forming a second contact region within the silicon carbide epitaxial layer, and forming a PN junction at the interface between the second contact region and the silicon carbide epitaxial layer, the breakdown resistance and stability of the silicon carbide MOSFET device are improved. 3. By using a self-aligned process to simultaneously fabricate the first and second contact regions, one photolithography process is reduced, simplifying the process flow of silicon carbide MOSFET devices and lowering the processing cost of silicon carbide MOSFET devices. Attached Figure Description

[0021] Figure 1 This is a cross-sectional structural schematic diagram of the silicon carbide MOSFET device in the embodiments of this application; Figure 2 This is a schematic diagram of the device cross-sectional structure corresponding to step S1 in the process of manufacturing the silicon carbide MOSFET device in the embodiments of this application; Figure 3 This is a schematic diagram of the device cross-sectional structure corresponding to step S3 in the process of manufacturing the silicon carbide MOSFET device in the embodiments of this application; Figure 4 This is a schematic diagram of the device cross-sectional structure corresponding to step S5 in the process of manufacturing the silicon carbide MOSFET device in the embodiments of this application; Figure 5 This is a schematic diagram of the device cross-sectional structure corresponding to steps S71 and S72 in the process of manufacturing the silicon carbide MOSFET device in the embodiments of this application; Figure 6 This is a schematic diagram of the device cross-sectional structure corresponding to step S81 in the process of manufacturing the silicon carbide MOSFET device in the embodiments of this application; Figure 7 This is a schematic diagram of the device cross-sectional structure corresponding to step S82 in the process of manufacturing the silicon carbide MOSFET device in the embodiments of this application; Figure 8 This is a schematic diagram of the device cross-sectional structure corresponding to step S9 in the process of manufacturing the silicon carbide MOSFET device in the embodiments of this application; Figure 9 This is a schematic diagram of the device cross-sectional structure corresponding to step S10 in the process of manufacturing a silicon carbide MOSFET device in the embodiments of this application.

[0022] Explanation of reference numerals in the attached figures: 11. Silicon carbide substrate layer; 12. Silicon carbide epitaxial layer; 121. Doped well region; 122. First contact region; 123. Second contact region; 124. Source junction; 125. Active region; 13. Gate oxide layer; 14. Gate layer; 141. Gate gap; 15. Self-aligned insulating interlayer; 151. Corrected opening; 16. First conductive layer; 17. Second conductive layer; 181. First photomask layer; 182. Second photomask layer. Detailed Implementation

[0023] The following is in conjunction with the appendix Figure 1-9 This application will be described in further detail.

[0024] This application discloses a silicon carbide MOSFET device.

[0025] Reference Figure 1 The silicon carbide MOSFET device disclosed in this application includes: a silicon carbide substrate layer 11, a silicon carbide epitaxial layer 12, a doped well region 121, a first contact region 122, a second contact region 123, a source junction 124, a gate oxide layer 13, a gate layer 14, a self-aligned insulating interlayer layer 15, a first conductive layer 16, and a second conductive layer 17.

[0026] A silicon carbide epitaxial layer 12 is formed on and stacked with a silicon carbide substrate 11. The silicon carbide epitaxial layer 12 exhibits an N-type characteristic.

[0027] A doped well region 121 is formed within the silicon carbide epitaxial layer 12, located on the side of the silicon carbide epitaxial layer 12 opposite to the silicon carbide substrate layer 11, and exposed on the upper surface of the silicon carbide epitaxial layer 12. That is, the upper surface of the doped well region 121 is flush with the upper surface of the silicon carbide epitaxial layer 12, and the lower surface is located within the silicon carbide epitaxial layer 12. The doped well region 121 is doped with aluminum ions, wherein the aluminum ion doping concentration is between 0.5e18cm⁻¹. -3 up to 5e18cm -3 Between 0.5 μm and 0.8 μm, the implantation depth of aluminum ions is between 0.5 μm and 0.8 μm, that is, the depth of the doped well region 121 formed on the silicon carbide epitaxial layer 12 is between 0.5 μm and 0.8 μm, and the doped well region 121 exhibits a positive polarity P-type characteristic.

[0028] The source junction 124 is formed within the doped well region 121, located on the side of the doped well region 121 opposite to the silicon carbide substrate 11, and exposed on the upper surface of the silicon carbide epitaxial layer 12. That is, the upper surface of the doped well region 121 is flush with the upper surface of the silicon carbide epitaxial layer 12, and the lower surface is located within the doped well region 121. The source junction 124 is doped with nitrogen ions, wherein the nitrogen ion doping concentration is between 1e19cm⁻¹. -3 Up to 1e20cm -3Between them, the doped source junction 124 exhibits a negative polarity N+ type characteristic. The doped well region 121 forms an active region 125 on the upper surface between the source junction 124 and the silicon carbide epitaxial layer 12.

[0029] Gate oxide layer 13 and gate layer 14 are sequentially stacked and patterned on silicon carbide epitaxial layer 12 to cover active region 125. Gate oxide layer 13 covers the upper surface of doped well region 121 between silicon carbide epitaxial layer 12 and source junction 124, and extends to cover part of silicon carbide epitaxial layer 12 and part or all of source junction 124. Gate oxide layer and gate layer 14 form gate gap 141 between two adjacent doped well regions 121. Gate oxide layer 13 is a thermally oxidized silicon oxide layer with a thickness between 30 nm and 200 nm. Gate layer 14 is a conductive polysilicon layer with a thickness between 50 nm and 200 nm.

[0030] A self-aligned interlayer insulating layer 15 is formed on the silicon carbide epitaxial layer 12 to cover the sides of the gate layer 14 and the gate oxide layer 13 and reduce the gate gap 141. The self-aligned interlayer insulating layer 15 extends to cover a portion of the source junction 124 and a portion of the silicon carbide epitaxial layer 12. The self-aligned interlayer insulating layer (15) self-aligns to expose the doped well region 121 between the source junctions 124 for forming the first contact region 122 and the region of the gate gap 141 for forming the second contact region 123 of the silicon carbide epitaxial layer 12.

[0031] The first contact region 122 is formed within the doped well region 121 based on the self-aligned insulating interlayer 15, and the second contact region 123 is formed within the silicon carbide epitaxial layer 12 based on the self-aligned insulating interlayer 15. Both the first contact region 122 and the second contact region 123 are exposed on the upper surface of the doped well region 121. The upper surface of the first contact region 122 is flush with the upper surface of the doped well region 121, and its lower surface is located within the doped well region 121. The upper surface of the second contact region 123 is flush with the upper surface of the silicon carbide epitaxial layer 12, and its lower surface is located within the silicon carbide epitaxial layer 12. A source junction 124 connects the first contact region 122 and the doped well region 121. Both the first contact region 122 and the second contact region 123 are doped with aluminum ions activated under an argon atmosphere, wherein the aluminum ion doping amount is 1e19cm. -3 Up to 1e20cm -3 The first contact region 122 and the second contact region 123, after doping, both exhibit positive polarity P+ type characteristics. The depth of the second contact region 123 is the same as the depth of the first contact region 122, that is, the depth of the first contact region 122 embedded in the doped well region 121 and the depth of the second contact region 123 embedded in the silicon carbide epitaxial layer 12 are the same.

[0032] The self-aligned insulating interlayer 15 also has a correction opening 151 corresponding to the enlargement correction of the first contact area 122 and a reduced gate gap 141, so that part of the upper surface of the source junction 124 is exposed through the correction opening 151; the upper surface of the second contact area 123 is exposed through the reduced gate gap 141. The gate gap 141 before and after reduction is smaller than the correction opening 151.

[0033] A first conductive layer 16 is formed on the silicon carbide epitaxial layer 12 to cover the self-aligned insulating interlayer 15. Based on the modified opening 151, the first conductive layer 16 also covers the first contact region 122 and the exposed portion of the source junction 124. Based on the reduced gate gap 141, the first conductive layer 16 also covers the second contact region 123. The first conductive layer 16 forms an ohmic contact with the silicon carbide epitaxial layer 12 in the first contact region 122, and the first conductive layer 16 also forms an ohmic contact with the silicon carbide epitaxial layer 12 in the second contact region 123. The first conductive layer 16 has good surface adhesion.

[0034] The second conductive layer 17 is formed on the side of the silicon carbide substrate 11 opposite to the silicon carbide epitaxial layer 12. The first conductive layer 16 and the second conductive layer 17 are made of alloy metal.

[0035] The implementation principle of the silicon carbide MOSFET device provided in Embodiment 1 of this application is as follows: The first conductive layer 16, the self-aligned insulating interlayer 15, the gate layer 14, the gate oxide layer 13, the first contact region 122, the source junction 124, the doped well region 121, the silicon carbide epitaxial layer 12, the silicon carbide substrate layer 11, and the second conductive layer 17 constitute a silicon carbide transistor device (NMOS transistor). The first conductive layer 16 serves as the source, and the second conductive layer 17 serves as the drain. The carrier movement directions are as follows: first conductive layer 16, source junction 124, upper surface of the doped well region 121, silicon carbide epitaxial layer 12, silicon carbide substrate layer 11, and second conductive layer 17. The interface between the first contact region 122 and the source junction 124, and the interface between the second contact region 123 and the silicon carbide epitaxial layer 12, both constitute PN junctions.

[0036] On the one hand, by forming a gate gap 141 between two adjacent gate layers 14, the size of the gate and gate oxide is reduced, the gate oxide interface state density of the silicon carbide MOSFET device is reduced, Qgd is reduced, and carrier transport scattering is reduced, thereby improving the carrier mobility and thus improving the performance and reliability of the silicon carbide MOSFET device. On the other hand, by adding a second contact region 123 at the position corresponding to the gate gap 141, a PN junction is added accordingly, which improves the breakdown resistance and stability of the silicon carbide MOSFET device.

[0037] This embodiment also provides a method for fabricating a silicon carbide MOSFET device, used to fabricate the silicon carbide MOSFET device in this embodiment. (Refer to...) Figures 2 to 9 The method for fabricating a silicon carbide MOSFET device provided in this application includes the following specific steps: S1. A silicon carbide epitaxial layer 12 is provided on a silicon carbide substrate layer 11.

[0038] For details, please refer to Figure 2 A silicon carbide substrate 11 and a silicon carbide epitaxial layer 12 are selected, and the selected silicon carbide substrate 11 and silicon carbide epitaxial layer 12 are cleaned and dried. The polarity of the silicon carbide substrate 11 and silicon carbide epitaxial layer 12 is specifically N-type.

[0039] S2. A first photolithographic mask layer 181 is formed on the silicon carbide epitaxial layer 12 and patterned to expose the area of ​​the silicon carbide epitaxial layer 12 used to form the doped well region 121. A specific pattern of the first photolithographic mask layer 181 can be referred to Figure 3 .

[0040] S3. A doped well region 121 is formed in the silicon carbide epitaxial layer 12, and the doped well region 121 is exposed on the upper surface of the silicon carbide epitaxial layer 12.

[0041] For details, please refer to Figure 3 Aluminum ions are implanted into the silicon carbide epitaxial layer 12 exposed to the first photomask layer 181 to form a doped well region 121. The implantation depth of aluminum ions is controlled to be between 0.5 μm and 0.8 μm, and the doping amount is between 0.5e18 cm⁻¹. -3 up to 5e18cm -3 Therefore, the polarity of the doped well region 121 is specifically P-type.

[0042] S4. A second photolithographic mask layer 182 is formed on the silicon carbide epitaxial layer 12 and patterned to expose the doped well region 121 used to form the source junction 124.

[0043] S5. Multiple source junctions 124 are formed within the doped well region 121. The source junctions 124 are exposed on the upper surface of the doped well region 121. An active region 125 is formed on the upper surface of the doped well region 121 between the source junctions 124 and the silicon carbide epitaxial layer 12. The polarity of the source junctions 124 is specifically N+ type.

[0044] For details, please refer to Figure 4 Nitrogen ions are implanted into the doped well region 121 exposed to the second photolithography mask layer 182 to form a source junction 124, and the nitrogen ion doping level is controlled to be between 1e19cm. -3 Up to 1e20cm -3 .

[0045] S6. Remove the second photolithography mask layer 182.

[0046] S71. A gate oxide layer 13 and a gate layer 14 with the same pattern are formed on the silicon carbide epitaxial layer 12 to cover the active region 125; the gate oxide layer 13 covers the doped well region 121 on the upper surface between the silicon carbide epitaxial layer 12 and the source junction 124, and extends to cover part of the silicon carbide epitaxial layer 12 and part of the source junction 124, forming a gate gap 141 between two adjacent gate layers 14.

[0047] For details, please refer to Figure 5 A thermally oxidized silicon layer with a thickness between 30 nm and 200 nm and a conductive polysilicon layer with a thickness between 50 nm and 200 nm are sequentially fabricated on the silicon carbide epitaxial layer 12. The layers are patterned using the same mask. The patterned gate oxide layer 13 and gate layer 14 cover the doped well region 121 on the upper surface between the silicon carbide epitaxial layer 12 and the source junction 124, extending to cover a portion of the silicon carbide epitaxial layer 12 and a portion of the source junction 124, exposing a portion of the source junction 124, the doped well region 121 between the source junctions 124, and a portion of the silicon carbide epitaxial layer 12. A gate gap 141 is formed between two adjacent gate layers 14 at the exposed position of the silicon carbide epitaxial layer 12. The width of the gate gap 141 is smaller than the width of the exposed source junction 124 and the width of the doped well region 121 between the source junctions 124.

[0048] S72. A self-aligned interlayer insulating layer 15 is formed on the silicon carbide epitaxial layer 12 to completely cover the sides of the gate layer 14 and the gate oxide layer 13 and reduce the gate gap 141. The self-aligned interlayer insulating layer 15 also extends to cover the source junction 124. The self-aligned interlayer insulating layer 15 exposes the doped well region 121 between the source junction 124 for forming the first contact region 122 and the region of the silicon carbide epitaxial layer 12 aligned with the gate gap 141 for forming the second contact region 123.

[0049] For details, please refer to Figure 5 A self-aligned insulating interlayer 15 covering the gate layer 14 is fabricated and patterned on the silicon carbide epitaxial layer 12. The patterned self-aligned insulating interlayer 15 completely covers the sides of the gate layer 14 and the gate oxide layer 13, extending to cover a portion of the silicon carbide epitaxial layer 12 to reduce the gate gap 141, exposing the area of ​​the silicon carbide epitaxial layer 12 used to form the second contact region 123, and extending to cover the source junction 124, exposing the doped well region 121 between the source junctions 124 used to form the first contact region 122. The width of the reduced gate gap 141 is smaller than the width of the doped well region 121 between the source junctions 124.

[0050] S81. Based on the self-aligned insulating interlayer 15, a first contact region 122 is formed between the source junctions 124 within the doped well region 121, and a second contact region 123 is formed in the region of the silicon carbide epitaxial layer 12 aligned with the gate gap 141. The first contact region 122 is exposed on the upper surface of the silicon carbide epitaxial layer 12, and the source junctions 124 connect the first contact region 122 and the doped well region 121. The second contact region 123 is exposed on the upper surface of the silicon carbide epitaxial layer 12. The polarity of the first contact region 122 and the second contact region 123 is specifically P+ type. The second contact region 123 is formed based on the contact hole pattern of the self-aligned insulating interlayer 15 in the gate gap 141, and the formation area of ​​the second contact region 123 can be slightly larger than the contact hole pattern of the gate gap 141 by using a heavily doped diffusion method (e.g., ...). Figure 6 (As shown).

[0051] For details, please refer to Figure 6 Simultaneously, aluminum ions are implanted into the silicon carbide epitaxial layer 12 exposed to the self-aligned insulating interlayer 15 and the doped well region 121 exposed to the self-aligned insulating interlayer 15 after aligning the reduced gate gap 141, controlling the aluminum ion doping level to be between 1e19cm. -3 Up to 1e20cm -3 The self-aligned insulating interlayer 15, the silicon carbide epitaxial layer 12, and the upper surface of the doped well region 121 are cleaned. A carbon film is formed on the upper surface of the self-aligned insulating interlayer 15, the silicon carbide epitaxial layer 12, and the doped well region 121 for protection. Aluminum ions in the silicon carbide epitaxial layer 12 and the doped well region 121 are activated in an argon atmosphere, simultaneously forming the corresponding first contact region 122 and second contact region 123. In this embodiment, the self-aligned insulating interlayer 15 is used as a mask for fabricating the first contact region 122 and the second contact region 123, reducing one photolithography process and simplifying the fabrication process of the silicon carbide MOSFET device. The self-aligned insulating interlayer 15 is retained in the product structure of the silicon carbide MOSFET device.

[0052] S82. Enlarge the correction opening 151 of the self-aligned insulating interlayer 15 corresponding to the first contact area 122, so that part of the upper surface of the source junction 124 is exposed to the correction opening 151 of the self-aligned insulating interlayer 15.

[0053] For details, please refer to Figure 7The sidewalls of the self-aligned insulating interlayer 15 above the first contact region 122 are etched using a plasma dry side etching (SPACER) process. During this process, because the reduced gate gap 141 is smaller than the opening above the first contact region 122, the sidewall effect protection is good, resulting in extremely low etching efficiency of the plasma within the smaller gate gap 141. The opening of the self-aligned insulating interlayer 15 above the first contact region 122 is larger, leading to higher etching efficiency within the larger opening. Therefore, it is possible to correct and enlarge the opening of the self-aligned insulating interlayer 15 corresponding to the first contact region 122, partially exposing the upper surface of the source junction 124. However, the opening of the self-aligned insulating interlayer 15 corresponding to the second contact region 123 may not be corrected or may only be slightly enlarged, but it does not expose the essential surface of the silicon carbide epitaxial layer 12; that is, the gate gap 141 only exposes the second contact region 123.

[0054] S9. A first conductive layer 16 is formed on the silicon carbide epitaxial layer 12 to cover the self-aligned insulating interlayer 15. Based on the modified opening 151, the first conductive layer 16 also covers the first contact area 122 and the exposed portion of the source junction 124. Based on the reduced gate gap 141, the first conductive layer 16 also covers the second contact area 123. Please refer to [the relevant documentation] for details. Figure 8 A specific method for preparing the first conductive layer 16 includes depositing metal on the front side of the wafer on the silicon carbide epitaxial layer 12 and photolithographically etching a high-temperature alloy to form an ohmic contact between the first contact region 122 and the second contact region 123.

[0055] S10. A second conductive layer 17 is fabricated on the back side of the silicon carbide substrate 11. Please refer to [the relevant documentation] for details. Figure 9 One specific method for preparing the second conductive layer 17 includes forming a metal deposit on the back side of the silicon carbide substrate layer 11 wafer.

[0056] The implementation principle of Embodiment 2 of this application is as follows: the silicon carbide MOSFET device of this application embodiment can be fabricated through fabrication processes such as SPACER process and self-aligned mask process.

[0057] It should be noted that the silicon carbide MOSFET device in this application is a general concept, including but not limited to conventional MOSFET products or IGBT devices.

[0058] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A silicon carbide MOSFET device, characterized in that, include: A silicon carbide epitaxial layer (12) is provided in which a doped well region (121) is exposed on the upper surface of the silicon carbide epitaxial layer (12); a plurality of source junctions (124) are provided in the doped well region (121) and exposed on the upper surface of the silicon carbide epitaxial layer (12); the doped well region (121) forms an active region (125) on the upper surface between the source junctions (124) and the silicon carbide epitaxial layer (12). A gate oxide layer (13) and a gate layer (14) of the same pattern are disposed on the silicon carbide epitaxial layer (12) to cover the active region (125); the gate oxide layer (13) covers the doped well region (121) on the upper surface between the silicon carbide epitaxial layer (12) and the source junction (124), and extends to cover part of the silicon carbide epitaxial layer (12) and part of the source junction (124), forming a gate gap (141) between two adjacent gate layers (14). A self-aligned interlayer insulating layer (15) is formed on the silicon carbide epitaxial layer (12) to cover the sides of the gate layer (14) and the gate oxide layer (13) and reduce the gate gap (141). The self-aligned interlayer insulating layer (15) also extends to cover a portion of the source junction (124). The self-aligned interlayer insulating layer (15) self-aligns to expose the doped well region (121) between the source junction (124) for forming a first contact region (122) and the region of the silicon carbide epitaxial layer (12) aligned with the gate gap (141) for forming a second contact region (123). Based on the self-aligned interlayer insulating layer (15), the first contact region (122) is formed in the doped well region. Within the well region (121), the second contact region (123) is formed within the silicon carbide epitaxial layer (12). The first contact region (122) and the second contact region (123) are exposed on the upper surface of the doped well region (121). The source junction (124) is connected to the first contact region (122) and the doped well region (121). The self-aligned insulating interlayer (15) has a correction opening (151) corresponding to the enlargement correction of the first contact region (122) and a reduced gate gap (141), so that part of the upper surface of the source junction (124) is exposed to the correction opening (151), and the upper surface of the second contact region (123) is exposed to the reduced gate gap (141). A first conductive layer (16) is formed on the silicon carbide epitaxial layer (12) to cover the self-aligned insulating interlayer (15); based on the modified opening (151), the first conductive layer (16) also covers the first contact area (122) and the exposed portion of the source junction (124), and based on the reduced gate gap (141), the first conductive layer (16) also covers the second contact area (123).

2. The silicon carbide MOSFET device according to claim 1, characterized in that, The reduced gate gap (141) is smaller than the modified opening (151).

3. The silicon carbide MOSFET device according to claim 1, characterized in that, It also includes a silicon carbide substrate (11) and a second conductive layer (17), wherein the silicon carbide epitaxial layer (12) is disposed on the silicon carbide substrate (11) and the second conductive layer (17) is disposed on the back side of the silicon carbide substrate (11).

4. The silicon carbide MOSFET device according to claim 1, characterized in that, The silicon carbide epitaxial layer (12) and the source junction (124) have the same doping type. The doping type of the doped well region (121), the first contact region (122) and the second contact region (123) are the same but different from the doping type of the source junction (124).

5. The silicon carbide MOSFET device according to claim 4, characterized in that, The doping concentration of the first contact region (122) is greater than the doping concentration of the doped well region (121).

6. The silicon carbide MOSFET device according to claim 5, characterized in that, Both the first contact region (122) and the second contact region (123) are doped with aluminum ions activated under an argon atmosphere, wherein the doping amount of aluminum ions is between 1e19cm. -3 Up to 1e20cm -3 between.

7. The silicon carbide MOSFET device according to claim 5, characterized in that, The source junction (124) is doped with nitrogen ions, wherein the nitrogen ion doping amount is between 1e19cm. -3 Up to 1e20cm -3 between.

8. The silicon carbide MOSFET device according to claim 5, characterized in that, The doped well region (121) is doped with aluminum ions, wherein the amount of aluminum ions doped is between 0.5e18cm. -3 up to 5e18cm -3 The implantation depth of aluminum ions ranges from 0.5 μm to 0.8 μm.

9. The silicon carbide MOSFET device according to claim 1, characterized in that, The gate oxide layer (13) is a silicon oxide layer after thermal oxidation treatment, and the thickness of the silicon oxide layer is between 30nm and 200nm; the gate layer (14) is a conductive polysilicon layer, and the thickness of the conductive polysilicon layer is between 50nm and 200nm.

10. A method for fabricating a silicon carbide MOSFET device, characterized in that, include: S1. A silicon carbide epitaxial layer (12) is provided on a silicon carbide substrate layer (11). S3. A doped well region (121) is formed in the silicon carbide epitaxial layer (12), and the doped well region (121) is exposed on the upper surface of the silicon carbide epitaxial layer (12). S5. A source junction (124) is formed in the doped well region (121). The source junction (124) is exposed on the upper surface of the doped well region (121). An active region (125) is formed on the upper surface between the source junction (124) and the silicon carbide epitaxial layer (12). S71. A gate oxide layer (13) and a gate layer (14) with the same pattern are formed on the silicon carbide epitaxial layer (12) to cover the active region (125); the gate oxide layer (13) covers the doped well region (121) on the upper surface between the silicon carbide epitaxial layer (12) and the source junction (124), and extends to cover part of the silicon carbide epitaxial layer (12) and part of the source junction (124), forming a gate gap (141) between two adjacent gate layers (14). S72. A self-aligned insulating interlayer (15) is formed on the silicon carbide epitaxial layer (12) to completely cover the sides of the gate layer (14) and the gate oxide layer (13) and reduce the gate gap (141). The self-aligned insulating interlayer (15) also extends to cover the source junction (124). The self-aligned insulating interlayer (15) exposes the doped well region (121) between the source junction (124) for forming the first contact region (122) and the region of the silicon carbide epitaxial layer (12) aligned with the gate gap (141) for forming the second contact region (123). S81. Based on the self-aligned insulating interlayer (15), a first contact region (122) is formed between the source junctions (124) in the doped well region (121), and a second contact region (123) is formed in the region of the silicon carbide epitaxial layer (12) aligned with the gate gap (141). The first contact region (122) is exposed on the upper surface of the silicon carbide epitaxial layer (12), the source junctions (124) are connected to the first contact region (122) and the doped well region (121), and the second contact region (123) is exposed on the upper surface of the silicon carbide epitaxial layer (12). S82. Enlarge the modified opening (151) of the self-aligned insulating interlayer (15) corresponding to the first contact area (122), so that part of the upper surface of the source junction (124) is exposed to the modified opening (151) of the self-aligned insulating interlayer (15). S9. A first conductive layer (16) is formed on the silicon carbide epitaxial layer (12) to cover the self-aligned insulating interlayer (15). Based on the modified opening (151), the first conductive layer (16) also covers the first contact area (122) and the exposed portion of the source junction (124). Based on the reduced gate gap (141), the first conductive layer (16) also covers the second contact area (123).

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