Three-loop low-dropout linear regulator circuit based on dual power transistor

Abstract

The application discloses a three-loop low-dropout linear voltage regulator circuit based on double power tubes, relates to the technical field of power management chips, and solves the mutual trade-off problem of loop stability, loop bandwidth and output transient response of a low-dropout linear voltage regulator without an off-chip capacitor in the prior art; the circuit comprises a power supply rejection enhancement module, a first loop module, a second loop module, a third loop module and a double power tube module, the double power tube module is used for adjusting an output end voltage according to the first loop module, the second loop module, the third loop module and the power supply rejection enhancement module, and determining the output of the voltage regulator circuit; the system's load capacity is improved, a large output capacitor or a large compensation capacitor is not needed, and the problem of stability and loop bandwidth can also be adaptively solved.

Description

Technical Field

[0001] This invention relates to the field of power management chip technology, and in particular to a three-loop low-dropout linear regulator circuit based on dual power transistors. Background Technology

[0002] In recent years, power supply chips have become increasingly mature, and various technologies have been gradually improved, especially low-voltage linear regulator chips. They are mainly divided into: low-dropout linear regulators with external capacitors and those without external capacitors. Among them, low-dropout linear regulators without external capacitors have become one of the research hotspots in recent years. Since the entire circuit system is integrated inside the chip, the module occupies a smaller area in specific applications, effectively improving the integration density.

[0003] However, in existing technologies, transient response is often a challenging issue when designing capacitorless low-dropout linear regulators. A small output capacitor can lead to significant transient overshoot during output load transitions, causing malfunctions in subsequent circuits and impacting chip performance. Common solutions include designing a larger loop bandwidth to improve the output transient response, which sacrifices quiescent current and increases system power consumption; or using a relatively large output capacitor to improve transient characteristics, but this makes loop stability design difficult, typically achieved using a large Miller compensation capacitor at the cost of reduced loop bandwidth. Alternatively, a transient auxiliary module can be designed to detect transient output voltage changes and directly or indirectly affect the power transistor to improve transient response, but this also results in increased power consumption and design complexity. Summary of the Invention

[0004] This invention provides a three-loop low-dropout linear regulator circuit based on dual power transistors, which solves the trade-off between loop stability, loop bandwidth, and output transient response in existing low-dropout linear regulators without external capacitors. This improves the system's load capacity without requiring excessively large output capacitors or Miller compensation capacitors, and can adaptively address the issues of stability and loop bandwidth.

[0005] This invention provides a three-loop low-dropout linear regulator circuit based on dual power transistors, the circuit comprising:

[0006] The system includes a power suppression enhancement module, a first loop module, a second loop module, a third loop module, and a dual power transistor module; among which:

[0007] The first loop module is used to generate a feedback voltage VFB and a reference voltage VREF through resistors R1 and R2, thereby obtaining the accurate output Vout of the final low dropout linear regulator.

[0008] The second loop module is used to amplify the small signal at the output terminal of the dual power transistor module according to the two common-gate amplification circuit composed of PMOS transistor M1 and NMOS transistor M2 in the second loop module, and transmit it to the common gate of the first power transistor MP1 and the second power transistor MP2, so as to adjust the common gate voltage of the first power transistor MP1 and the second power transistor MP2.

[0009] The third loop module is used to determine the substrate voltage of the PMOS transistor M12 in the third loop module based on the current mirrored from the second power transistor MP2 to the third loop module, so as to adjust the substrate voltage of the second power transistor MP2.

[0010] The power suppression enhancement module is used to mirror the current flowing through the power suppression enhancement module to the second loop module, so that the disturbance transmitted from the power supply voltage VDD terminal to the common gate of the first power transistor MP1 and the second power transistor MP2 is proportional to the disturbance on the power supply voltage VDD terminal.

[0011] The dual power transistor module is used to adjust the output voltage according to the first loop module, the second loop module, the third loop module, and the power supply suppression enhancement module to determine the output of the voltage regulator circuit.

[0012] In one possible implementation, the dual-power transistor module includes: a first power transistor MP1 and a second power transistor MP2; wherein:

[0013] The gates of the first power transistor MP1 and the second power transistor MP2 are connected to the gate voltage VG terminal, and the source and substrate of the first power transistor MP1 and the source of the second power transistor MP2 are connected to the power supply voltage VDD terminal.

[0014] The substrate of the second power transistor MP2 is connected to the VDDA terminal, the drains of the first power transistor MP1 and the second power transistor MP2 are connected to the output Vout terminal, and the second power transistor MP2 forms a back gate control.

[0015] In one possible implementation, the first loop module includes: an error amplifier EA, a PMOS transistor M1, an NMOS transistor M8, and a capacitor Cfb; wherein:

[0016] One end of the resistor R1 is connected to the output Vout terminal, and the other end of the resistor R1 and one end of the resistor R2 are connected to the negative phase terminal of the error amplifier EA and the feedback voltage VFB.

[0017] The other end of the resistor R2 and the source of the NMOS transistor M8 are connected to the GND terminal.

[0018] The positive input of the error amplifier EA is connected to the reference voltage VREF, the negative input of the error amplifier EA is connected to the feedback voltage VFB, and the output of the error amplifier EA is connected to the gate of the PMOS transistor M1.

[0019] The source of the PMOS transistor M1, the drain of the second power transistor MP2 in the dual power transistor module, and the drain of the first power transistor MP1 are connected to the output Vout terminal. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M8. The gate of the NMOS transistor M8 is connected to the bias voltage Vbias terminal.

[0020] In one possible implementation, the second loop module includes: capacitor C1; wherein:

[0021] The source of the PMOS transistor M1 and one end of the capacitor C1 are connected to the output Vout terminal of the dual power module.

[0022] The transconductance of the PMOS transistor M1 and the capacitor C1 connected across the source and drain of the PMOS transistor M1 constitute a compensation zero point, which is used to cancel the pole generated at the drain of the PMOS transistor M1.

[0023] In one possible implementation, the second loop module further includes: PMOS transistors M3, M4, M5, NMOS transistors M6, M7, and M8; wherein:

[0024] The gate of the PMOS transistor M1 is connected to the output terminal of the error amplifier EA, and the drain of the PMOS transistor M1, the other end of the capacitor C1, the source of the NMOS transistor M2, and the drain of the NMOS transistor M8 are connected.

[0025] The gate of the NMOS transistor M8 is connected to the bias voltage Vbias terminal, and the source of the NMOS transistor M8 is connected to the GND terminal.

[0026] The gate of the NMOS transistor M2 is connected to the bias voltage VB terminal, and the drain of the NMOS transistor M2 is connected to the gate and drain of the PMOS transistor M3 and the gate of the PMOS transistor M4.

[0027] The drain of the PMOS transistor M4 is connected to the gate and drain of the NMOS transistor M6 and the gate of the NMOS transistor M7.

[0028] The sources of NMOS transistors M6 and M7 are connected to GND;

[0029] The drain of the NMOS transistor M7 and the drain of the PMOS transistor M5 are connected to the gate VG terminal of the dual power transistor.

[0030] The gate of the PMOS transistor M5 is connected to the VA terminal;

[0031] The sources of PMOS transistors M3, M4, and M5, the source of the first power transistor MP1 in the dual power transistor module, the substrate, and the source of the second power transistor MP2 are connected to the power supply voltage VDD terminal.

[0032] In one possible implementation, the third loop module includes: a resistor Rb and a capacitor Cc; wherein:

[0033] The source of the PMOS transistor M12 and one end of the resistor Rb are connected to the power supply voltage VDD terminal. The gate of the PMOS transistor M12 is connected to the gate VG terminal of the dual power transistor. The substrate of the PMOS transistor M12 and the substrate of the second power transistor are connected to the VDDA terminal.

[0034] One end of the capacitor Cc is connected to the VDDA terminal, and the other end of the capacitor Cc is connected to the output Vout terminal;

[0035] The PMOS transistor M12, the resistor Rb, and the capacitor Cc form the adjustable left half-plane zero point in the third loop module, which is used to compensate for the secondary poles in the third loop module to increase the stability of the third loop circuit.

[0036] In one possible implementation, the third loop module further includes: PMOS transistor M13, NMOS transistor M14, and NMOS transistor M15; wherein:

[0037] The drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M13.

[0038] The gate of the PMOS transistor M13 is connected to the feedback voltage VFB, and the drain of the PMOS transistor M13 is connected to the gate and drain of the NMOS transistor M14 and the gate of the NMOS transistor M15.

[0039] The sources of NMOS transistors M14 and M15 are connected to the GND terminal, and the drain of NMOS transistor M15, the other end of the resistor Rb, and one end of the capacitor Cc are connected.

[0040] In one possible implementation, the power supply suppression enhancement module includes: an NMOS transistor M9; wherein:

[0041] The bias voltage Vbias terminal is connected to the gate of the NMOS transistor M9 and is used to provide static bias current for the power supply suppression enhancement module.

[0042] In one possible implementation, the power suppression enhancement module further includes: PMOS transistor M10, PMOS transistor M11, NMOS transistor M9, and capacitor C2;

[0043] The source of the PMOS transistor M10 is connected to the power supply voltage VDD terminal, and the gate and drain of the PMOS transistor M10 are connected to the source and gate of the PMOS transistor M11, respectively.

[0044] The drain of the PMOS transistor M11 and one end of the capacitor C2 are connected to the VA terminal.

[0045] The drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M10, and the source of the NMOS transistor M9 and the other end of the capacitor C2 are connected to the GND terminal.

[0046] One or more technical solutions provided in this invention have at least the following technical effects or advantages:

[0047] This invention employs a three-loop low-dropout linear regulator circuit based on dual power transistors. The circuit includes: a power supply rejection enhancement module, a first loop module, a second loop module, a third loop module, and a dual power transistor module. The dual power transistor module adjusts the output voltage based on the first loop module, the second loop module, the third loop module, and the power supply rejection enhancement module to determine the regulator circuit's output. The first loop module generates a feedback voltage VFB through resistors R1 and R2, which clamps the feedback voltage VFB to the reference voltage VREF, resulting in the precise output Vout of the final low-dropout linear regulator. Compared to other loops, this first loop is a slow loop, used to improve the overall system gain to ensure the accuracy of the actual output Vout, especially its power supply rejection and load regulation characteristics at low frequencies. The second loop module amplifies the small signal at the output of the dual power transistor module using a double common-gate amplifier circuit composed of PMOS transistor M1 and NMOS transistor M2. This signal is then amplified by the transconductance enhancement stage composed of PMOS transistors M3, M4, M6, M7, and M5, and transmitted to the gate of the dual power transistors, and then through the power transistors... The common-source amplification inherent in the module itself regulates the output. The third loop module mirrors the current flowing through the second power transistor MP2 to the third loop module, determining the substrate voltage of the PMOS transistor M12 in the third loop module. This allows for adjustment of the substrate voltage of the second power transistor MP2. The actual position of the main pole can be adjusted by regulating the resistor Rb, the compensation capacitor Cc, and the back-gate transconductance to achieve relatively high loop bandwidth and stability. The power supply suppression enhancement module mirrors the current flowing through it to the second loop module, ensuring that the power supply voltage VDD is transmitted to the first power transistor MP1 and... The disturbance at the common gate of the second power transistor MP2 is proportional to the disturbance at the power supply voltage VDD terminal. The dual power transistor module is used to adjust the output voltage according to the first loop module, the second loop module, the third loop module, and the power supply suppression enhancement module to determine the output of the regulator circuit. This effectively solves the trade-off between loop stability, loop bandwidth, and output transient response in existing low-dropout linear regulators without external capacitors. At the same time, the dual power transistors can also improve the system's load capacity without requiring excessively large output capacitors or excessively large Miller compensation capacitors, and can also adaptively solve the problems of stability and loop bandwidth. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments of the present invention or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A circuit diagram of a three-loop low-dropout linear regulator based on dual power transistors provided in an embodiment of the present invention;

[0050] Figure 2 The simulation waveform of the power supply rejection ratio of the output voltage Vout provided in the embodiment of the present invention;

[0051] Figure 3 The transient response simulation waveform of the output voltage Vout is provided for an embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0053] This invention provides a three-loop low-dropout linear regulator circuit based on dual power transistors, such as... Figure 1 The circuit shown includes: a power supply suppression enhancement module, a first loop module, a second loop module, a third loop module, and a dual power transistor module.

[0054] The dual power transistor module is used to adjust the output voltage based on the first loop module, the second loop module, the third loop module, and the power supply suppression enhancement module, thereby determining the output of the voltage regulator circuit.

[0055] In one specific embodiment, the dual-power transistor module includes: a first power transistor MP1 and a second power transistor MP2; wherein: the gates of the first power transistor MP1 and the second power transistor MP2 are connected to the gate voltage VG terminal; the source and substrate of the first power transistor MP1 and the source of the second power transistor MP2 are connected to the power supply voltage VDD terminal; the substrate of the second power transistor MP2 is connected to the VDDA terminal; the drains of the first power transistor MP1 and the second power transistor MP2 are connected to the output Vout terminal; and the second power transistor MP2 forms a back-gate control. The back-gate effect formed by this back-gate control reduces the threshold voltage of the second power transistor MP2, reduces the required power transistor area, thereby reducing its gate parasitic capacitance, accelerating gate transient charging, and facilitating loop compensation in the module.

[0056] In one specific embodiment, the first loop module includes resistors R1 and R2; wherein resistors R1 and R2 are connected in series and connected to the output Vout terminal of the dual power transistor module; the feedback voltage VFB generated by the voltage difference between resistors R1 and R2 clamps the reference voltage VREF, thereby obtaining the accurate output Vout of the final low-dropout linear regulator. Compared to other modules in this circuit, this module is a slow loop, used to improve the gain of the entire circuit to ensure the accuracy of the actual output Vout, especially the power supply rejection characteristics and load regulation characteristics at low frequencies.

[0057] In one specific embodiment, the first loop module further includes: an error amplifier EA, a PMOS transistor M1, an NMOS transistor M8, and a capacitor Cfb; wherein: one end of resistor R1 is connected to the output Vout terminal, the other end of resistor R1 and one end of resistor R2 are connected to the negative inverting input of the error amplifier EA and the feedback voltage VFB; the other end of resistor R2 and the source of the NMOS transistor M8 are connected to the GND terminal; the positive inverting input of the error amplifier EA is connected to the reference voltage VREF terminal, the negative inverting input of the error amplifier EA is connected to the feedback voltage VFB, and the output terminal of the error amplifier EA is connected to the gate of the PMOS transistor M1; the source of the PMOS transistor M1, the drain of the second power transistor MP2 in the dual power transistor module, and the drain of the first power transistor MP1 are connected to the output Vout terminal, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M8; and the gate of the NMOS transistor M8 is connected to the bias voltage Vbias terminal.

[0058] The second loop module is used to amplify the small signal at the output of the dual power transistor module according to the two common-gate amplifier circuits composed of PMOS transistor M1 and NMOS transistor M2 in the second loop module, and transmit it to the common gate of the first power transistor MP1 and the second power transistor MP2 to adjust the common gate voltage of the first power transistor MP1 and the second power transistor MP2.

[0059] In one specific embodiment, the second loop module includes: a capacitor C1; wherein: the source of the PMOS transistor M1 and one end of the capacitor C1 are connected to the output Vout terminal of the dual power module; the transconductance of the PMOS transistor M1 and the capacitor C1 connected across the source and drain of the PMOS transistor M1 constitute a compensation zero point, which is used to cancel the pole generated at the drain of the PMOS transistor M1.

[0060] In one specific embodiment, the second loop module further includes: PMOS transistors M3, M4, M5, M6, M7, and M8; wherein: the gate of PMOS transistor M1 is connected to the output terminal of error amplifier EA; the drain of PMOS transistor M1, the other end of capacitor C1, the source of NMOS transistor M2, and the drain of NMOS transistor M8 are connected; the gate of NMOS transistor M8 is connected to the bias voltage Vbias terminal; the source of NMOS transistor M8 is connected to the GND terminal; the gate of NMOS transistor M2 is connected to the bias voltage VB terminal; and the drain of NMOS transistor M2 is connected to... The gate and drain of PMOS transistor M3 and the gate of PMOS transistor M4 are connected; the drain of PMOS transistor M4 is connected to the gate and drain of NMOS transistor M6 and the gate of NMOS transistor M7; the sources of NMOS transistors M6 and M7 are connected to GND; the drain of NMOS transistor M7 and the drain of PMOS transistor M5 are connected to the gate VG terminal of the dual power transistor; the gate of PMOS transistor M5 is connected to the VA terminal; the sources of PMOS transistors M3, M4, and M5, the source and substrate of the first power transistor MP1 in the dual power transistor module, and the source of the second power transistor MP2 are connected to the power supply voltage VDD terminal.

[0061] In the second loop module, NMOS transistor M8 acts as a bias transistor to provide static operating current for PMOS transistors M1 and M2 in the loop. PMOS transistors M1 and M2 form two common-gate amplifier circuits to amplify the small signal at the output. The signal is then amplified by the transconductance enhancement stage composed of PMOS transistors M3, M4, M6, M7, and M5 and transmitted to the gate of the dual power transistor module. The output is then adjusted by the common-source amplification effect of the power transistors themselves, completing the negative feedback process of the second loop module. Compared with other modules in this circuit, this module is a fast loop module, providing the circuit with a larger loop bandwidth and a higher transient response speed to cope with the transient changes in the load. The transconductance of PMOS transistor M1 in this module and the capacitor C1 connected across its two ends form a compensation zero Z1 to cancel the pole P1 generated at the drain of PMOS transistor M1. At the same time, there is a gate pole P2 of the dual power transistor in this loop. This pole is composed of the gate parasitic capacitance of the dual power transistor and the output impedance of the transconductance enhancement stage composed of the preceding PMOS transistor M5 and NMOS transistor M7. This pole falls within the loop bandwidth.

[0062] The third loop module is used to determine the substrate voltage of the PMOS transistor M12 in the third loop module based on the current mirrored from the second power transistor MP2 to the third loop module, so as to adjust the substrate voltage of the second power transistor MP2.

[0063] In one specific embodiment, the third loop module includes a resistor Rb and a capacitor Cc; wherein: the source of the PMOS transistor M12 and one end of the resistor Rb are connected to the power supply voltage VDD terminal; the gate of the PMOS transistor M12 is connected to the gate VG terminal of the dual power transistor; the substrate of the PMOS transistor M12 is connected to the substrate of the second power transistor; one end of the capacitor Cc is connected to the back gate control voltage VDDA terminal; and the other end of the capacitor Cc is connected to the output Vout terminal; the PMOS transistor M12, the resistor Rb, and the capacitor Cc form the adjustable left half-plane zero point in the third loop module, which is used to compensate for the secondary poles in the third loop module to increase the stability of the third loop circuit.

[0064] In one specific embodiment, the third loop module further includes: PMOS transistor M13, NMOS transistor M14, and NMOS transistor M15; wherein: the drain of PMOS transistor M12 is connected to the source of PMOS transistor M13; the gate of PMOS transistor M13 is connected to the feedback voltage VFB; the drain of PMOS transistor M13 is connected to the gate and drain of NMOS transistor M14 and the gate of NMOS transistor M15; the sources of NMOS transistors M14 and M15 are connected to the GND terminal; and the drain of NMOS transistor M15, the other end of resistor Rb, and one end of capacitor Cc are connected.

[0065] The third loop module fully utilizes the second power transistor MP2 of the dual power transistor module to form a back-gate control, providing an additional control loop to enhance the circuit's loop control capability. The load current flowing through the second power transistor MP2 is sampled by the PMOS transistor M12, and the sampled current flows through the sampling resistor Rb to generate substrate bias, driving the substrate of the second power transistor MP2. This increases the proportion of the back-gate transconductance in the transconductance of the second power transistor MP2, thereby improving the control capability of the output. Here, the back-gate transconductance pushes the output capacitor to the high-frequency range, thereby improving its impact on loop stability. Meanwhile, the sum of the transconductance formed by the PMOS transistor M12 and the resistor Rb, together with the compensation capacitor Cc, forms an adjustable zero point Z2 in the left half-plane of the loop. This zero point is used to compensate for the secondary poles in the loop, ensuring loop stability. The output main pole P3 is composed of the resistor Rb, the back gate transconductance, the output load, and the compensation capacitor Cc. The actual position of the main pole can be adjusted by adjusting the resistor Rb, the compensation capacitor Cc, and the back gate transconductance to obtain relatively high loop bandwidth and loop stability.

[0066] The power supply suppression enhancement module is used to mirror the current flowing through the power supply suppression enhancement module to the second loop module, so that the disturbance transmitted from the power supply voltage VDD terminal to the common gate of the first power transistor MP1 and the second power transistor MP2 is proportional to the disturbance on the power supply voltage VDD terminal.

[0067] In one specific embodiment, the power supply suppression enhancement module includes: an NMOS transistor M9; wherein: the gate of the NMOS transistor M9 is connected to the bias voltage Vbias terminal, and is used to provide a static bias current for the power supply suppression enhancement module. A PMOS transistor M10 is a mirror transistor, mirroring its current to a PMOS transistor M5. A PMOS transistor M11 and capacitor C2 form a low-pass notch network to filter out disturbance signals from VDD and transmit them to the PMOS transistor M5. The amplification effect of the PMOS transistor M5 ensures that the disturbance transmitted from VDD to the gate VG terminal of the power transistor is proportional to the disturbance at the VDD terminal, thus canceling them out by the difference between the gate and source voltages of the power transistor. This minimizes the disturbance signal transmitted to the output Vout, ensuring the power supply suppression characteristics of the output.

[0068] In one specific embodiment, the power suppression enhancement module further includes: a PMOS transistor M10, a PMOS transistor M11, an NMOS transistor M9, and a capacitor C2; the source of the PMOS transistor M10 is connected to the power supply voltage VDD terminal, and the gate and drain of the PMOS transistor M10 are connected to the source and gate of the PMOS transistor M11, respectively; the drain of the PMOS transistor M11 and one end of the capacitor C2 are connected to the VA terminal; the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M10, and the source of the NMOS transistor M9 and the other end of the capacitor C2 are connected to the GND terminal.

[0069] In this invention, the circuit proposed in this invention is simulated through simulation experiments, and the transient characteristics and power supply rejection ratio characteristics are verified and explained. For example... Figure 2 The figure shown is a simulated waveform of the power supply rejection ratio (PSRR) at the output voltage Vout terminal proposed in this invention. From... Figure 2 As can be seen, the power rejection ratio of the output Vout terminal is significantly enhanced after power rejection enhancement, especially between 1KHz and 10MHz.

[0070] In this invention, both the second and third loop modules are used to improve the transient characteristics of the system. When the load current increases, the output voltage Vout decreases. In the second loop module, the two common-gate amplifier circuits composed of PMOS transistor M1 and NMOS transistor M2 amplify the small signal changes at the output terminal. After being amplified by the transconductance enhancement stage composed of PMOS transistors M3, M4, M5, M6, and M7, the amplified signal is transmitted to the gate VG terminals of the first power transistor MP1 and the second power transistor MP2, causing the gate voltage VG of the dual power transistors to decrease. This allows the current supplied to the load by the dual power transistors to increase rapidly, improving the transient response when the load current increases. The third loop module addresses the output voltage undershoot issue by sampling the load current flowing through the second power transistor MP2 using the PMOS transistor M12. This sampled current flows through the sampling resistor Rb, generating VDDA, which biases the substrate of the second power transistor MP2 and drives its substrate. This decreases VDDA, increasing the voltage difference VSB between the source and substrate of MP2. This enhances the back gate's control over MP2, allowing the current supplied to the load by MP2 to increase rapidly, thus mitigating the output voltage undershoot caused by increased load current. Conversely, the opposite is also true.

[0071] Figure 3 This is a simulation waveform diagram of the transient response of the output voltage Vout provided in an embodiment of the present invention. Figure 3 As can be seen, VOUT1 is the transient waveform of the regulator output with the back gate control loop of the third loop module, and VOUT2 is the transient waveform of the regulator output without the back gate control loop of the third loop module. It is obvious that the back gate control loop of the third loop module can effectively improve the transient response of the loop.

[0072] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0073] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A three-loop low-dropout linear regulator circuit based on dual power transistors, characterized in that, include: The system includes a power suppression enhancement module, a first loop module, a second loop module, a third loop module, and a dual power transistor module; among which: The first loop module is used to generate a feedback voltage VFB and a reference voltage VREF through resistors R1 and R2, and input the feedback voltage VFB and the reference voltage VREF to the negative input terminal and the positive input terminal of the error amplifier EA, respectively, to obtain the accurate output Vout of the low dropout linear regulator. The second loop module is used to amplify the small signal at the output terminal of the dual power transistor module according to the two common-gate amplification circuit composed of PMOS transistor M1 and NMOS transistor M2 in the second loop module, and transmit it to the common gate of the first power transistor MP1 and the second power transistor MP2, so as to adjust the common gate voltage of the first power transistor MP1 and the second power transistor MP2. The third loop module is used to determine the substrate voltage of the PMOS transistor M12 in the third loop module based on the current mirrored from the second power transistor MP2 to the third loop module, so as to adjust the substrate voltage of the second power transistor MP2. The power suppression enhancement module is used to mirror the current flowing through the power suppression enhancement module to the second loop module, so that the disturbance transmitted from the power supply voltage VDD terminal to the common gate of the first power transistor MP1 and the second power transistor MP2 is proportional to the disturbance on the power supply voltage VDD terminal. The dual power transistor module is used to adjust the output voltage according to the first loop module, the second loop module, the third loop module, and the power supply suppression enhancement module to determine the output of the voltage regulator circuit.

2. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 1, characterized in that, The dual-power transistor module includes: a first power transistor MP1 and a second power transistor MP2; wherein: The gates of the first power transistor MP1 and the second power transistor MP2 are connected to the gate voltage VG terminal, and the source and substrate of the first power transistor MP1 and the source of the second power transistor MP2 are connected to the power supply voltage VDD terminal. The substrate of the second power transistor MP2 is connected to the VDDA terminal, and the drains of the first power transistor MP1 and the second power transistor MP2 are connected to the output Vout terminal. The first power transistor MP1 and the second power transistor MP2 form a back gate control.

3. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 1, characterized in that, The first loop module includes: an error amplifier EA, a PMOS transistor M1, an NMOS transistor M8, and a capacitor Cfb; wherein: One end of the resistor R1 is connected to the output Vout terminal, and the other end of the resistor R1 and one end of the resistor R2 are connected to the negative phase terminal of the error amplifier EA and the feedback voltage VFB. The other end of the resistor R2 and the source of the NMOS transistor M8 are connected to the GND terminal. The positive input of the error amplifier EA is connected to the reference voltage VREF, the negative input of the error amplifier EA is connected to the feedback voltage VFB, and the output of the error amplifier EA is connected to the gate of the PMOS transistor M1. The source of the PMOS transistor M1, the drain of the second power transistor MP2 in the dual power transistor module, and the drain of the first power transistor MP1 are connected to the output Vout terminal. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M8. The gate of the NMOS transistor M8 is connected to the bias voltage Vbias terminal.

4. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 1, characterized in that, The second loop module includes: capacitor C1; wherein: The source of the PMOS transistor M1 and one end of the capacitor C1 are connected to the output Vout terminal of the dual power transistor module. The transconductance of the PMOS transistor M1 and the capacitor C1 connected across the source and drain of the PMOS transistor M1 constitute a compensation zero point, which is used to cancel the pole generated at the drain of the PMOS transistor M1.

5. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 4, characterized in that, The second loop module further includes: PMOS transistors M3, M4, M5, NMOS transistors M6, M7, and M8; wherein: The gate of the PMOS transistor M1 is connected to the output terminal of the error amplifier EA, and the drain of the PMOS transistor M1, the other end of the capacitor C1, the source of the NMOS transistor M2, and the drain of the NMOS transistor M8 are connected. The gate of the NMOS transistor M8 is connected to the bias voltage Vbias terminal, and the source of the NMOS transistor M8 is connected to the GND terminal. The gate of the NMOS transistor M2 is connected to the bias voltage VB terminal, and the drain of the NMOS transistor M2 is connected to the gate and drain of the PMOS transistor M3 and the gate of the PMOS transistor M4. The drain of the PMOS transistor M4 is connected to the gate and drain of the NMOS transistor M6 and the gate of the NMOS transistor M7. The sources of NMOS transistors M6 and M7 are connected to GND; The drain of the NMOS transistor M7 and the drain of the PMOS transistor M5 are connected to the gate VG terminal of the dual power transistor. The gate of the PMOS transistor M5 is connected to the VA terminal; The sources of PMOS transistors M3, M4, and M5, the source of the first power transistor MP1 in the dual power transistor module, the substrate, and the source of the second power transistor MP2 are connected to the power supply voltage VDD terminal.

6. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 1, characterized in that, The third loop module includes: a resistor Rb and a capacitor Cc; wherein: The source of the PMOS transistor M12 and one end of the resistor Rb are connected to the power supply voltage VDD terminal. The gate of the PMOS transistor M12 is connected to the gate VG terminal of the dual power transistor. The substrate of the PMOS transistor M12 and the substrate of the second power transistor MP2 are both connected to the VDDA terminal. One end of the capacitor Cc is connected to the VDDA terminal, and the other end of the capacitor Cc is connected to the output Vout terminal; The PMOS transistor M12, the resistor Rb, and the capacitor Cc form the adjustable left half-plane zero point in the third loop module, which is used to compensate for the secondary poles in the third loop module to increase the stability of the third loop circuit.

7. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 6, characterized in that, The third loop module further includes: PMOS transistor M13, NMOS transistor M14, and NMOS transistor M15; wherein: The drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M13. The gate of the PMOS transistor M13 is connected to the feedback voltage VFB, and the drain of the PMOS transistor M13 is connected to the gate and drain of the NMOS transistor M14 and the gate of the NMOS transistor M15. The sources of NMOS transistors M14 and M15 are connected to the GND terminal, and the drain of NMOS transistor M15, the other end of the resistor Rb, and one end of the capacitor Cc are connected.

8. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 1, characterized in that, The power suppression enhancement module includes: an NMOS transistor M9; wherein: The bias voltage Vbias terminal is connected to the gate of the NMOS transistor M9 and is used to provide static bias current for the power supply suppression enhancement module.

9. The three-loop low-dropout linear regulator circuit based on dual power transistors according to claim 8, characterized in that, The power suppression enhancement module also includes: PMOS transistor M10, PMOS transistor M11, NMOS transistor M9, and capacitor C2; The source of the PMOS transistor M10 is connected to the power supply voltage VDD terminal, and the gate and drain of the PMOS transistor M10 are connected to the source and gate of the PMOS transistor M11, respectively. The drain of the PMOS transistor M11 and one end of the capacitor C2 are connected to the VA terminal. The drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M10, and the source of the NMOS transistor M9 and the other end of the capacitor C2 are connected to the GND terminal.

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