Row scanning unit, row scanning cascade circuit and driving method

Abstract

The application provides a row scanning unit, a row scanning cascade circuit and a driving method. The row scanning unit comprises an input module, an output module, a pull-down maintenance control module, a maintenance module, a pull-down module, a first reset module and a second reset module. By connecting each module in the row scanning unit with at least one of the first node and the second node, the mutual restriction of each module is realized, the residual charge in the row scanning unit can be released while the output function of the row scanning unit is realized, so that the reset and zero of the entire row scanning unit can be realized faster and better, and the problems of low leakage current of Oxide TFT and easy charge residue are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a row scanning unit, a row scanning cascade circuit and a driving method. Background Art

[0002] In the display field, GOA (Gate Driven on Array) technology utilizes TFT (Thin Film Transistor) integrated designs on display glass substrates to achieve gate shift waveform output. This technology can replace the functions of gate driver ICs (Gate Driver Integrated Circuits), eliminating the use and manufacturing process of Gate Driver ICs and significantly reducing panel costs. Furthermore, GOA technology can further simplify designs and achieve narrow bezels in high-mobility semiconductor technologies such as oxide and LTPS (Low-Temperature Polycrystalline Silicon).

[0003] Currently, GOA technology has become a core and widely used technology in display panels. However, in the field of oxide semiconductors, TFT characteristics are easily degraded by moisture. At the same time, oxide TFTs have low leakage current and are prone to charge retention.

[0004] Therefore, when GOA is applied to oxide semiconductor technology, it is necessary to consider the characteristics of oxide and design the GOA circuit. Summary of the Invention

[0005] The main technical problem solved by the present application is to provide a row scanning unit, a row scanning cascade circuit and a driving method to solve the problem in the prior art that the leakage current of oxide is low and the charge is easily retained.

[0006] In order to solve the above technical problems, the first technical solution provided by the present application is to provide a row scanning unit, wherein the row scanning unit includes:

[0007] An input module, configured to transmit a signal according to the N-1th stage to pull the first node to a high potential; N is an integer greater than 1;

[0008] an output module, in response to the first node being at a high potential, receiving a first clock signal to output an output signal to a signal output terminal;

[0009] A pull-down maintenance control module, configured to pull the potential of the second node up to a high potential;

[0010] a maintaining module, in response to the second node being at a high potential, to pull down the potentials of the signal output terminal and the first node to a low potential;

[0011] a pull-down module, configured to pull down the potential of the second node to a low potential;

[0012] a first reset module, configured to pull down the potential of the first node to a low potential according to the N+2th stage transmission signal;

[0013] The second reset module is configured to pull down the potentials of the first node, the second node and the signal output end to a low potential according to a second clock signal.

[0014] The control end of the input module is connected to the N-1th stage transmission signal, the input end of the input module is connected to the constant voltage high potential signal, and the output end of the input module is connected to the first node;

[0015] The control end of the output module is connected to the first node, the input end of the output module is connected to the first clock signal, and the output end of the output module is connected to the signal output end;

[0016] The control end of the pull-down maintenance control module is connected to the constant voltage high potential signal, the input end of the pull-down maintenance control module is connected to the constant voltage high potential signal, and the output end of the pull-down maintenance control module is connected to the second node;

[0017] The control end of the maintenance module is connected to the second node, the input end of the maintenance module is connected to the signal output end and the first node; the output end of the maintenance module is connected to a constant voltage low potential signal;

[0018] The control end of the pull-down module is connected to the first node and the N-1th stage transmission signal, the input end of the pull-down module is connected to the second node, and the output end of the pull-down module is connected to the constant voltage low potential signal;

[0019] The control end of the first reset module is connected to the N+2th stage transmission signal, the input end of the first reset module is connected to the first node, and the output end of the first reset module is connected to the constant voltage low potential signal;

[0020] The control end of the second reset module is connected to the second clock signal, the input end of the second reset module is connected to the first node and the signal output end, and the output end of the second reset module is connected to the constant voltage low potential signal.

[0021] The input module includes a first transistor, a gate of the first transistor is connected to the N-1th stage transmission signal, a drain of the first transistor is connected to a constant voltage high potential signal, and a source of the first transistor is connected to the first node;

[0022] The pull-down module includes a second transistor and a third transistor, wherein the gate of the second transistor is connected to the N-1th stage transmission signal, the drain of the second transistor is connected to the second node, and the source of the second transistor is connected to a constant voltage low potential signal; the gate of the third transistor is connected to the first node, the drain of the third transistor is connected to the second node, and the source of the third transistor is connected to the constant voltage low potential signal;

[0023] The first reset module includes a fourth transistor, a gate of the fourth transistor is connected to the (N+2)th stage transmission signal, a drain of the fourth transistor is connected to the first node, and a source of the fourth transistor is connected to the constant low-potential signal;

[0024] The pull-down maintenance control module includes a fifth transistor, a gate of the fifth transistor and a drain of the fifth transistor are both connected to the constant voltage high potential signal, and a source of the fifth transistor is connected to the second node.

[0025] The signal output end includes a first output end, and the first output end is used to output the Nth level gate driving signal.

[0026] in,

[0027] The output module includes a sixth transistor and a capacitor, wherein the gate of the sixth transistor is connected to the first node, the drain of the sixth transistor is connected to the first clock signal, and the source of the sixth transistor is connected to the first output terminal; one end of the capacitor is connected to the first node, and the other end is connected to the first output terminal;

[0028] The maintaining module includes a seventh transistor and an eighth transistor, wherein the gate of the seventh transistor is connected to the second node, the drain of the seventh transistor is connected to the first output terminal, and the source of the seventh transistor is connected to the constant low-voltage signal; the gate of the eighth transistor is connected to the second node, the drain of the eighth transistor is connected to the first node, and the source of the eighth transistor is connected to the constant low-voltage signal;

[0029] The second reset module includes a ninth transistor, a tenth transistor, and an eleventh transistor, the gate of the ninth transistor being connected to the second clock signal, the drain of the ninth transistor being connected to the first node, and the source of the ninth transistor being connected to the constant-voltage low-potential signal; the gate of the tenth transistor being connected to the second clock signal, the drain of the tenth transistor being connected to the first output terminal, and the source of the tenth transistor being connected to the constant-voltage low-potential signal; the gate of the eleventh transistor being connected to the second clock signal, the drain of the eleventh transistor being connected to the second node, and the source of the eleventh transistor being connected to the constant-voltage low-potential signal.

[0030] The signal output end further includes a second output end, and the second output end is used to output the Nth stage transmission signal.

[0031] The output module further includes a twelfth transistor, a gate of the twelfth transistor connected to the first node, a drain of the twelfth transistor connected to the first clock signal, a source of the twelfth transistor connected to the first node and connected to the second output end through the first node;

[0032] The maintaining module further includes a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the second node, a drain of the thirteenth transistor is connected to the second output terminal, and a source of the thirteenth transistor is connected to the constant low-potential signal;

[0033] The second reset module further includes a fourteenth transistor, a gate of the fourteenth transistor is connected to the second clock signal, a drain of the fourteenth transistor is connected to the second output terminal, and a source of the fourteenth transistor is connected to the constant low-potential signal.

[0034] Among them, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor and the fourteenth transistor are all oxide thin film transistors.

[0035] In order to solve the above technical problem, the second technical solution provided by the present application is: providing a row scanning cascade circuit, wherein the row scanning cascade circuit includes the above row scanning unit.

[0036] In order to solve the above technical problems, the third technical solution provided by the present application is as follows: providing a driving method of a row scanning unit, wherein the row scanning unit is the row scanning unit described above, and the driving timing sequence of the row scanning unit sequentially includes an input phase, a first output phase, a second output phase, a reset phase, and a blank phase; the blank phase sequentially includes a first time period and a second time period in chronological order;

[0037] The driving method includes:

[0038] In the input phase, the N-1th stage transmission signal is at a high potential, and the first clock signal, the second clock signal, and the N+2th stage transmission signal are all at a low potential; the input module pulls the potential of the first node to a high potential, and the pull-down module pulls the potential of the second node to a low potential;

[0039] In the first output stage, the first clock signal is at a high level, the second clock signal, the N-1th stage transmission signal, and the N+2th stage transmission signal are all at a low level; the output module outputs a high level to the signal output terminal;

[0040] In the second output stage, the first clock signal, the second clock signal, the N-1th stage transmission signal, and the N+2th stage transmission signal are all at low potentials; the output module outputs a low potential to the signal output terminal;

[0041] In the reset phase, the first clock signal and the (N+2)th stage transmission signal are both at high potentials, and the second clock signal and the (N-1)th stage transmission signal are both at low potentials; the first reset module pulls down the potential of the first node from a high potential to a low potential, the pull-down module stops working so that the pull-down maintenance control module pulls up the potential of the second node from a low potential to a high potential, and the maintenance module continuously pulls down the potential of the first node and the potential of the signal output end and maintains them at a low potential;

[0042] In the blank phase, the first clock signal, the N-1th level transmission signal and the N+2th level transmission signal are all at low potential; in the first time period, the second clock signal is at high potential, and the first node and the signal output end are both discharged through the second reset module; in the second time period, the second clock signal is at low potential.

[0043] Beneficial effects of the present application: Different from the prior art, the present application provides a row scanning unit, a row scanning cascade circuit and a driving method. The row scanning unit includes an input module, an output module, a pull-down maintenance control module, a maintenance module, a pull-down module, a first reset module and a second reset module. The input module is used to transmit a signal according to the N-1th level to pull the first node to a high potential; N is an integer greater than 1; the output module receives a first clock signal in response to the first node being a high potential to output an output signal to the signal output terminal; the pull-down maintenance control module is used to pull the potential of the second node to a high potential; the maintenance module responds to the second node being a high potential to pull the potential of the signal output terminal and the first node to a low potential; the pull-down module is used to pull the potential of the second node to a low potential; the first reset module is used to transmit a signal according to the N+2th level to pull the potential of the first node to a low potential; the second reset module is used to pull the potentials of the first node, the second node and the signal output terminal to a low potential according to the second clock signal. By connecting each module in the row scanning unit to at least one of the first node and the second node, mutual restraint of each module is achieved. While realizing the output function of the row scanning unit, the residual charge in the row scanning unit can be released, so as to achieve the reset and clearing of the entire row scanning unit faster and better, thereby improving the problem of low leakage current and easy charge residue of the oxide TFT. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 This is a module diagram of an embodiment of a row scanning unit provided by the present application;

[0046] Figure 2 1 is a structural diagram of a first embodiment of a row scanning unit provided by the present application;

[0047] Figure 3 is a structural diagram of a second embodiment of a row scanning unit provided by the present application;

[0048] Figure 4 This is a structural diagram of an embodiment of a row scanning cascade circuit provided by the present application;

[0049] Figure 5 This is a flow chart of an embodiment of a driving method of a row scanning unit provided in the present application;

[0050] Figure 6This is the timing diagram corresponding to the row scanning unit provided in this application.

[0051] Description of Figure Numbers:

[0052] Row scanning unit-100, input module-10, output module-20, pull-down maintenance control module-30, maintenance module-40, pull-down module-50, first reset module-60, second reset module-70, first node-PU, second node-PD, constant voltage high potential signal / high potential signal line-VGH, constant voltage low potential signal / low potential signal line-VSS, first clock signal / first clock signal line-CK, second clock signal / second clock signal line-CLR, signal output terminal / output signal-Ouput, first output terminal-Ouput1, second output terminal-Ouput2, N-1th stage transmission signal-Tn-1, Nth stage transmission signal-Tn, The Nth gate drive signal -Gn, the N+1th stage transmission signal -Tn+1, the N+2th stage transmission signal -Tn+2, the row scanning cascade circuit -200, the input signal -Input, the reset signal -Reset, the first time period -t1, the second time period -t2, the first transistor -M1, the second transistor -M2, the third transistor -M3, the fourth transistor -M4, the fifth transistor -M5, the sixth transistor -M6, the seventh transistor -M7, the eighth transistor -M8, the ninth transistor -M9, the tenth transistor -M10, the eleventh transistor -M11, the twelfth transistor -M12, the thirteenth transistor -M13, the fourteenth transistor -M14, and the capacitor -C. DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0054] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0055] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0057] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0058] See also Figure 1 , Figure 1 1 is a module diagram of an embodiment of a row scanning unit provided in this application.

[0059] The present application provides a row scanning unit 100 , which includes an input module 10 , an output module 20 , a pull-down maintenance control module 30 , a maintenance module 40 , a pull-down module 50 , a first reset module 60 , and a second reset module 70 .

[0060] The input module 10 is configured to transmit a signal Tn-1 according to the N-1th stage to pull the first node PU to a high potential. N and n are both integers greater than 1.

[0061] In response to the first node PU being at a high level, the output module 20 receives the first clock signal CK to output the output signal Ouput to the signal output terminal Ouput.

[0062] The pull-down sustain control module 30 is used to pull up the potential of the second node PD to a high potential.

[0063] In response to the second node PD being at a high potential, the maintenance module 40 pulls down the potentials of the signal output terminal Ouput and the first node PU to a low potential.

[0064] The pull-down module 50 is used to pull down the potential of the second node PD to a low potential.

[0065] The first reset module 60 is configured to pull the potential of the first node PU down to a low potential according to the (N+2)th stage transmission signal Tn+2.

[0066] The second reset module 70 is configured to pull down the potentials of the first node PU, the second node PD and the signal output terminal Ouput to a low potential according to the second clock signal CLR.

[0067] Specifically, the control end of the input module 10 is connected to the N-1th stage transmission signal Tn-1, the input end of the input module 10 is connected to the constant voltage high potential signal VGH, and the output end of the input module 10 is connected to the first node PU.

[0068] The control end of the output module 20 is connected to the first node PU, the input end of the output module 20 is connected to the first clock signal CK, and the output end of the output module 20 is connected to the signal output end Ouput.

[0069] The control terminal of the pull-down maintenance control module 30 is connected to the constant voltage high potential signal VGH, the input terminal of the pull-down maintenance control module 30 is connected to the constant voltage high potential signal VGH, and the output terminal of the pull-down maintenance control module 30 is connected to the second node PD.

[0070] The control terminal of the maintenance module 40 is connected to the second node PD, the input terminal of the maintenance module 40 is connected to the signal output terminal Ouput and the first node PU, and the output terminal of the maintenance module 40 is connected to the constant low potential signal VSS.

[0071] The control end of the pull-down module 50 is connected to the first node PU and the (N-1)th stage transmission signal Tn-1, the input end of the pull-down module 50 is connected to the second node PD, and the output end of the pull-down module 50 is connected to the constant low potential signal VSS.

[0072] The control end of the first reset module 60 is connected to the (N+2)th stage transmission signal Tn+2, the input end of the first reset module 60 is connected to the first node PU, and the output end of the first reset module 60 is connected to the constant low potential signal VSS.

[0073] The control end of the second reset module 70 is connected to the second clock signal CLR, the input end of the second reset module 70 is connected to the first node PU and the signal output end Ouput, and the output end of the second reset module 70 is connected to the constant low potential signal VSS.

[0074] It should be noted that the signal output terminal Ouput may include only the first output terminal Ouput1, and the first output terminal Ouput1 is used to output the N-th stage gate drive signal Gn; or the signal output terminal Ouput may include the first output terminal Ouput1 and the second output terminal Ouput2 (such as Figure 3 As shown), the first output terminal Ouput1 is used to output the N-th stage gate driving signal Gn, and the second output terminal Ouput2 is used to output the N-th stage transmission signal Tn.

[0075] It should be understood that when the signal output terminal Ouput only includes the first output terminal Ouput1 , the first output terminal Ouput1 is used not only for outputting the N-th stage gate driving signal Gn, but also for outputting the N-th stage transmission signal Tn.

[0076] In this embodiment, the signal output terminal Ouput only includes the first output terminal Ouput1 , and the first output terminal Ouput1 is used to output the N-th stage gate driving signal Gn and the N-th stage transmission signal Tn.

[0077] See also Figure 1 and Figure 2 , Figure 2 It is a structural diagram of the first embodiment of the row scanning unit provided in this application.

[0078] Furthermore, the input module 10 includes a first transistor M1 , a gate of the first transistor M1 connected to the N-1th stage transmission signal Tn-1, a drain of the first transistor M1 connected to the constant voltage high potential signal VGH, and a source of the first transistor M1 connected to the first node PU.

[0079] The pull-down module 50 includes a second transistor M2 and a third transistor M3, the gate of the second transistor M2 is connected to the N-1th stage transmission signal Tn-1, the drain of the second transistor M2 is connected to the second node PD, and the source of the second transistor M2 is connected to the constant voltage low potential signal VSS; the gate of the third transistor M3 is connected to the first node PU, the drain of the third transistor M3 is connected to the second node PD, and the source of the third transistor M3 is connected to the constant voltage low potential signal VSS.

[0080] The first reset module 60 includes a fourth transistor M4 , a gate of which is connected to the (N+2)th stage transmission signal Tn+2, a drain of which is connected to the first node PU, and a source of which is connected to the constant low potential signal VSS.

[0081] The pull-down maintenance control module 30 includes a fifth transistor M5 , a gate of the fifth transistor M5 and a drain of the fifth transistor M5 are both connected to the constant high potential signal VGH, and a source of the fifth transistor M5 is connected to the second node PD.

[0082] The output module 20 includes a sixth transistor M6 and a capacitor C. The gate of the sixth transistor M6 is connected to the first node PU, the drain of the sixth transistor M6 is connected to the first clock signal CK, and the source of the sixth transistor M6 is connected to the first output terminal Ouput1. One end of the capacitor C is connected to the first node PU, and the other end is connected to the first output terminal Ouput1.

[0083] The maintenance module 40 includes a seventh transistor M7 and an eighth transistor M8, the gate of the seventh transistor M7 is connected to the second node PD, the drain of the seventh transistor M7 is connected to the first output terminal Ouput1, and the source of the seventh transistor M7 is connected to the constant low-voltage signal VSS; the gate of the eighth transistor M8 is connected to the second node PD, the drain of the eighth transistor M8 is connected to the first node PU, and the source of the eighth transistor M8 is connected to the constant low-voltage signal VSS.

[0084] The second reset module 70 includes a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The gate of the ninth transistor M9 is connected to the second clock signal CLR, the drain of the ninth transistor M9 is connected to the first node PU, and the source of the ninth transistor M9 is connected to the constant low-voltage signal VSS; the gate of the tenth transistor M10 is connected to the second clock signal CLR, the drain of the tenth transistor M10 is connected to the first output terminal Ouput1, and the source of the tenth transistor M10 is connected to the constant low-voltage signal VSS; the gate of the eleventh transistor M11 is connected to the second clock signal CLR, the drain of the eleventh transistor M11 is connected to the second node PD, and the source of the eleventh transistor M11 is connected to the constant low-voltage signal VSS.

[0085] The first transistor M1 , the second transistor M2 , the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 , the eighth transistor M8 , the ninth transistor M9 , the tenth transistor M10 and the eleventh transistor M11 are all oxide thin film transistors.

[0086] It should be understood that at least one of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 can be a transistor of other types, and no further restrictions are imposed here.

[0087] In this embodiment, the row scanning unit 100 replaces the gate driver IC's functionality, effectively reducing the cost of the gate driver IC. Furthermore, the row scanning unit 100 of this embodiment includes 11 transistors, utilizing fewer transistors to implement its output function, thereby achieving a narrow border effect. Furthermore, the row scanning unit 100 of this embodiment utilizes the high mobility of oxide, allowing the transistors of this embodiment to be smaller than those of amorphous silicon transistors. Using this transistor in oxide products can further reduce the product's border while ensuring reliability, achieving an even narrower border effect. Secondly, the signal level transmission between the row scanning units 100 in this embodiment adopts the Nth level gate drive signal Gn (i.e., the gate drive signal of this level) instead of the Nth level transmission signal Tn (i.e., the level transmission signal of this level), which further optimizes the number of transistors and signal routing, and can better achieve the narrow frame effect. At the same time, the use of the maintenance module 40, the first reset module 60 and the second reset module 70 in the row scanning unit 100 of this embodiment releases the residual charge in the row scanning unit 100, which can realize the reset and clearing of the entire row scanning unit 100 faster and better, so as to improve the problem that the leakage current of the oxide TFT is low and the charge is easily retained.

[0088] See also Figures 1 to 3 , Figure 3 It is a structural diagram of the second embodiment of the row scanning unit provided in this application.

[0089] The second embodiment of the row scanning unit 100 provided in the present application is basically similar in structure to the first embodiment of the row scanning unit 100 provided in the present application, except that the signal output terminal Ouput not only includes the first output terminal Ouput1, but also includes the second output terminal Ouput2, and the second output terminal Ouput2 is used to output the Nth stage transmission signal Tn.

[0090] In this embodiment, the signal output terminal Ouput includes a first output terminal Ouput1 and a second output terminal Ouput2. The first output terminal Ouput1 is used to output the Nth stage gate driving signal Gn, and the second output terminal Ouput2 is used to output the Nth stage transmission signal Tn.

[0091] The input module 10 includes a first transistor M1 , a gate of the first transistor M1 connected to the N-1th stage transmission signal Tn-1, a drain of the first transistor M1 connected to the constant voltage high potential signal VGH, and a source of the first transistor M1 connected to the first node PU.

[0092] The pull-down module 50 includes a second transistor M2 and a third transistor M3, the gate of the second transistor M2 is connected to the N-1th stage transmission signal Tn-1, the drain of the second transistor M2 is connected to the second node PD, and the source of the second transistor M2 is connected to the constant voltage low potential signal VSS; the gate of the third transistor M3 is connected to the first node PU, the drain of the third transistor M3 is connected to the second node PD, and the source of the third transistor M3 is connected to the constant voltage low potential signal VSS.

[0093] The first reset module 60 includes a fourth transistor M4 , a gate of which is connected to the (N+2)th stage transmission signal Tn+2, a drain of which is connected to the first node PU, and a source of which is connected to the constant low potential signal VSS.

[0094] The pull-down maintenance control module 30 includes a fifth transistor M5 , a gate of the fifth transistor M5 and a drain of the fifth transistor M5 are both connected to the constant high potential signal VGH, and a source of the fifth transistor M5 is connected to the second node PD.

[0095] The output module 20 includes a sixth transistor M6 and a capacitor C. The gate of the sixth transistor M6 is connected to the first node PU, the drain of the sixth transistor M6 is connected to the first clock signal CK, and the source of the sixth transistor M6 is connected to the first output terminal Ouput1. One end of the capacitor C is connected to the first node PU, and the other end is connected to the first output terminal Ouput1. In addition to the sixth transistor M6 and the capacitor C, the output module 20 also includes a twelfth transistor M12. The gate of the twelfth transistor M12 is connected to the first node PU, the drain of the twelfth transistor M12 is connected to the first clock signal CK, and the source of the twelfth transistor M12 is connected to the first node PU and connected to the second output terminal Ouput2 through the first node PU.

[0096] The maintenance module 40 includes a seventh transistor M7 and an eighth transistor M8. The gate of the seventh transistor M7 is connected to the second node PD, the drain of the seventh transistor M7 is connected to the first output terminal Ouput1, and the source of the seventh transistor M7 is connected to the constant low voltage signal VSS. The gate of the eighth transistor M8 is connected to the second node PD, the drain of the eighth transistor M8 is connected to the first node PU, and the source of the eighth transistor M8 is connected to the constant low voltage signal VSS. In addition to the seventh transistor M7 and the eighth transistor M8, the maintenance module 40 also includes a thirteenth transistor M13. The gate of the thirteenth transistor M13 is connected to the second node PD, the drain of the thirteenth transistor M13 is connected to the second output terminal Ouput2, and the source of the thirteenth transistor M13 is connected to the constant low voltage signal VSS.

[0097] The second reset module 70 includes a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The gate of the ninth transistor M9 is connected to the second clock signal CLR, the drain of the ninth transistor M9 is connected to the first node PU, and the source of the ninth transistor M9 is connected to the constant low voltage signal VSS. The gate of the tenth transistor M10 is connected to the second clock signal CLR, the drain of the tenth transistor M10 is connected to the first output terminal Ouput1, and the source of the tenth transistor M10 is connected to the constant low voltage signal VSS. The gate of the eleventh transistor M11 is connected to the second clock signal CLR, the drain of the eleventh transistor M11 is connected to the second node PD, and the source of the eleventh transistor M11 is connected to the constant low voltage signal VSS. In addition to the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11, the second reset module 70 also includes a fourteenth transistor M14. The gate of the fourteenth transistor M14 is connected to the second clock signal CLR, the drain of the fourteenth transistor M14 is connected to the second output terminal Ouput2, and the source of the fourteenth transistor M14 is connected to the constant low voltage signal VSS.

[0098] The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 are all oxide thin film transistors.

[0099] It should be understood that at least one of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 can be a transistor of other types, and no excessive restrictions are imposed here.

[0100] In this embodiment, compared to the first embodiment of the row scanning unit 100 provided in this application, the row scanning unit 100 of this embodiment has three more transistors, which can also achieve a narrow frame effect and faster and better reset and clear the row scanning unit 100. Secondly, in this embodiment, the current stage transmission signal is output from the second output terminal Ouput2, so that the first output terminal Ouput1 does not need to output the current stage transmission signal, which can optimize the output function of the first output terminal Ouput1.

[0101] The present application provides a row scanning unit 100 , which includes an input module 10 , an output module 20 , a pull-down maintenance control module 30 , a maintenance module 40 , a pull-down module 50 , a first reset module 60 , and a second reset module 70 . The input module 10 is used to pull the first node PU to a high potential according to the N-1th stage transmission signal Tn-1; N is an integer greater than 1; the output module 20 receives the first clock signal CK in response to the first node PU being a high potential to output the output signal Ouput to the signal output terminal Ouput; the pull-down maintenance control module 30 is used to pull the potential of the second node PD to a high potential; the maintenance module 40 is used to pull the first node PU to a high potential according to the N-1th stage transmission signal Tn-1; and in response to the second node PD being a high potential to pull the potential of the signal output terminal Ouput and the first node PU to a low potential; the pull-down module 50 is used to pull the potential of the second node PD to a low potential; the first reset module 60 is used to pull the potential of the first node PU to a low potential according to the N+2th stage transmission signal Tn+2; the second reset module 70 is used to pull the potentials of the first node PU, the second node PD and the signal output terminal Ouput to a low potential according to the second clock signal CLR. By connecting each module in the row scanning unit 100 to one of the first node PU and the second node PD respectively, mutual restraint of each module is achieved. While realizing the output function of the row scanning unit 100, the residual charge in the row scanning unit 100 can be released, so as to realize the reset and clearing of the entire row scanning unit 100 faster and better, thereby improving the problem of low leakage current of the oxide TFT and easy charge residue.

[0102] See also Figure 4 , Figure 4 1 is a schematic structural diagram of an embodiment of a row scanning cascade circuit provided in this application.

[0103] The present application provides a row scanning cascade circuit 200, which includes a plurality of cascaded row scanning units 100. Each row scanning unit 100 is respectively connected to a first clock signal line CK, a second clock signal line CLR, a low potential signal line VSS, and a high potential signal line VGH.

[0104] The input signal Input of each level of row scanning unit 100 is the output signal Ouput of the previous level of row scanning unit 100, and the reset signal Reset of each level of row scanning unit 100 is the output signal Ouput of the next-lower level row scanning unit 100. That is, the input signal Input of the Nth level of row scanning unit 100 is the output signal Ouput of the N-1th level of row scanning unit 100, and the reset signal Reset of the Nth level of row scanning unit 100 is the output signal Ouput of the N+2th level of row scanning unit 100. N and n are both integers greater than 1. Among them, the output signal Ouput of the N-1th level of row scanning unit 100 to the output signal Ouput of the N+2th level of row scanning unit 100 are respectively expressed as Ouput(n-1), Ouput(n), Ouput(n+1), and Ouput(n+2).

[0105] Furthermore, for the first-stage row scanning unit 100, since there is no previous-stage row scanning unit 100, a frame start signal (not shown) is used as the input signal. Since the last-stage row scanning unit 100 does not provide a reset signal Reset from the next-stage row scanning unit 100, a redundant row scanning unit (not shown) can be designed to provide the reset signal Reset to the last-stage row scanning unit 100.

[0106] See also Figures 1 to 6 , Figure 5 1 is a flow chart of an embodiment of a driving method of a row scanning unit provided in this application. Figure 6 This is the timing diagram corresponding to the row scanning unit provided in this application.

[0107] The present application provides a method for driving a row scanning unit 100. The row scanning unit 100 is the row scanning unit 100 described above. The driving timing sequence of the row scanning unit 100 sequentially includes an input phase, a first output phase, a second output phase, a reset phase, and a blank phase. The blank phase sequentially includes a first time period t1 and a second time period t2.

[0108] The specific steps of the driving method of the row scanning unit 100 are as follows:

[0109] S10: In the input stage, the N-1th stage transmission signal is at a high potential, and the first clock signal, the second clock signal and the N+2th stage transmission signal are all at a low potential; the input module pulls the potential of the first node to a high potential, and the pull-down module pulls the potential of the second node to a low potential.

[0110] Specifically, during the input phase, the N-1th stage transmission signal Tn-1 is at a high potential, and the input module 10, pull-down maintenance control module 30, and pull-down module 50 are operational. The constant high-voltage signal VGH charges the output module 20 via the input module 10, pulling the potential of the first node PU to a high potential. The pull-down module 50 quickly pulls the potential of the second node PD to a low potential. This ensures that even when the pull-down maintenance control module 30 is operational, the maintenance module 40 remains inactive, maintaining the first node PU at a high potential. It can be understood that as long as the second node PD is at a low potential, the maintenance module 40 remains inactive.

[0111] S20: In the first output stage, the first clock signal is at a high potential, the second clock signal, the N-1th stage transmission signal, and the N+2th stage transmission signal are all at a low potential; the output module outputs a high potential to the signal output terminal.

[0112] Specifically, the first clock signal CK is at a high potential, and the first node PU is maintained at a high potential, the output module 20 works, and the first clock signal CK outputs a high potential to the signal output terminal Ouput through the output module 20 .

[0113] S30: In the second output stage, the first clock signal, the second clock signal, the (N-1)th stage transmission signal, and the (N+2)th stage transmission signal are all at low potentials; the output module outputs a low potential to the signal output terminal.

[0114] Specifically, the first clock signal CK is at a low potential, and the first node PU remains at a high potential. The output module 20 works, the first clock signal CK outputs a low potential to the signal output terminal Ouput through the output module 20, and the second node PD continues to remain at a low potential.

[0115] S40: In the reset stage, the first clock signal and the N+2th level transmission signal are both high potentials, and the second clock signal and the N-1th level transmission signal are both low potentials; the first reset module pulls down the potential of the first node from a high potential to a low potential, and the pull-down module stops working so that the pull-down maintenance control module pulls up the potential of the second node from a low potential to a high potential, and the maintenance module continuously pulls down the potential of the first node and the potential of the signal output end and maintains them at a low potential.

[0116] Specifically, when the (N+2)th stage transmission signal Tn+2 is at a high level, the first reset module 60 operates, causing the potential of the first node PU to be pulled down from a high level to a low level. When the first node PU is at a low level, the output module 20 stops operating, and the pull-down maintenance control module 30 operates. The constant high-voltage signal VGH is pulled up to a high level by the pull-down maintenance control module 30, causing the maintenance module 40 to operate. At this time, the maintenance module 40 continuously pulls down and maintains the potential of the first node PU and the potential of the signal output terminal Ouput at a low level.

[0117] It should be noted that, compared to the prior art, the driving method of the row scanning unit 100 of the present application uses the reset signal Reset as the N+2-th stage transmission signal Tn+2, rather than the N+1-th stage transmission signal Tn+1. That is, in the present application, the input signal Input of each row scanning unit 100 is the output signal Ouput of the previous row scanning unit 100, and the reset signal Reset of each row scanning unit 100 is the output signal Ouput of the next-lower row scanning unit 100.

[0118] S50: In the blank phase, the first clock signal, the N-1th stage transmission signal and the N+2th stage transmission signal are all at low potential; in the first time period, the second clock signal is at high potential, and the first node and the signal output end are both discharged through the second reset module; in the second time period, the second clock signal is at low potential.

[0119] Specifically, in the first time period t1 of the blank phase, the second clock signal CLR is at a high level, the second reset module 70 works, and the first node PU and the signal output end Ouput are both discharged through the second reset module 70 until the residual charge in the row scanning unit 100 is cleared, thereby achieving the reset and clearing state of the entire row scanning unit 100.

[0120] The lengths of the first time period t1 and the second time period are not limited here. It is only necessary to ensure that the second clock signal CLR is at a low potential before the next frame is started to prevent the first node PU from being discharged through the second reset module 70 when the next frame is started.

[0121] It should be noted that the pull-down maintenance control module 30 is in an operating state during the input phase, the first output phase, the second output phase, the reset phase and the blank phase.

[0122] First specific implementation method:

[0123] When the row scanning unit 100 is the first embodiment of the row scanning unit 100 provided in this application, the driving method of the row scanning unit 100 is specifically as follows:

[0124] In the input stage, the N-1th stage transmission signal Tn-1 is at a high potential, and the first transistor M1, the second transistor M2 and the fifth transistor M5 are all turned on. The constant voltage high potential signal VGH charges the capacitor C through the first transistor M1, and pulls the potential of the first node PU to a first high potential. The second transistor M2 quickly pulls the potential of the second node PD down to a low potential, so that even if the fifth transistor M5 is turned on, the maintenance module 40 is still in a stopped working state, and the capacitor C cannot be discharged through the first node PU and the maintenance module 40 to keep the first node PU at a high potential. It can be understood that as long as the second node PD is at a low potential, the maintenance module 40 is in a stopped working state. The first node PU is at a high potential, which turns on the third transistor M3, and the third transistor M3 continuously pulls down the potential of the second node PD and keeps it at a low potential.

[0125] It should be noted that, in the driving method of the present application, transistors that are not emphasized to be turned on are all turned off.

[0126] In the first output stage, the first clock signal CK is at a high potential, the first node PU remains at a high potential, the sixth transistor M6 is turned on, and the first clock signal CK outputs a high potential to the first output terminal Ouput1 through the sixth transistor M6. Due to the generation of parasitic capacitance, the potential of the first node PU jumps from the first high potential to the second high potential. The second high potential is greater than the first high potential. The N-1 stage transmission signal Tn-1 is at a low potential, and the second transistor M2 and the first transistor M1 are turned off. Since the first node PU is at a high potential, the third transistor M3 is continuously turned on, and the third transistor M3 continues to pull down the potential of the second node PD and maintain it at a low potential.

[0127] In the second output stage, the first clock signal CK is at a low potential, and the potential of the first node PU jumps from the second high potential to the first high potential, that is, the first node PU remains at a high potential, the sixth transistor M6 and the third transistor M3 continue to be turned on, the first clock signal CK outputs a low potential to the first output terminal Ouput1 through the sixth transistor M6, and the second node PD continues to remain at a low potential.

[0128] It should be noted that the (N+1)th stage transmission signal Tn+1 is at a high level only in the second output stage.

[0129] During the reset phase, the (N+2)th stage transmission signal Tn+2 is at a high potential, the fourth transistor M4 is turned on, and the capacitor C discharges sequentially through the first node PU and the fourth transistor M4, causing the potential of the first node PU to be pulled down from a high potential to a low potential. The first node PU is at a low potential, the third transistor M3 and the sixth transistor M6 are turned off, the fifth transistor M5 is turned on, and the constant voltage high potential signal VGH pulls the second node PD to a high potential via the fifth transistor M5, causing the seventh transistor M7 and the eighth transistor M8 to be turned on. At this time, the seventh transistor M7 continuously pulls down the potential of the first output terminal Ouput1 and maintains it at a low potential, and the eighth transistor M8 continuously pulls down the potential of the first node PU and maintains it at a low potential.

[0130] In the first time period t1 of the blank phase, the second clock signal CLR is at a high potential, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all turned on, the first node PU is discharged through the ninth transistor M9, the first output end Ouput1 is discharged through the tenth transistor M10, and the second node PD is discharged through the eleventh transistor M11 until the residual charge in the circuit is cleared, thereby achieving a reset and clearing state for the entire row scanning unit 100.

[0131] It should be noted that the fifth transistor M5 is turned on in the input stage, the first output stage, the second output stage, the reset stage and the blank stage.

[0132] Second specific implementation:

[0133] When the row scanning unit 100 is the second embodiment of the row scanning unit 100 provided in this application, the driving method of the row scanning unit 100 is specifically as follows:

[0134] In the input stage, the N-1th stage transmission signal Tn-1 is at a high potential, and the first transistor M1, the second transistor M2 and the fifth transistor M5 are all turned on. The constant voltage high potential signal VGH charges the capacitor C through the first transistor M1, and pulls the potential of the first node PU to a first high potential. The second transistor M2 quickly pulls the potential of the second node PD down to a low potential, so that even if the fifth transistor M5 is turned on, the maintenance module 40 is still in a stopped working state, and the capacitor C cannot be discharged through the first node PU and the maintenance module 40 to keep the first node PU at a high potential. It can be understood that as long as the second node PD is at a low potential, the maintenance module 40 is in a stopped working state. The first node PU is at a high potential, which turns on the third transistor M3, and the third transistor M3 continuously pulls down the potential of the second node PD and keeps it at a low potential.

[0135] In the first output stage, the first clock signal CK is at a high potential, the first node PU is maintained at a high potential, the sixth transistor M6 and the twelfth transistor M12 are turned on, the first clock signal CK outputs a high potential to the first output terminal Ouput1 through the sixth transistor M6, and the first clock signal CK outputs a high potential to the second output terminal Ouput2 through the twelfth transistor M12. Due to the generation of parasitic capacitance, the potential of the first node PU jumps from the first high potential to the second high potential. The second high potential is greater than the first high potential. The N-1 stage transmission signal Tn-1 is at a low potential, and the second transistor M2 and the first transistor M1 are turned off. Since the first node PU is at a high potential, the third transistor M3 is continuously turned on, and the third transistor M3 continues to pull down the potential of the second node PD and maintains it at a low potential.

[0136] In the second output stage, the first clock signal CK is at a low potential, and the potential of the first node PU jumps from the second high potential to the first high potential, that is, the first node PU remains at a high potential, the twelfth transistor M12, the sixth transistor M6 and the third transistor M3 continue to be turned on, the first clock signal CK outputs a low potential to the first output terminal Ouput1 through the sixth transistor M6, and the first clock signal CK outputs a low potential to the second output terminal Ouput2 through the twelfth transistor M12, and the second node PD continues to maintain a low potential.

[0137] It should be noted that the (N+1)th stage transmission signal Tn+1 is at a high level only in the second output stage.

[0138] During the reset phase, the N+2th stage transmission signal Tn+2 is at a high potential, the fourth transistor M4 is turned on, and the capacitor C discharges sequentially through the first node PU and the fourth transistor M4, causing the potential of the first node PU to be pulled down from a high potential to a low potential. Since the first node PU is at a low potential, the third transistor M3 and the sixth transistor M6 are turned off, the fifth transistor M5 is turned on, and the constant voltage high potential signal VGH pulls the second node PD to a high potential via the fifth transistor M5, causing the seventh transistor M7, the eighth transistor M8, and the thirteenth transistor M13 to be turned on. At this time, the seventh transistor M7 continuously pulls down the potential of the first output terminal Ouput1 and maintains it at a low potential, the eighth transistor M8 continuously pulls down the potential of the first node PU and maintains it at a low potential, and the thirteenth transistor M13 continuously pulls down the potential of the second output terminal Ouput2 and maintains it at a low potential.

[0139] In the first time period t1 of the blank phase, the second clock signal CLR is at a high potential, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11 and the fourteenth transistor M14 are all turned on, the first node PU is discharged through the ninth transistor M9, the first output end Ouput1 is discharged through the tenth transistor M10, the second node PD is discharged through the eleventh transistor M11, and the second output end Ouput2 is discharged through the fourteenth transistor M14, until the residual charge in the row scanning unit 100 is cleared, thereby achieving a reset and clearing state of the entire row scanning unit 100.

[0140] It should be noted that the fifth transistor M5 is turned on in the input stage, the first output stage, the second output stage, the reset stage and the blank stage.

[0141] The above is only an implementation method of the present application and does not limit the scope of patent protection of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present application.

Claims

1. A row scanning unit, characterized in that: The row scanning unit includes: An input module, configured to transmit a signal according to the N-1th stage to pull the first node to a high potential; N is an integer greater than 1; an output module, in response to the first node being at a high potential, receiving a first clock signal to output an output signal to a signal output terminal; A pull-down maintenance control module, configured to pull the potential of the second node up to a high potential; a maintaining module, in response to the second node being at a high potential, to pull down the potentials of the signal output terminal and the first node to a low potential; a pull-down module, configured to pull down the potential of the second node to a low potential; a first reset module, configured to pull down the potential of the first node to a low potential according to the N+2th stage transmission signal; a second reset module, configured to pull down the potentials of the first node, the second node and the signal output end to a low potential according to a second clock signal; The driving timing sequence of the row scanning unit includes an input phase, a first output phase, a second output phase, a reset phase and a blank phase in sequence; the blank phase includes a first time period and a second time period in chronological order; In the input stage, the N-1th stage transmission signal is at a high potential, and the first clock signal, the second clock signal, and the N+2th stage transmission signal are all at a low potential; the input module pulls the potential of the first node to a high potential, and the pull-down module pulls the potential of the second node to a low potential; In the first output stage, the first clock signal is at a high level, the second clock signal, the N-1th stage transmission signal, and the N+2th stage transmission signal are all at a low level; the output module outputs a high level to the signal output terminal; In the second output stage, the first clock signal, the second clock signal, the N-1th stage transmission signal, and the N+2th stage transmission signal are all at low potentials; the output module outputs a low potential to the signal output terminal; In the reset phase, the first clock signal and the (N+2)th stage transmission signal are both at high potentials, and the second clock signal and the (N-1)th stage transmission signal are both at low potentials; the first reset module pulls down the potential of the first node from a high potential to a low potential, the pull-down module stops working so that the pull-down maintenance control module pulls up the potential of the second node from a low potential to a high potential, and the maintenance module continuously pulls down the potential of the first node and the potential of the signal output end and maintains them at a low potential; In the blank phase, the first clock signal, the N-1th level transmission signal and the N+2th level transmission signal are all at low potential; in the first time period, the second clock signal is at high potential, and the first node and the signal output end are both discharged through the second reset module; in the second time period, the second clock signal is at low potential.

2. The row scanning unit according to claim 1, wherein: The control end of the input module is connected to the N-1th stage transmission signal, the input end of the input module is connected to the constant voltage high potential signal, and the output end of the input module is connected to the first node; The control end of the output module is connected to the first node, the input end of the output module is connected to the first clock signal, and the output end of the output module is connected to the signal output end; The control end of the pull-down maintenance control module is connected to the constant voltage high potential signal, the input end of the pull-down maintenance control module is connected to the constant voltage high potential signal, and the output end of the pull-down maintenance control module is connected to the second node; The control end of the maintenance module is connected to the second node, the input end of the maintenance module is connected to the signal output end and the first node; the output end of the maintenance module is connected to a constant voltage low potential signal; The control end of the pull-down module is connected to the first node and the N-1th stage transmission signal, the input end of the pull-down module is connected to the second node, and the output end of the pull-down module is connected to the constant voltage low potential signal; The control end of the first reset module is connected to the N+2th stage transmission signal, the input end of the first reset module is connected to the first node, and the output end of the first reset module is connected to the constant voltage low potential signal; The control end of the second reset module is connected to the second clock signal, the input end of the second reset module is connected to the first node and the signal output end, and the output end of the second reset module is connected to the constant voltage low potential signal.

3. The row scanning unit according to claim 1, wherein: The input module includes a first transistor, the gate of the first transistor is connected to the N-1th stage transmission signal, the drain of the first transistor is connected to the constant voltage high potential signal, and the source of the first transistor is connected to the first node; The pull-down module includes a second transistor and a third transistor, wherein the gate of the second transistor is connected to the N-1th stage transmission signal, the drain of the second transistor is connected to the second node, and the source of the second transistor is connected to a constant voltage low potential signal; the gate of the third transistor is connected to the first node, the drain of the third transistor is connected to the second node, and the source of the third transistor is connected to the constant voltage low potential signal; The first reset module includes a fourth transistor, a gate of the fourth transistor is connected to the (N+2)th stage transmission signal, a drain of the fourth transistor is connected to the first node, and a source of the fourth transistor is connected to the constant low-potential signal; The pull-down maintenance control module includes a fifth transistor, a gate of the fifth transistor and a drain of the fifth transistor are both connected to the constant voltage high potential signal, and a source of the fifth transistor is connected to the second node.

4. The row scanning unit according to claim 3, characterized in that: The signal output end includes a first output end, and the first output end is used to output the Nth stage gate driving signal.

5. The row scanning unit according to claim 4, characterized in that: The output module includes a sixth transistor and a capacitor, wherein the gate of the sixth transistor is connected to the first node, the drain of the sixth transistor is connected to the first clock signal, and the source of the sixth transistor is connected to the first output terminal; one end of the capacitor is connected to the first node, and the other end is connected to the first output terminal; The maintaining module includes a seventh transistor and an eighth transistor, wherein the gate of the seventh transistor is connected to the second node, the drain of the seventh transistor is connected to the first output terminal, and the source of the seventh transistor is connected to the constant low-voltage signal; The gate of the eighth transistor is connected to the second node, the drain of the eighth transistor is connected to the first node, and the source of the eighth transistor is connected to the constant low potential signal; The second reset module includes a ninth transistor, a tenth transistor, and an eleventh transistor, wherein the gate of the ninth transistor is connected to the second clock signal, the drain of the ninth transistor is connected to the first node, and the source of the ninth transistor is connected to the constant low-potential signal; The gate of the tenth transistor is connected to the second clock signal, the drain of the tenth transistor is connected to the first output terminal, and the source of the tenth transistor is connected to the constant low-voltage signal; the gate of the eleventh transistor is connected to the second clock signal, the drain of the eleventh transistor is connected to the second node, and the source of the eleventh transistor is connected to the constant low-voltage signal.

6. The row scanning unit according to claim 5, characterized in that: The signal output end further includes a second output end, and the second output end is used to output the Nth stage transmission signal.

7. The row scanning unit according to claim 6, characterized in that: The output module further includes a twelfth transistor, wherein a gate of the twelfth transistor is connected to the first node, a drain of the twelfth transistor is connected to the first clock signal, and a source of the twelfth transistor is connected to the first node and is connected to the second output terminal through the first node; The maintaining module further includes a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the second node, a drain of the thirteenth transistor is connected to the second output terminal, and a source of the thirteenth transistor is connected to the constant low-potential signal; The second reset module further includes a fourteenth transistor, a gate of the fourteenth transistor is connected to the second clock signal, a drain of the fourteenth transistor is connected to the second output terminal, and a source of the fourteenth transistor is connected to the constant low-potential signal.

8. The row scanning unit according to claim 7, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor and the fourteenth transistor are all oxide thin film transistors.

9. A row scanning cascade circuit, characterized in that: The invention comprises a plurality of row scanning units according to any one of claims 1 to 8.

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