Methods and entities for identification

Abstract

An identification method 20 includes: - sending at least one request 22 for acquiring data to a chip 14 by an entity 12; - receiving data 26 from the chip by the entity; and - identifying a lineage associated with the chip by the entity based on the received data.

Description

Technical Field

[0001] This invention generally relates to authentication methods.

[0002] This invention also relates to identifying entities. Background Technology

[0003] It is known that a chip is authenticated by sending a challenge to a chip with Physically Unclonable Functionality (PUF) and receiving a corresponding response. The chip can only be authenticated if the response is a predetermined reference response.

[0004] However, this existing technological solution means that, during chip production or personalization, all responses for all chips must be registered in a database in order to identify such registered chips. Furthermore, since this operation involves online, real-time registration, such registration needs to be performed securely in a secure environment during time-critical procedures.

[0005] A solution is needed that allows for reducing the time required to perform such identification and thus reducing the corresponding costs. Summary of the Invention

[0006] This invention proposes a solution that meets the above requirements by providing an identification method.

[0007] According to the present invention, the method includes:

[0008] - An entity sends at least one request to the chip to obtain data;

[0009] - Data is received from the chip by the entity; and

[0010] - The entity identifies the family associated with the chip based on the received data.

[0011] The principle of this invention is that an entity such as a server identifies a group or family of N chips. N is greater than or equal to 2.

[0012] Instead of using a mapping between a chip and a single identification chip, there are N chips mapped to the same family.

[0013] Therefore, no registration is required for the individual reference data that allows for the identification of the relevant chips.

[0014] It is possible to identify all chips in a family using only one chip per family.

[0015] This significantly reduces the time required to produce or personalize related chips.

[0016] Unlike the solutions of the prior art described above, the solution of the present invention does not require registering one or more reference responses for each chip to identify the chip.

[0017] Unlike the solutions of the prior art described above, the solution of the present invention allows for a reduction in the time and corresponding costs of manufacturing or customizing chips of a given family.

[0018] According to another aspect, the present invention is an identification entity.

[0019] According to the present invention, the entity is configured as follows:

[0020] - Send at least one request to the chip to obtain data;

[0021] - Receive data from the chip; and

[0022] - Identify the family lineage associated with the chip based on the received data.

[0023] The entity may include a local chip host device and / or a (remote) server. Attached Figure Description

[0024] Additional features and advantages of the invention will become apparent from the detailed description of preferred embodiments thereof, which is given by way of indicative rather than limiting example in conjunction with the following drawings:

[0025] - Figure 1 In particular, according to the simplified diagram of the present invention, it has a server and a chip as entities, the server being adapted to send a request to the chip to obtain data, receive data from the chip as a response to the request, and identify the family associated with the chip based on the received data;

[0026] - Figure 2 According to a specific embodiment of the invention Figure 1 The message flow between the server and the chip allows the server to determine the probability distribution of responses based on those responses, and to identify the chip-related family based on that probability distribution; and

[0027] - Figure 3 An example of a specific reference Gaussian probability distribution of the response provided by the chip according to an embodiment of the present invention is shown, such that... Figure 2 The server identification is related to the family of chips. Detailed Implementation

[0028] The following discussion considers the case in which the identification method of the present invention is implemented by a server and a chip as physical entities.

[0029] This invention does not impose any restrictions on the type of chip.

[0030] The chip may or may not be included in the security element (or SE).

[0031] In this description, an SE is a smart object comprising one or more chips that act as one or more tamper-proof components to protect access to stored and / or processed data and are designed to transmit data with one or more external devices (e.g., an SE host device).

[0032] The SE (Secure Enclosure) may include a chip integrated into the device, such as a secure enclosed space, or a chip communicatively coupled to the device serving as the SE host device and included in a smart card (or other medium). The SE may be attached to its host device or removable from it. As a removable SE, the SE may include a Secure Removable Module (or SRM), a USB (Universal Serial Bus) type smart dongle, a (micro)secure digital (or SD) type card or a multimedia type card (or MMC), or any format card to be coupled to the host device.

[0033] The embodiments described below are for illustrative purposes only and are not intended to limit the scope of the invention.

[0034] Figure 1 The server (or SR) 12 and chip 14 are shown schematically as entities.

[0035] SR 12 is hosted by one or more computer devices, each computer device including data processing components such as one or more controllers, a central processing unit (or CPU) and / or one or more processors (not shown), and one or more input / output (or I / O) interfaces for exchanging data with the outside.

[0036] SR 12 includes (or is connected to) one or more SR memories 122 as data storage components.

[0037] SR 12 is configured to send one or more requests to acquire data to chip 14.

[0038] Each request preferably includes data.

[0039] SR 12 is configured to receive data from chip 14 as a request response.

[0040] SR 12 is adapted to identify the family associated with chip 14 based on the received data.

[0041] SR 12 is connected to chip 14 via bidirectional link 13.

[0042] Chip 14 includes one or more (hardware) (micro)processors, one or more (micro)controllers and / or CPUs as computing devices, as data processing components, and includes or is connected to I / O interfaces, all of which are internally connected to each other via an internal bidirectional data bus.

[0043] Chip 14 may include one or more memories as data storage components.

[0044] The chip I / O interface may include one or more wired and / or contactless interfaces to exchange with SR 12 via one or more contact (or CT) and / or contactless (or CTL) type links 13.

[0045] In this description, the adjective "CTL" specifically indicates that the communication component in question communicates using one or more short-range (or SR) radio frequency (or RF) links. The SR RF can be set at approximately 13.56 MHz.

[0046] The chip I / O interface may include one or more wireless interfaces for exchanging with SR 12 over one or more long-range (or LR) type RF links 13 via one or more communication networks (not shown). The LR RF may be set in hundreds or thousands of megahertz, such as approximately 850, 900, 1800, 1900 and / or 2100 MHz.

[0047] Chip 14 is configured to receive one or more requests for data acquisition from SR 12.

[0048] Each request preferably includes data.

[0049] Chip 14 is configured to send data to SR 12 in response to each request.

[0050] Chip 14 preferably includes one (or more) PUF type elements 142.

[0051] One or more PUF-type elements allow for the provision of at least a partial response based on the received request.

[0052] The design or implementation of a Physically Unclonable Function (PUF) is described in WO 2019 / 081138 A1, published on May 2, 2019, entitled "Method of implementing a Physically Unclonable Function". An interesting feature to utilize is the margin check described in this patent document. In short, by defining an edge level to distinguish between "0" and "1", a certain number of "0"s and "1"s can be expected from the PUF response. The theoretical distribution of PUF technology is a Gaussian probability distribution, where around the mean, the number of "0"s and "1"s is equal, i.e., 50% each. For all PUFs following this Gaussian probability distribution, the number of "0"s relative to the number of "1"s can be probabilistically guessed relative to the predefined edge level. To illustrate the Gaussian probability distribution, it is assumed that the chip family, denoted by fx, has a 40% edge level defined with respect to the symbol 1. Figure 3 The Gaussian probability distribution thus obtained is shown. Then, for all chips included in family fx, the theoretical proportion with "0" (or "1") as the original PUF value (or RPVx) is approximately 63% (or 37%).

[0053] To identify a chip (i.e., to determine if it belongs to a given family of chips), a specific edge level must be selected, and the theoretical (or actual) number of "1"s and "0"s to be obtained at that parameter must be recorded on the SR 12 side. The common part of the RPVx becomes the identity of a family, rather than the identity of the chip.

[0054] Therefore, only one chip 14 is needed per family to register the identity of the relevant family fx.

[0055] For example, RPVx from a chip in the same family as the first family can be distributed according to a first Gaussian probability distribution N(μ1, σ1), while for another chip in the second family, RPVy can be distributed according to a first Gaussian probability distribution N(μ2, σ2).

[0056] As an alternative to or supplement to one or more PUF elements, chip 14 includes one or more random access memories (or RAM). The RAM allows for at least a partial response based on the received request.

[0057] As an alternative to or supplement to one or more PUF elements, chip 14 includes one or more trigger elements. These trigger elements allow for at least a partial response based on a received request.

[0058] Figure 2The message flow 20, which involves SR 12 and chip 14, is shown to identify the family lineage associated with chip 14.

[0059] Assume that SR 12 has previously registered one or more reference probability distributions. Each reference Gaussian probability distribution includes, for example, a Gaussian probability distribution with a predetermined mean μ and a predetermined standard deviation σ.

[0060] SR 12 sends a request to chip 14 22 to obtain a response to the challenge, the request including or accompanying the challenge.

[0061] The query (value) includes a value associated with one or more parameters. These parameters (one or more) include a predetermined clock, a predetermined current, and / or a predetermined voltage.

[0062] Chip 14 uses the (received) challenge to generate response 24.

[0063] Chip 14 sends response 26 to SR 12 as a request response.

[0064] These steps 22 (sending the request), 24 (generating the response), and 26 (sending the response) are repeated at least a predetermined threshold number of times.

[0065] Thresholds include, for example, 32.

[0066] SR 12 uses these responses to determine the probability distribution of the 210 response.

[0067] SR 12 checks whether the probability distribution of the 212 response matches a predetermined reference probability distribution.

[0068] SR 12 only identifies the family associated with chip 14 when the probability distribution of the response matches the reference probability distribution.

[0069] Otherwise, that is, if the probability distribution of the response does not match any reference probability distribution, then SR 12 does not identify any lineage of 213 associated with chip 14.

[0070] This chip family identification method can be used to identify the wafer to which the chip belongs, the manufacturing plant that produced the chip, the company that purchased the chip, products that integrate or include the chip, and / or the country that manufactured the chip.

[0071] The solution of this invention allows for the identification of chip families.

[0072] The solution of the present invention is simple to implement and therefore inexpensive.

[0073] The solution of this invention is very safe.

Claims

1. An identification method, the method comprising: The entity sends at least one request to the chip to obtain data; The entity receives data from the chip; as well as The entity identifies the family associated with the chip based on the received data. The method also includes: a) The entity sends a request to the chip to obtain a response to a challenge, the request including or accompanied by the challenge; b) The chip generates a response using the challenge; c) The entity receives the response from the chip as a request response; d) Repeat the following steps at least a predetermined threshold number of times: a) receive a request, b) generate a response, and c) send the response; e) The entity determines the probability distribution of the response based on the response; f) The entity detects whether the probability distribution of the response matches a predetermined reference probability distribution; and g) If the probability distribution of the response matches the reference probability distribution, then the entity identifies the family associated with the chip. The chip includes at least one physically unclonable functional PUF element, which provides at least a portion of the response.

2. The method according to claim 1, wherein, The query includes a set of at least one value associated with at least one predetermined parameter.

3. The method according to claim 2, wherein, The at least one parameter includes at least one element from the following groups: - Scheduled clock; - Preset current; - Predetermined voltage.

4. The method according to claim 1, wherein, The chip includes at least one random access memory (RAM) element, which provides at least a portion of the response.

5. The method according to claim 1, wherein, The chip includes at least one trigger element that provides at least a portion of the response.

6. The method according to claim 1, wherein, The chip family identification includes the identification of at least one element from the following groups: The chip to which the chip belongs; The manufacturing plant that produced the chip; The company that purchased the chip; Products integrating the aforementioned chip; The country that manufactured the chip.

7. An authentication entity configured as follows: Send at least one request to the chip to acquire data; Receive data from the chip; and The family lineage associated with the chip is identified based on the received data. The entity is also configured as follows: a) The entity sends a request to the chip to obtain a response to a challenge, the request including or accompanied by the challenge; b) The chip generates a response using the challenge; c) The entity receives the response from the chip as a request response; d) Repeat the following steps at least a predetermined threshold number of times: a) receive a request, b) generate a response, and c) send the response; e) The entity determines the probability distribution of the response based on the response; f) The entity detects whether the probability distribution of the response matches a predetermined reference probability distribution; as well as g) If the probability distribution of the response matches the reference probability distribution, then the entity identifies the family associated with the chip. The chip includes at least one physically unclonable functional PUF element, which provides at least a portion of the response.

Images