System and method for evaluating the reliability of semiconductor die packages

Abstract

A system and method for evaluating the reliability of semiconductor die packages is configured to sort a plurality of semiconductor dies based on a comparison of an In-Line Part Average Test (I-PAT) score of each of a plurality of semiconductor dies with a known good die (KGD) subsystem to a plurality of I-PAT score thresholds, wherein semiconductor die data includes the I-PAT score of each of the plurality of semiconductor dies, wherein the I-PAT score represents a weighted defect rate of the corresponding semiconductor die. The semiconductor dies may be filtered before sorting to remove risky semiconductor dies. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data regarding the sorted plurality of semiconductor dies to a plurality of semiconductor die package manufacturer subsystems.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 149,367, filed on February 15, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to semiconductor devices, and more particularly to systems and methods for evaluating the reliability of semiconductor die packages. Background Art

[0004] The fabrication of semiconductor devices may typically require hundreds or thousands of processing steps to form a functional device. During these processing steps, various inspection and / or metrology measurements may be performed to identify defects and / or monitor various parameters on the device, and electrical tests may be performed instead of or in addition to the various inspection and / or metrology measurements to confirm or assess the functionality of the device. However, while some detected defects and metrology errors may be significant enough to clearly indicate device failure, smaller variations may cause early reliability failures of the device after exposure to its operating environment. Risk-averse users of semiconductor devices (e.g., such as automotive, military, aerospace, and medical applications, for example) are now looking for failure rates in the parts per billion (PPB) range, exceeding current parts per million (PPM) levels. As the demand for semiconductor devices in automotive, military, aerospace, and medical applications continues to increase, assessing the reliability of semiconductor die packages from which semiconductor die are made is key to meeting these industrial needs. Therefore, it is desirable to provide systems and methods for assessing the reliability of semiconductor die packages. Summary of the invention

[0005] According to one or more embodiments of the present disclosure, a system is disclosed. In one illustrative embodiment, the system includes a controller communicatively coupled to a plurality of semiconductor die supplier subsystems and a plurality of semiconductor die packaging manufacturer subsystems. In another illustrative embodiment, the controller includes one or more processors and a memory. In another illustrative embodiment, the memory is configured to store a set of program instructions. In another illustrative embodiment, the one or more processors are configured to execute program instructions, so that the one or more processors receive semiconductor die data about a plurality of semiconductor die from the plurality of semiconductor die supplier subsystems. In another illustrative embodiment, the semiconductor die data includes an in-line part average test (I-PAT) score for each of the plurality of semiconductor die. In another illustrative embodiment, the I-PAT score represents a weighted defect rate of the corresponding semiconductor die. In another illustrative embodiment, the one or more processors are configured to execute program instructions, so that the one or more processors sort the plurality of semiconductor die with a known good die (KGD) subsystem based on a comparison of the I-PAT score of each of the plurality of semiconductor die with a plurality of I-PAT score thresholds. In another illustrative embodiment, the one or more processors are configured to execute program instructions causing the one or more processors to transmit semiconductor die reliability data regarding the sorted plurality of semiconductor dies to the plurality of semiconductor die packaging manufacturer subsystems.

[0006] According to one or more embodiments of the present disclosure, a method is disclosed. In one illustrative embodiment, the method may include, but is not limited to, receiving semiconductor die data about a plurality of semiconductor dies from a plurality of semiconductor die supplier subsystems via a controller. In another illustrative embodiment, the semiconductor die data includes an in-line part average test (I-PAT) score for each of the plurality of semiconductor dies. In another illustrative embodiment, the I-PAT score represents a weighted defect rate of the corresponding semiconductor die. In another illustrative embodiment, the method may include, but is not limited to, sorting the plurality of semiconductor dies based on a comparison of the I-PAT score of each of the plurality of semiconductor dies with a plurality of I-PAT score thresholds using a known good die (KGD) subsystem via the controller. In another illustrative embodiment, the method may include, but is not limited to, transmitting semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packaging manufacturer subsystems via the controller.

[0007] According to one or more embodiments of the present disclosure, a system is disclosed. In one illustrative embodiment, the system includes a plurality of semiconductor die supplier subsystems. In another illustrative embodiment, the system includes a plurality of semiconductor die packaging manufacturer subsystems. In another illustrative embodiment, the system includes a controller communicatively coupled to the plurality of semiconductor die supplier subsystems and the plurality of semiconductor die packaging manufacturer subsystems. In another illustrative embodiment, the controller includes one or more processors and a memory. In another illustrative embodiment, the memory is configured to store a set of program instructions. In another illustrative embodiment, the one or more processors are configured to execute program instructions so that the one or more processors receive semiconductor die data about a plurality of semiconductor die from the plurality of semiconductor die supplier subsystems. In another illustrative embodiment, the semiconductor die data includes an in-line part average test (I-PAT) score for each of the plurality of semiconductor die. In another illustrative embodiment, the I-PAT score represents a weighted defect rate of the corresponding semiconductor die. In another illustrative embodiment, the one or more processors are configured to execute program instructions, thereby causing the one or more processors to sort the plurality of semiconductor dies with a known good die (KGD) subsystem based on a comparison of the I-PAT score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds. In another illustrative embodiment, the one or more processors are configured to execute program instructions, thereby causing the one or more processors to transmit semiconductor die reliability data regarding the sorted plurality of semiconductor dies to the plurality of semiconductor die packaging manufacturer subsystems.

[0008] It should be understood that both the foregoing summary and the following detailed description are exemplary and illustrative only and do not necessarily limit the invention as claimed.The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the summary serve to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Many advantages of the present disclosure may be better understood by those skilled in the art by referring to the accompanying drawings, in which:

[0010] Figure 1A is a block diagram view of a system for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure;

[0011] Figure 1B is a block diagram of a system for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure;

[0012] Figure 2Ais a block diagram of a semiconductor die supplier subsystem or a semiconductor die package manufacturer subsystem for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure;

[0013] Figure 2B is a block diagram of a semiconductor die supplier subsystem or a semiconductor die package manufacturer subsystem for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure;

[0014] Figure 3 is a conceptual diagram of a system for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure;

[0015] Figure 4A is a flow chart illustrating steps performed in a method for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure;

[0016] Figure 4B is a flow chart illustrating steps performed in a method for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure; and

[0017] Figure 4C is a flow chart illustrating steps performed in a method for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] Reference will now be made in detail to the disclosed subject matter illustrated in the accompanying drawings. The present disclosure has been particularly shown and described with respect to specific embodiments and specific features thereof. The embodiments described herein are to be regarded as illustrative and not restrictive. It will be readily apparent to one of ordinary skill in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present disclosure.

[0019] The fabrication of semiconductor devices may typically require hundreds or thousands of processing steps to form a functional device. During these processing steps, various inspection and / or metrology measurements may be performed to identify defects and / or monitor various parameters on the device, and electrical testing may be performed instead of or in addition to the various inspection and / or metrology measurements to confirm or assess the functionality of the device. For example, a semiconductor die manufacturer may employ electrical testing and a baseline Pareto method to identify defects and / or monitor various parameters on the device. For example, electrical testing and a baseline Pareto method may be employed to find "killer" defects that may lead to immediate device failure.

[0020] However, while some detected defects and metrology errors may be significant enough to clearly indicate device failure, smaller variations may cause early reliability failures of the device after exposure to its operating environment. For example, semiconductor die manufacturers may also employ part average testing (PAT) methods (including but not limited to in-line part average testing (I-PAT)) to locate latent reliability defects (LRDs) (or reliability defects or latent defects, for purposes of this disclosure). For example, an LRD may be a minor defect that may not cause a failure during manufacturing / testing or may not cause an immediate device failure during operation (e.g., compared to a fatal defect), but may cause an early failure of the device during operation when used in a working environment. An example of determining LRDs during semiconductor device fabrication that can be found is U.S. patent application Ser. No. 17 / 151,583, filed on Jan. 18, 2021, the entire contents of which are incorporated herein. Exemplary uses of PAT methods (including but not limited to I-PAT methods) during semiconductor device fabrication can be found in U.S. Patent No. 10,761,128, issued on September 1, 2020, and U.S. Patent Application No. 17 / 101,856, filed on November 23, 2020, the entire contents of each of which are incorporated herein.

[0021] Risk-averse users of semiconductor devices, such as automotive, military, aerospace, and medical applications, for example, are now looking for failure rates in the parts-per-billion (PPB) range, exceeding current parts-per-million (PPM) levels. As the demand for semiconductor devices in automotive, military, aerospace, and medical applications continues to increase, evaluating the reliability of the semiconductor die packages from which the semiconductor dies are fabricated is key to meeting these industry demands.

[0022] As the expansion of Moore's Law slows, semiconductor chip designers may seek additional or alternative ways to improve device performance in various stages of semiconductor die package fabrication while continuing to meet or exceed desired failure rates. One such stage includes back-end of line (BEOL) packaging, where a variety of 2.5D (or 2.5 dimensional) and / or 3D (or three dimensional) die stacking techniques may be employed. For example, the techniques may be used to reduce overall package size, lower power consumption, and improve bandwidth of a system including a semiconductor die package, or the like.

[0023] The complexity of semiconductor die packages can range from memory packages or image sensors stacked on logic to function-specific chiplet components from multiple suppliers (e.g., manufacturers, distributors, or the like) to heterogeneous integration in high-performance computer systems. As complexity increases, the semiconductor die count in a semiconductor die package almost always increases rapidly as well. In addition to the (usually expensive) interconnect costs, the aggregate cost of all semiconductor dies in a semiconductor die package also results in a high-cost semiconductor die package.

[0024] Testing semiconductor die packages may require integration of all semiconductor dies before the semiconductor die package can be tested for full functionality. However, in the event that even a single die or chiplet in a semiconductor die package fails, the semiconductor die package typically still fails because rework is typically not feasible due to the integrated nature of the semiconductor die. Additionally, testing semiconductor dies is increasingly difficult due to the use of "bare" dies, or dies without molded packages or leads. Without molded packages or leads, bare dies may be difficult to probe or test, which may limit the evaluation of each die during various electrical tests before or after the semiconductor die is integrated into the semiconductor die package.

[0025] Previous methods for selecting semiconductor dies for integration into semiconductor die packages involve relying on known mature device designs and electrical test results to increase the probability that the semiconductor die integrated into the package will be a good semiconductor die. However, based on the semiconductor die yield and test coverage, electrical testing alone allows a predictable number of failed dies to escape (e.g., thus falsely pass inspection). The cumulative effect of escapes will increase with the increase in the number of semiconductor dies in the semiconductor die package, thus degrading the yield of the completed semiconductor die package. In addition, due to the lack of package leads, electrical testing is not easily applicable to technologies that employ bare semiconductor dies, resulting in poor screening of semiconductor dies for low reliability examples. In addition, selected semiconductor dies (e.g., advanced design rule device semiconductor dies) in semiconductor die packages may have less process maturity, thereby requiring additional screening or electrical testing to ensure reliability, which increases cost and production downtime. Furthermore, semiconductor package integrators may not be able to assess the relative reliability scores of semiconductor dies in semiconductor die packages using electrical testing, where the semiconductor dies are sourced from multiple suppliers, such that the integrators may be unable to reject high risk semiconductor dies and / or produce semiconductor die packages with varying target reliability levels and price points.

[0026] Figures 1A to 4C Systems and methods for evaluating the reliability of semiconductor die packages in accordance with one or more embodiments of the present disclosure are generally described.

[0027] Embodiments of the present disclosure relate to systems and methods for evaluating the reliability of semiconductor die packages.

[0028] In particular, embodiments of the present disclosure relate to semiconductor die packaging manufacturers reducing yield loss (and thus reducing costs, reducing manufacturing downtime, or the like) by relying on the determination of known good die (KGD) for use in semiconductor die packaging.

[0029] In addition, embodiments of the present disclosure relate to implementing an I-PAT method to generate a defect rate score or ranking (e.g., weighted or unweighted) for one or more semiconductor dies across one or more semiconductor distributors. For example, the defect rate score or ranking may be utilized during semiconductor die packaging in addition to or in lieu of the score or ranking used during semiconductor die fabrication. In addition, the defect rate score or ranking may be utilized to improve the assessment of KGDs or die packaging containing KGDs. Furthermore, the defect rate score or ranking may be utilized to filter or reject risky semiconductor dies from semiconductor die packaging.

[0030] In addition, embodiments of the present disclosure relate to pairing semiconductor die or semiconductor die sub-packages with similar reliability risk profiles. For example, semiconductor die or semiconductor die sub-packages may be obtained from a semiconductor chip packaging manufacturer, and the semiconductor die may be selected and paired with other semiconductor die or semiconductor die sub-packages of similar scores or rankings to ensure that a selected reliability is met in a final semiconductor die package having a selected score or ranking.

[0031] In addition, embodiments of the present disclosure relate to classifying semiconductor die packages into different performance and / or price or value categories. For example, semiconductor die packages may be separated and provided to a selection industry based on a selection score or ranking of the semiconductor die packages.

[0032] Figures 1A to 3 A system 100 for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure is described.

[0033] Reference Figure 1A and 1B In one embodiment, system 100 includes a controller or server 102. Controller or server 102 may include one or more processors 104 configured to execute program instructions maintained on or stored in memory 106 (e.g., a memory medium, a memory device, or the like).

[0034] In this regard, the one or more processors 104 of the controller or server 102 may perform any of the various process steps described throughout this disclosure. For example, the one or more processors 104 of the controller or server 102 may be configured to receive scores for one or more semiconductor dies, rank one or more semiconductor dies, filter and sort one or more semiconductor dies, and transmit data regarding one or more filtered and sorted semiconductor dies.

[0035] In another embodiment, the system 100 includes a user interface 108 coupled (e.g., physically coupled, electrically coupled, communicatively coupled, or the like) to the controller or server 102. For example, the user interface 108 can be a separate device coupled to the controller or server 102. By way of another example, the user interface 108 and the controller or server 102 can be located within a common or shared housing. However, it should be noted herein that the controller or server 102 may not include, require, or be coupled to the user interface 108.

[0036] In another embodiment, the system 100 includes one or more die vendor subsystems 110 coupled (e.g., physically coupled, electrically coupled, communicatively coupled, or the like) to the controller or server 102. For example, the one or more die vendor subsystems 110 may transmit semiconductor die data 112 (which may be received by the controller or server 102).

[0037] In another embodiment, the system 100 includes one or more semiconductor die packaging manufacturer subsystems 114. For example, the controller or server 102 may transmit the semiconductor die reliability data 116 to the one or more semiconductor die packaging manufacturer subsystems 114.

[0038] like Figure 1A As illustrated in FIG. 1 , the semiconductor die data 112 may be directly transmitted between one or more die supplier subsystems 110 and the controller or server 102 , and / or the semiconductor die data 112 may be directly transmitted between the controller or server 102 and one or more semiconductor die packaging manufacturer subsystems 114 .

[0039] like Figure 1B1, the semiconductor die data 112 may be transmitted between the one or more die supplier subsystems 110 and the controller or server 102 via one or more auxiliary controllers or servers 118, and / or the semiconductor die data 112 may be transmitted between the controller or server 102 and the one or more semiconductor die packaging manufacturer subsystems 114 via one or more auxiliary controllers or servers 120. The one or more auxiliary controllers or servers 118, 120 may include, but are not limited to, one or more processors configured to execute program instructions maintained on a memory (e.g., a memory medium, a memory device, or the like), maintained on a user interface, or the like. The semiconductor die data 112 and / or the semiconductor die reliability data 116 may be passed through the one or more auxiliary controllers or servers 118, 120 without modification. However, it is noted herein that the one or more auxiliary controllers or servers 118 , 120 may be configured to execute program instructions to modify the semiconductor die data 112 and / or the semiconductor die reliability data 116 as they pass through the one or more auxiliary controllers or servers 118 , 120 , respectively.

[0040] The one or more semiconductor die packaging manufacturer subsystems 114 may be configured to transmit information to the one or more semiconductor die supplier subsystems 110. For example, the information may be transmitted directly between the one or more semiconductor die packaging manufacturer subsystems 114 and the one or more semiconductor die supplier subsystems 110. By way of another example, the information may be transmitted via the controller or server 102 (and potentially via one or more auxiliary controllers or servers 118, 120). In general, the information may be a design request, a design iteration as part of a feedback or feed-forward loop to resolve a defect, or the like.

[0041] Figure 2A and 2B The semiconductor die supplier subsystem 110 and / or the semiconductor die packaging subsystem 114 of the system 100 for evaluating the reliability of semiconductor die packages according to one or more embodiments of the present disclosure are illustrated. It should be noted herein that the semiconductor die supplier subsystem 110 can be configured to perform processing steps for making and / or analyzing semiconductor dies, as described throughout the present disclosure. Additionally, it should be noted herein that the semiconductor die packaging subsystem 114 can be configured to perform processing steps for making and / or analyzing semiconductor die packages, as described throughout the present disclosure.

[0042] In one embodiment, the semiconductor die supplier subsystem 110 and / or the semiconductor die packaging subsystem 114 include at least one inspection tool 200 (e.g., an in-line sample analysis tool) for detecting defects in one or more layers of the sample 202. The semiconductor die supplier subsystem 110 and / or the semiconductor die packaging subsystem 114 may generally include any number or type of inspection tools 200. For example, the inspection tool 200 may include an optical inspection tool configured to detect defects based on interrogation of the sample 202 with light from any source, such as, but not limited to, a laser source, a lamp source, an X-ray source, or a broadband plasma source. By way of another example, the inspection tool 200 may include a particle beam inspection tool configured to detect defects based on interrogation of the sample with one or more particle beams, such as, but not limited to, an electron beam, an ion beam, or a neutral particle beam. For example, the inspection tool 200 may include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For purposes of the present disclosure, it is noted herein that at least one inspection tool 200 may be a single inspection tool 200 or may represent a group of inspection tools 200 .

[0043] In one non-limiting example, in the case of the semiconductor die supplier subsystem 110, the sample 202 may be a semiconductor wafer of a plurality of semiconductor wafers, wherein each semiconductor wafer of the plurality of semiconductor wafers includes a plurality of layers, wherein each layer of the plurality of layers includes a plurality of semiconductor dies, wherein each semiconductor die of the plurality of semiconductor dies includes a plurality of blocks.

[0044] In another non-limiting example, in the case of the semiconductor die packaging subsystem 114 , the sample 202 may be a semiconductor die package formed of a plurality of semiconductor dies arranged on a substrate inside an advanced die package or a 3D die package in a 2.5D lateral combination of bare dies.

[0045] For the purposes of this disclosure, a defect may be considered as any deviation of a fabricated layer or a fabricated pattern in a layer from a designed characteristic, including but not limited to physical, mechanical, chemical or optical properties. In addition, a defect may be considered as any deviation of the alignment or bonding of components in a fabricated semiconductor die package. Furthermore, a defect may have any size relative to a semiconductor die or a feature thereon. In this manner, a defect may be smaller than a semiconductor die (e.g., at the scale of one or more patterned features) or may be larger than a semiconductor die (e.g., as part of a wafer-level scratch or pattern). For example, a defect may include a deviation in the thickness or composition of a sample layer before or after patterning. By another example, a defect may include a deviation in the size, shape, orientation or position of a patterned feature. By another example, a defect may include imperfections associated with a lithography and / or etching step, such as, but not limited to, a bridge (or lack thereof), a pit or a hole between adjacent structures. By another example, a defect may include a damaged portion of a sample 202, such as, but not limited to, a scratch or chip. For example, the severity of the defect (e.g., the length of a scratch, the depth of a pit, the measured magnitude or polarity of the defect, etc.) may be of importance and taken into consideration. By another example, the defect may include a foreign particle introduced to the sample 202. By another example, the defect may be a misaligned and / or misjoined package component on the sample 202. Therefore, it should be understood that the examples of defects in the present disclosure are provided for illustrative purposes only and should not be construed as limiting.

[0046] In another embodiment, the semiconductor die supplier subsystem 110 and / or the semiconductor die packaging subsystem 114 include at least one metrology tool 204 (e.g., an in-line sample analysis tool) for measuring one or more properties of the sample 202 or one or more layers thereof. For example, the metrology tool 204 may characterize properties such as, but not limited to, layer thickness, layer composition, critical dimension (CD), overlay, or lithography process parameters (e.g., illumination intensity or dose during a lithography step). In this regard, the metrology tool 204 may provide information about the fabrication of the sample 202, one or more layers of the sample 202, or one or more dies of the sample 202 that may be related to the probability of manufacturing defects that may lead to reliability issues for the resulting fabricated devices. For purposes of this disclosure, it should be noted herein that the at least one metrology tool 204 may be a single metrology tool 204 or may represent a group of metrology tools 204.

[0047] In another embodiment, the semiconductor die vendor subsystem 110 and / or the semiconductor die packaging subsystem 114 include at least one testing tool 206 for testing functionality of one or more portions of a manufactured device.

[0048] For example, the semiconductor die vendor subsystem 110 and / or the semiconductor die packaging subsystem 114 may include any number or type of electrical test tools 206a for completing preliminary probing at the wafer level. For example, the preliminary probing may not be designed to attempt to force failures at the wafer level.

[0049] By way of another example, the semiconductor die supplier subsystem 110 and / or the semiconductor die packaging subsystem 114 may include any number or type of stress testing tools 206b for testing, verifying, or otherwise characterizing properties of one or more portions of a fabricated device at any point in the manufacturing cycle. For example, the stress testing tools 206b may include, but are not limited to, pre-burn-in electrical wafer sort and final testing (e.g., e-test) or post-burn-in electrical testing configured to heat the sample 202 (e.g., an oven or other heat source), cool the sample 202 (e.g., a refrigerator or other cold source), operate the sample 202 at an improper voltage (e.g., a power supply), or the like.

[0050] In another embodiment, defects are identified using any combination of inline sample analysis tools (e.g., inspection tool 200, metrology tool 204, test tool 206 (including electrical test tool 206a and / or stress test tool 206b), or the like) after one or more processing steps (e.g., photolithography, etching, alignment, bonding, or the like) for the layers of interest in the semiconductor die and / or semiconductor die package. In this regard, defect detection at various stages of the manufacturing process may be referred to as inline defect detection.

[0051] In another embodiment, the semiconductor die vendor subsystem 110 and / or the semiconductor die packaging subsystem 114 include a controller 208. The controller 208 may include one or more processors 210 configured to execute program instructions maintained on a memory 212 (e.g., a memory medium, a memory device, or the like). Furthermore, the controller 208 may be communicatively coupled with any of the components of the semiconductor die vendor subsystem 110 and / or the semiconductor die packaging subsystem 114, including but not limited to the inspection tool 200, the metrology tool 204, the test tool 206 (including the electrical test tool 206a and / or the stress test tool 206b), or the like.

[0052] The one or more processors 210 of the controller 208, the one or more processors 104 of the controller or server 102, and / or the one or more processors of the one or more auxiliary controllers or servers 118, 120 may include any processor or processing element known in the art. For the purposes of this disclosure, the term "processor" or "processing element" may be broadly defined to encompass any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, the one or more processors 210 of the controller 208, the one or more processors 104 of the controller or server 102, and / or the one or more processors of the one or more auxiliary controllers or servers 118, 120 may include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in a memory). In one embodiment, one or more processors 210 of controller 208, one or more processors 104 of controller or server 102, and / or one or more processors of one or more auxiliary controllers or servers 118, 120 may be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a networked computer, or any other computer system configured to execute programs (which are configured to operate components of system 100 or in conjunction with components of system 100) as described throughout this disclosure.

[0053] The memory 212 of the controller 208, the memory 106 of the controller or server 102, and / or the memory of one or more auxiliary controllers or servers 118, 120 may include any storage media known in the art suitable for storing program instructions executable by the one or more processors 210 of the associated respective controller 208, the one or more processors 104 of the controller or server 102, and / or the one or more processors of the one or more auxiliary controllers or servers 118, 120. For example, the memory 212 of the controller 208, the memory 106 of the controller or server 102, and / or the memory of one or more auxiliary controllers or servers 118, 120 may include non-transitory storage media. By way of another example, the memory 212 of the controller 208, the memory 106 of the controller or server 102, and / or the memory of one or more auxiliary controllers or servers 118, 120 may include, but are not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical storage devices (e.g., magnetic disks), tapes, solid-state drives, and the like. It should be further noted that the memory 212 of the controller 208, the memory 106 of the controller or server 102, and / or the memory of one or more auxiliary controllers or servers 118, 120 may be housed in a common controller housing with the one or more processors 210. In one embodiment, the memory 212 of the controller 208, the memory 106 of the controller or server 102, and / or the memory of one or more auxiliary controllers or servers 118, 120 may be remotely located relative to the physical location of the one or more processors 210 of the respective controller 208, the one or more processors 104 of the controller or server 102, and / or the one or more processors of the one or more auxiliary controllers or servers 118, 120. For example, the one or more processors 210 of the respective controller 208, the one or more processors 104 of the controller or server 102, and / or the one or more processors of the one or more auxiliary controllers or servers 118, 120 may access a remote memory (e.g., a server) that is accessible via a network (e.g., the Internet, an intranet, and the like).

[0054] In another embodiment, the semiconductor die vendor subsystem 110 and / or the semiconductor die packaging subsystem 114 include a user interface 214 coupled (e.g., physically coupled, electrically coupled, communicatively coupled, or the like) to the controller 208. For example, the user interface 214 may be a separate device coupled to the controller 208. By way of another example, the user interface 214 and the controller 208 may be located within a common or shared housing. However, it should be noted herein that the controller 208 may not include, require, or be coupled to the user interface 214.

[0055] The user interface 214 of the controller 208, the user interface 108 of the controller or server 102, and / or the user interface coupled to one or more auxiliary controllers or servers 118, 120 may include, but is not limited to, one or more desktop computers, laptop computers, tablet computers, and the like. The user interface 214 of the controller 208, the user interface 108 of the controller or server 102, and / or the user interface coupled to one or more auxiliary controllers or servers 118, 120 may include a display for displaying data of the system 100 to a user. The display of the user interface 214 of the controller 208, the user interface 108 of the controller or server 102, and / or the user interface coupled to one or more auxiliary controllers or servers 118, 120 may include any display known in the art. For example, the display may include, but is not limited to, a liquid crystal display (LCD), an organic light emitting diode (OLED) based display, or a CRT display. Those skilled in the art will recognize that any display device capable of being integrated with the user interface 214 of the controller 208, the user interface 108 of the controller or server 102, and / or a user interface coupled to one or more auxiliary controllers or servers 118, 120 is suitable for implementation in the present disclosure. In another embodiment, the user may input selections and / or instructions in response to data displayed to the user via a user input device of the user interface 214 of the controller 208, the user interface 108 of the controller or server 102, and / or a user interface coupled to one or more auxiliary controllers or servers 118, 120.

[0056] In one embodiment, the semiconductor die supplier subsystem 110 and / or the semiconductor die packaging subsystem 114 include at least one semiconductor manufacturing tool or semiconductor fabrication tool 216. For example, the semiconductor fabrication tool 216 may include any tool known in the art, including but not limited to an etcher, a scanner, a stepper, a cleaner, or the like. For example, a fabrication process may include fabricating a plurality of dies distributed over a surface of a sample (e.g., a semiconductor wafer or the like), wherein each die includes a plurality of patterned layers of material forming device components. Each patterned layer may be formed by the semiconductor fabrication tool 216 via a series of steps including material deposition, photolithography, etching for producing a pattern of interest, and / or one or more exposure steps (e.g., performed by a scanner, a stepper, or the like). By way of another example, the semiconductor fabrication tool 216 may include any tool known in the art configured to package and / or combine semiconductor dies into 2.5D and / or 3D semiconductor die packages. For example, a fabrication process may include but not limited to aligning semiconductor dies and / or electrical components on semiconductor dies. Additionally, the fabrication process may include, but is not limited to, joining semiconductor dies and / or electrical components on the semiconductor dies via hybrid bonding (e.g., die to die, die to wafer, wafer to wafer, or the like), solder, adhesives, fasteners, or the like. For purposes of this disclosure, it is noted herein that at least one semiconductor fabrication tool 216 may be a single semiconductor fabrication tool 216 or may represent a group of semiconductor fabrication tools 216.

[0057] It should be noted herein that for the purposes of this disclosure, the terms "fabrication process" and "manufacturing process" and corresponding variations of the terms (e.g., "fabrication line" and "manufacturing line", "fabricator" and "manufacturer" or the like) may be considered equivalent.

[0058] It should be noted herein that for the purpose of this disclosure, Figure 2A The embodiments described in Figure 2B The embodiments described in the embodiment may be considered as part of the same semiconductor die supplier subsystem 110 and / or semiconductor die packaging subsystem 114 or a different system 100 or a subsystem of a different system 100. In addition, it should be noted herein that Figure 2A The components within the semiconductor die supplier subsystem 110 and / or the semiconductor die packaging subsystem 114 and Figure 2B The components within the semiconductor die vendor subsystem 110 and / or the semiconductor die packaging subsystem 114 illustrated in FIG. 2 may communicate directly or may communicate through the controller 208 .

[0059] Figure 3 A system 100 for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure is described. Figures 4A to 4CA method or process for evaluating the reliability of a semiconductor die package according to one or more embodiments of the present disclosure is described. It should be noted herein that Figures 4A to 4C The steps of the method or process may be wholly or partly performed by Figures 1A to 3 However, it should be further recognized that Figures 4A to 4C The method or process is not limited to Figures 1A to 3 The system 100 described in the foregoing description is not limited to the foregoing, as additional or alternative system-level embodiments may implement all or a portion of the steps of a method or process.

[0060] Figure 4A A method or process 400 for fabricating a semiconductor die according to one or more embodiments of the present disclosure is illustrated.

[0061] It should be noted herein that any step of the method or process 400 may include any selected die within any selected number of samples 202. For example, a population may include, but is not limited to, selected die from a single sample 202, multiple samples 202 within a batch (e.g., a production batch), or selected samples 202 across multiple batches.

[0062] In step 402, one or more semiconductor dies are fabricated. In one embodiment, one or more semiconductor die suppliers fabricate one or more semiconductor wafers 300 including one or more semiconductor dies 302 using one or more semiconductor die supplier subsystems 110, as described throughout this disclosure.

[0063] In step 404, one or more semiconductor dies are scored. In one embodiment, one or more semiconductor dies 302 are scored using online screening implemented by I-PAT weighted outlier detection. For example, I-PAT summarizes the defect rate of each die across multiple layers. Using multiple defect attributes collected at run time, the I-PAT system can identify defects and assign defects to one of several weighted categories. Each semiconductor die can obtain a total score based on the sum of the number of each weighted defect detected across the inspected layer. It is recommended to remove or closely deploy semiconductor dies with extremely high weighted scores that are outliers from the rest of the group during electrical testing and / or stress testing. It should be noted herein that the score can be traced back to each specific semiconductor die 302 of one or more semiconductor dies 302. Exemplary uses of PAT methods (including but not limited to I-PAT methods) during semiconductor device fabrication can be found in U.S. Patent No. 10,761,128, issued on September 1, 2020, and U.S. Patent Application No. 17 / 101,856, filed on November 23, 2020, the entire contents of which were each previously incorporated herein.

[0064] It should be noted herein that one or more semiconductor die suppliers may implement thresholds to prevent semiconductor die 302 with fatal defects or known LRDs from entering the market, such as extremely high weighted scores that are considered outliers from the rest of the population and recommended for removal or tight deployment during electrical testing and / or stress testing. However, the thresholds implemented by one or more semiconductor die suppliers may not be as stringent as the thresholds implemented by one or more semiconductor die packaging manufacturers. Thus, additional thresholds may need to be in place, including thresholds based on scores generated using in-line screening implemented through I-PAT weighted outlier detection.

[0065] In step 406, data about the one or more semiconductor dies is transmitted. In one embodiment, a score of the one or more semiconductor dies is transmitted. It should be noted herein that the score may be combined with electrical test data and / or stress test data of the one or more semiconductor dies 302. Additionally, the score may be combined with other supporting information, such as an embedded electronic chip identification (ECID) or other unique physical or electrical identifier of the one or more semiconductor dies 302 that persists after singulation, testing, and / or die ranking. Furthermore, the score may be paired with other supporting information that adds context to each ranking, such as, but not limited to, a batch score, range, and mean, rolling average, or the like of the one or more semiconductor dies 302 and / or the one or more semiconductor wafers 302 from which the one or more semiconductor dies 302 originated.

[0066] In step 408, data is received from one or more semiconductor die packaging manufacturers in a feed-forward or feedback loop. In one embodiment, the data is used to improve semiconductor die fabrication systems and processes or methods.

[0067] Figure 4B A method or process 410 for fabricating a semiconductor die according to one or more embodiments of the present disclosure is illustrated. It is noted herein that the method or process 410 may be performed immediately after the method or process 400, a selected amount of time after the method or process 400, or independently of the method or process 400.

[0068] In step 412, scores for one or more semiconductor dies are received. In one embodiment, semiconductor die data 112 including scores for one or more semiconductor dies 302 and other supporting information is transmitted from one or more semiconductor die suppliers to the controller or server 102 (e.g., via one or more semiconductor die supplier subsystems 110 and / or one or more auxiliary controllers or servers 118), as described throughout this disclosure. In another embodiment, a known good die (KGD) subsystem 306 is configured to operate on the controller or server 102. In another embodiment, the KGD subsystem 306 is configured to maintain a KGD database 308 into which data including scores for one or more semiconductor dies 302 and other supporting information may be entered.

[0069] It should be noted herein that the KGD subsystem 306 and / or the KGD database 308 may be maintained and / or configured to operate on a physical server (e.g., on-site or third party) or on a network-based cloud storage. For example, a third-party physical server and / or network-based cloud storage may be implemented as part of a subscription service.

[0070] In step 414, one or more semiconductor dies are filtered. In one embodiment, risky semiconductor dies 302 are filtered out as semiconductor die rejects 310. For example, risky semiconductor dies 302 having a high weighted defect rate score equal to or above a high risk I-PAT score threshold 312 (e.g., which may cause the entire semiconductor die package 304 to fail) may be marked by the KGD subsystem 306 as semiconductor die rejects 310 and removed from consideration for the semiconductor die package 304. It should be noted herein that risky semiconductor dies 302 having a high weighted defect rate equal to or above a high risk I-PAT score threshold 312 may be removed by the semiconductor die supplier if determined during fabrication of the semiconductor die 302.

[0071] In step 416, the one or more semiconductor dies are ranked. For example, the KGD subsystem 306 can take into account one or more I-PAT score thresholds based on scores including the I-PAT outlier weighted metric when ranking the semiconductor dies 302 recommended for the semiconductor die package 304. By way of another example, the KGD subsystem 306 can be configured to compare the I-PAT scores of the one or more semiconductor dies 302 in conjunction with electrical test data, stress test data, and / or other supporting information to rank the one or more semiconductor dies 302.

[0072] In one embodiment, the one or more semiconductor dies 302 are ranked to determine which of the one or more semiconductor dies 302 should go into which semiconductor die packages 304. For example, more reliable semiconductor dies 302 having weighted defectivity scores below a high risk I-PAT score threshold 312 may be considered for semiconductor die packages 304, and additional I-PAT score thresholds may be applied to determine the quality of the remaining semiconductor dies 302 to pair or bin the semiconductor dies 302 into semiconductor die stacks of similar attributes based on suitability and likely reliability.

[0073] In one non-limiting example, semiconductor dies 302 having a low or lowest weighted defectivity score that is equal to or equal to the low risk I-PAT score threshold 314 may be marked as premium or highest quality semiconductor dies 304a. For example, premium or highest quality semiconductor dies 304a from one or more semiconductor die suppliers may be included in a high reliability semiconductor package based on the determination by the KGD subsystem 306. For example, at least twenty premium or highest quality semiconductor dies 304a from one or more semiconductor die suppliers may be included in a high reliability semiconductor package.

[0074] By way of another example, semiconductor dies 302 having a medium weighted defectivity score corresponding to a medium risk I-PAT score threshold within the I-PAT score range 316 and between the I-PAT score thresholds 312, 314 may be marked as passing or lower quality semiconductor dies 304b, 304c, ..., 304N, where N represents any number of semiconductor die groups defined by the number of I-PAT score thresholds. For example, passing or lower quality semiconductor dies 304b, 304c, ..., 304N from one or more semiconductor die suppliers may be included in a lower or lowest reliability semiconductor package based on a determination by the KGD subsystem 306. For example, no more than five passing or lower quality semiconductor dies 304b, 304c, ..., 304N from one or more semiconductor die suppliers may be included in a lower or lowest reliability semiconductor package.

[0075] It should be noted herein that the KGD subsystem 306 may take into account more than the I-PAT score thresholds 312, 314 to further define a medium risk I-PAT score threshold within the I-PAT score range 316. Therefore, it should be understood that the examples of I-PAT score thresholds in the present disclosure are provided for illustrative purposes only and should not be construed as limiting.

[0076] In general, semiconductor dies with similar reliability risk profiles (e.g., containing similar I-PAT scores, electrical test data, stress test data, physical or electrical identifiers containing embedded ECIDs, or the like) can be sorted to provide market segmentation. For example, market segments may require different reliability levels (e.g., parts per million (PPM), parts per billion (PPB), or the like). By another example, market segments may have different price requirements. This increased market segmentation can allow for the varying price and performance requirements of a broad market for stacked semiconductor die packages to be provided by predicting die reliability. For example, since a die with a high I-PAT score that passes electrical and / or stress testing is a possible source of failure for the entire semiconductor die package, it should be rejected from any semiconductor die stacking, thereby improving yield and saving money. By another example, semiconductor dies with very low I-PAT scores and good electrical and / or stress test results can be considered advanced "known good dies" designated for the most critical applications. By way of another example, a die with a passing but high I-PAT score may still be used in a less expensive market segment with lower reliability requirements.

[0077] It should be noted herein that the KGD subsystem 306 is applicable to all semiconductor die assessments used in any stacking method, and is believed to be of particular value for bare semiconductor dies in advanced devices that currently lack thorough electrical testing capabilities.

[0078] In this regard, the KGD subsystem 306 can generate additional thresholds for semiconductor die packaging manufacturers. Adding I-PAT information improves the ability of the supply chain to adjudicate "known good die" and generate more predictable die stack reliability while providing the unique needs of multiple segments. By utilizing the scores generated by applying the I-PAT weighted defect rate outlier screening, the KGD subsystem 306 provides independent and highly correlated detection of semiconductor dies 302 that may fail electrical testing and / or stress testing. In addition, the KGD subsystem 306 can provide additional benefits of identifying potential die defect rate driving failure mechanisms that exist in test coverage gaps, statistical test escapes, untested failure modes, untestable die areas, and / or unactivated latent failures that are not seen in current methods centered on electrical testing and / or stress testing. In addition, any overlap of I-PAT data with existing electrical test data and / or stress test data serves as an independent confirmation of the applicability of semiconductor dies, while also bringing additional valuable data for determining appropriate semiconductor die deployment.

[0079] In another embodiment, the KGD subsystem 306 may compare and trend the I-PAT scores and final package yield over time for semiconductor dies from one or more semiconductor die suppliers to assist semiconductor die packaging manufacturers in quality enhancement and semiconductor die supplier management.

[0080] In step 418, data regarding the one or more filtered and sorted semiconductor dies is transmitted. In one embodiment, the semiconductor die reliability data 116 is transmitted to a semiconductor die packaging manufacturer (eg, via the semiconductor die packaging manufacturer subsystem 114).

[0081] Figure 4C A method or process 420 for making a semiconductor die package according to one or more embodiments of the present disclosure is illustrated. It is noted herein that method or process 420 may be performed immediately after method or process 410, a selected amount of time after method or process 410, or independently of method or process 410.

[0082] In step 422, data regarding the one or more filtered and ranked semiconductor dies is received. In one embodiment, the data regarding the one or more filtered and ranked semiconductor dies 302 as determined by the KGD subsystem 306 is transmitted from the controller or server 102 to the one or more semiconductor die packaging manufacturers (e.g., via the one or more semiconductor die packaging manufacturers subsystems 114 and / or the one or more auxiliary controllers or servers 120).

[0083] In step 424, one or more semiconductor die packages 304 are fabricated. In one embodiment, one or more semiconductor die packaging manufacturers obtain one or more filtered and sorted semiconductor dies 302. For example, one or more semiconductor die packaging manufacturers may manually select one or more filtered and sorted semiconductor dies 302 before delivery. By way of another example, one or more semiconductor die packaging manufacturers may buy semiconductor dies 302 in bulk and then separate out one or more filtered and sorted semiconductor dies 302.

[0084] In another embodiment, one or more semiconductor die package manufacturers produce one or more semiconductor die packages 304 including one or more filtered and sorted semiconductor dies 302, as described throughout this disclosure, with one or more semiconductor die package manufacturer subsystems 114. For example, the sorted and filtered semiconductor dies 302 may be obtained and utilized when manufacturing one or more semiconductor die packages 304 in a 2.5D and / or 3D arrangement.

[0085] In step 426 , the data is transmitted to one or more semiconductor die suppliers in a feed forward or feedback loop. In one embodiment, the data is used to improve semiconductor die fabrication systems and processes or methods based at least on the semiconductor die reliability data generated by the KGD subsystem 306 .

[0086] It should be noted herein that one illustrative example involves a semiconductor die packaging manufacturer in the automotive, military, aerospace, and / or medical industries that receives bare die assemblies for 3D semiconductor die stacking from three separate semiconductor die suppliers, wherein each bare die assembly is delivered by three separate semiconductor die suppliers, and wherein uncertain reliability due to lack of information (e.g., memory and logic) hinders testing during semiconductor wafer probing.

[0087] Without the use of the KGD subsystem 306, semiconductor die packaging manufacturers in the automotive, military, aerospace, and / or medical industries operating with failure rates in the parts per billion (PPB) range may need to integrate components into 3D semiconductor die packages based on limited bare die test data and random pairing or binning of components. The yield of components combined with the multiplicative effects of untestable failures and other test gaps creates expensive and unpredictable yield losses when packaging without clear ownership or improvement paths.

[0088] However, using the KGD subsystem 306, semiconductor die packaging manufacturers in the automotive, military, aerospace, and / or medical industries that operate with failure rates in the parts per billion (PPB) range can utilize the I-PAT scores from each incoming semiconductor die supplier to reject any outlier components outright to reduce yield loss costs and integration costs for other die components. Additionally, semiconductor die packaging manufacturers can pair or sort semiconductor dies of similar I-PAT scores into stacks that have the highest probability of being reliably used in the most mission and safety-critical roles, while reusing other components in less critical applications. Furthermore, the I-PAT score can be used as a quality metric to manage the supply chain and drive continuous improvement.

[0089] It should be noted herein that the system 100 and its subsystems 110, 114, 306 and corresponding methods or processes 400, 410, 420 may be operated by a separate semiconductor die supplier (e.g., having one or more semiconductor die supplier subsystems 110), a semiconductor die packaging manufacturer (e.g., having one or more semiconductor die packaging manufacturer subsystems 114), a third party operator of the controller or server 102, and / or a third party operator of one or more auxiliary controllers or servers 118, 120.

[0090] Additionally, it should be noted herein that the one or more semiconductor die supplier subsystems 110, the one or more semiconductor die packaging manufacturer subsystems 114, the controller or server 102, and / or the one or more auxiliary controllers or servers 118, 120 may be co-owned. In one non-limiting example, a semiconductor die packaging manufacturer may own the one or more semiconductor die packaging manufacturer subsystems 114 and the controller or server 102, thereby making the KGD subsystem 306 a local subsystem that can receive data from multiple semiconductor die suppliers (e.g., via the one or more semiconductor die supplier subsystems 110).

[0091] In another non-limiting example, a semiconductor die supplier may own one or more semiconductor die supplier subsystems 110 and one or more auxiliary controllers or servers 118. In another non-limiting example, a semiconductor die packaging manufacturer may own one or more semiconductor die packaging manufacturer subsystems 114 and one or more auxiliary controllers or servers 120.

[0092] Therefore, it should be understood that the examples of subsystems or controllers or servers described throughout this disclosure are provided for illustrative purposes only and should not be construed as limiting.

[0093] The semiconductor die data 112 and / or the semiconductor die reliability data 116 may be in a non-standardized format such that one or more semiconductor die vendor subsystems 110 and / or one or more semiconductor die packaging manufacturer subsystems 114 may be configured to operate using data in a non-standardized data format. For example, the semiconductor die data 112 and / or the semiconductor die reliability data 116 may be formatted for use with different operating systems (including but not limited to Android, Apple iOS, Microsoft Windows, Apple macOS, Linux, ChromeOS, Unix, Ubuntu, proprietary operating systems requiring proprietary or non-proprietary data formats, or the like).

[0094] The controller or server 102 may be configured to operate using data in a standardized data format to evaluate the reliability of semiconductor die packages. For example, the data may be formatted for use with a single operating system (or complementary operating systems) from the above non-limiting list. The system 100 may be configured to convert the semiconductor die data 112 and / or the semiconductor die reliability data 116 from a variety of non-standardized data formats into data in a standardized data format for the controller or server 102.

[0095] In one non-limiting example, the one or more semiconductor die vendor subsystems 110 may generate the semiconductor die data 112 in a non-standardized data format and during or after the method or process 400 .

[0096] For example, the one or more semiconductor die vendor subsystems 110 may convert the semiconductor die data 112 to a standardized data format before transmission to the controller or server 102 .

[0097] Additionally, one or more semiconductor die vendor subsystems 110 may transmit semiconductor die data 112 in a non-standardized data format to the controller or server 102 , and the controller or server 102 may convert the semiconductor die data 112 to a standardized data format upon receipt and prior to use in the method or process 410 .

[0098] In another non-limiting example, one or more semiconductor die packaging manufacturer subsystems 114 may use semiconductor die reliability data 116 in a non-standardized data format.

[0099] For example, the one or more semiconductor die packaging manufacturer subsystems 114 may receive the semiconductor die reliability data 116 in a standardized data format and convert the semiconductor die reliability data 116 to a non-standardized data format after receipt and before use in the method or process 420 .

[0100] In addition, the controller or server 102 may convert the semiconductor die reliability data 116 into a non-standardized data format during or after the method or process 410 and before transmitting to one or more semiconductor die packaging manufacturer subsystems 114, and the one or more semiconductor die packaging manufacturer subsystems 114 may receive the semiconductor die reliability data 116 in a non-standardized data format.

[0101] It should be noted herein that the distinction of operating with a "standardized data format" and / or a "non-standardized data format" is not intended to be limiting. For example, one or more semiconductor die supplier subsystems 110 and / or one or more semiconductor die packaging manufacturer subsystems 114 may be configured to operate with standardized data. By another example, the controller or server 102 may be configured to operate with non-standardized data. By another example, one or more semiconductor die supplier subsystems 110, one or more semiconductor die packaging manufacturer subsystems 114, and the controller or server 102 may be configured to operate with standardized data. By another example, one or more semiconductor die supplier subsystems 110, one or more semiconductor die packaging manufacturer subsystems 114, and the controller or server 102 may be configured to operate with non-standardized data. Therefore, it should be understood that the examples of data formats in the present disclosure are provided for illustrative purposes only and should not be construed as limiting.

[0102] It should be noted herein that the methods or processes 400, 410, 420 are not limited to the steps and / or sub-steps provided. The methods or processes 400, 410, 420 may include more or fewer steps and / or sub-steps. The methods or processes 400, 410, 420 may perform the steps and / or sub-steps simultaneously. The methods or processes 400, 410, 420 may perform the steps and / or sub-steps sequentially (including in the order provided or in an order other than that provided). Therefore, the above description should not be construed as limiting the scope of the present disclosure but is merely illustrative.

[0103] In this regard, advantages of the present disclosure include reducing yield loss (and thus reducing costs, reducing manufacturing downtime, or the like) for semiconductor die packaging manufacturers by relying on the determination of known good dies (KGDs) for use in semiconductor die packages. Advantages of the present disclosure also include implementing an I-PAT method to generate defect rate scores or rankings (e.g., weighted or unweighted) for one or more semiconductor dies across one or more semiconductor distributors. Advantages of the present disclosure also include pairing semiconductor dies or semiconductor die sub-packages with similar reliability risk profiles. Advantages of the present disclosure also include classifying semiconductor die packages into different performance and / or price or value categories.

[0104] The subject matter described herein sometimes illustrates different components contained in or connected to other components. It should be understood that such depicted architectures are exemplary only, and in fact many other architectures that realize the same functionality can be implemented. In a conceptual sense, any arrangement of components for realizing the same functionality is effectively "associated" so that the desired functionality is realized. Therefore, any two components combined to realize a specific functionality in this article can be regarded as "associated" with each other so that the desired functionality is realized, without considering the architecture or intermediate components. Similarly, any two components so associated can also be regarded as "connected" or "coupled" to each other to realize the desired functionality, and any two components that can be so associated can also be regarded as "coupleable" to each other to realize the desired functionality. Specific examples that can be coupled include but are not limited to components that can physically interact and / or physically interact and / or components that can wirelessly interact and / or wirelessly interact and / or components that can logically interact and / or logically interact.

[0105] It is believed that the present disclosure and many of its attendant advantages will be appreciated from the foregoing description, and it will be appreciated that various changes may be made to the form, construction, and arrangement of components without departing from the disclosed subject matter or sacrificing all of its significant advantages. The forms described are merely illustrative, and the following claims are intended to cover and encompass such changes. Furthermore, it should be understood that the invention is defined by the appended claims.

Claims

1. A system comprising: A controller, wherein the controller comprises one or more processors and a memory, wherein the memory is configured to store a set of program instructions, wherein the one or more processors are configured to execute the program instructions, thereby causing the one or more processors to: receiving semiconductor die data regarding a plurality of semiconductor dies from a plurality of semiconductor die supplier subsystems, wherein the semiconductor die data includes an In-Line Part Average Test (I-PAT) score for each of the plurality of semiconductor dies, wherein the I-PAT score represents a weighted defect rate of the corresponding semiconductor die; filtering a high risk subset of the plurality of semiconductor dies with a known good die (KGD) subsystem, wherein the high risk subset of the plurality of semiconductor dies includes one or more semiconductor die rejects having corresponding I-PAT scores equal to or above a high risk I-PAT score threshold of a plurality of I-PAT score thresholds; sorting, with the KGD subsystem, the plurality of semiconductor dies based on a comparison of the I-PAT score of each of the plurality of semiconductor dies to the plurality of I-PAT score thresholds; and Semiconductor die reliability data regarding the sorted plurality of semiconductor dies is transmitted to a plurality of semiconductor die packaging manufacturer subsystems.

2. The system of claim 1 , wherein the subset of semiconductor dies including the one or more semiconductor die rejects having corresponding I-PAT scores equal to or above the high risk I-PAT score threshold is rejected based on semiconductor die data received from at least two of the plurality of semiconductor die supplier subsystems.

3. The system of claim 1 , wherein the plurality of I-PAT score thresholds comprises a low risk I-PAT score threshold that is lower than the high risk I-PAT score threshold, The one or more processors are configured to execute program instructions, thereby causing the one or more processors to rank a low-risk subset of the plurality of semiconductor dies, wherein the low-risk subset of the plurality of semiconductor dies includes semiconductor dies having corresponding I-PAT scores equal to or below the low-risk I-PAT score threshold.

4. The system of claim 3 , wherein the low-risk subset of semiconductor dies including semiconductor dies having corresponding I-PAT scores equal to or below the low-risk I-PAT score threshold is ranked based on semiconductor die data received from at least two of the plurality of semiconductor die supplier subsystems.

5. The system of claim 3, wherein the low risk subset of semiconductor die including semiconductor die having corresponding I-PAT scores equal to or below the low risk I-PAT score threshold can be used in one or more semiconductor die packages manufactured for a market segment in at least one of the automotive, military, aerospace, or medical industries operating with failure rates in the parts per billion (PPB) range. 6 . The system of claim 3 , wherein the plurality of I-PAT score thresholds include at least one medium-risk I-PAT score threshold between the high-risk I-PAT score threshold and the low-risk I-PAT score threshold.

7. The system of claim 6, wherein the ranking the plurality of semiconductor dies based on the at least one medium-risk I-PAT score threshold comprises: ranking a subset of the plurality of semiconductor dies based on a reliability risk profile, wherein the reliability risk profile of the subset of the plurality of semiconductor dies comprises an I-PAT score corresponding to the at least one medium-risk I-PAT score threshold.

8. The system of claim 7, wherein the reliability risk profile of the subset of the plurality of semiconductor dies further comprises at least one of electrical test data, stress test data, or a physical or electrical identifier including an embedded electronic chip identification (ECID) of a corresponding semiconductor die in the subset of the plurality of semiconductor dies.

9. The system of claim 6, wherein a medium risk subset of semiconductor dies including semiconductor dies having I-PAT scores corresponding to the at least one medium risk I-PAT score threshold is ranked based on semiconductor die data received from at least two of the plurality of semiconductor die supplier subsystems.

10. The system of claim 6, wherein the ranked medium risk subset of semiconductor dies including semiconductor dies having I-PAT scores corresponding to the at least one medium risk I-PAT score threshold is transmitted as semiconductor die reliability data to at least two of the plurality of semiconductor die packaging vendors.

11. The system of claim 10, wherein a first ranked portion of the medium risk subset of semiconductor dies including semiconductor dies is usable in one or more semiconductor die packages manufactured by a first semiconductor die package vendor of the plurality of semiconductor die packages for a first market segment having a first price requirement, A second graded portion of the medium risk subset of semiconductor dies including semiconductor dies therein may be used in one or more semiconductor die packages manufactured by a second semiconductor die package vendor of the plurality of semiconductor die packages for a second market segment having a second price requirement.

12. The system of claim 1, wherein at least some of the plurality of semiconductor die vendor subsystems use one or more non-standardized data formats, wherein the controller uses a standardized data format, The one or more processors are further configured to execute program instructions so that the one or more processors: The semiconductor die data is converted from the one or more non-standardized data formats to the standardized data format after receipt.

13. The system of claim 1 , wherein at least some of the plurality of semiconductor die packaging manufacturer subsystems use one or more non-standardized data formats, wherein the controller uses a standardized data format, The one or more processors are further configured to execute program instructions so that the one or more processors: The semiconductor die reliability data is converted from the standardized data format to the one or more non-standardized data formats prior to transmission to the at least some of the plurality of semiconductor die packaging manufacturer subsystems.

14. A method comprising: receiving semiconductor die data regarding a plurality of semiconductor dies from a plurality of semiconductor die supplier subsystems via a controller, wherein the semiconductor die data includes an In-Line Part Average Test (I-PAT) score for each of the plurality of semiconductor dies, wherein the I-PAT score represents a weighted defect rate of the corresponding semiconductor die; filtering, via the controller, a high risk subset of the plurality of semiconductor dies with a known good die (KGD) subsystem, wherein the high risk subset of the plurality of semiconductor dies includes one or more semiconductor die rejects having corresponding I-PAT scores equal to or above a high risk I-PAT score threshold of a plurality of I-PAT score thresholds; sorting, with the KGD subsystem via the controller, the plurality of semiconductor dies based on a comparison of the I-PAT score of each of the plurality of semiconductor dies to the plurality of I-PAT score thresholds; and Semiconductor die reliability data regarding the sorted plurality of semiconductor dies is transmitted to a plurality of semiconductor die packaging manufacturer subsystems via the controller.

15. The method of claim 14, wherein the subset of semiconductor dies including the one or more semiconductor die rejects having corresponding I-PAT scores equal to or above the high risk I-PAT score threshold is rejected based on semiconductor die data received from at least two of the plurality of semiconductor die supplier subsystems.

16. The method of claim 14, wherein the plurality of I-PAT score thresholds comprises a low risk I-PAT score threshold that is lower than the high risk I-PAT score threshold, Wherein the method further comprises: A low risk subset of the plurality of semiconductor dies is ranked, via the controller, wherein the low risk subset of the plurality of semiconductor dies includes semiconductor dies having corresponding I-PAT scores that are equal to or below the low risk I-PAT score threshold.

17. The method of claim 16, wherein the low-risk subset of semiconductor dies including semiconductor dies having corresponding I-PAT scores equal to or below the low-risk I-PAT score threshold is ranked based on semiconductor die data received from at least two of the plurality of semiconductor die supplier subsystems.

18. The method of claim 16, wherein the low-risk subset of semiconductor dies including semiconductor dies having corresponding I-PAT scores equal to or below the low-risk I-PAT score threshold can be used in one or more semiconductor die packages manufactured for market segments in the automotive or aerospace industries operating with failure rates in the parts per billion (PPB) range.

19. The method of claim 16, wherein the plurality of I-PAT score thresholds include at least one moderate risk I-PAT score threshold between the high risk I-PAT score threshold and the low risk I-PAT score threshold.

20. The method of claim 19, wherein the ranking the plurality of semiconductor dies based on the at least one medium-risk I-PAT score threshold comprises: ranking a subset of the plurality of semiconductor dies based on a reliability risk profile, wherein the reliability risk profile of the subset of the plurality of semiconductor dies comprises an I-PAT score corresponding to the at least one medium-risk I-PAT score threshold.

21. The method of claim 20, wherein the reliability risk profile of the subset of the plurality of semiconductor dies further comprises at least one of electrical test data, stress test data, or a physical or electrical identifier including an embedded electronic chip identification (ECID) of a corresponding semiconductor die in the subset of the plurality of semiconductor dies.

22. The method of claim 19, wherein a medium risk subset of semiconductor dies including semiconductor dies having I-PAT scores corresponding to the at least one medium risk I-PAT score threshold is ranked based on semiconductor die data received from at least two of the plurality of semiconductor die vendor subsystems.

23. The method of claim 19, wherein the ranked medium risk subset of semiconductor dies including semiconductor dies having I-PAT scores corresponding to the at least one medium risk I-PAT score threshold is transmitted as semiconductor die reliability data to at least two of the plurality of semiconductor die packaging manufacturers.

24. The method of claim 23, wherein a first ranked portion of the medium risk subset of semiconductor dies including semiconductor dies may be used in one or more semiconductor die packages manufactured by a first semiconductor die package vendor of the plurality of semiconductor die packages for a first market segment having a first price requirement, A second graded portion of the medium risk subset of semiconductor dies including semiconductor dies therein may be used in one or more semiconductor die packages manufactured by a second semiconductor die package vendor of the plurality of semiconductor die packages for a second market segment having a second price requirement.

25. The method of claim 14, wherein at least some of the plurality of semiconductor die vendor subsystems use one or more non-standardized data formats, wherein the controller uses a standardized data format.

26. The method of claim 25, further comprising: The semiconductor die data is converted, via the controller, from the one or more non-standardized data formats to the standardized data format after receipt.

27. The method of claim 25, wherein the at least some of the plurality of semiconductor die vendor subsystems are configured to convert the semiconductor die data from the one or more non-standardized data formats to the standardized data format prior to being received by the controller.

28. The method of claim 14, wherein at least some of the plurality of semiconductor die packaging manufacturer subsystems use one or more non-standardized data formats, wherein the controller uses a standardized data format.

29. The method of claim 28, further comprising: The semiconductor die reliability data is converted, via the controller, from the standardized data format to the one or more non-standardized data formats prior to transmission to the at least some of the plurality of semiconductor die packaging manufacturer subsystems.

30. The method of claim 28, wherein the at least some of the plurality of semiconductor die packaging manufacturer subsystems are configured to convert the semiconductor die reliability data from the standardized data format to the one or more non-standardized data formats after being transmitted by the controller.

31. The method of claim 14, wherein the plurality of semiconductor die packaging manufacturer subsystems are configured to transmit data to the plurality of semiconductor die supplier subsystems in a feed-forward or feedback loop based on the semiconductor die reliability data.

32. A system comprising: Multiple semiconductor die vendor subsystems; Multiple semiconductor die packaging manufacturer subsystems; and A controller, wherein the controller comprises one or more processors and a memory, wherein the memory is configured to store a set of program instructions, wherein the one or more processors are to execute the program instructions, thereby causing the one or more processors to: receiving semiconductor die data regarding a plurality of semiconductor dies from the plurality of semiconductor die supplier subsystems, wherein the semiconductor die data includes an In-Line Part Average Test (I-PAT) score for each of the plurality of semiconductor dies, wherein the I-PAT score represents a weighted defect rate of the corresponding semiconductor die; filtering a high risk subset of the plurality of semiconductor dies with a known good die (KGD) subsystem, wherein the high risk subset of the plurality of semiconductor dies includes one or more semiconductor die rejects having corresponding I-PAT scores equal to or above a high risk I-PAT score threshold of a plurality of I-PAT score thresholds; sorting, with the KGD subsystem, the plurality of semiconductor dies based on a comparison of the I-PAT score of each of the plurality of semiconductor dies to the plurality of I-PAT score thresholds; and Semiconductor die reliability data regarding the sorted plurality of semiconductor dies is transmitted to the plurality of semiconductor die packaging manufacturer subsystems.

33. The system of claim 32, wherein at least some of the plurality of semiconductor die vendor subsystems use one or more non-standardized data formats, wherein the controller uses a standardized data format, Wherein the at least some of the plurality of semiconductor die vendor subsystems are configured to convert the semiconductor die data from the one or more non-standardized data formats to the standardized data format prior to being received by the controller.

34. The system of claim 32, wherein at least some of the plurality of semiconductor die packaging manufacturer subsystems use one or more non-standardized data formats, wherein the controller uses a standardized data format, Wherein the at least some of the plurality of semiconductor die packaging manufacturer subsystems are configured to convert the semiconductor die reliability data from the standardized data format to the one or more non-standardized data formats after being transmitted by the controller.

35. The system of claim 32, wherein the plurality of semiconductor die packaging manufacturer subsystems are configured to transmit data to the plurality of semiconductor die supplier subsystems in a feed-forward or feedback loop based on the semiconductor die reliability data.

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