Array substrate, manufacturing method thereof, and liquid crystal panel

Abstract

The application discloses an array substrate and a manufacturing method thereof and a liquid crystal panel, and belongs to the technical field of display. The column substrate comprises a substrate and a plurality of patterned film layer structures which are stacked on the substrate. The part of the patterned film layer structures in the first spliced display area is formed based on a first mask and a second mask of a mask plate. The part of the patterned film layer structures in the normal display area is formed based on the first mask of the mask plate. The part of the patterned film layer structures in the non-display area is formed based on the second mask of the mask plate. Therefore, in the process of forming the patterned film layer structures in the array, the photoresist in the first spliced display area does not need to be exposed separately by using an additional mask plate, the number of exposure times is effectively reduced, and the manufacturing process of a large-size display panel prepared based on the array substrate is simplified.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its manufacturing method, and a liquid crystal panel. Background Technology

[0002] To meet people's demand for viewing large-screen images, large-size display panels need to be installed in display devices.

[0003] Currently, in the fabrication of large-size display panels, the patterned film structure in the display panel often requires the use of a splicing exposure process. For example, when creating a patterned film structure in a large-size display panel, firstly, a continuous film structure needs to be formed on the substrate and coated with photoresist; then, different sections of the photoresist are exposed separately using the same mask; next, the exposed photoresist is developed, and the continuous film structure formed on the substrate is etched; finally, the photoresist on the substrate is peeled off, thus forming the patterned film structure on the substrate.

[0004] However, currently, when exposing the photoresist film on the substrate, a baffle needs to be placed in the splicing area between two partitions, and after exposing each partition, the splicing area is exposed separately. Thus, when making patterned film layer structures in large-size display panels, multiple exposures are required, making the manufacturing process of large-size display panels more complex. Summary of the Invention

[0005] This application provides an array substrate and its manufacturing method, as well as a liquid crystal panel. It solves the problem of the complex manufacturing process of large-size display panels in the prior art. The technical solution is as follows:

[0006] On one hand, an array substrate is provided, the array substrate having a display area and a non-display area located around the display area; the array substrate includes:

[0007] A substrate, and a plurality of patterned film structures stacked on the substrate;

[0008] The patterned film structure is used to form a plurality of sub-pixels, the plurality of sub-pixels including: a plurality of first sub-pixels located in the display area, and a plurality of virtual sub-pixels located in the non-display area;

[0009] The area of ​​the orthogonal projection of the pixel electrode in the virtual sub-pixel onto the substrate is greater than the area of ​​the orthogonal projection of the pixel electrode in the first sub-pixel onto the substrate.

[0010] Optionally, the display area includes: a plurality of normal display areas arranged in an array, and a first splicing display area located between two adjacent normal display areas; a plurality of first sub-pixels are distributed in the normal display area, and the plurality of sub-pixels further include: a plurality of second sub-pixels located in the first splicing display area;

[0011] Wherein, the area of ​​the orthogonal projection of the pixel electrode in the second sub-pixel onto the substrate is less than or equal to the area of ​​the orthogonal projection of the pixel electrode in the first sub-pixel onto the substrate.

[0012] Optionally, the plurality of sub-pixels further includes: a plurality of third sub-pixels, a portion of which is located within the normal display area and another portion of which is located within the first splicing display area;

[0013] In the length direction parallel to the first splicing display area, the width of the portion of the third sub-pixel located within the first splicing display area is less than or equal to the width of the portion of the third sub-pixel located within the normal display area.

[0014] Optionally, the display area further includes: a second splicing display area located between two first splicing display areas arranged along the row direction and two first splicing display areas arranged along the column direction, and the plurality of sub-pixels further includes: a fourth sub-pixel located within the second splicing display area;

[0015] The area of ​​the orthogonal projection of the pixel electrode in the fourth sub-pixel onto the substrate is less than or equal to the area of ​​the orthogonal projection of the pixel electrode in the second sub-pixel onto the substrate.

[0016] Optionally, the normal display area has multiple alignment areas;

[0017] The film structure closest to the substrate among the multiple patterned film structures is a first conductive layer, which includes multiple first alignment structures located in the alignment region.

[0018] Each of the multiple patterned film structures, except for the first conductive layer, includes a second alignment structure located within the alignment region, wherein the orthographic projections of the second alignment structures in each film structure on the substrate do not overlap.

[0019] Within the same alignment region, multiple first alignment structures correspond one-to-one with multiple second alignment structures, and the positional relationship between the orthographic projection of the first alignment structure on the substrate and the orthographic projection of the corresponding second alignment structure on the substrate satisfies a preset positional relationship.

[0020] Optionally, the orthographic projections of each first alignment structure on the substrate are located within the orthographic projections of different first sub-pixels on the substrate, and the orthographic projections of the first alignment structure and the corresponding second alignment structure on the substrate are located within the orthographic projections of the same first sub-pixel on the substrate.

[0021] Optionally, the first alignment structure includes: at least one first strip structure and at least one second strip structure, wherein the length direction of the first strip structure intersects the length direction of the second strip structure;

[0022] The second alignment structure corresponding to the first alignment structure includes: at least one third strip structure and at least one fourth strip structure;

[0023] Wherein, the length direction of the third strip structure is parallel to the length direction of the first strip structure, and the distance between the orthographic projection of the third strip structure on the substrate and the orthographic projection of the first strip structure on the substrate is within a first preset value range;

[0024] The length direction of the fourth strip structure is parallel to the length direction of the second strip structure, and the distance between the orthographic projection of the fourth strip structure on the substrate and the orthographic projection of the second strip structure on the substrate is within a second preset range.

[0025] Optionally, the number of the first strip structure and the number of the second strip structure are both one, and the number of the third strip structure and the number of the fourth strip structure in the second alignment structure are both two;

[0026] The first strip structure is located between the two third strip structures, and the difference between the distance between the orthographic projection of the two third strip structures on the substrate and the distance between the orthographic projection of the first strip structure on the substrate is less than a first preset threshold.

[0027] The second strip structure is located between the two fourth strip structures, and the difference between the distance between the orthographic projection of the two fourth strip structures on the substrate and the distance between the orthographic projection of the second strip structure on the substrate is less than a second preset threshold.

[0028] Optionally, the first alignment structure is an electrode block, and both the first strip structure and the second strip structure are strip grooves located within the electrode block. The orthographic projection of the second alignment structure on the substrate is located within the orthographic projection of the corresponding first alignment structure on the substrate.

[0029] Optionally, the multiple patterned film structures, excluding the first conductive layer, are respectively: an active layer pattern, a second conductive layer, a planarization layer, and a pixel electrode layer, wherein the active layer pattern, the second conductive layer, the planarization layer, and the pixel electrode layer are stacked sequentially along a direction perpendicular to and away from the substrate;

[0030] The array substrate further includes: a gate insulating layer disposed entirely between the active layer pattern and the first conductive layer;

[0031] The third and fourth strip structures in the active layer pattern, the second conductive layer, and the pixel electrode layer are all strip-shaped protrusions; the third and fourth strip structures in the planarization layer are all strip-shaped grooves.

[0032] Optionally, the first conductive layer further includes: a gate of a thin-film transistor in the sub-pixel, and a gate line electrically connected to the gate;

[0033] The active layer pattern further includes: the active layer of the thin-film transistor in the sub-pixel;

[0034] The second conductive layer further includes: a first electrode and a second electrode of the thin-film crystal in the sub-pixel, and a data line electrically connected to the first electrode;

[0035] The planarization layer also has connection vias;

[0036] The pixel electrode layer further includes: a pixel electrode in the sub-pixel, wherein the pixel electrode is electrically connected to the second electrode through the connection via.

[0037] Optionally, no pixel electrode is disposed in the first sub-pixel where the orthographic projection on the substrate overlaps with the second alignment structure in the pixel electrode layer;

[0038] Alternatively, the pixel electrode in the first sub-pixel whose orthogonal projection on the substrate overlaps with the second alignment structure in the pixel electrode layer has a hollow structure, and the orthogonal projections of the second alignment structure and the corresponding first alignment structure in the pixel electrode layer on the substrate are both located within the orthogonal projection of the hollow structure on the substrate.

[0039] Optionally, the first conductive layer further includes: an auxiliary signal line, wherein the orthographic projection of the auxiliary signal line on the substrate overlaps with the orthographic projection of the pixel electrode in at least a portion of the sub-pixels on the substrate, and does not coincide with the orthographic projection of the first alignment structure on the substrate.

[0040] Optionally, the auxiliary signal line includes: an auxiliary signal line body, and a bent winding electrically connected to the auxiliary signal line body, wherein at least a portion of the first alignment structure is located within the area enclosed by the bent winding.

[0041] Optionally, the first conductive layer further includes: a plurality of auxiliary alignment structures located in the alignment region, wherein the plurality of auxiliary alignment structures correspond one-to-one with the plurality of first alignment structures, and the orthographic projections of the auxiliary alignment structures and the corresponding first alignment structures on the substrate are located within the orthographic projection of the same first sub-pixel on the substrate.

[0042] Optionally, the plurality of alignment regions in the normal display area are evenly distributed at the edge of the normal display area.

[0043] On the other hand, a method for manufacturing an array substrate is provided, the array substrate having a display area and a non-display area located around the display area; the method includes:

[0044] Multiple patterned film structures are sequentially stacked on a substrate;

[0045] The patterned film structure is used to form a plurality of sub-pixels, the plurality of sub-pixels including: a plurality of first sub-pixels located in the display area, and a plurality of virtual sub-pixels located in the non-display area;

[0046] The area of ​​the orthogonal projection of the pixel electrode in the virtual sub-pixel onto the substrate is greater than the area of ​​the orthogonal projection of the pixel electrode in the first sub-pixel onto the substrate.

[0047] Optionally, the display area includes: a plurality of normal display areas arranged in an array, and a first splicing display area located between two adjacent normal display areas; forming each of the patterned film layer structures includes:

[0048] A continuous film structure is formed on the substrate;

[0049] A photoresist film is formed on the film structure, and a mask is used to sequentially expose the portions of the photoresist film located within the plurality of normal display areas;

[0050] The exposed photoresist film is developed, and the entire film structure is etched to form a patterned film structure on the substrate.

[0051] The exposure operation performed on the portion of the photoresist film located within a normal display area includes:

[0052] A first exposure area is formed in the first normal display area and the target splicing display area using the first mask in the mask plate, and a second exposure area is formed in the non-display area and the target splicing display area using the second mask in the mask plate;

[0053] Move the mask plate in the direction toward the second normal display area until the first mask can cover the second normal display area and the second exposure area located in the target splicing display area, and the second mask can cover the first exposure area located in the target splicing display area;

[0054] The first normal display area is any one of the plurality of normal display areas, the second normal display area is a normal display area adjacent to the first normal display area, and the target splicing display area is a first splicing display area located between the first normal display area and the second normal display area.

[0055] Optionally, the unit area of ​​the first exposure area is smaller than the unit area of ​​the second exposure area.

[0056] In another aspect, a liquid crystal panel is provided, comprising: an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is any of the array substrates described above.

[0057] The beneficial effects of the technical solutions provided in this application include at least the following:

[0058] An array substrate includes a substrate and a plurality of patterned film structures stacked on the substrate. Since the portion of the patterned film structure located within a first splicing display area is formed based on a first mask and a second mask of a photomask, and the first mask can also form the portion of the patterned film structure located within a normal display area, and the second mask can also form the portion of the patterned film structure located within a non-display area, the formation of the patterned film structure in this array eliminates the need for separate exposure of the photoresist within the first splicing display area using an additional photomask. This effectively reduces the number of exposures and simplifies the subsequent manufacturing process of large-size display panels based on this array substrate. Furthermore, the formation of the film structure within the first splicing display area requires two exposures, both of which utilize the first and second masks of the photomask. After both exposures and development of the photoresist film, only the photoresist formed within the first exposure area based on the first mask is retained. Therefore, in the patterned film layer structure formed based on the same mask in the array substrate, the unit area of ​​the pattern located in the first splicing display area is approximately equal to the unit area of ​​the pattern located in the normal display area. Thus, the uniformity of each patterned film layer structure in the array substrate of this application embodiment is good, resulting in a better display effect for the display panel subsequently formed based on this array substrate. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a top view of an array substrate provided in an embodiment of this application;

[0061] Figure 2 yes Figure 1 The diagram shows the film structure of the array substrate at point A-A'.

[0062] Figure 3 yes Figure 1 The image shows a partial enlarged view of the array substrate at point B;

[0063] Figure 4 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at point C;

[0064] Figure 5This is a schematic diagram illustrating two exposures of a target splicing display area provided in an embodiment of this application;

[0065] Figure 6 This is a schematic diagram of the structure of a mask provided in an embodiment of this application;

[0066] Figure 7 This is another schematic diagram of two exposures of the target splicing display area provided in an embodiment of this application;

[0067] Figure 8 This is a top view of another array substrate provided in the embodiments of this application;

[0068] Figure 9 yes Figure 8 The diagram shows the film structure of the array substrate at point A-A'.

[0069] Figure 10 This is a top view of a first sub-pixel in an array substrate provided in an embodiment of this application;

[0070] Figure 11 This is a top view of another first sub-pixel in the array substrate provided in the embodiments of this application;

[0071] Figure 12 This is a top view of yet another first sub-pixel in the array substrate provided in the embodiments of this application;

[0072] Figure 13 This is a top view of another first sub-pixel in the array substrate provided in the embodiments of this application. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0074] Please refer to Figure 1 , Figure 1 This is a top view of an array substrate provided in an embodiment of this application. The array substrate 000 has a display area 001 and a non-display area 002 located around the display area 001. For a clearer view of the film structure of the array substrate 000, please refer to... Figure 2 , Figure 2 yes Figure 1 The diagram shows a schematic of the film structure of the array substrate at A-A'. The array substrate 000 may include: a substrate 100, and a plurality of patterned film structures 100a stacked on the substrate 100.

[0075] Multiple patterned film structures 100a are used to form multiple sub-pixels. For a clearer view of the structure of these multiple sub-pixels, please refer to... Figure 3 , Figure 3 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at point B. The plurality of sub-pixels, composed of multiple patterned film structures 100a, may include: a first sub-pixel 100a1 located within the display area 001, and a virtual sub-pixel 100a3 located within the non-display area 002. In this application, the orthographic projection of the pixel electrode in the virtual sub-pixel 100a3 onto the substrate 100 is larger than the area of ​​the orthographic projection of the pixel electrode in the first sub-pixel 100a1 onto the substrate 100.

[0076] It should be noted that, in the embodiments of this application, the area of ​​the orthographic projection of the pixel electrode of a sub-pixel onto the substrate refers to the area enclosed by the outer contour of the orthographic projection of this pixel electrode onto the substrate. It should also be noted that the embodiments of this application are illustrated by the example where the orthographic projections of the pixel electrodes of each virtual sub-pixel arranged in the non-display area are all larger than the area of ​​the orthographic projection of the pixel electrode of the first sub-pixel. In other possible implementations, the orthographic projections of the pixel electrodes of some virtual sub-pixels arranged in the non-display area may be larger than the area of ​​the orthographic projection of the pixel electrode of the first sub-pixel, while the orthographic projections of the pixel electrodes of another set of virtual sub-pixels may be equal to the area of ​​the orthographic projection of the pixel electrode of the first sub-pixel. The embodiments of this application do not limit this.

[0077] In the embodiments of this application, such as Figure 1 As shown, the display area 001 may include: a plurality of normal display areas 001a arranged in an array, and a first splicing display area 001b located between two adjacent normal display areas 001a. Here, the plurality of normal display areas 001a within the display area 001 may be arranged in an array as at least one row and / or at least one column. Figure 1 The illustration is based on the example of multiple normal display areas 001a arrays arranged in two rows and two columns within display area 001.

[0078] like Figure 3 and Figure 4 , Figure 4 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at point C. Multiple first sub-pixels 100a1 are distributed within the normal display area 001a of the array substrate 000. The multiple sub-pixels, composed of multiple patterned film structures 100a, may further include multiple second sub-pixels 100a2 located within the first splicing display area 001b. Here, the orthographic projection of the pixel electrode in the virtual sub-pixel 100a3 onto the substrate 100 is also larger than the area of ​​the orthographic projection of the pixel electrode in the second sub-pixel 100a2 onto the substrate 100.

[0079] In this embodiment, in each patterned film structure 100a in the array substrate 000, the portion located within the normal display area 001a is formed based on a first mask of a mask plate, the portion located within the non-display area 002 is formed based on a second mask of a mask plate, and the portion located within the first splicing display area 001b is formed based on both the first and second masks. Here, the first mask and the second mask are masks located in different areas of the same mask plate.

[0080] It should be noted that each patterned film structure 100a in the array substrate 000 is formed based on a mask in a photomask. For example, when it is necessary to form a certain patterned film structure in the array substrate 000, firstly, a whole-layer film structure can be formed on the substrate 100 and a photoresist film can be coated; then, the same photomask is used to perform an exposure operation on the portion of the photoresist film located within multiple normal display areas 001a; then, the exposed photoresist film is developed and the whole-layer film structure is etched; finally, the photoresist on the substrate is peeled off, and a patterned film structure can be formed on the substrate 100.

[0081] The exposure operation performed on a portion of the photoresist film located within a normal display area may include: forming a first exposure area within the first normal display area and the target spliced ​​display area using a first mask in a masking plate, and forming a second exposure area within a non-display area and the target spliced ​​display area using a second mask in the masking plate; moving the masking plate in a direction toward the second normal display area until the first mask can cover the second normal display area and the second exposure area located within the target spliced ​​display area, and the second mask can cover the first exposure area located within the target spliced ​​display area. Here, the first normal display area is any one of a plurality of normal display areas 001a, the second normal display area is a normal display area adjacent to the first normal display area, and the target spliced ​​display area is the first spliced ​​display area located between the first normal display area and the second normal display area.

[0082] It should be noted that after exposing the photoresist film using the mask in the photomask, an exposure area can be formed in the photoresist film. Subsequently, after developing the exposed photoresist film, the photoresist outside the exposure area is removed, while the photoresist inside the exposure area is retained to obtain a photoresist pattern. Therefore, in the patterned film structure 100a formed based on the same photomask in the array substrate 000, the portion located in the normal display area 001a is formed based on the first mask of this photomask, the portion located in the non-display area 002 is formed based on the second mask of this photomask, and the portion located in the first splicing display area 001b is formed based on both the first and second masks of this photomask.

[0083] It should also be noted that while the first and second masks in the photomask have similar shapes, the unit area of ​​the second exposure area formed by exposing the photoresist film using the second mask is larger than the unit area of ​​the first exposure area formed by exposing the photoresist film using the first mask. Thus, in the patterned film structure 100a formed on the same photomask in the array substrate 000, the unit area of ​​the pattern located in the non-display area 002 is larger than the unit area of ​​the pattern located in the normal display area 001a. Consequently, the orthographic projection of the virtual sub-pixel 100a3 located in the non-display area 002 onto the substrate 100 is larger than the area of ​​the orthographic projection of the first sub-pixel 100a1 located in the normal display area 001a onto the substrate 100. It should be pointed out that the unit area of ​​the pattern in this embodiment refers to the area of ​​the pattern within the same region, for example, the region may refer to the sub-pixel region in the array substrate 000.

[0084] In this embodiment, the portion of the photoresist film located within the first splicing display area is exposed twice. For example, as... Figure 5 As shown, Figure 5 This is a schematic diagram illustrating a double exposure of a target splicing display area according to an embodiment of this application. During the exposure of the portion of the photoresist film located within the first normal display area AA1 by the first mask in the photomask, the first and second masks in the same photomask can be used to perform a first exposure of the photoresist within the target splicing display area AA2, forming a first exposure area B11 and a second exposure area B12 within the portion of the photoresist film located within the target splicing display area AA2. During the exposure of the portion of the photoresist film located within the second normal display area AA3 by the first mask in the photomask, the first and second masks in the same photomask can be used to perform a second exposure of the photoresist within the target splicing display area AA2, forming a first exposure area B21 and a second exposure area B22 within the portion of the photoresist film located within the target splicing display area AA2.

[0085] Here, in the portion of the photoresist film located within the target splicing display area AA2, the center point of the first exposure area B11 formed during the first exposure coincides with the center point of the second exposure area B22 formed during the second exposure, and the center point of the second exposure area B12 formed during the first exposure coincides with the center point of the first exposure area B21 formed during the second exposure. Furthermore, since the unit area of ​​the first exposure area is smaller than that of the second exposure area, after two exposures of the portion of the photoresist film located within the target splicing display area AA2, and after development of the photoresist film, only the photoresist within the smaller unit area of ​​the first exposure area will be retained; that is, only the photoresist within the first exposure area B11 formed during the first exposure and the first exposure area B12 formed during the second exposure will be retained. It should be noted that... Figure 5 In the diagram, the dotted pattern represents the exposed area formed during the first exposure, and the white pattern represents the exposed area formed during the second exposure. Figure 5 The first row of exposure areas represents the exposure area formed only during the first exposure, the second row of exposure areas represents the exposure area formed only during the second exposure, and the third row of exposure areas represents the exposure area formed during the first exposure, which is formed during both exposures.

[0086] Thus, in the patterned film structure 100a formed on the same mask in the array substrate 000, the unit area of ​​the pattern located in the first splicing display area 001b is smaller than the unit area of ​​the pattern located in the non-display area 002. Consequently, the area of ​​the orthographic projection of the second sub-pixel 100a2 located in the first splicing display area 001b onto the substrate 100 is smaller than the area of ​​the orthographic projection of the virtual sub-pixel 100a3 located in the non-display area 002 onto the substrate 100.

[0087] In related technologies, if a double-exposure method is used to form the film layer structure within the first splicing display area, the same mask is used for both exposures. This results in a smaller unit area of ​​the film layer structure formed in the first splicing display area compared to the unit area of ​​the film layer structure formed in the normal display area. This leads to poor uniformity of the patterned film layer structure within the array substrate, consequently resulting in a poor display effect in the subsequent display panel formation.

[0088] In this embodiment, the formation of the film layer structure within the first splicing display area 001b requires two exposures. Both exposures utilize both the first and second masks from the photomask. After the two exposures and development of the photoresist film, only the photoresist within the first exposure area formed by the first mask is retained. Similarly, the formation of the film layer structure within the normal display area 001a requires one exposure. After this exposure and development of the photoresist film, only the photoresist within the first exposure area formed by the first mask is retained. Therefore, in the patterned film layer structures 100a formed on the same photomask in the array substrate 000, the unit area of ​​the pattern within the first splicing display area 001b is approximately equal to the unit area of ​​the pattern within the normal display area 001a. Thus, the uniformity of the various patterned film layer structures 100a within the array substrate 000 in this embodiment is good, resulting in a better display effect for the subsequent display panel formed on this array substrate 000.

[0089] In summary, the array substrate provided in this application includes: a substrate, and a plurality of patterned film structures stacked on the substrate. Since the portion of the patterned film structure located within the first splicing display area is formed based on the first and second masks of a mask plate, and the portion of the patterned film structure located within the normal display area can also be formed based on the first mask, and the portion of the patterned film structure located within the non-display area can also be formed based on the second mask, the formation of the patterned film structure in this array eliminates the need for separate exposure of the photoresist within the first splicing display area using an additional mask plate. This effectively reduces the number of exposures and simplifies the subsequent manufacturing process of the large-size display panel fabricated based on this array substrate. Furthermore, the formation of the film structure within the first splicing display area requires two exposures, both of which utilize the first and second masks of the mask plate. After the two exposures and development of the photoresist film, only the photoresist formed within the first exposure area based on the first mask is retained. Therefore, in the patterned film layer structure formed based on the same mask in the array substrate, the unit area of ​​the pattern located in the first splicing display area is approximately equal to the unit area of ​​the pattern located in the normal display area. Thus, the uniformity of each patterned film layer structure in the array substrate of this application embodiment is good, resulting in a better display effect for the display panel subsequently formed based on this array substrate.

[0090] In one exemplary implementation, exposure errors typically occur during the double exposure of the same area in the photoresist film. Therefore, in the patterned film structure 100a formed on the same mask in the array substrate 000, the unit area of ​​the pattern within the first splicing display area 001b is slightly smaller than the unit area of ​​the pattern within the normal display area 001a. For example, when this patterned film structure 100a includes signal lines, the width of the signal lines within the first splicing display area 001b is 0.1 to 2 micrometers smaller than the width of the signal lines within the normal display area 001a. Consequently, the area of ​​the orthographic projection of the second sub-pixel 100a2 within the first splicing display area 001b onto the substrate 100 is less than or equal to the area of ​​the orthographic projection of the first sub-pixel 100a1 within the normal display area 001a onto the substrate 100.

[0091] Optional, such as Figure 1 As shown, the display area 001 of the array substrate 000 may further include a second splicing display area 001d located between two first splicing display areas 001b arranged in the row direction and two first splicing display areas 001b arranged in the column direction. The plurality of sub-pixels composed of multiple patterned film structures 100a may further include multiple fourth sub-pixels located within the second splicing display area 001d. In one possible implementation, since four exposure processes are required in the second splicing display area 001d during the fabrication of the patterned film structures 100a in the array substrate 000, the unit area of ​​the pattern portion within the second splicing display area 001d is slightly smaller than the unit area of ​​the pattern portion within the first splicing display areas 001b in the patterned film structures 100a formed based on the same mask in the array substrate 000. Thus, the area of ​​the orthographic projection of the fourth sub-pixel located in the second splicing display area 001d onto the substrate 100 is less than or equal to the area of ​​the orthographic projection of the second sub-pixel 100a2 located in the first splicing display area 001b onto the substrate 100.

[0092] In the embodiments of this application, such as Figure 4As shown, the multiple sub-pixels composed of multiple patterned film layer structures 100a may further include multiple third sub-pixels 100a4. Here, a portion of the third sub-pixels 100a4 may be located within the normal display area 001a, and another may be located within the first splicing display area 00a2. In this case, the boundary line between the first splicing display area 001b and the normal display area 001a in the array substrate 000 is located within the area where the third sub-pixels 100a4 are located. Since the pattern area within the area where the third sub-pixels 100a1 are located is larger than the pattern area between two adjacent columns of sub-pixels, when the boundary between the first splicing display area 001b and the normal display area 001a is located within the area where the third sub-pixels 100a4 are located, it can be ensured that the arrangement of the patterned film layer structures within the first splicing display area 001b is relatively uniform.

[0093] For example, in the length direction parallel to the first splicing display area 100a1, that is... Figure 4 In the X direction, the width of the portion of the third sub-pixel 100a4 located within the first splicing display area 001b is less than or equal to the width of the third sub-pixel 100a4 located within the normal display area 001a. It should be noted that, in the length direction parallel to the first splicing display area 100a1, the width of the portion of the third sub-pixel 100a4 located within the first splicing display area 001b can be equal to the width of the third sub-pixel 100a4 located within the normal display area 001a. However, in some exemplary implementations, due to the inherent exposure error during two exposures, the width of the portion of the third sub-pixel 100a4 located within the first splicing display area 001b will be slightly smaller than the width of the third sub-pixel 100a4 located within the normal display area 001a.

[0094] In order to fabricate the array substrate that simultaneously includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a virtual sub-pixel in the above embodiments, it is necessary to block a portion of the second mask in the photoresist film during the exposure process using a photomask. The following embodiments will describe this in detail:

[0095] Please refer to Figure 6 , Figure 6This is a schematic diagram of a photomask provided in an embodiment of this application. The photomask 111 may include a first mask 111a and a second mask 111b distributed around the first mask 111a. During the formation of the patterned film structure 100a in the array substrate 000, after a full layer of photoresist film is formed on the substrate, the first mask 111a in the photomask 111 is used to expose portions of the normal display area 001a and the first spliced ​​display area 001b in the photoresist film, and the second mask 111b in the photomask 111 is used to expose portions of the first spliced ​​display area 001b and the non-display area 002 in the photoresist film.

[0096] Please refer to Figure 7 , Figure 7 This is a schematic diagram of another method for double exposure of the target splicing display area provided in this application embodiment. In order to form the third sub-pixel 100a4 in the array substrate, during the exposure of the portion of the photoresist film located within the first normal display area AA1 by the first mask 111a in the mask 111, a shielding plate 222 is used to shield the portion of the second mask 111b of the mask 111 that is close to the second normal display area AA3. Similarly, during the exposure of the portion of the photoresist film located within the second normal display area AA3 by the first mask 111a in the mask 111, a shielding plate 222 is used to shield the portion of the second mask 111b of the mask 111 that is close to the first normal display area AA1.

[0097] Assume that the second mask 111b in mask 222 can form the film layer structure within the two rows of sub-pixels. Further assume that while the first mask 111a in mask 111 exposes the portion of the photoresist film located within the first normal display area AA1, the exposure of the target splicing display area AA2 is the first exposure; and while the first mask 111a in mask 111 exposes the portion of the photoresist film located within the second normal display area AA3, the exposure of the target splicing display area AA2 is the second exposure.

[0098] Therefore, during the first exposure of the target splicing display area AA2, the portion of the first mask 111a of the mask plate 111 used to form a row of half-sub-pixels needs to be exposed to the target splicing display area AA2 to form the first exposure area B11 within the target splicing display area AA2. Furthermore, the blocking plate 222 needs to block the portion of the second mask 111b of the mask plate 111 used to form a row of half-sub-pixels, so that the unblocked portion of the second mask 111b exposes the target splicing display area AA2 to form the second exposure area B12 within the target splicing display area AA2. Subsequently, a row of half-sub-pixels can be formed based on the first exposure area B11, and a half-row of sub-pixels can be formed based on the second exposure area B12.

[0099] During the second exposure of the target splicing display area AA2, the portion of the first mask 111a of the mask plate 111 used to form half a row of sub-pixels needs to be exposed to the target splicing display area AA2 to form the first exposure area B12 within the target splicing display area AA2. Furthermore, the blocking plate 222 needs to block the portion of the second mask 111b of the mask plate 111 used to form half a row of sub-pixels, allowing the unblocked portion of the second mask 111b to expose the target splicing display area AA2, thus forming the second exposure area B12 within the target splicing display area AA2. If the influence of the first exposure is not considered, then subsequently, half a row of sub-pixels can be formed based on the first exposure area B21, and subsequently, a row and a half row of sub-pixels can be formed based on the second exposure area B22.

[0100] In this scenario, considering the impact of both exposures, after the first exposure forms the first exposure area B11, the area containing this first exposure area B11 is the same as the area containing the second exposure area B22 formed in the subsequent second exposure. Furthermore, the area of ​​the first exposure area B11 is smaller than the area of ​​the second exposure area B22. Therefore, the second exposure area B22 formed in the second exposure does not affect the area of ​​the first exposure area B11 formed in the first exposure. Similarly, after the first exposure forms the second exposure area B12, the area containing this second exposure area B12 is the same as the area containing the first exposure area B21 formed in the subsequent second exposure. Furthermore, the area of ​​the second exposure area B12 is larger than the area of ​​the first exposure area B21. Therefore, after the second exposure, the second exposure area B12 formed in the first exposure can be treated as the first exposure area B21. This ensures that when the portion of the photoresist film located within the target splicing display area AA2 is exposed twice, and after development of the photoresist film, only the photoresist within the first exposure area B11 formed in the first exposure and the first exposure area B12 formed in the second exposure will be retained.

[0101] Thus, if the photoresist film is exposed in the above manner during the process of forming the patterned film structure in the array substrate 000, the third sub-pixel 100a4 can be formed in the array substrate 000 thereafter.

[0102] It should be noted that the first normal display area AA1 and the second normal display area AA3 shown in the above embodiments are illustrated using two normal display areas arranged horizontally as an example. The exposure method for the two normal display areas arranged vertically and the first splicing display area located between them is the same as the exposure method for the normal display areas arranged horizontally and the first splicing display area located between them, and will not be described again in this embodiment.

[0103] Optional, please refer to Figure 8 and Figure 9 , Figure 8 This is a top view of another array substrate provided in an embodiment of this application. Figure 9 yes Figure 8 The diagram shows the film structure of the array substrate at A-A'. Each normal display area 001a in the array substrate 000 has multiple alignment areas 001c.

[0104] In the array substrate 000, the film structure closest to the substrate 100 among the multiple patterned film structures 100a is the first conductive layer 200. The first conductive layer 200 may include multiple first alignment structures 201 located within each alignment region 001c. Figure 8 and Figure 9 Not marked in the text, will be added later. Figure 10 (This is annotated in the text). The orthographic projections of each first alignment structure 201 on the substrate 100 do not coincide.

[0105] In the array substrate 000, all patterned film structures 100a except for the first conductive layer 200 include: a second alignment structure located in the alignment region. Figure 8 and Figure 9 (Not marked in the text). The orthographic projections of the second alignment structure in each patterned film structure 100a onto the substrate 100 do not coincide.

[0106] In this application, the area in the normal display area 001a of the array substrate 000 where the first alignment structure 201 and the second alignment structure 202 are disposed can be referred to as the alignment region 001c. Within the same alignment region 001c, there are multiple first alignment structures 201 and multiple second alignment structures, and these multiple first alignment structures 201 can correspond one-to-one with the multiple second alignment structures. It should be noted that since each patterned film structure 100a within the same alignment region 001c has one second alignment structure, the number of first alignment structures 201 and the number of second alignment structures within the same alignment region 001c are the same as the number of film layers in the multiple patterned film structures 100a, excluding the first conductive layer 200.

[0107] For example, such as Figure 9 As shown, the number of film layers in the multiple patterned film layer structures 100a, excluding the first conductive layer 200, is four: an active layer pattern 300, a second conductive layer 400, a planarization layer 500, and a pixel electrode layer 600. The active layer pattern 300, the second conductive layer 400, the planarization layer 500, and the pixel electrode layer 600 can be sequentially stacked along a direction perpendicular to and away from the substrate 100. Therefore, the number of first alignment structures 201 and second alignment structures within the same alignment region 001c is four. It should be noted that the array substrate 000, in addition to containing multiple patterned film layer structures 100a, also includes integrally formed film layer structures. For example, the array substrate 000 may also include an integrally formed gate insulating layer 700 located between the active layer pattern 300 and the first conductive layer 200. Here, the patterned film structure in the array substrate 000 refers to the film structure that needs to be formed based on a mask and through a patterning process, while the film structure set in an integral layer in the array substrate 000 refers to the film structure that does not need to be formed through a patterning process.

[0108] In this application, the positional relationship between the orthographic projection of the first alignment structure 201 on the substrate 100 and the orthographic projection of the corresponding second alignment structure on the substrate 100 satisfies a preset positional relationship. Here, satisfying the preset positional relationship means that the distance between the orthographic projection of the first alignment structure 201 on the substrate 100 and the orthographic projection of the corresponding second alignment structure on the substrate 100 is within a preset range, and the first alignment structure 201 and the second alignment structure 202 are parallel to each other.

[0109] In this embodiment, to ensure a good display effect with the display panel formed on the array substrate 000, it is necessary to ensure that the position of each stacked patterned film layer structure 100a does not shift during the formation of multiple stacked patterned film layer structures 100a. To this end, by designing a first alignment structure 201 and a second alignment structure, and ensuring that the positional relationship between the orthographic projection of each first alignment structure 201 on the substrate 100 and the orthographic projection of the corresponding second alignment structure on the substrate 100 satisfies a preset positional relationship, it can be guaranteed that none of the patterned film layer structures 100a will shift relative to the first conductive layer 200.

[0110] For example, during the fabrication of the array substrate 000, after forming a first conductive layer 200 containing multiple first alignment structures on the substrate 100, it is necessary to form other patterned film structures on the first conductive layer. During the formation of these other patterned film structures, after exposing the photoresist film using the exposure method described in the above embodiments and developing the exposed photoresist film, a photoresist pattern with the same shape as this patterned film structure can be obtained. Therefore, this photoresist pattern includes a photoresist alignment structure with the same shape as the second alignment structure in the patterned film structure. Subsequently, after determining that the positional relationship between the orthographic projection of this photoresist alignment structure on the substrate 100 and the orthographic projection of the corresponding first alignment structure 201 on the substrate 201 satisfies a preset relationship, subsequent etching processing can be performed; otherwise, the photoresist pattern needs to be stripped, and the photoresist coating, exposure, and development process needs to be repeated. In this case, during the subsequent etching process to obtain a patterned film structure, the positional relationship between the orthographic projection of the second alignment structure in this patterned film structure on the substrate 100 and the orthographic projection of the corresponding first alignment structure 201 on the substrate 201 satisfies a preset relationship.

[0111] Optionally, the first conductive layer 200 in the array substrate 000 typically includes signal lines electrically connected to the sub-pixels, and these signal lines are generally located on the periphery of the sub-pixel's region. Therefore, to ensure that the first alignment structure 201 does not affect the positional distribution of the signal lines, both the first alignment structure 201 and its corresponding second alignment structure can be disposed within the sub-pixel's region. That is, the orthographic projections of the first alignment structure 201 and its corresponding second alignment structure on the substrate 100 can lie within the same orthographic projection of the first sub-pixel 100a1 on the substrate 100. Furthermore, to facilitate subsequent determination of the positional relationship between the second alignment structure and its corresponding first alignment structure in different patterned film structures, each first alignment structure 201 and its corresponding second alignment structure can be disposed within a different sub-pixel's region. That is, the orthographic projections of each first alignment structure 201 on the substrate 100 lie within different orthographic projections of the first sub-pixel 100a1 on the substrate 100.

[0112] In the embodiments of this application, such as Figure 10 , Figure 11 , Figure 12 and Figure 13 As shown, Figure 10 This is a top view of a first sub-pixel in an array substrate provided in an embodiment of this application. Figure 11 This is a top view of another first sub-pixel in the array substrate provided in the embodiments of this application. Figure 12 This is a top view of another first sub-pixel in the array substrate provided in the embodiments of this application. Figure 13 This is a top view of another first sub-pixel in the array substrate provided in this application embodiment. The first alignment structure 201 may include at least one first strip structure 2011 and at least one second strip structure 2022. The length direction of the first strip structure 2011 may intersect the length direction of the second strip structure 2012. For example, the length direction of the first strip structure 2011 may be perpendicular to the length of the second strip structure 2012.

[0113] Optionally, the first alignment structure 201 can be an electrode block, in which case the first strip structure 2011 and the second strip structure 2012 can be strip-shaped grooves located within the electrode block. In this case, the orthographic projection of the alignment structure 401 corresponding to the first alignment structure 201 on the substrate 100 lies within the orthographic projection of the first alignment structure 201 on the substrate 100. In other possible implementations, the first alignment structure 2011 and the second alignment structure 2012 can also both be strip-shaped protrusions, thus the first alignment structure can be at least two electrode strips. This application does not limit this aspect.

[0114] It should be noted that, Figure 10This illustrates the positional relationship between the first alignment structure 201 and the second alignment structure 302 in the active layer pattern 300. Figure 11 This shows the positional relationship between the first alignment structure 201 and the second alignment structure 401 in the second conductive layer 400. Figure 12 This diagram illustrates the positional relationship between the first alignment structure 201 and the second alignment structure 502 in the planarization layer 500. Figure 13 Shown Figure 11 This illustrates the positional relationship between the first alignment structure 201 and the second alignment structure 602 in the pixel electrode layer 600. The following embodiments will use... Figure 11 The positional relationship between the second alignment structure 401 and the corresponding first alignment structure 201 is explained in detail using the example of the second alignment structure 401 and the corresponding first alignment structure 201.

[0115] like Figure 11 As shown, the second alignment structure 401 corresponding to the first alignment structure 201 may include at least one third strip structure 4011 and at least one fourth strip structure 4012.

[0116] In the first alignment structure 201 and the corresponding second alignment structure 401, the length direction of the third strip structure 4011 can be parallel to the length direction of the first strip structure 2011, and the distance between the orthographic projection of the third strip structure 4011 on the substrate 100 and the orthographic projection of the first strip structure 2011 on the substrate 100 is within a first preset range; the length direction of the fourth strip structure 4012 can be parallel to the length direction of the second strip structure 2012, and the distance between the orthographic projection of the fourth strip structure 4012 on the substrate 100 and the orthographic projection of the second strip structure 2012 on the substrate 100 is within a second preset range. Thus, the positional relationship between the orthographic projections of the first alignment structure 201 and the second alignment structure 401 on the substrate satisfies a preset relationship, ensuring that the second conductive layer 400 containing the second alignment structure 401 will not shift relative to the first conductive layer 100 in any direction.

[0117] For example, the number of first stripe structures 2011 and second stripe structures 2012 in the first alignment structure 201 is one; the number of third stripe structures 4011 and fourth stripe structures 4012 in the second alignment structure 401 is two. In the first alignment structure 201 and the corresponding second alignment structure 401, the first stripe structure 2011 can be located between two third stripe structures 4011, and the difference in distance between the orthographic projection of the two third stripe structures 4011 on the substrate 100 and the orthographic projection of the first stripe structure 2012 on the substrate 100 is less than a first preset threshold; the second stripe structure 2012 can be located between two fourth stripe structures 4012, and the difference in distance between the orthographic projection of the two fourth stripe structures 4012 on the substrate 100 and the orthographic projection of the second stripe structure 4012 on the substrate 100 is less than a second preset threshold. Here, the first preset threshold can be equal to the second preset threshold, and both the first and second preset thresholds can be 1.5 micrometers. That is, when the difference between the orthographic projections of the two third strip structures 4011 on the substrate 100 and the orthographic projection of the first strip structure 2012 on the substrate 100 is less than 1.5 micrometers, and the difference between the orthographic projections of the two fourth strip structures 4012 on the substrate 100 and the orthographic projection of the second strip structure 4012 on the substrate 100 is also less than 1.5 micrometers, the positional relationship between the orthographic projections of the first alignment structure 201 and the second alignment structure 401 on the substrate satisfies the preset relationship.

[0118] It should be noted that, for the positional relationship between the second alignment structure and the first alignment structure in the multiple patterned film structures other than the second conductive layer 400, the positional relationship between the second alignment structure 401 and the first alignment structure 201 in the second conductive layer 400 can be referred to. This application embodiment will not elaborate on this.

[0119] In this embodiment, the active layer pattern 300, the second conductive layer 400, and the pixel electrode layer 600 in the array substrate 000 are all patterned structures. Therefore, the third and fourth strip structures in these structures can both be strip-shaped protrusions. For the planarization layer 500 in the array substrate 000, since it is an insulating layer and requires multiple vias, the third and fourth strip structures in this layer are both strip-shaped grooves.

[0120] Optionally, multiple alignment regions 001c within each normal display area 001a can be evenly arranged at the edge positions of this normal display area 001a. Since, in each patterned film structure 100a in the array substrate 000, if a patterned film structure is offset relative to the first conductive layer 200, the film offset phenomenon is more obvious at the edge positions. Therefore, the alignment regions 001c can be set at the edge positions within the normal display area 001a. In this way, after the positions of each first alignment structure 201 and the corresponding second alignment structure within the alignment region 001c, projected onto the substrate 100, satisfy a preset positional relationship, it can be ensured that the patterned film structure containing the second alignment structure will not be offset from the first conductive layer 200 at any position.

[0121] In this application, the first conductive layer 200 includes, in addition to the first alignment structure 201, the first conductive layer 200 may also include: the gate 202 of the thin film transistor in the sub-pixel, and the gate line 203 electrically connected to the gate 202.

[0122] In addition to the second alignment structure, the active layer pattern 300 may also include an active layer 301 of a thin-film transistor in a sub-pixel. The orthographic projection of the active layer 301 of the thin-film transistor onto the substrate 100 may coincide with the orthographic projection of the gate 202 of the thin-film transistor onto the substrate 100, and the active layer 301 and the gate 202 may be insulated from each other by a gate insulating layer 700.

[0123] In addition to the second alignment structure 401, the second conductive layer 400 may also include: a first electrode 402 and a second electrode 403 of a thin-film transistor in a sub-pixel, and a data line 404 electrically connected to the first electrode 402.

[0124] In addition to having a second alignment structure, the planarization layer 500 also has a connecting via 501.

[0125] In addition to the second alignment structure 401, the pixel electrode layer 600 may also include a pixel electrode 601 in a sub-pixel. The pixel electrode 601 can be electrically connected to the second electrode 403 of a thin-film transistor via a connecting via 501.

[0126] In this application, the array substrate 300 contains multiple gate lines 203 and multiple data lines 404 arranged in parallel, and the length direction of the gate lines 203 can be perpendicular to the length direction of the data lines 404. Thus, any two adjacent gate lines 203 and any two adjacent data lines 404 can form a sub-pixel region, and one sub-pixel can be arranged within a sub-pixel region.

[0127] Optional, such as Figure 13As shown, since the pixel electrode 601 in the sub-pixel is usually block-shaped, the horizontal distance between the pixel electrode 601 and the gate line 203 is relatively small, as is the horizontal distance between the pixel electrode 601 and the data line 404. Therefore, in order to properly arrange the second alignment structure 602 in the pixel electrode layer 600 within the sub-pixel region, a hollow structure 6011 can be provided in the pixel electrode 601 of the first sub-pixel whose orthographic projection on the substrate 100 overlaps with the second alignment structure 602 in the pixel electrode layer 600. This ensures that the orthographic projections of the second alignment structure 602 in the pixel electrode layer 600 and the corresponding first alignment structure 201 on the substrate 100 are both located within the orthographic projection of this hollow structure 6011 on the substrate 100. Thus, the pixel electrodes 601 arranged within the sub-pixel region do not affect the positional distribution of the second alignment structure 602. This ensures that during the fabrication of the pixel electrode layer 600, the positional relationship between the photoresist alignment structures corresponding to the first alignment structure 202 and the second alignment structure 602 can be used to ensure that the pixel electrode layer 600 does not shift relative to the first conductive layer 200. In other possible implementations, pixel electrodes may not be provided in the pixel electrodes 601 within the first sub-pixel whose orthographic projection onto the substrate 100 overlaps with the second alignment structure 602 in the pixel electrode layer 600.

[0128] In this embodiment, the first conductive layer 200 may further include an auxiliary signal line 204. The orthographic projection of the auxiliary signal line 204 onto the substrate 100 may overlap with the orthographic projection of the pixel electrode 601 in at least a portion of the sub-pixels onto the substrate 100. The overlapping portion of the auxiliary signal line 204 and the pixel electrode 601 can form a storage capacitor Cst, which maintains the pixel voltage applied to the pixel electrode 601, thus preventing changes in the pixel voltage used to maintain the pixel electrode 102. In this application, since the first alignment structure 201 is also arranged within the sub-pixel region where the pixel electrode 102 is located, to ensure that the first alignment structure 201 does not affect the auxiliary signal line 204, it is necessary to ensure that the orthographic projection of the auxiliary signal line 204 onto the substrate 100 does not coincide with the orthographic projection of the first alignment structure 202 onto the substrate 100. It should be noted that, since the first sub-pixel whose orthographic projection on the substrate 100 overlaps with the second alignment structure 602 in the pixel electrode layer 600 may not have a pixel electrode, or the pixel electrode 601 in this first sub-pixel may have a hollow structure 6011. Therefore, the orthographic projection of the auxiliary signal line 204 on the substrate 100 may not overlap with the orthographic projection of this first sub-pixel on the substrate 100, but the orthographic projection of the auxiliary signal line 204 on the substrate 100 must overlap with the orthographic projections of the pixel electrodes 601 in other sub-pixels on the substrate 100.

[0129] For example, the auxiliary signal line 204 may include: an auxiliary signal line body 2041, and a bent winding 2042 electrically connected to the auxiliary signal line body 2041. At least a portion of the first alignment structure 204 is located within the area enclosed by the bent winding 2042. This ensures that the orthographic projection of the first alignment structure 204 on the substrate 101 does not coincide with the orthographic projection of the auxiliary signal line 204 on the substrate. Here, the length direction of the auxiliary signal line body 2041 may be parallel to the length direction of the gate line 203; the bent winding 2042 consists of two first portions extending along the length direction of the data line 404, and a second portion located between these two first portions, the length direction of the second portion of the bent winding 2042 may be parallel to the length direction of the gate line 203. It should be noted that the area enclosed by the bent winding 2042 in this embodiment is not a closed area, but an open area.

[0130] In the embodiments of this application, such as Figure 10 and Figure 11 As shown, the first conductive layer 200 may further include a plurality of auxiliary alignment structures 205 located within the alignment region 001c. Each of the auxiliary alignment structures 205 corresponds one-to-one with a plurality of first alignment structures 202, and the orthographic projections of each auxiliary alignment structure 205 and its corresponding first alignment structure 202 onto the substrate 100 lie within the orthographic projection of the same first sub-pixel 100a1 onto the substrate 100. Here, the auxiliary alignment structure 205 may include an electrode block, an annular groove within the electrode block, and a cross-shaped groove within the annular groove.

[0131] For example, during the formation of a patterned film structure in the array substrate 000, excluding the first conductive layer 200, after forming a photoresist alignment structure corresponding to the second alignment structure in this patterned film structure, it is necessary to determine whether the positional relationship between this photoresist alignment structure and the corresponding first alignment structure 201 satisfies a preset positional relationship. In determining whether the positional relationship satisfies the preset positional relationship, it is necessary to acquire an image containing this photoresist alignment structure and the corresponding first alignment structure 100a1, and identify the photoresist alignment structure and the first alignment structure in the image to determine whether the positional relationship satisfies the preset positional relationship. However, because the patterned structure within the array substrate 000 is relatively complex, and the widths of the first strip structure 2011 and the second strip structure 2012 in the first alignment structure 201 are small, as are the widths of the third and fourth strip structures in the second alignment structure, the photoresist alignment structure and the first alignment structure in the image are not easily identified. To improve the efficiency of identifying the photoresist alignment structure and the first alignment structure in the image, an auxiliary alignment structure 205 can be provided within the first conductive layer 200. The auxiliary alignment structure 205 is easier to identify than the first alignment structure. Thus, the auxiliary alignment structure 205 can be identified first, followed by the identification of the photoresist alignment structure and the first alignment structure surrounding the auxiliary alignment structure 205, effectively improving the efficiency of identifying the photoresist alignment structure and the first alignment structure in the image.

[0132] In summary, the array substrate provided in this application includes: a substrate, and a plurality of patterned film structures stacked on the substrate. Since the portion of the patterned film structure located within the first splicing display area is formed based on the first and second masks of a mask plate, and the portion of the patterned film structure located within the normal display area can also be formed based on the first mask, and the portion of the patterned film structure located within the non-display area can also be formed based on the second mask, the formation of the patterned film structure in this array eliminates the need for separate exposure of the photoresist within the first splicing display area using an additional mask plate. This effectively reduces the number of exposures and simplifies the subsequent manufacturing process of the large-size display panel fabricated based on this array substrate. Furthermore, the formation of the film structure within the first splicing display area requires two exposures, both of which utilize the first and second masks of the mask plate. After the two exposures and development of the photoresist film, only the photoresist formed within the first exposure area based on the first mask is retained. Therefore, in the patterned film layer structure formed based on the same mask in the array substrate, the unit area of ​​the pattern located in the first splicing display area is approximately equal to the unit area of ​​the pattern located in the normal display area. Thus, the uniformity of each patterned film layer structure in the array substrate of this application embodiment is good, resulting in a better display effect for the display panel subsequently formed based on this array substrate.

[0133] This application also provides a method for manufacturing an array substrate, used to manufacture the array substrate described in the above embodiments. The array substrate has a display area and a non-display area located around the display area; the method includes: sequentially forming a plurality of patterned film layer structures stacked on a substrate.

[0134] The multiple patterned film structures are used to form multiple sub-pixels, which include multiple first sub-pixels located in the display area and multiple virtual sub-pixels located in the non-display area; the area of ​​the pixel electrode in the virtual sub-pixel projected onto the substrate is larger than the area of ​​the pixel electrode in the first sub-pixel projected onto the substrate.

[0135] Optionally, the display area includes: multiple normal display areas arranged in an array, and a first splicing display area located between two adjacent normal display areas; forming each patterned film layer structure includes:

[0136] A monolithically arranged film structure is formed on a substrate; a photoresist film is formed on the film structure, and a mask is used to sequentially expose portions of the photoresist film located in multiple normal display areas; the exposed photoresist film is developed, and the monolithically arranged film structure is etched to form a patterned film structure on the substrate.

[0137] The exposure operation performed on the portion of the photoresist film located within a normal display area includes: forming a first exposure area within the first normal display area and the target spliced ​​display area using a first mask in a masking plate, and forming a second exposure area within the non-display area and the target spliced ​​display area using a second mask in the masking plate; moving the masking plate in a direction toward the second normal display area until the first mask can cover the second normal display area and the second exposure area located within the target spliced ​​display area, and the second mask can cover the first exposure area located within the target spliced ​​display area. Here, the first normal display area is any one of a plurality of normal display areas, the second normal display area is a normal display area adjacent to the first normal display area, and the target spliced ​​display area is the first spliced ​​display area located between the first normal display area and the second normal display area.

[0138] Optionally, the unit area of ​​the first exposure area is smaller than the unit area of ​​the second exposure area.

[0139] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific process and principle of the above-described array substrate manufacturing method can be referred to the corresponding content in the aforementioned embodiments of the array substrate structure, and will not be repeated here.

[0140] In summary, the array substrate manufacturing method provided in this application includes: forming a plurality of patterned film layer structures stacked on a substrate. Since the portion of the patterned film layer structure located within the first splicing display area is formed based on the first and second masks of a mask plate, and the portion of the patterned film layer structure located within the normal display area can also be formed based on the first mask, and the portion of the patterned film layer structure located within the non-display area can also be formed based on the second mask, the process of forming the patterned film layer structure in this array eliminates the need for separate exposure of the photoresist within the first splicing display area using an additional mask plate, effectively reducing the number of exposures and simplifying the subsequent manufacturing process of the large-size display panel fabricated based on this array substrate. Furthermore, the process of forming the film layer structure within the first splicing display area requires two exposures, and both exposures utilize the first and second masks of the mask plate simultaneously. After the two exposures and the development of the photoresist film, only the photoresist formed within the first exposure area based on the first mask is retained. Therefore, in the patterned film layer structure formed based on the same mask in the array substrate, the unit area of ​​the pattern located in the first splicing display area is approximately equal to the unit area of ​​the pattern located in the normal display area. Thus, the uniformity of each patterned film layer structure in the array substrate of this application embodiment is good, resulting in a better display effect for the display panel subsequently formed based on this array substrate.

[0141] This application also provides a liquid crystal panel. This liquid crystal panel can be integrated into any large-size display device with display functionality, such as a television or screen. The array substrate may include: an array substrate and a color filter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the color filter substrate. This array substrate can be the array substrate shown in the above embodiments.

[0142] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0143] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0144] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate has a display area and a non-display area located around the display area; the array substrate includes: A substrate, and a plurality of patterned film structures stacked on the substrate; The patterned film structure is used to form a plurality of sub-pixels, the plurality of sub-pixels including: a plurality of first sub-pixels located in the display area, and a plurality of virtual sub-pixels located in the non-display area; The area of ​​the pixel electrode in the virtual sub-pixel projected onto the substrate is greater than the area of ​​the pixel electrode in the first sub-pixel projected onto the substrate. The display area includes: a plurality of normal display areas arranged in an array, and a first splicing display area located between two adjacent normal display areas, wherein the two adjacent normal display areas include a first normal display area and a second normal display area; the portion of the patterned film structure located within the first splicing display area is formed based on a first mask and a second mask of a mask plate, wherein the first mask and the second mask are different regions of the mask plate; the portion of the patterned film structure located within the normal display area is formed based on the first mask of the mask plate; and the portion of the patterned film structure located within the non-display area is formed based on the second mask of the mask plate, such that the portion of the patterned film structure located within the first splicing display area can be formed based on a first exposure process and a second exposure process; the first exposure process is the process of performing an exposure operation on the first splicing display area while forming the portion of the patterned film structure located within the first normal display area based on the first mask of the mask plate; and the second exposure process is the process of performing an exposure operation on the first splicing display area while forming the portion of the patterned film structure located within the second normal display area based on the first mask of the mask plate.

2. The array substrate according to claim 1, characterized in that, The normal display area is distributed with a plurality of first sub-pixels, and the plurality of sub-pixels further includes a plurality of second sub-pixels located in the first splicing display area; Wherein, the area of ​​the orthogonal projection of the pixel electrode in the second sub-pixel onto the substrate is less than or equal to the area of ​​the orthogonal projection of the pixel electrode in the first sub-pixel onto the substrate.

3. The array substrate according to claim 2, characterized in that, The plurality of sub-pixels further includes: a plurality of third sub-pixels, a portion of which is located within the normal display area and another portion is located within the first splicing display area; In the length direction parallel to the first splicing display area, the width of the portion of the third sub-pixel located within the first splicing display area is less than or equal to the width of the portion of the third sub-pixel located within the normal display area.

4. The array substrate according to claim 2, characterized in that, The display area further includes: a second splicing display area located between two first splicing display areas arranged along the row direction and two first splicing display areas arranged along the column direction; the plurality of sub-pixels further includes: a fourth sub-pixel located within the second splicing display area. The area of ​​the orthogonal projection of the pixel electrode in the fourth sub-pixel onto the substrate is less than or equal to the area of ​​the orthogonal projection of the pixel electrode in the second sub-pixel onto the substrate.

5. The array substrate according to any one of claims 1 to 4, characterized in that, The normal display area has multiple alignment regions; The film structure closest to the substrate among the multiple patterned film structures is a first conductive layer, which includes multiple first alignment structures located in the alignment region. Each of the multiple patterned film structures, except for the first conductive layer, includes a second alignment structure located within the alignment region, wherein the orthographic projections of the second alignment structures in each film structure on the substrate do not overlap. Within the same alignment region, multiple first alignment structures correspond one-to-one with multiple second alignment structures, and the positional relationship between the orthographic projection of the first alignment structure on the substrate and the orthographic projection of the corresponding second alignment structure on the substrate satisfies a preset positional relationship.

6. The array substrate according to claim 5, characterized in that, The orthographic projections of each first alignment structure on the substrate are located within the orthographic projections of different first sub-pixels on the substrate, and the orthographic projections of the first alignment structure and the corresponding second alignment structure on the substrate are located within the orthographic projections of the same first sub-pixel on the substrate.

7. The array substrate according to claim 6, characterized in that, The first alignment structure includes: at least one first strip structure and at least one second strip structure, wherein the length direction of the first strip structure intersects the length direction of the second strip structure; The second alignment structure corresponding to the first alignment structure includes: at least one third strip structure and at least one fourth strip structure; Wherein, the length direction of the third strip structure is parallel to the length direction of the first strip structure, and the distance between the orthographic projection of the third strip structure on the substrate and the orthographic projection of the first strip structure on the substrate is within a first preset value range; The length direction of the fourth strip structure is parallel to the length direction of the second strip structure, and the distance between the orthographic projection of the fourth strip structure on the substrate and the orthographic projection of the second strip structure on the substrate is within a second preset range.

8. The array substrate according to claim 7, characterized in that, The number of the first strip structure and the second strip structure is one, and the number of the third strip structure and the fourth strip structure in the second alignment structure are two. The first strip structure is located between the two third strip structures, and the difference between the distance between the orthographic projection of the two third strip structures on the substrate and the distance between the orthographic projection of the first strip structure on the substrate is less than a first preset threshold. The second strip structure is located between the two fourth strip structures, and the difference between the distance between the orthographic projection of the two fourth strip structures on the substrate and the distance between the orthographic projection of the second strip structure on the substrate is less than a second preset threshold.

9. The array substrate according to claim 8, characterized in that, The first alignment structure is an electrode block, and both the first strip structure and the second strip structure are strip grooves located within the electrode block. The orthographic projection of the second alignment structure on the substrate is located within the orthographic projection of the corresponding first alignment structure on the substrate.

10. The array substrate according to claim 9, characterized in that, The multiple patterned film structures, excluding the first conductive layer, are as follows: an active layer pattern, a second conductive layer, a planarization layer, and a pixel electrode layer. The active layer pattern, the second conductive layer, the planarization layer, and the pixel electrode layer are stacked sequentially along a direction perpendicular to and away from the substrate. The array substrate further includes: a gate insulating layer disposed entirely between the active layer pattern and the first conductive layer; The third and fourth strip structures in the active layer pattern, the second conductive layer, and the pixel electrode layer are all strip-shaped protrusions; the third and fourth strip structures in the planarization layer are all strip-shaped grooves.

11. The array substrate according to claim 10, characterized in that, The first conductive layer further includes: the gate of the thin-film transistor in the sub-pixel, and a gate line electrically connected to the gate; The active layer pattern further includes: the active layer of the thin-film transistor in the sub-pixel; The second conductive layer further includes: a first electrode and a second electrode of the thin-film crystal in the sub-pixel, and a data line electrically connected to the first electrode; The planarization layer also has connection vias; The pixel electrode layer further includes: a pixel electrode in the sub-pixel, wherein the pixel electrode is electrically connected to the second electrode through the connection via.

12. The array substrate according to claim 11, characterized in that, No pixel electrode is disposed in the first sub-pixel where the orthographic projection on the substrate overlaps with the second alignment structure in the pixel electrode layer; Alternatively, the pixel electrode in the first sub-pixel whose orthogonal projection on the substrate overlaps with the second alignment structure in the pixel electrode layer has a hollow structure, and the orthogonal projections of the second alignment structure and the corresponding first alignment structure in the pixel electrode layer on the substrate are both located within the orthogonal projection of the hollow structure on the substrate.

13. The array substrate according to any one of claims 6 to 12, characterized in that, The first conductive layer further includes: an auxiliary signal line, wherein the orthographic projection of the auxiliary signal line on the substrate overlaps with the orthographic projection of the pixel electrode in at least a portion of the sub-pixels on the substrate, and does not coincide with the orthographic projection of the first alignment structure on the substrate.

14. The array substrate according to claim 13, characterized in that, The auxiliary signal line includes: an auxiliary signal line body, and a bent winding electrically connected to the auxiliary signal line body, wherein at least a portion of the first alignment structure is located within the area enclosed by the bent winding.

15. The array substrate according to claim 14, characterized in that, The first conductive layer further includes: a plurality of auxiliary alignment structures located in the alignment region, wherein the plurality of auxiliary alignment structures correspond one-to-one with the plurality of first alignment structures, and the orthographic projections of the auxiliary alignment structures and the corresponding first alignment structures on the substrate are located within the orthographic projection of the same first sub-pixel on the substrate.

16. The array substrate according to any one of claims 6 to 12, characterized in that, The plurality of alignment regions in the normal display area are evenly distributed at the edge of the normal display area.

17. A method for manufacturing an array substrate, characterized in that, The array substrate has a display area and a non-display area located around the display area; the method includes: Multiple patterned film structures are sequentially stacked on a substrate; The patterned film structure is used to form a plurality of sub-pixels, the plurality of sub-pixels including: a plurality of first sub-pixels located in the display area, and a plurality of virtual sub-pixels located in the non-display area; The area of ​​the pixel electrode in the virtual sub-pixel projected onto the substrate is greater than the area of ​​the pixel electrode in the first sub-pixel projected onto the substrate. The display area includes: a plurality of normal display areas arranged in an array, and a first splicing display area located between two adjacent normal display areas, wherein the two adjacent normal display areas include a first normal display area and a second normal display area; the portion of the patterned film structure located within the first splicing display area is formed based on a first mask and a second mask of a mask plate, wherein the first mask and the second mask are different regions of the mask plate; the portion of the patterned film structure located within the normal display area is formed based on the first mask of the mask plate; and the portion of the patterned film structure located within the non-display area is formed based on the second mask of the mask plate, such that the portion of the patterned film structure located within the first splicing display area can be formed based on a first exposure process and a second exposure process; the first exposure process is the process of performing an exposure operation on the first splicing display area while forming the portion of the patterned film structure located within the first normal display area based on the first mask of the mask plate; and the second exposure process is the process of performing an exposure operation on the first splicing display area while forming the portion of the patterned film structure located within the second normal display area based on the first mask of the mask plate.

18. The method according to claim 17, characterized in that, Forming each of the patterned film structures includes: A continuous film structure is formed on the substrate; A photoresist film is formed on the film structure, and the photomask is used to sequentially expose portions of the photoresist film located within the plurality of normal display areas. The exposed photoresist film is developed, and the entire film structure is etched to form a patterned film structure on the substrate. The exposure operation performed on the portion of the photoresist film located within a normal display area includes: The first mask in the masking plate is used to form a first exposure area in the first normal display area and the target splicing display area, and the second mask in the masking plate is used to form a second exposure area in the non-display area and the target splicing display area; Move the mask plate in the direction toward the second normal display area until the first mask can cover the second normal display area and the second exposure area located in the target splicing display area, and the second mask can cover the first exposure area located in the target splicing display area; The first normal display area is any one of the plurality of normal display areas, the second normal display area is a normal display area adjacent to the first normal display area, and the target splicing display area is a first splicing display area located between the first normal display area and the second normal display area.

19. The method according to claim 18, characterized in that, The unit area of ​​the first exposure area is smaller than the unit area of ​​the second exposure area.

20. A liquid crystal panel, characterized in that, include: An array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 16.

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