Parallel access in memory arrays

Abstract

This application relates to parallel access in memory arrays. A set of memory cells of a memory device can be associated with an array of conductive structures, where such structures can be coupled using a set of transistors or other switching components activated by a first driver. The set of memory cells can be divided into two or more subsets of memory cells, where each subset can be associated with a respective second driver for driving access current through the memory cells of the subset. Two or more of such second drivers can operate simultaneously, which can support distributing current or distributing associated circuit structures over different footprints of the memory device as compared to other different implementations with a single such second driver.

Description

[0001] CROSS REFERENCE

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 686,240, titled “PARALLEL ACCESS IN A MEMORY ARRAY” by BOLANDRINA et al., filed March 3, 2022, assigned to the assignee hereof and expressly incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The technical field relates to parallel access in a memory array. BACKGROUND

[0004] Memory devices are widely used in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like to store information. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells can be programmed to one of two supported states, commonly denoted as a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the states stored in the memory device. To store information, a component can write (e.g., program, set, assign) the states in the memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, and the like. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logical state for a long period of time, even in the absence of an external power source. Memory cells configured in a volatile configuration can lose a stored state when disconnected from an external power source. SUMMARY

[0006] A device is described. The device can include a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each of the plurality of pillars coupled with a respective plurality of memory cells; a plurality of activation lines, each activation line usable to activate a respective set of the plurality of pillars along the second direction, having the second number of pillars; a plurality of first word lines, each first word line coupled with respective memory cells of each pillar in a first subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and a third number of pillars along the second direction and less than the second number of pillars; a first word line driver usable to bias one of the plurality of first word lines; a plurality of second word lines, each second word line coupled with respective memory cells of each pillar in a second subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and the third number of pillars along the second direction; and a second word line driver usable to bias one of the plurality of second word lines.

[0007] A method is described. The method can include accessing a memory array including a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each of the plurality of pillars coupled with a respective plurality of memory cells, wherein the accessing includes: coupling each pillar in a set of pillars along the second direction having the second number of pillars with a respective sense line; biasing, with a first word line driver, a first word line coupled with respective memory cells of each pillar in a first subset of the set of pillars during the coupling of each pillar in the set with the respective sense line, the first subset associated with a third number of pillars along the second direction and less than the second number of pillars; and biasing, with a second word line driver, a second word line coupled with respective memory cells of each pillar in a second subset of the set of pillars during the coupling of each pillar in the set with the respective sense line, the second subset associated with the third number of pillars along the second direction.

[0008] An apparatus is described. The apparatus can include a memory array comprising a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells; a first word line driver; a second word line driver; and circuitry coupled with the memory array, wherein to access the memory array, the circuitry can be used to: couple each pillar in a group of pillars along the second direction having the second number of pillars with a respective sense line; bias, with the first word line driver, a first word line coupled with respective memory cells of each pillar of a first subset of the group of pillars during coupling of each pillar in the group with the respective sense line, the first subset associated with a third number of pillars along the second direction that is less than the second number of pillars; and bias, with the second word line driver, a second word line coupled with respective memory cells of each pillar of a second subset of the group of pillars during coupling of each pillar in the group with the respective sense line, the second subset associated with the third number of pillars along the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a memory array that supports parallel access in a memory array is shown in accordance with examples disclosed herein.

[0010] Figure 2 A top view of an example of a memory array that supports parallel access in a memory array is shown in accordance with examples disclosed herein.

[0011] Figure 3A And 3B A side view of an example of a memory array that supports parallel access in a memory array is shown in accordance with examples disclosed herein.

[0012] Figures 4 to 6 An example of a layout that supports parallel access in a memory array is shown in accordance with examples disclosed herein.

[0013] Figure 7 A block diagram of a memory device that supports parallel access in a memory array is shown in accordance with examples disclosed herein.

[0014] Figure 8 A flow diagram showing one or more methods that support parallel access in a memory array is shown in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0015] In some memory architectures, memory cells can be accessed (e.g., written to, read from) based on current through the memory cells. For example, in some material memory architectures (e.g., memory architectures implementing one or more chalcogenide memory elements), a logic state can be written to a memory cell based on current (e.g., amount of current, direction of current) driven through the memory cell, and can be read from the memory cell based on current through the memory cell (e.g., presence of current, absence of current, amount of current) in accordance with or in response to a read bias on the memory cell. In some such architectures, memory cells can be accessed based on various decoding procedures or architectures, which can involve transistor or other switching components for accessing selected memory cells according to an addressing scheme. For example, to access a particular memory cell, a voltage can be applied to a gate of some transistors to couple some conductive structures (e.g., for coupling an access line across a channel of the transistors), and a voltage can not be applied to a gate of some other transistors to maintain isolation between other conductive structures.

[0016] For a given set of memory cells (e.g., a section of memory cells, a tile of memory cells), in accordance with an addressing scheme for the set of memory cells, drivers associated with driving access current through the memory cells can be associated with relatively higher current as compared to drivers associated with coupling conductive structures (e.g., drivers associated with biasing transistor gates, drivers associated with activating transistor channels). In some examples, drivers associated with relatively higher current can be associated with relatively larger footprint area of a memory die or relatively higher current density or relatively larger footprint area or both through interconnect structures such as socket regions, among other differences, as compared to drivers associated with relatively lower current. In some examples, differences between drivers associated with different current levels for the same set of memory cells can make implementation in a memory device challenging.

[0017] According to examples disclosed herein, drivers associated with different current levels of a set of memory cells can be configured to facilitate various aspects of the layout or operation of a memory device. For example, a set of memory cells of a memory device can be associated with an array of conductive structures, where such structures (e.g., along a direction of the array) can be coupled using a set of transistors or other switching components activated by a first driver (e.g., a select driver, a gate driver). The set of memory cells can be divided into two or more subsets of memory cells (e.g., where different subsets are arranged along a direction of the array), where each subset can be associated with a respective second driver (e.g., a read driver, a write driver, a memory cell current driver) for driving access current through the memory cells of the subset. In some examples, two or more of such second drivers can operate concurrently (e.g., to support aspects of parallel access of multiple subsets of memory cells), which can support distributing circuit structures or distributing current across different (e.g., larger) footprints of a memory device, different from other different implementations having a single such second driver. By configuring multiple sets of memory cells associated with multiple second drivers for each first driver according to examples disclosed herein, implementations of a memory device can have improved layout density, improved addressing flexibility, reduced or otherwise improved current magnitude or current density through conductive structures, reduced path length between memory cells and sensing circuitry, or reduced charge leakage or other power consumption, or any combination thereof, among other benefits.

[0018] Features of the disclosure are first described in the context of memory devices and arrays of reference Figure 1 , 2 , 3A, and 3B. Features of the disclosure are described in the context of example layouts of reference Figures 4-6 . These and other features of the disclosure are further illustrated by and described with reference to device diagrams and flowcharts relating to parallel access in a memory array described with reference to Figure 7 and 8 .

[0019] Figure 1 An example of a memory device 100 that supports parallel access in a memory array according to examples disclosed herein is shown. In some examples, the memory device 100 can be referred to or include a memory die, a memory chip, or an electronic memory device. The memory device 100 can be used to provide physical memory locations (e.g., addresses) that can be used or referenced by a system (e.g., a host device coupled with the memory device 100).

[0020] The memory device 100 can include one or more memory cells 105, each of which can be programmable to store different logic states (e.g., a programmed one of a set of two or more possible states). For example, a memory cell 105 can be used to store one bit of information (e.g., a logic 0 or a logic 1). In some examples, a memory cell 105 (e.g., a multi-level memory cell 105) can be used to store more than one bit of information (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, memory cells 105 can be arranged in an array.

[0021] The memory cells 105 can store logic states using a configurable material, which can be referred to as a memory element, a storage element, a memory storage element, a material element, a material storage element, a material portion, or a polarity- written material portion, among others. The configurable material of the memory cells 105 can refer to a chalcogenide-based storage component. For example, a chalcogenide storage element can be used for a phase change memory cell, a threshold memory cell, or a self-select memory cell, among other architectures.

[0022] In some examples, the material of the memory cells 105 can include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (IN), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some examples, a SAG alloy can also include silicon (Si), such a chalcogenide material can be referred to as a SiSAG alloy. In some examples, a SAG alloy can include silicon (Si) or indium (In) or a combination thereof, such a chalcogenide material can be referred to as a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some examples, a chalcogenide glass can include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (CI), or fluorine (F), each in atomic or molecular form.

[0023] In some examples, the memory cells 105 can be an example of a phase change memory cell. In such examples, the material used for the memory cells 105 can be based on an alloy (e.g., the alloys listed above) and can be operated so as to change to different physical states (e.g., undergo a phase change) during normal operation of the memory cells 105. For example, a phase change memory cell 105 can be associated with a relatively disordered configuration of atoms (e.g., a relatively amorphous state) and a relatively ordered configuration of atoms (e.g., a relatively crystalline state). The relatively disordered configuration of atoms can correspond to a first logic state (e.g., a RESET state, a logic 0), and the relatively ordered configuration of atoms can correspond to a second logic state (e.g., a logic state different from the first logic state, a SET state, a logic 1).

[0024] In some examples (e.g., for threshold memory cells 105 or self-select memory cells 105), some or all of the set of logical states supported by a memory cell 105 can be associated with a relatively disordered atomic configuration of a chalcogenide material (e.g., a material in an amorphous state can be used to store a different logical state). In some examples, a storage element of a memory cell 105 can be an example of a self-select storage element. In such examples, the material used for a memory cell 105 can be based on an alloy (e.g., an alloy listed above), and can be operated so as to change to different physical states during normal operation of the memory cell 105. For example, a self-select memory cell can have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state can correspond to a first logical state (e.g., a RESET state, a logical 0), and the low threshold voltage state can correspond to a second logical state (e.g., a logical state different from the first logical state, a SET state, a logical 1).

[0025] During a write operation (e.g., a program operation) of a self-select or threshold memory cell 105, a polarity used for the write operation can affect (e.g., determine, set, program) a performance or characteristic of the material of the memory cell 105, such as a threshold characteristic (e.g., a threshold voltage) of the material. A difference between threshold characteristics of the material of the memory cell 105 for different logical states stored by the material of the memory cell 105 (e.g., a difference between threshold voltages when the material stores a logical state ‘0’ versus a logical state ‘1’) can correspond to a read window of the memory cell 105.

[0026] The memory device 100 can include access lines (e.g., row lines 115 each extending along the illustrative x-direction, column lines 125 each extending along the illustrative y-direction) arranged in a pattern, such as a grid-like pattern. The access lines can be formed of one or more conductive materials. In some examples, a row line 115 or some portion thereof can be referred to as a word line. In some examples, a column line 125 or some portion thereof can be referred to as a digit line or a bit line. References to access lines or the like can be interchanged without loss of understanding. The memory cells 105 can be positioned at intersections of the access lines, such as intersections of the row lines 115 and the column lines 125. In some examples, the memory cells 105 can also be arranged (e.g., addressed) along the illustrative z-direction (e.g., in implementations in which multiple sets of memory cells 105 are located at different levels (e.g., tiers, decks, planes) along the illustrative z-direction). In some examples, a memory device 100 that includes memory cells 105 at different levels can be supported by different configurations of access lines, decoders, and other support circuitry.

[0027] Operations such as read operations and write operations can be performed on memory cells 105 by activating access lines, such as one or more of row lines 115 or column lines 125, and other access lines associated with alternative configurations. For example, by activating a row line 115 and a column line 125 (e.g., applying a voltage to a row line 115 or a column line 125), a memory cell 105 can be accessed at their intersection. The intersection between row lines 115 and column lines 125 and other access lines in various two-dimensional or three-dimensional configurations can be referred to as an address of a memory cell 105. In some examples, an access line can be an electrically conductive line coupled with a memory cell 105 and can be used to perform an access operation on a memory cell 105. In some examples, memory device 100 can perform operations in response to commands that can be issued by a host device coupled with memory device 100 or can be generated by memory device 100 (e.g., local memory controller 150).

[0028] Accessing memory cells 105 can be controlled by one or more decoders, such as row decoder 110 or column decoder 120, and other examples. For example, row decoder 110 can receive a row address from local memory controller 150 and activate a row line 115 based on the received row address. Column decoder 120 can receive a column address from local memory controller 150 and can activate a column line 125 based on the received column address.

[0029] Sensing component 130 can be used to detect a state of a memory cell 105 (e.g., material state, resistance state, threshold state) and determine a logic state of a memory cell 105 based on the detected state. Sensing component 130 can include one or more sense amplifiers to convert (e.g., amplify) a signal generated by accessing a memory cell 105 (e.g., a signal of a column line 125 or other access line). Sensing component 130 can compare a signal detected from a memory cell 105 to a reference 135 (e.g., a reference voltage, a reference charge, a reference current). The logic state of a detected memory cell 105 can be provided as an output of sensing component 130 (e.g., to input / output component 140) and can be indicated to another component of memory device 100 or a host device coupled with memory device 100.

[0030] The local memory controller 150 can control access to the memory cells 105 through various components, such as the row decoder 110, the column decoder 120, the sense component 130, and others. In some examples, one or more of the row decoder 110, the column decoder 120, and the sense component 130 can be co-located with the local memory controller 150. The local memory controller 150 can be used to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with the memory device 100), translate the information into signaling usable by the memory device 100, perform one or more operations on the memory cells 105, and transmit data from the memory device 100 to the host device based on performing the one or more operations. The local memory controller 150 can generate row address signals and column address signals to activate access lines, such as the target row line 115 and the target column line 125. The local memory controller 150 can also generate and control various signals (e.g., voltages, currents) used during operation of the memory device 100. In general, the amplitude, shape, or duration of the signals applied as discussed herein can vary and can differ for the various operations discussed in operating the memory device 100.

[0031] The local memory controller 150 can be used to perform one or more access operations on one or more memory cells 105 of the memory device 100. Examples of access operations can include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, access operations can be performed or otherwise coordinated by the local memory controller 150 in response to an access command (e.g., from a host device). The local memory controller 150 can be used to perform other access operations not listed here or other operations related to operations of the memory device 100 that are not directly related to accessing the memory cells 105.

[0032] In some examples of the memory device 100, memory cells 105 can be accessed (e.g., written to, read from) based on current through the memory cells 105. For example, a logic state can be written to a memory cell 105 based on current (e.g., amount of current, direction of current) driven through the memory cell 105, and a logic state can be read from a memory cell 105 based on current (e.g., presence of current, absence of current, amount of current) through the memory cell 105 in response to a read bias on the memory cell 105. In some examples, memory cells 105 can be accessed based on various decoding architectures, which can implement transistors or other switching components (e.g., of row decoders 110, of column decoders 120) for accessing selected memory cells 105 according to an addressing scheme. For example, to access a particular memory cell 105, a voltage can be applied to the gates of some transistors to couple some conductive structures (e.g., for coupling access lines across transistor channels), and a voltage can not be applied to the gates of other transistors to maintain isolation between other conductive structures.

[0033] For a given set of memory cells 105 (e.g., a section of memory cells, a tile of memory cells), according to an addressing scheme for the set of memory cells 105, drivers associated with driving access current through memory cells 105 can be associated with relatively higher current, as compared to drivers associated with coupling conductive structures (e.g., drivers associated with biasing transistor gates, drivers associated with activating transistor channels, drivers associated with row decoders, drivers associated with column decoders). In some examples, drivers associated with relatively higher current can be associated with relatively larger footprint of a memory die or relatively higher current density through interconnect structures such as socket regions, as compared to drivers associated with relatively lower current, among other differences. In some examples, differences between drivers associated with different current levels of the same set of memory cells 105 can make implementation in the memory device 100 challenging.

[0034] According to examples disclosed herein, drivers associated with different current levels of a set of memory cells 105 can be configured to facilitate various aspects of the layout or operation of the memory device 100. For example, a set of memory cells 105 of the memory device 100 can be associated with an array of conductive structures, where such structures (e.g., along a direction of the array) can be coupled using a set of transistors or other switching components activated by a first driver (e.g., a selection driver, a gate driver, a driver associated with the row decoder 110, a driver associated with the column decoder 120). The set of memory cells 105 can be divided into two or more subsets of memory cells 105 (e.g., where different subsets are arranged along a direction of the array), where each subset can be associated with a respective second driver (e.g., a read driver, a write driver, a memory cell current driver) for driving access current through the memory cells 105 of the subset. In some examples, two or more of such second drivers can operate simultaneously, which can support distributing circuit structures or distributing current across different footprints of the memory device 100 (e.g., a larger footprint of a memory die, a larger footprint of a substrate) than other different implementations having a single such second driver. By configuring multiple sets of memory cells 105 associated with multiple second drivers for each first driver according to examples disclosed herein, implementations of the memory device 100 can have improved layout density, improved addressing flexibility, reduced or otherwise improved current magnitude or current density through conductive structures, reduced path lengths between memory cells and sensing circuitry, or reduced charge leakage or other power consumption, among other benefits.

[0035] The memory device 100 can include any number of non-transitory computer- readable media that support parallel access in a memory array. For example, the local memory controller 150, the row decoder 110, the column decoder 120, the sense component 130, or the input / output component 140, or any combination thereof, can include or have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing functions attributed herein to the memory device 100. For example, such instructions, when executed by the memory device 100, can cause the memory device 100 to perform one or more of the associated functions described herein.

[0036] Figure 2 、 3A FIGS. 3A and 3B show top views of examples of a memory array 200 that supports parallel access in a memory array, according to examples disclosed herein. The memory array 200 can be included in the memory device 100 and shows an example of a three-dimensional arrangement of memory cells 105 that can be accessed by various conductive structures (e.g., access lines). Figure 2 FIGS. 3A and 3B show top views of examples of a memory array 200 that supports parallel access in a memory array, according to examples disclosed herein. The memory array 200 can be included in the memory device 100 and shows an example of a three-dimensional arrangement of memory cells 105 that can be accessed by various conductive structures (e.g., access lines).Figure 3A and 3B a top cross-sectional view (e.g., cross-section A-A) of the cut plane A-A as shown. Figure 3A illustrating the memory array 200 relative to Figure 2 a side cross-sectional view (e.g., cross-section B-B) of the cut plane B-B as shown. Figure 3B illustrating the memory array 200 relative to Figure 2 a side cross-sectional view (e.g., cross-section C-C) of the cut plane C-C as shown. The cross-sectional view can be an example of a cross-sectional view of the memory array 200 with some aspects (e.g., dielectric structures) removed for clarity. Elements of the memory array 200 can be described relative to the x-direction, the y-direction, and the z-direction, as illustrated in each of Figure 2 , 3A and 3B. Although Figure 2 , 3A and 3B contain some elements labeled with a numerical designator, other corresponding elements are not labeled, but they are the same or should be understood to be similar in an effort to increase visibility and clarity of the features depicted. Further, although some number of repeating elements are illustrated in the illustrative example of the memory array 200, the techniques in accordance with the examples described herein can be applied to any number of such elements, or a ratio of numbers between one repeating element and another.

[0037] In the example of the memory array 200, the memory cells 105 and the word lines 205 can be distributed along the z-direction according to tiers 230 (e.g., decks, layers, planes, as illustrated in Figure 3A and 3B ). In some examples, the z-direction can be orthogonal to a substrate (not shown) of the memory array 200, which can be below the illustrated structures along the z-direction. Although the illustrative example of the memory array 200 includes four tiers 230, a memory array 200 in accordance with the examples disclosed herein can include any number of one or more tiers 230 along the z-direction (e.g., 64 tiers, 128 tiers).

[0038] Each word line 205 can be an example of a portion of an access line formed of one or more electrically conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown, a word line 205 can be formed as a comb structure including portions (e.g., protrusions, tines) extending along a y-direction through gaps (e.g., alternating gaps) between pillars 220. For example, as shown, a memory array 200 can include two word lines 205 per level 230 (e.g., odd word lines 205-a-nl and even word lines 205-a-n2 for a given level n), where such word lines 205 of a same level 230 can be described as interleaved (e.g., with portions of odd word lines 205-a-nl protruding along a y-direction between portions of even word lines 205-a-n2, and vice versa). In some examples, an odd word line 205 (e.g., of a level 230) can be associated with a first memory cell 105 on a first side (e.g., along an x-direction) of a given pillar 220, and an even word line (e.g., of a same level 230) can be associated with a second memory cell 105 on a second side (e.g., along an x-direction, opposite the first memory cell 105) of the given pillar 220. Thus, in some examples, a memory cell 105 of a given level 230 can be addressed (e.g., selected, activated) according to an even word line 205 or an odd word line 205.

[0039] Each pillar 220 can be an example of a portion of an access line formed of one or more electrically conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown, pillars 220 can be arranged in a two-dimensional array (e.g., in an xy-plane) having a first number of pillars 220 along a first direction (e.g., eight pillars along an x-direction, eight rows of pillars) and having a second number of pillars 220 along a second direction (e.g., five pillars along a y-direction, five columns of pillars). Although the illustrative example of a memory array 200 includes a two-dimensional arrangement of eight pillars 220 along an x-direction and five pillars 220 along a y-direction, a memory array 200 according to examples disclosed herein can include any number of pillars 220 along an x-direction and any number of pillars 220 along a y-direction. Further, as shown, each pillar 220 can be coupled with a respective set of memory cells 105 (e.g., one or more memory cells 105 per level 230 along a z-direction). A pillar 220 can have a cross-sectional area in an xy-plane extending along a z-direction. Although shown with a circular cross-sectional area in an xy-plane, a pillar 220 can be formed with different shapes, such as an elliptical, square, rectangular, polygonal, or other cross-sectional area in an xy-plane.

[0040] The memory cells 105 can each include a chalcogenide material. In some examples, the memory cells 105 can be examples of threshold memory cells. Each memory cell 105 can be accessed (e.g., addressed, selected) according to an intersection between a word line 205 (e.g., a tier selection, which can include an even or odd selection within the tier 230) and a pillar 220. For example, as shown, a selected memory cell 105-a of the tier 230-a-3 can be accessed according to an intersection between the pillar 220-a-43 and the word line 205-a-32.

[0041] The memory cells 105 can be accessed (e.g., written, read) by applying an access bias (e.g., an access voltage V access , which can be a positive voltage or a negative voltage) on the memory cells 105. In some examples, the access bias can be applied by biasing a selected word line 205 with a first voltage (e.g., V access / 2) and by biasing a selected pillar 220 with a second voltage (e.g., -V access / 2), which can have an opposite sign from the first voltage. With respect to the selected memory cell 105-a, a corresponding access bias (e.g., the first voltage) can be applied to the word line 205-a-32, while other unselected word lines 205 can be grounded (e.g., biased to 0 V). In some examples, the word line bias can be provided by a word line driver (not shown) coupled with one or more of the word lines 205.

[0042] To apply a corresponding access bias (e.g., the second voltage) to the pillar 220, the pillar 220 can be configured to selectively couple with a sense line 215 (e.g., a digit line, a column line, an access line extending along the y direction) via a respective transistor 225. In some examples, the transistor 225 can be a vertical transistor (e.g., a transistor having a channel along the z direction, a transistor having a semiconductor junction along the z direction), which can be formed above a substrate of the memory array 200 using various techniques (e.g., thin-film techniques). In some examples, a selected pillar 220, a selected sense line 215, or a combination thereof can be an example of a selected column line 125 (e.g., a bit line) described. Figure 1

[0043] ​Transistor 225 may be activated by gate lines 210 (e.g., activation lines, select lines, row lines, access lines extending along the x-direction) coupled to the respective gates of a group of transistors 225 (e.g., a group along the x-direction). In other words, each of the posts 220 may have a first end (e.g., a bottom end facing the negative z-direction) configured to be coupled to an access line (e.g., a sense line 215). In some instances, gate lines 210, transistors 225, or both may be considered components of row decoder 110 (e.g., as post decoder components). In some instances, the selection (e.g., bias) of post 220 or sense line 215, or various combinations thereof, may be supported by column decoder 120 or sense component 130, or both.

[0044] To adjust the corresponding access bias (e.g., -V) access / 2) An access bias is applied to post 220-a-43, and sensing line 215-a-4 can be biased using an access bias. Gate line 210-a-3 can be grounded (e.g., biased to 0V) or otherwise biased with an activation voltage. In an example where transistor 225 is an n-type transistor, gate line 210-a-3 biased with a voltage relatively higher than sensing line 215-a-4 can activate transistor 225-a (e.g., operate transistor 225-a in the on state), thereby coupling post 220-a-43 to sensing line 215-a-4 and biasing post 220-a-43 with an associated access bias. However, transistor 225 may contain different channel types or may operate according to different bias schemes to support various access operations.

[0045] In some instances, unselected posts 220 of the memory array 200 may be electrically floating when transistor 225-a is activated, or may be coupled to another voltage source (e.g., ground, via a high-resistance path, via a leakage path, along the end of post 220 opposite to transistor 225) to prevent voltage drift of post 220. For example, applying a ground voltage to gate line 210-a-3 may not activate other transistors coupled to gate line 210-a-3 because the ground voltage of gate line 210-a-3 may not be greater than the voltage of other sensing lines 215 (e.g., which may be biased with a ground voltage or may be floating). Furthermore, including... Figure 3A Other unselected gate lines 210 of the gate line 210-a-5 shown can be used with a voltage equal to or similar to the access bias (e.g., -V). read / 2, or some other negative bias or bias relatively close to the access bias voltage) such that none of the transistors 225 along the unselected gate line 210 are activated. Thus, the transistor 225-b coupled with the gate line 210-a-5 can be deactivated (e.g., operate in a non-conducting state), thereby isolating the voltage of the sense line 215-a-4 from the pillar 220-a-45 and other pillars 220.

[0046] In a write operation, the memory cell 105 can be written to by applying a write bias (e.g., where V access = V write , which can be a positive voltage or a negative voltage) on the memory cell 105. In some examples, the polarity of the write bias can affect (e.g., determine, set, program) the performance or characteristics of the material of the memory cell 105, such as the threshold voltage of the material. For example, applying a write bias having a first polarity can set the material of the memory cell 105 at a first threshold voltage, which can be associated with storing a logic 0. Further, applying a write bias having a second polarity (e.g., opposite the first polarity) can set the material of the memory cell at a second threshold voltage, which can be associated with storing a logic 1. The difference between the threshold voltage of the material of the memory cell 105 for different logic states stored by the material of the memory cell 105 (e.g., the difference between the threshold voltage when the material stores a logic state ‘0’ relative to when it stores a logic state ‘1’) can correspond to a read window of the memory cell 105.

[0047] In a read operation, the memory cell 105 can be read by applying a read bias (e.g., where V access = V read , which can be a positive voltage or a negative voltage) on the memory cell 105. In some examples, the logic state of the memory cell 105 can be evaluated based on whether the memory cell 105 is thresholded in the presence of the applied read bias. For example, such a read bias can cause a memory cell 105 storing a first logic state (e.g., logic 0) to be thresholded (e.g., allow current to flow, allow current above a threshold current), and can not cause a memory cell 105 storing a second logic state (e.g., logic 1) to be thresholded (e.g., can not allow current to flow, can allow current below a threshold current).

[0048] For a given set of memory cells 105 associated with the memory array 200 (e.g., a section of memory cells, a tile of memory cells), in accordance with the addressing scheme of the memory array 200, drivers associated with driving access current through the memory cells 105 (e.g., drivers coupled with the word lines 205, word line drivers, drivers coupled with the sense lines 215) can be associated with relatively higher current as compared to drivers associated with the coupled conductive structures (e.g., drivers associated with the activation transistors 225, gate line drivers). In some examples, drivers associated with relatively higher current can be associated with a relatively larger footprint of the memory array 200 (e.g., along the x-direction, along the y-direction) or a relatively higher current density through interconnect structures such as a socket region, among other differences, as compared to drivers associated with relatively lower current. In some examples, differences between drivers associated with different current levels of the memory array 200 can make implementation of the memory array 200 challenging.

[0049] In accordance with examples disclosed herein, drivers associated with different current levels of the memory array 200 can be configured to facilitate various aspects of layout or operation. For example, the memory array 200 can be associated with an array of conductive structures (e.g., the pillars 220, the sense lines 215, the word lines 205), where such structures can be coupled (e.g., along the y-direction) using transistors 225 activated by first drivers (e.g., selection drivers, gate drivers). The memory cells 105 can be divided into two or more subsets (e.g., different subsets arranged or divided along the y-direction), where each subset can be associated with a respective second driver (e.g., a read driver, a write driver, a memory cell current driver, a word line driver) for driving access current through the memory cells 105 of the subset. In some examples, two or more of such second drivers can operate concurrently (e.g., to support aspects of parallel word line access), which can support distributing circuit structures or distributing current over different (e.g., larger) footprints of the memory array 200 as compared to implementations having a single such second driver. By configuring the memory array 200 to operate with multiple second drivers for each first driver in accordance with examples disclosed herein, implementations of the memory device 100 including the memory array 200 can have improved layout density, improved addressing flexibility, reduced or otherwise improved current magnitudes or current densities through conductive structures, reduced path lengths between memory cells and sense circuitry, or reduced charge leakage or other power consumption, or any combination thereof, among other benefits.

[0050] Figure 4An example of a layout 400 (e.g., a first dual comb layout) that supports parallel access according to examples disclosed herein is shown. The layout 400 can be an example of aspects of the memory array 200 described with reference to Figure 2 , 3A and 3B. For example, the layout 400 can include an arrangement of word lines 205-b, gate lines 210-b, and sense lines 215-b, which can be examples of the respective components described with reference to Figure 2 , 3A and 3B. The layout 400 can also include various arrangements of pillars 220 (e.g., a two-dimensional array of pillars 220), memory cells 105 (e.g., a three-dimensional array of memory cells 105), and transistors 225 (e.g., a two-dimensional array of transistors 225), which can likewise be examples of the respective components described with reference to Figure 2 , 3A and 3B, although such components are omitted from Figure 4 for clarity of illustration. Aspects of the layout 400 can be described with reference to an x-direction (e.g., a row direction), a y-direction (e.g., a column direction), and a z-direction (e.g., a tier direction).

[0051] Layout 400 can include a section 405-a (e.g., an array, a tile, a section of memory cells 105, a section of a memory die) that can include a plurality of sub-sections 410-a (e.g., sub-sections 410-a-l and 410-a-2). In various examples, a memory device 100 (e.g., a memory die) can include any number of one or more sections 405 according to layout 400, each section 405 can include any number of two or more sub-sections 410. Sub-sections 410 can each include a respective subset of components of a section 405, such as a respective subset of word lines 205, a respective subset of sense lines 215, a respective subset of pillars 220 (not shown), a respective subset of transistors 225 (not shown), or a respective subset of memory cells 105 (not shown), among other subsets of components of a section 405. For example, a section 405 can include a two-dimensional array of pillars 220, including a first number of pillars 220 along the y-direction (e.g., j pillars) and a second number of pillars 220 along the x-direction (e.g., i pillars). Each sub-section 410 can include a respective subset of pillars 220, such as a two-dimensional array of a first number of pillars 220 along the y-direction (e.g., j pillars) and a respective subset of a second number of pillars along the x-direction (e.g., i / 2 pillars for embodiments having two sub-sections 410 of a section 405). Sub-sections 410-a can illustrate an example of sectioning section 405-a into sub-sections along the x-direction. In various examples, the relative positioning of constituent features of one or more sub-sections 410 of a section 405 can be reversed (e.g., along the y-direction), among other differences in configuring a section 405 according to examples disclosed herein.

[0052] Layout 400 can include a set of i sense lines 215-b (e.g., sense lines 215-b-1 through 215-b-i) along the x direction (e.g., addressed along the x direction, arranged along the x direction), and each sense line 215-b can extend along the y direction (e.g., across a section 405-a, along a column of pillars 220). The sense lines 215-b can be divided among sub-sections 410-a, and the sense lines 215-b of a sub-section 410-a can be coupled with a respective sense amplifier array 420-a of the sub-section 410-a. A sense amplifier array 420 can refer to a sense amplifier of a sense component 130. In some examples, a sense amplifier array 420 can include a respective sense amplifier for each sense line 215 of a sub-section 410. In some other examples, a sense amplifier array 420 can include fewer sense amplifiers than sense lines 215 of a sub-section 410 (e.g., fewer than i / 2 sense amplifiers in the example of layout 400), and a sub-section 410 can include respective multiplexers 415 that can be used to couple selected ones of the sense lines 215 with the sense amplifiers of the sense amplifier array 420. In an illustrative example, each of sub-sections 410-a can include 64 sense lines 215-b, and each of sense amplifier arrays 420-a can include 16 sense amplifiers, such that each multiplexer 415-a can support 4: 1 multiplexing. Additionally or alternatively, one or more sense amplifier arrays 420 can be shared among sub-sections 410. For example, sub-sections 410-a-1 and 410-a-2 can share a single sense amplifier array 420, which can be included in a single sub-section 410-a (e.g., as shown), or which can span multiple sub-sections 410-a.

[0053] Layout 400 can also include a set of j gate lines 210-b (e.g., gate lines 210-b-1 through 210-b-j) along the y direction (e.g., addressed along the y direction, arranged along the y direction), and each gate line 210-b can extend along the x direction (e.g., across a section 405-a, along a row of pillars 220). Each gate line 210-b can be coupled with the gates of a set of transistors 225 (e.g., i transistors 225 along the x direction, which can correspond to i pillars 220 and i sense lines 215 along the x direction), which can each be used to couple a respective pillar 220 with one of the sense lines 215-b. As shown, each gate line 210 can extend across each sub-section 410 of a section 405, and can accordingly activate the transistors 225 in each sub-section 410.

[0054] Layout 400 can also include, for each sub-section 410-a, a respective plurality of k word lines 205-b along the z-direction (e.g., addressed along the z-direction, arranged along the z-direction), and each word line 205-b can include a portion extending along the y-direction between the pillars 220 of the respective sub-section 410-a. For example, sub-section 410-a-l can include a set of word lines 205-b-l l to 205-b-k l, and sub-section 410-a-2 can include a set of word lines 205-b-12 to 205-b-k2, where illustrated word lines 205-b-l l and 205-b-12 can be associated with a same level 230 (e.g., a first level). In some examples, illustrated word lines 205-b-l l and 205-b-12 of layout 400 can be portions of a plurality of sets of word lines 205 referred to as “odd” word lines, where the portions extend along a positive y-direction, and such word lines 205-b can be interleaved with a corresponding plurality of sets of “even” word lines 205 (not shown), where the portions extend along a negative y-direction (e.g., according to alternating gaps between the pillars 220).

[0055] According to examples disclosed herein, drivers associated with different current levels of layout 400 can be configured to facilitate various aspects of the layout or operation of a memory device 100 including layout 400 (e.g., one or more sections 405-a). For example, a section 405-a can be associated with an array of conductive structures (e.g., word lines 205-b, sense lines 215-b, pillars 220), where such structures can be coupled using gate lines 210 activated by gate line drivers 430-a (e.g., along the x-direction). Section 405-a can be divided into a plurality of sub-sections 410-a (e.g., two sub-sections 410-a) along the x-direction, where each sub-section 410-a can be associated with a respective driver (e.g., a respective word line driver 425-a) for driving access current through memory cells 105 of the sub-section 410-a.

[0056] The gate line driver 430 can be coupled with each of the gate lines 210 in the section 405 and can bias one or more of the coupled gate lines 210 (e.g., with an activation bias, with a deactivation bias). Although the gate line driver 430-a is shown alongside (e.g., along the x-direction, which can be on the same level as the gate lines 210-b) the gate lines 210-b, the gate line driver 430 can be positioned above or below (e.g., along the z-direction) the gate lines 210, the word lines 205, or the sense lines 215, or any combination thereof (e.g., including thin film transistors formed between access lines and a substrate of the section 405, including transistors formed at least partially through a doped portion of a semiconductor substrate, such as doped crystalline silicon). As shown, the gate line driver 430-a can bias each of the gate lines 210-b via the same end (e.g., one end of the gate lines 210-b in a relatively negative position along the x-direction). In some cases, the gate line driver 430 can be coupled with the gate lines 210 along the z-direction via one or more conductors (e.g., a via, a plug connection).

[0057] The gate line driver 430 can be configured to bias one or more gate lines 210 with an activation voltage. For example, the activation voltage driven by the gate line driver 430-a can be associated with activating a subset of the transistors 225 (e.g., a subset of the pillars 220) associated with the sub-section 410-a-l and a subset of the transistors 225 (e.g., a subset of the pillars 220) associated with the sub-section 410-a-2, such as a row of transistors 225 along the x-direction across the section 405-a. The activation voltage of the gate lines 210 can involve relatively low current (e.g., associated with intrinsic capacitance of the activated gate lines 210-b, associated with leakage of the activated gate lines 210-b into surrounding dielectric, associated with gate-to-channel current through one or more transistors 225), which can be referred to as gate line consumption. In some examples, such activation can be associated with simultaneously activating transistors 225 or pillars 220 associated with multiple word lines 205-b, which can support simultaneously accessing memory cells 105 of different sub-sections 410 (e.g., via multiple activated word lines 205-b).

[0058] Each word line driver 425 can be coupled with a subset of word lines 205, which can form a stack of word lines 205 along the z-direction of a section 405, and the word line driver 425 can bias (e.g., individually, independently) one or more coupled word lines 205 of the stack (e.g., with an activation bias, with a deactivation bias, with an access bias). For example, a word line driver 425 can bias a set of one or more coupled word lines 205 with a first voltage (e.g., an activation bias, to drive a current through the set of memory cells 105 coupled with the one or more word lines). While (e.g., in parallel with) being biased with the first voltage, the word line driver 425 can bias another set of one or more other coupled word lines 205 with a second bias (e.g., a deactivation bias), or isolate another set of one or more other word lines 205 from a voltage source (e.g., set the one or more other word lines 205 in a floating condition), or both, among other bias conditions. In some examples, such independent biasing can support driving an access current through memory cells 105 coupled with word lines 205 biased with the first voltage, and not driving an access current through memory cells 105 coupled with word lines 205 biased with the second voltage or set in a floating condition. Thus, under such conditions, the pillars 220 and sense lines 215 can each carry current for those memory cells 105 coupled with activated word lines (e.g., a single memory cell 105 being accessed), and not carry current for those memory cells coupled with deactivated or floating word lines 205 (e.g., those memory cells 105 not being accessed).

[0059] While the word line drivers 425-a-1 and 425-a-2 are shown as being alongside (e.g., along the y-direction, which can be on the same level as the one or more word lines 205-b) the word lines 205-b, the word line drivers 425 can be positioned above or below (e.g., along the z-direction) the gate lines 210, the word lines 205, or the sense lines 215, or any combination thereof (e.g., including thin film transistors formed between access lines and a substrate of a section 405, including transistors formed at least partially through a doped portion of a semiconductor substrate, such as doped crystalline silicon). As shown, the word line drivers 425-a can bias each of the word lines 205-b via the same end (e.g., one end of the word lines 205-b in a relatively negative position along the y-direction). In some cases, the word line drivers 425 can be coupled with the word lines 205 along the z-direction via one or more conductors (e.g., vias, plug connections).

[0060] The word line drivers 425 can be configured to bias the word lines 205 with an access voltage (e.g., V accessone or more memory cells 105 coupled with the one or more word lines 205 can involve relatively higher current than activating a gate line 210 (e.g., associated with writing a state to one or more memory cells 105, associated with reading a state from one or more memory cells 105). In some examples, one or more word lines 205 of a sub-section 410 can be biased by a word line driver 425 of a section 405. For example, a word line driver 425-a-1 of a section 405-a can be configured to bias one or more word lines 205 (e.g., word line 205-b-11) of a sub-section 410-a-1, and a word line driver 425-a-2 of the section 405-a can be configured to bias one or more word lines 205 (e.g., word line 205-b-12) of a sub-section 410-a-2. In some examples, a word line driver 425 of a section 405 can be configured to bias one or more word lines 205 of a sub-section 410 based on a bias voltage (e.g., a voltage bias, a current bias, a voltage and current bias, a voltage bias and a current bias, a voltage bias of at least a portion of a voltage bias, a current bias of at least a portion of a current bias, a voltage bias of at least a portion of a voltage bias and a current bias of at least a portion of a current bias, as described herein) of one or more memory cells 105 coupled with the one or more word lines 205. For example, a word line driver 425 can bias a word line 205 with such an access voltage bias can drive current through a memory cell 105 coupled with one or more pillars 220 activated by a gate line driver 430 (e.g., through an activated channel of one or more transistors 225). In some examples, accessing a coupled memory cell 105 can involve relatively higher current than activating a gate line 210 (e.g., associated with writing a state to one or more memory cells 105, associated with reading a state from one or more memory cells 105).

[0061] In various examples, word line drivers 425 of a section 405 can be operated simultaneously. For example, a word line driver 425-a-1 can be used to bias one or more word lines 205 (e.g., word line 205-b-11) of a sub-section 410-a-1, at the same time as a word line driver 425-a-2 biases one or more word lines 205 (e.g., word line 205-b-12) of a sub-section 410-a-2. In some examples, two or more word line drivers 425 of a section 405 can be configured to bias word lines 205 of a same level 230 (e.g., simultaneously, according to a same address along the z-direction). For example, operation of a section 405-a can be configured for a word line driver 425-a-1 to bias a word line 205-b-m1, at the same time as a word line driver 425-a-2 biases a word line 205-b-m2, where values of m can correspond to levels 230 of the section 405-a selected by a level decoder or word line decoder associated with the section 405-a. In some examples, biasing word lines 205 of a same level 230 can support improved uniformity (e.g., voltage uniformity, current uniformity) for read or write operations, or relatively simpler decoding logic or circuitry (e.g., operating multiple sub-sections 410 with a common decoder or decoder output), among other advantages. Additionally or alternatively, two or more word line drivers 425 of a section 405 can be configured to bias word lines 205 of different levels 230 (e.g., simultaneously, according to different addresses along the z-direction). For example, operation of a section 405-a can be for a word line driver 425-a-1 to bias a word line 205-b-m1, at the same time as a word line driver 425-a-2 biases a word line 205-b-n2, where values of m and n can correspond to levels 230 of the section 405-a selected by one or more level decoders or word line decoders associated with the section 405-a (e.g., where m and n can be different, or can be the same, depending on a given access scenario). In some examples, supporting biasing of word lines 205 of different levels 230 can support improved addressing or access flexibility.

[0062] According to examples disclosed herein, word line drivers 425 can be implemented to support various groupings of odd and even word lines 205. In some examples, a common word line driver 425 can be implemented for biasing interleaved word lines 205 of a given sub-section 410 (e.g., a group including both odd and even word lines 205). For example, section 405-a (e.g., sub-section 410-a-l) can be configured such that word line driver 425-a-l can be used to bias word lines 205-b-l l through 205-b-k l (e.g., a group of odd word lines) and bias another group of word lines 205-b (e.g., a group of even word lines, not shown) of sub-section 410-a-l interleaved with word lines 205-b-l l through 205-b-k l. In some other examples, a first word line driver 425 of a sub-section 410 can be implemented for biasing odd word lines 205 of the sub-section 410, and a second word line driver 425 of the sub-section 410 can be implemented for biasing even word lines 205 of the sub-section 410. For example, section 405-a (e.g., sub-section 410-a-l) can be configured such that word line driver 425-a-l can be used to bias word lines 205-b-l l through 205-b-k l (e.g., a group of odd word lines), and another word line driver 425-a (not shown) can be used to bias another group of word lines 205-b (e.g., a group of even word lines, not shown) of sub-section 410-a-l interleaved with word lines 205-b-l l through 205-b-k l. In some examples, such other word line drivers 425-a can be located at positions of sub-section 410-a-l opposite word line driver 425-a-l along the y-direction, which can include positions alongside (e.g., at opposite positive positions along the y-direction) sense amplifier array 420-a-l. In some examples, simultaneous (e.g., parallel) biasing of various combinations of word lines 205-b by one or more word line drivers 425-a can be configured to avoid activation of multiple memory cells 105 associated with the same string 220 or sense line 215-b (e.g., avoid driving access current through multiple memory cells 105 along the same string 220 or sense line 215-b).

[0063] By configuring section 405 with one gate line driver 430 and multiple word line drivers 425, layout 400 illustrates examples for implementing aspects of a memory array according to techniques disclosed herein with improved layout density (e.g., along the x-direction, the y-direction, or both), improved addressing flexibility, reduced or otherwise improved current magnitude or current density through conductive structures, reduced path length between memory cells and sense circuitry or reduced charge leakage or other power consumption, among other benefits.

[0064] For example, to maintain a controlled access voltage in the presence of relatively high current, word line drivers 425 can individually or collectively involve a relatively larger footprint (e.g., along the x-direction, along the y-direction) than gate line drivers 430. The subdividing functionality for driving memory cell access current among multiple word line drivers 425 for each gate line driver 430 can improve layout flexibility for section 405. Moreover, by supporting simultaneous operation of multiple word line drivers 425, current for accessing multiple memory cells 105 of section 405 can be distributed among conductive structures of greater quantity or cross-sectional area, such as vias or sockets along the z-direction, or other portions of word lines 205 that can otherwise be subject to relatively high current density (e.g., as compared to current density of word lines 205 associated with all pillars 220 or memory cells 105 along the x-direction). In some examples, such reduction in current density can support a reduction in thermal concentration (e.g., hot spots) in section 405, which can improve reliability or efficiency of operating section 405. In some examples, such techniques can support more columns (e.g., more sense lines 215) of section 405 for a given activated row (e.g., for a given activated gate line 210), which can support improved access performance for a given amount of gate lines. In some examples, such distribution can support target parallelism using fewer sections 405.

[0065] In some examples, subdividing section 405 into multiple subsections 410 can improve aspects of sensing states of memory cells 105, such as reducing a relative distance between memory cells 105 and sense amplifiers of sense amplifier array 420. For example, section 405 can be configured with access lines (e.g., collector lines) between memory cells 105 and sense amplifiers oriented at least partially along the x-direction. In some examples, such access lines can be associated with multiplexing functionality between sense lines 215 and such sense amplifiers (e.g., as part of multiplexer 415). By subdividing section 405 into multiple subsections 410 along the x-direction, such access lines can be relatively shorter (e.g., reduced along the x-direction by an amount proportional to the number of subsections 410), which can support lower leakage, lower intrinsic capacitance, or reduced sensing latency, among other benefits.

[0066] Figure 5 An example of a layout 500 (e.g., a second dual- comb layout) that supports parallel access is shown in accordance with examples disclosed herein. Layout 500 can be an example of aspects of memory array 200 described with reference to Figure 2 、 3A and 3B. For example, layout 500 can include an arrangement of word lines 205-c, gate lines 210-c, and sense lines 215-c, which can be examples of aspects of word lines 205, gate lines 210, and sense lines 215 described with reference to Figure 2, 3A Layout 500 can also include various arrangements of pillars 220, memory cells 105, and transistors 225, which can likewise be instances of the respective components described with reference to Figure 2 , 3A and 3B, but for clarity of illustration, such components are omitted from FIG. 5B. Aspects of layout 500 can be described with reference to x-direction, y-direction, and z-direction. Figure 5

[0067] Layout 500 can include sections 405-b, each of which can include a plurality of subsections 410-b. Each of sections 405-b and subsections 410-b, and constituent components, can be instances of aspects of the respective features described with reference to layout 400. For example, section 405-b-2 can include a set of i sense lines 215-c along the x-direction, which can be divided between subsections 410-b-3 and 410-b-4. In various examples, the sense lines 215-c of a subsection 410-b can or can not be coupled with a respective sense amplifier array 420-b of the subsection 410-b with a respective multiplexer 415-b. Section 405-b-2 can also include a set of j gate lines 210-c along the y-direction, each of which can extend along the x-direction. Each gate line 210-c can be coupled with the gates of a row of transistors 225 (e.g., i transistors 225 along the x-direction, which can correspond to i pillars 220 and i sense lines 215 along the x-direction), each of which can be used to couple a respective pillar 220 with one of the sense lines 215-c. As shown, each gate line 210-c can extend across each subsection 410-b of section 405-b-2, and can accordingly activate the transistors 225 in each subsection 410-b.

[0068] ​In the example of the layout 500, the section 405-b can be associated with (e.g., include a portion of) a respective plurality of sets of k word lines 205-c along the z-direction, each word line 205-c can include a portion that extends along the y-direction between the pillars 220 of a respective subsection 410-b of the adjacent section 405. For example, the sections 405-b-l and 405-b-2 can be associated with a set of word lines 205-c-l l to 205-c-k l, each of which can include a portion that extends along the y-direction into the subsection 410-b-l of the section 405-b-l and the subsection 410-b-3 of the section 405-b-2. Each of the word lines 205-c-l l to 205-c-k l can be an example of a word line 205 that is coupled with respective memory cells 105 of each pillar 220 of the subsection 410-b-l and coupled with respective memory cells 105 of each pillar 220 of the subsection 410-b-3. Further, the sections 405-b-2 and 405-b-3 can be associated with a set of word lines 205-c-l 2 to 205-c-k2, each of which can include a portion that extends along the y-direction into the subsection 410-b-4 of the section 405-b-2 and the subsection 410-b-6 of the section 405-b-3. Each of the word lines 205-c-l 2 to 205-c-k2 can be an example of a word line 205 that can be coupled with respective memory cells 105 of each pillar 220 of the subsection 410-b-4 and coupled with respective memory cells 105 of each pillar 220 of the subsection 410-b-6.

[0069] In some examples, the illustrated word lines 205-c-l l and 205-c-l 2 can be associated with the same tier 230 (e.g., the first tier) along the z-direction. In some examples, the illustrated word lines 205-c of the layout 500 can be portions of a plurality of sets of word lines 205 referred to as “odd” word lines, such word lines 205-c can be interleaved with a corresponding plurality of sets of “even” word lines 205 (e.g., according to alternating gaps between the pillars 220). However, these sets of word lines 205 can be arranged or operated according to different configurations.

[0070] According to examples disclosed herein, drivers associated with different current levels of the layout 500 can be configured to facilitate various aspects of the layout or operation of a memory device 100 including the layout 500 (e.g., one or more sections 405-b). For example, the sections 405-b can each be associated with a respective array of conductive structures (e.g., word lines 205-b, sense lines 215-b, pillars 220), where such structures can be coupled using gate lines 210 activated by gate line drivers 430 (e.g., gate line drivers 430-b associated with the section 405-b-2). Each section 405-b can be divided into a plurality of subsections 410-b, where each subsection 410-b can be associated with a respective driver (e.g., a respective word line driver 425-b) for driving access current through memory cells 105 of the subsection 410-b.

[0071] In examples of the layout 500, the gate line drivers 430-b of the sections 405-b can be coupled with each gate line 210-c in the sections 405-b. The gate line drivers 430-b can be configured to bias one or more of the coupled gate lines 210-c, which can be associated with activating a row of transistors 225 across the sections 405-b along the x-direction. As shown, the gate line drivers 430-b can be used to bias each gate line 210-c in the sections 405-b via the same end (e.g., at an opposite negative location along the x-direction). In some examples, such activation can be associated with simultaneously activating transistors 225 or pillars 220 associated with multiple word lines 205-c, which can support simultaneously accessing memory cells 105 of different subsections 410-b (e.g., via multiple activated word lines 205-c).

[0072] In examples of the layout 500, each word line driver 425-b can be coupled with word lines 205-c associated with multiple sections 405-b (e.g., word lines 205-c associated with multiple subsections 410-b) and can be coupled with a subset of word lines 205-c associated with a given section 405-b. Further, each word line driver 425-b can be associated with a cross-sectional area of multiple sections 405-b, which can include circuitry located between the shown access lines and the substrate. However, in other examples, such word line drivers 425-b can be associated with a cross-sectional area of a single section 405, associated with a cross-sectional area of more than two sections 405, or associated with circuitry located above the shown access lines relative to the substrate, among other configurations.

[0073] In the example of layout 500, word line drivers 425-b can bias word lines 205-c associated with a given section 405-b via different ends (e.g., along the y-direction) of the section 405-b. For example, with respect to section 405-b-2, word line driver 425-b-l can bias word lines 205-c-l l through 205-c-k l via one end of section 405-b-2 at a relatively negative position along the y-direction, and word line driver 425-b-2 can bias word lines 205-c-12 through 205-c-k2 via one end of section 405-b-2 at a relatively positive position along the y-direction.

[0074] Word line drivers 425-b can be configured to bias one or more word lines 205-c with an access voltage, which can be associated with accessing one or more memory cells 105 associated with one or more sections 405-b. For example, word line drivers 425-b can drive current through memory cells 105 coupled with one or more pillars 220 activated by one or more gate line drivers 430-b (e.g., through activated channels of one or more transistors 225). In an illustrative example, word line driver 425-b-l can be used to drive current through memory cells 105 of section 405-b-2 (e.g., of sub-section 410-b-3) when gate line 210-c of section 405-b-2 is activated. Additionally or alternatively (e.g., depending on whether gate lines 210-c of adjacent sections 405-b can be activated simultaneously), word line driver 425-b-l can be used to drive current through memory cells 105 of section 405-b-l (e.g., of sub-section 410-b-l) when gate line 210-c of section 405-b-l is activated. In various examples, word line drivers 425-b associated with a given section 405-b can operate simultaneously, which can include various configurations or operations for biasing word lines 205-c of different sub-sections 410-b according to the same tier 230 or for biasing word lines 205-c of different sub-sections 410-b according to different tiers 230 or various combinations thereof, including techniques similar to those described with reference to layout 400.

[0075] According to examples disclosed herein, word line drivers 425-b can be implemented to support various groupings of odd and even word lines 205-c. In some examples, a first word line driver 425-b can be implemented for biasing odd word lines 205-c associated with a sub-section 410-b, a second word line driver 425-b can be implemented for biasing even word lines 205-c associated with the sub-section 410-b (e.g., where such second word line drivers 425-b can be located at an end of the sub-section 410-b opposite such first word line drivers 425-b along the y-direction). For example, layout 500 can be configured such that word line driver 425-b-1 can be used to bias word lines 205-c-11 through 205-c-k1 (e.g., a group of odd word lines), another word line driver 425-b (not shown, which can be located in or otherwise associated with sub-sections 410-b-3 and 410-b-5) can be used to bias another group of word lines 205-b associated with sub-sections 410-b-3 and 410-b-5, which are interleaved with word lines 205-c-11 through 205-c-k1 (e.g., interleaved within sub-section 410-b-3, a group of even word lines, not shown). In some other examples, a common word line driver 425-b can be implemented for biasing interleaved word lines 205-c associated with a given sub-section 410-b (e.g., a group including both odd and even word lines 205-c). In some examples, various combinations of one or more word line drivers 425-b biasing groups of word lines 205-c simultaneously (e.g., in parallel) can be configured to avoid multiple memory cells 105 associated with the same string 220 or sense line 215-c being activated (e.g., to avoid driving access current through multiple memory cells 105 along the same string 220 or sense line 215-c).

[0076] According to techniques disclosed herein, by configuring sections 405-b to be associated with multiple word line drivers 425-b for a given gate line driver 430-b, layout 500 shows another example for implementing aspects of a memory array with improved layout density (e.g., along the x-direction, the y-direction, or both), improved addressing flexibility, reduced or otherwise improved current magnitude or current density through conductive structures, reduced path length between memory cells and sense circuitry, or reduced charge leakage or other power consumption, among other benefits.

[0077] Figure 6 An example of a layout 600 (e.g., a four-finger layout) that supports parallel access according to examples disclosed herein is shown. Layout 600 can be for implementing reference Figure 2 、 3Aand 3B. For example, the layout 600 can include arrangements of word lines 205-d, gate lines 210-d, and sense lines 215-d, which can be examples of the respective components described with reference to Figure 2 , 3A and 3B. The layout 600 can also include various arrangements of pillars 220, memory cells 105, and transistors 225, which likewise can be examples of the respective components described with reference to Figure 2 , 3A, and 3B, although such components are omitted from FIG. 6 for clarity of illustration, Figure 6 Aspects of the layout 600 can be described with reference to x-directions, y-directions, and z-directions.

[0078] The layout 600 can include segments 405-c, each of which can include a plurality of subsegments 410-c. Each of the segments 405-c and subsegments 410-c and constituent components can be examples of aspects of the respective features described with reference to the layouts 400 and 500. For example, the segment 405-c-2 can include a set of i sense lines 215-c along the x-direction, which can be divided among the subsegments 410-c-l through 410-c-4. In various examples, the sense lines 215-d can be coupled with respective sense amplifier arrays 420-c, with or without respective multiplexers 415-c. The segment 405-c-2 can also include a set of j gate lines 210-d along the y-direction, each of which can extend along the x-direction. Each gate line 210-c can be coupled with the gates of a row of transistors 225 (e.g., i transistors 225 along the x-direction, which can correspond to i pillars 220 and i sense lines 215 along the x-direction), each of which can be used to couple a respective pillar 220 with one of the sense lines 215-d.

[0079] In the example of layout 600, sections 405-c can be associated with (e.g., include at least a portion of) respective groups of k word lines 205-c along the z-direction. As shown, each word line 205-c can include a portion that extends between pillars 220 of a single section 405 (e.g., as with word lines 205-b of layout 400). However, in some other examples, each word line 205-c can include a portion that extends between pillars 220 of multiple sections 405 (e.g., as with word lines 205-c of layout 500, where word lines 205-d-11 and 205-d-12 can extend into sections 405-c-l and 405-c-2, and word lines 205-d-13 and 205-d-14 can extend into sections 405-c-2 and 405-c-3). In some examples, shown word lines 205-d-11 through 205-d-14 can be associated with a same tier 230 (e.g., a first tier) along the z-direction. In some examples, shown word lines 205-d of layout 500 can be portions of a group of word lines 205 referred to as “odd” word lines, which can be interleaved with a corresponding group of “even” word lines 205 (e.g., according to alternating gaps between pillars 220). However, these groups of word lines 205 can be arranged or operated according to different configurations.

[0080] According to examples disclosed herein, drivers associated with different current levels of layout 600 can be configured to facilitate various aspects of the layout or operation of a memory device 100 that includes layout 600 (e.g., one or more sections 405-c). For example, sections 405-c can each be associated with a respective array of conductive structures (e.g., word lines 205-d, sense lines 215-d, pillars 220), where such structures can be coupled using gate lines 210 activated by gate line drivers 430 (e.g., gate line drivers 430-c associated with section 405-c-2). Each section 405-c can be divided into a plurality of subsections 410-c (e.g., four subsections 410-c-l through 410-c-4), where each subsection 410-c can be associated with a respective driver (e.g., a respective word line driver 425-c) for driving access current through memory cells 105 of the subsection 410-c.

[0081] In the example of layout 600, word line drivers 425-c of sections 405-c can bias word lines 205-d via different ends (e.g., along the y-direction) of the sections 405-c. For example, word line drivers 425-c-l and 405-c-2 can bias word lines 205-d via one end of section 405-c-2 at a relatively negative position along the y-direction, and word line drivers 425-c-3 and 425-c-4 can bias word lines 205-d via one end of section 405-c-2 at a relatively positive position along the y-direction.

[0082] Two or more word line drivers 425-c of a section 405-c can operate simultaneously, which can include various configurations or operations for biasing word lines 205-d of different sub-sections 410-c according to a same level 230 or for biasing word lines 205-d of different sub-sections 410-c according to different levels 230 or various combinations thereof. In some examples, operation of a section 405-c-2 can be configured such that word line drivers 425-c-l through 425-c-4 simultaneously bias word lines 205-d-mi through 205-d-m4 (e.g., according to common level addressing between sub-sections 410-c), where the value of m can correspond to a level 230 of section 405-c-2 selected by a level decoder or word line decoder associated with section 405-c-2. In some other examples, operation of section 405-c-2 can be for word line drivers 425-c-l and 425-c-2 to bias word lines 205-d-mi and 205-d-m2, which is simultaneous with word line drivers 425-c-3 and 425-c-4 biasing word lines 205-d-n3 and 205-d-n4 (e.g., according to grouped addressing of sub-sections 410-c), where m and n can be different or the same depending on a given access scenario. In some other examples, operation of section 405-c-2 can be for word line drivers 425-c-l through 425-c-4 to simultaneously bias word lines 205-d-mi, 205-d-n2, 205-d-03, and 205-d-p4 (e.g., according to independent level addressing between sub-sections 410-c), where any of m, n, o, and p can be different or the same depending on a given access scenario.

[0083] According to techniques disclosed herein, by configuring a section 405-c to be associated with multiple word line drivers 425-c for a given gate line driver 430-c, layout 600 shows another example for implementing aspects of a memory array with improved layout density (e.g., along the x-direction, the y-direction, or both), improved addressing flexibility, reduced or otherwise improved current magnitude or current density through conductive structures, reduced path length between memory cells and sensing circuitry, or reduced charge leakage or other power consumption, among other benefits.

[0084] Figure 7 A block diagram 700 showing a memory device 720 supporting parallel comb- like access in a memory array according to examples disclosed herein. Memory device 720 can be a reference Figures 1 to 6Examples of aspects of the described memory devices. The memory device 720, or various components thereof, can be examples of means for performing various aspects of parallel comb access in a memory array as described herein. For example, the memory device 720 can include an access operation component 725, a pillar selection component 730 (e.g., which can be associated with the gate line driver 430), a set of word line drivers 735 (e.g., which can be associated with a set of word line drivers 425), a bias component 740 (e.g., which can be associated with the sense component 130 or the sense amplifier array 420), a memory cell read component 745, a memory cell write component 750, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0085] The access operation component 725 can be configured as, or otherwise support, means for accessing a memory array including a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells. In some examples, each memory cell of the respective plurality of memory cells includes a chalcogenide material.

[0086] In some examples, to support the accessing of the access operation component 725, the pillar selection component 730 can be configured as, or otherwise support, means for coupling each pillar of a set of pillars (e.g., having the second number of pillars) along the second direction with a respective sense line. In some examples, to support the accessing of the access operation component 725, the set of word line drivers 735 can be configured as, or otherwise support, means for biasing, with a first word line driver of the set of word line drivers 735 (e.g., during the coupling of each pillar of the set by the pillar selection component 730 with a respective sense line), a first word line coupled with respective memory cells of each pillar of a first subset of the set of pillars (e.g., the first subset is associated with a third number of pillars that is less than the second number of pillars along the second direction). In some examples, to support the accessing of the access operation component 725, the set of word line drivers 735 can be configured as, or otherwise support, means for biasing, with a second word line driver of the set of word line drivers 735 (e.g., during the coupling of each pillar of the set by the pillar selection component 730 with a respective sense line), a second word line coupled with respective memory cells of each pillar of a second subset of the set of pillars (e.g., the second subset is associated with the third number of pillars along the second direction). In some examples, biasing the first word line and biasing the second word line can be performed simultaneously by the set of word line drivers 735.

[0087] In some examples, the biasing component 740 can be configured as or otherwise support means for biasing a first set of sense lines of a plurality of sense lines coupled with a first subset of the set of pillars based at least in part on a first set of sense amplifiers. In some examples, the biasing component 740 can be configured as or otherwise support means for biasing a second set of sense lines of the plurality of sense lines coupled with a second subset of the set of pillars based at least in part on a second set of sense amplifiers. In some examples, the first set of sense lines can be a subset of the plurality of sense lines coupled with the first subset of the set of pillars, and the second set of sense lines can be a subset of the plurality of sense lines coupled with the second subset of the set of pillars.

[0088] In some examples, the memory cell reading component 745 can be configured as or otherwise support means for determining a logic state for each memory cell coupled with a first word line and a respective sense line of a first set of sense lines based at least in part on a current along the respective sense line associated with a bias of the first word line and a bias of the first set of sense lines. In some examples, the memory cell reading component 745 can be configured as or otherwise support means for determining a logic state for each memory cell coupled with a second word line and a respective sense line of a second set of sense lines based at least in part on a current along the respective sense line associated with a bias of the second word line and a bias of the second set of sense lines.

[0089] In some examples, the memory cell writing component 750 can be configured as or otherwise support means for writing a logic state to each memory cell coupled with a first word line and a respective sense line of a first set of sense lines based at least in part on a voltage polarity between a bias of the first word line and a bias of the respective sense line. In some examples, the memory cell writing component 750 can be configured as or otherwise support means for writing a logic state to each memory cell coupled with a second word line and a respective sense line of a second set of sense lines based at least in part on a voltage polarity between a bias of the second word line and a bias of the respective sense line.

[0090] In some examples, biasing the first word line can be performed via a first end of the plurality of pillars along a first direction. In some examples, biasing the second word line can be performed via a second end of the plurality of pillars opposite the first end along the first direction. In some examples, the first word line and the second word line can be associated with a same level of a memory array above a substrate. In some examples, the first word line can be associated with a first level of a memory array above a substrate, and the second word line can be associated with a second level of a memory array above a substrate, the second level being different than the first level.

[0091] Figure 8 A flow diagram illustrating a method 800 that supports parallel access in a memory array in accordance with examples as disclosed herein is shown. The operations of method 800 can be implemented by a memory device or its components as described herein (e.g., memory device 100, local memory controller 150). For example, the operations of method 800 can be performed by a memory device as described with reference to FIGS. 1-6 and 8A-8B, by a local memory controller as described with reference to FIGS. 1-6 and 8A-8B, or by a processing device as described with reference to FIGS. 1-6 and 8A-8B. Figures 1 to 7 In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0092] At 805, the method can include accessing a memory array including a plurality of columns arranged in a two-dimensional array of a first number of columns along a first direction and a second number of columns along a second direction. In some examples, each column of the plurality of columns can be coupled with a respective plurality of memory cells. Operation 805 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 805 can be performed by an access operation component 725 as described with reference to FIGS. 1-6 and 8A-8B. Figure 7 Access 805 can be performed in accordance with various techniques as disclosed herein, which can include operations 810, 815, or 820, or any combination thereof, as well as other operations.

[0093] In some examples, access 805 can include (e.g., at 810) coupling each column of a set of columns (e.g., having the second number of columns) along the second direction with a respective sense line. Operation 810 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 810 can be performed by a column selection component 730 as described with reference to FIGS. 1-6 and 8A-8B. Figure 7 In some examples, access 805 can include (e.g., at 810) coupling each column of a set of columns (e.g., having the second number of columns) along the second direction with a respective sense line. Operation 810 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 810 can be performed by a column selection component 730 as described with reference to FIGS. 1-6 and 8A-8B.

[0094] In some examples, access 805 can include (e.g., at 815) biasing, with a first word line driver, a first word line coupled with respective memory cells of each column of a first subset of the set of columns during the coupling of each column of the set with a respective sense line. In some examples, the first subset can be associated with a third number of columns that is less than the second number of columns along the second direction. Operation 815 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 815 can be performed by a word line driver set 735 as described with reference to FIGS. 1-6 and 8A-8B. Figure 7 In some examples, access 805 can include (e.g., at 815) biasing, with a first word line driver, a first word line coupled with respective memory cells of each column of a first subset of the set of columns during the coupling of each column of the set with a respective sense line. In some examples, the first subset can be associated with a third number of columns that is less than the second number of columns along the second direction. Operation 815 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 815 can be performed by a word line driver set 735 as described with reference to FIGS. 1-6 and 8A-8B.

[0095] In some examples, the accessing 805 can include (e.g., at 820) biasing, with the second word line driver, a second word line coupled with respective memory cells of each column of a second subset of the set of columns during the coupling of each column of the set with the respective sense line. In some examples, the second subset can be associated with a third number of columns along the second direction. The operations 820 can be performed according to the examples disclosed herein. Aspects of the operations 820 can be performed by the second word line driver 735 as described with reference to Figure 7 The described set of word line drivers 735 performs.

[0096] In some examples, an apparatus described herein can perform one or more methods, such as the method 800. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing aspects of the disclosure, or any combination thereof:

[0097] Aspect 1 : A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions or any combination thereof for accessing a memory array including a plurality of columns arranged in a two-dimensional array of a first number of columns along a first direction and a second number of columns along a second direction, each column of the plurality of columns coupled with a respective plurality of memory cells, wherein the accessing includes: coupling each column of a set of columns (e.g., having the second number of columns) along the second direction with a respective sense line; biasing, with a first word line driver, a first word line coupled with respective memory cells of each column of a first subset of the set of columns during the coupling of each column of the set with the respective sense line (e.g., the first subset is associated with a third number of columns along the second direction that is less than the second number of columns); and biasing, with a second word line driver, a second word line coupled with respective memory cells of each column of a second subset of the set of columns during the coupling of each column of the set with the respective sense line (e.g., the second subset is associated with the third number of columns along the second direction).

[0098] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further including operations, features, circuitry, logic, means, or instructions or any combination thereof for biasing a first set of sense lines based at least in part on coupling the first set of sense lines with a first set of sense amplifiers coupled with the first subset of the set of columns, and biasing a second set of sense lines based at least in part on coupling the second set of sense lines with a second set of sense amplifiers coupled with the second subset of the set of columns.

[0099] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2, wherein the first set of sense lines is a subset of the plurality of sense lines coupled with the first subset of the set of pillars, and the second set of sense lines is a subset of the plurality of sense lines coupled with the second subset of the set of pillars.

[0100] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 2-3, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: determining a logic state for each memory cell coupled with a respective sense line of the first set of sense lines based at least in part on a current along the respective sense line associated with the bias of the first word line and the bias of the first set of sense lines, and determining a logic state for each memory cell coupled with a respective sense line of the second set of sense lines based at least in part on a current along the respective sense line associated with the bias of the second word line and the bias of the second set of sense lines.

[0101] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 2-3, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: writing a logic state to each memory cell coupled with the first word line and a respective sense line of the first set of sense lines based at least in part on a voltage polarity between the bias of the first word line and the bias of the respective sense line of the first set of sense lines, and writing a logic state to each memory cell coupled with the second word line and a respective sense line of the second set of sense lines based at least in part on a voltage polarity between the bias of the second word line and the bias of the respective sense line of the second set of sense lines.

[0102] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-5, wherein biasing the first word line and biasing the second word line are performed simultaneously.

[0103] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-6, wherein biasing the first word line is performed via a first end of the plurality of pillars along the first direction, and biasing the second word line is performed via a second end of the plurality of pillars opposite the first end along the first direction.

[0104] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-7, wherein the first word line and the second word line are associated with a same level of the memory array above a substrate.

[0105] Aspect 9: The method, apparatus, or non-transitory computer- readable medium of any of Aspects 1-7, wherein the first word line is associated with a first level of the memory array above a substrate, the second word line is associated with a second level of the memory array above the substrate, the second level is different than the first level.

[0106] Aspect 10: The method, apparatus, or non-transitory computer- readable medium of any of Aspects 1-9, wherein each memory cell of the respective plurality of memory cells includes a chalcogenide material.

[0107] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0108] An apparatus is described. Summaries of aspects of the apparatus described herein are provided below:

[0109] Aspect 11: An apparatus comprising: a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells; a plurality of activation lines, each activation line usable to activate a respective group of the plurality of pillars along the second direction, having the second number of pillars; a plurality of first word lines, each first word line coupled with respective memory cells of each pillar of a first subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and a third number of pillars along the second direction and less than the second number of pillars; a first word line driver usable to bias one of the plurality of first word lines; a plurality of second word lines, each second word line coupled with respective memory cells of each pillar of a second subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and the third number of pillars along the second direction; and a second word line driver usable to bias one of the plurality of second word lines.

[0110] Aspect 12: The apparatus of Aspect 11, wherein: the first word line driver is usable to bias the one of the plurality of first word lines via a first end of the plurality of pillars along the first direction; and the second word line driver is usable to bias the one of the plurality of second word lines via a second end of the plurality of pillars along the first direction opposite the first end.

[0111] Aspect 13: The apparatus of Aspect 12, wherein: the plurality of first word lines are each coupled with respective memory cells of each column of a third subset of a second plurality of columns different from the plurality of columns; and the plurality of second word lines are each coupled with respective memory cells of each column of a fourth subset of a third plurality of columns different from the plurality of columns and the second plurality of columns.

[0112] Aspect 14: The apparatus of any one of Aspects 11 through 13, further comprising: a plurality of third word lines each coupled with respective memory cells of each column of a third subset of the plurality of columns arranged in a two-dimensional array of the first number of columns along the first direction and the third number of columns along the second direction; a third word line driver usable to bias one of the plurality of third word lines; a plurality of fourth word lines each coupled with respective memory cells of each column of a fourth subset of the plurality of columns arranged in a two-dimensional array of the first number of columns along the first direction and the third number of columns along the second direction; and a fourth word line driver usable to bias one of the plurality of fourth word lines.

[0113] Aspect 15: The apparatus of any one of Aspects 11 through 14, further comprising: a plurality of third word lines each coupled with respective memory cells of each column of the first subset of the plurality of columns, wherein the second word line driver is usable to bias one of the plurality of third word lines; and a plurality of fourth word lines each coupled with respective memory cells of each column of the second subset of the plurality of columns, wherein the first word line driver is usable to bias one of the plurality of third word lines.

[0114] Aspect 16: The apparatus of any one of Aspects 11 through 15, wherein the first word line driver is usable to bias the one of the plurality of first word lines while the second word line driver biases the one of the plurality of second word lines.

[0115] Aspect 17: The apparatus of any one of Aspects 11 through 16, wherein the one of the plurality of first word lines is associated with a same address along a third direction as the one of the plurality of second word lines.

[0116] Aspect 18: The apparatus of any one of Aspects 11 through 17, wherein the first word line driver is usable to bias the one of the plurality of first word lines at an address along a third direction different from the one of the plurality of second word lines.

[0117] Aspect 19: The apparatus of any one of aspects 11 through 18, wherein each memory cell of the respective plurality of memory cells includes a chalcogenide material.

[0118] Aspect 20: The apparatus of any one of aspects 11 through 19, wherein each memory cell of the respective plurality of memory cells is usable to store a respective logic state according to a threshold characteristic of the memory cell.

[0119] An apparatus is described. Summaries of aspects of the apparatus described herein are provided below:

[0120] Aspect 21 : An apparatus comprising: a memory array including a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells; a first word line driver; a second word line driver; and circuitry coupled with the memory array, wherein to access the memory array, the circuitry is usable to: couple each pillar in a group of pillars along the second direction having the second number of pillars with a respective sense line; bias, with the first word line driver, a first word line coupled with respective memory cells of each pillar of a first subset of the group of pillars during coupling of each pillar in the group with the respective sense line, the first subset associated with a third number of pillars along the second direction that is less than the second number of pillars; and bias, with the second word line driver, a second word line coupled with respective memory cells of each pillar of a second subset of the group of pillars during coupling of each pillar in the group with the respective sense line, the second subset associated with the third number of pillars along the second direction.

[0121] Aspect 22: The apparatus of aspect 21, wherein to access the memory array, the circuitry is usable to: bias a first set of sense lines based at least in part on coupling the first set of sense lines with a first set of sense amplifiers coupled with the first subset of the group of pillars; and bias a second set of sense lines based at least in part on coupling the second set of sense lines with a second set of sense amplifiers coupled with the second subset of the group of pillars.

[0122] Aspect 23: The apparatus of any one of aspects 21 through 22, wherein: the first word line driver is usable to bias the first word line via a first end of the plurality of pillars along the first direction; and the second word line driver is usable to bias the second word line via a second end of the plurality of pillars along the first direction opposite the first end.

[0123] Aspect 24: The apparatus of Aspect 23, wherein: the first word line is coupled with respective memory cells of each column of a third subset of a second plurality of columns different from the plurality of columns; and the second word line is coupled with respective memory cells of each column of a fourth subset of a third plurality of columns different from the plurality of columns and the second plurality of columns.

[0124] Aspect 25: The apparatus of any one of Aspects 21-24, wherein each memory cell of the respective plurality of memory cells includes a chalcogenide material.

[0125] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent multiple signals, which can be refracted as a single signal over a bus.

[0126] The terms “electronic communication,” “electrically conductive contact,” “connected,” and “coupled” can refer to a relationship between components in which a signal can flow from one component to another. Components are considered to be in electronic communication with one another (or in electrically conductive contact with one another, or connected to one another, or coupled to one another) if there exists any electrically conductive path that can support the flow of a signal between the components at any time. The electrically conductive path between components that are in electronic communication with one another (or in electrically conductive contact with one another, or connected to one another, or coupled to one another) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The electrically conductive path between connected components can be a direct electrically conductive path between the components, or the electrically conductive path between connected components can be an indirect electrically conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of a signal between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0127] The term “coupled” refers to a condition that moves from an open circuit relationship between components, in which a signal cannot currently be transmitted between the components through an electrically conductive path, to a closed circuit relationship between the components, in which a signal can be transmitted between the components through an electrically conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components through an electrically conductive path that previously did not allow signal flow.

[0128] The term "isolated" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is a break in the circuit between them. For example, components separated by a switch positioned between the two components are isolated from each other when the switch is open. When a controller isolates two components, the controller effects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

[0129] The term "layer" or "level" as used herein refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or level can be a three-dimensional structure having two dimensions greater than a third dimension, such as a thin film. A layer or level can include different elements, components, or materials. In some examples, a layer or level can be composed of two or more sub-layers or sub-levels.

[0130] Devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0131] Switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0132] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0133] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference label to refer to the first instance of a component and a second reference label to refer to the second instance of the component. If only the first reference label is used in the description, it is also intended to cover the second instance of the component, and vice versa.

[0134] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred across a computer-readable medium and executed by a processor. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0135] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, for example. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine, for example. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0136] As used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B, and need not be limited to only the single condition A without

[0137] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0138] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells; a plurality of activation lines, each activation line usable to activate a respective group of the plurality of pillars having the second number of pillars along the second direction; a plurality of first word lines, each first word line coupled with respective memory cells of each pillar of a first subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and a third number of pillars along the second direction and less than the second number of pillars; a first word line driver usable to bias one of the plurality of first word lines; a plurality of second word lines, each second word line coupled with respective memory cells of each pillar of a second subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and the third number of pillars along the second direction; and a second word line driver usable to bias one of the plurality of second word lines.

2. The memory device of claim 1, wherein: the first word line driver is usable to bias the one of the plurality of first word lines via a first end of the plurality of pillars along the first direction; and the second word line driver is usable to bias the one of the plurality of second word lines via a second end of the plurality of pillars along the first direction opposite the first end.

3. The memory device of claim 2, wherein: the plurality of first word lines are each coupled with respective memory cells of each pillar of a third subset of a second plurality of pillars different from the plurality of pillars; and the plurality of second word lines are each coupled with respective memory cells of each pillar of a fourth subset of a third plurality of pillars different from the plurality of pillars and the second plurality of pillars.

4. The memory device of claim 1, further comprising: a plurality of third word lines, each third word line coupled with respective memory cells of each pillar of a third subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and the third number of pillars along the second direction; a third word line driver usable to bias one of the plurality of third word lines; a plurality of fourth word lines, each fourth word line coupled with respective memory cells of each pillar of a fourth subset of the plurality of pillars arranged in a two-dimensional array of the first number of pillars along the first direction and the third number of pillars along the second direction; and a fourth word line driver usable to bias one of the plurality of fourth word lines.

5. The memory device of claim 1, further comprising: a plurality of third word lines, each third word line coupled with respective memory cells of each pillar of the first subset of the plurality of pillars, wherein the second word line driver is usable to bias one of the plurality of third word lines; and a plurality of fourth word lines, each fourth word line coupled with respective memory cells of each pillar of the second subset of the plurality of pillars, wherein the first word line driver is usable to bias one of the plurality of third word lines.

6. The memory device of claim 1, wherein the first word line driver is usable to bias the one of the plurality of first word lines while the second word line driver biases the one of the plurality of second word lines.

7. The memory device of claim 1, wherein the one of the plurality of first word lines is associated with a same address along a third direction as the one of the plurality of second word lines.

8. The memory device of claim 1, wherein the first word line driver is usable to bias the one of the plurality of first word lines at a different address along a third direction than the one of the plurality of second word lines.

9. The memory device of claim 1, wherein each memory cell of the respective plurality of memory cells comprises a chalcogenide material.

10. The memory device of claim 1, wherein each memory cell of the respective plurality of memory cells is usable to store a respective logic state according to a threshold characteristic of the memory cell.

11. A method for performing memory operations, comprising: accessing a memory array comprising a plurality of pillars arranged in a two- dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells, wherein the accessing comprises: coupling each pillar of a group of pillars having the second number of pillars along the second direction with a respective sense line; with a first word line driver, biasing, during coupling of each pillar of the group with the respective sense line, a first word line coupled with respective memory cells of each pillar of a first subset of the group of pillars, the first subset associated with a third number of pillars along the second direction that is less than the second number of pillars; and with a second word line driver, biasing, during coupling of each pillar of the group with the respective sense line, a second word line coupled with respective memory cells of each pillar of a second subset of the group of pillars, the second subset associated with the third number of pillars along the second direction.

12. The method of claim 11, further comprising: biasing, based at least in part on coupling a first group of sense lines of a plurality of sense lines coupled with the first subset of the group of pillars with a first group of sense amplifiers, the first group of sense lines; and biasing a second set of sense lines of a plurality of sense lines coupled with the second subset of the set of pillars and a second set of sense amplifiers based at least in part on the coupling.

13. The method of claim 12, wherein: the first set of sense lines is a subset of the plurality of sense lines coupled with the first subset of the set of pillars; and the second set of sense lines is a subset of the plurality of sense lines coupled with the second subset of the set of pillars.

14. The method of claim 12, further comprising: determining a logic state for each memory cell coupled with the first word line and a respective sense line of the first set of sense lines based at least in part on a current along the respective sense line associated with the bias of the first word line and the bias of the first set of sense lines; and determining a logic state for each memory cell coupled with the second word line and a respective sense line of the second set of sense lines based at least in part on a current along the respective sense line associated with the bias of the second word line and the bias of the second set of sense lines.

15. The method of claim 12, further comprising: writing a logic state to each memory cell coupled with the first word line and a respective sense line of the first set of sense lines based at least in part on a voltage polarity between the bias of the first word line and the bias of the respective sense line of the first set of sense lines; and writing a logic state to each memory cell coupled with the second word line and a respective sense line of the second set of sense lines based at least in part on a voltage polarity between the bias of the second word line and the bias of the respective sense line of the second set of sense lines.

16. The method of claim 11, wherein biasing the first word line and biasing the second word line are performed simultaneously.

17. The method of claim 11, wherein: biasing the first word line is performed via a first end of the plurality of pillars along the first direction; and biasing the second word line is performed via a second end of the plurality of pillars opposite the first end along the first direction.

18. The method of claim 11, wherein the first word line and the second word line are associated with a same level of the memory array above a substrate.

19. The method of claim 11, wherein: the first word line is associated with a first level of the memory array above a substrate; and the second word line is associated with a second level of the memory array above a substrate, the second level being different than the first level.

20. The method of claim 11, wherein each memory cell of the respective plurality of memory cells comprises a chalcogenide material.

21. A memory device, comprising: a memory array comprising a plurality of pillars arranged in a two-dimensional array of a first number of pillars along a first direction and a second number of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells; a first word line driver; a second word line driver; and circuitry coupled with the memory array, wherein to access the memory array, the circuitry is employable to: couple each pillar of a set of pillars having the second number of pillars along the second direction with a respective sense line; with the first word line driver, bias a first word line coupled with respective memory cells of each pillar of a first subset of the set of pillars, the first subset associated with a third number of pillars less than the second number of pillars along the second direction, during the coupling of each pillar of the set with the respective sense line; and with a second word line driver, bias a second word line coupled with respective memory cells of each pillar of a second subset of the set of pillars, the second subset associated with the third number of pillars along the second direction, during the coupling of each pillar of the set with the respective sense line.

22. The memory device of claim 21, wherein to access the memory array, the circuitry is employable to: bias a first set of sense lines based at least in part on coupling the first set of sense lines with a first set of sense amplifiers of a plurality of sense lines coupled with the first subset of the set of pillars; and bias a second set of sense lines based at least in part on coupling the second set of sense lines with a second set of sense amplifiers of the plurality of sense lines coupled with the second subset of the set of pillars.

23. The memory device of claim 21, wherein: the first word line driver is employable to bias the first word line via a first end of the plurality of pillars along the first direction; and the second word line driver is employable to bias the second word line via a second end of the plurality of pillars opposite the first end along the first direction.

24. The memory device of claim 23, wherein: the first word line is coupled with respective memory cells of each pillar of a third subset of a second plurality of pillars different from the plurality of pillars; and the second word line is coupled with respective memory cells of each pillar of a fourth subset of a third plurality of pillars different from the plurality of pillars and the second plurality of pillars.

25. The memory device of claim 21, wherein each memory cell of the respective plurality of memory cells comprises a chalcogenide material.

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