Method for etching silicon oxide

Abstract

The application discloses an etching method of silicon oxide, which comprises the following steps: providing a substrate, wherein the substrate comprises a silicon oxide layer, and a mask layer is arranged on the silicon oxide layer; introducing a first etching gas into a process chamber, and loading an upper electrode power signal and a lower electrode power signal into an upper electrode and a lower electrode of the process chamber respectively to etch the silicon oxide layer and form an etching groove in the silicon oxide layer, wherein the upper electrode power signal and the lower electrode power signal adopt a synchronous pulse mode. The application can simplify the etching process and obtain a silicon oxide structure with a high aspect ratio.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing, and more specifically, relates to a method for etching silicon oxide. Background Technology

[0002] With the development of Micro-Electro-Mechanical Systems (MEMS) technology, silicon has begun to emerge as a low-cost, easily processed structural material in the microelectronics field. However, as a functional material, silicon still has many shortcomings. In the field of novel MEMS devices—photoelectric transmission—its transmission loss is relatively high, and many different materials have shown better performance (quality factor Q) than silicon. Specifically, in the fields of optical waveguides, microwave technology, sensors, and biochips, devices based on silicon oxide, quartz, and glass have emerged.

[0003] However, the high-depth and wide silicon oxide microstructures obtained by current silicon oxide etching technology have problems such as complex process steps, low efficiency and low verticality of the etching morphology sidewalls, which cannot meet the needs of the MEMS field. Summary of the Invention

[0004] The purpose of this invention is to propose an etching method for silicon oxide that simplifies the etching process and yields silicon oxide morphology structures with a high aspect ratio.

[0005] To achieve the above objectives, the present invention proposes a method for etching silicon oxide, comprising:

[0006] A substrate is provided, the substrate comprising a silicon oxide layer;

[0007] A first etching gas is introduced into the process chamber, and an upper electrode power signal and a lower electrode power signal are respectively applied to the upper electrode and the lower electrode of the process chamber to etch the silicon oxide layer and form etching trenches in the silicon oxide layer. The upper electrode power signal and the lower electrode power signal adopt a synchronous pulse mode, which means that the upper electrode power signal and the lower electrode power signal are synchronized.

[0008] Optionally, the first etching gas includes a first carbon-fluorine gas and a byproduct removal gas;

[0009] In the step of etching the silicon oxide layer, when the upper electrode power signal and the lower electrode power signal are in the on cycle, the first carbon-fluorine gas etches the silicon oxide layer, and the by-product removal gas removes the by-products generated during etching; when the upper electrode power signal and the lower electrode power signal are in the off cycle, the by-products generated during etching are extracted.

[0010] Optionally, the ratio of C atoms to F atoms in the first fluorocarbon gas is greater than or equal to 1 / 2; and / or

[0011] The byproduct removal gas includes O2.

[0012] Optionally, the first etching gas further includes a diluting gas, which includes at least one of Ar and He.

[0013] Optionally, the first fluorocarbon gas includes C4F6, the byproduct removal gas includes O2, and the dilution gas includes Ar;

[0014] The gas flow rate ratio of Ar, C4F6 and O2 in the first etching gas is in the range of (50-70):(1.5-3):1.

[0015] Optionally, the process temperature used in the etching step of the silicon oxide layer is 60°C-80°C.

[0016] Optionally, in the step of etching the silicon oxide layer, the peak power range of the lower electrode power signal is 600-900W; and / or

[0017] The peak power range of the upper electrode power signal is 300-750W.

[0018] Optionally, the frequency range of the upper electrode power signal and the lower electrode power signal is 1000-2500Hz, and the pulse duty cycle range is 15-30%.

[0019] Optionally, in the step of etching the silicon oxide layer, the chamber pressure range is 4-7 mT.

[0020] Optionally, in the first etching gas:

[0021] The O2 gas flow rate range is 4-10 sccm;

[0022] Ar gas flow rate range is 250-450 sccm;

[0023] The gas flow rate range for C4F6 is 10-20 sccm.

[0024] Optionally, after etching the silicon oxide layer, the process further includes:

[0025] The residual byproducts on the top and sidewalls of the etched trench are removed using a second etching gas, which includes a second fluorocarbon gas and a second byproduct removal gas.

[0026] Optionally, the carbon-to-fluorine ratio of the second fluorocarbon gas is less than that of the first fluorocarbon gas; and / or

[0027] The second byproduct removal gas includes O2.

[0028] Optionally, the process parameters used for etching the silicon oxide layer with the second etching gas further include:

[0029] The pressure range of the process chamber is 10-30 mT;

[0030] The process temperature range is 60-80℃.

[0031] The beneficial effects of this invention are as follows:

[0032] In the silicon oxide etching method of this invention, the upper electrode power and the lower electrode power adopt a synchronous pulse mode during the etching process of silicon oxide, and the frequency and duty cycle of the upper electrode power signal and the lower electrode power signal are the same. During the synchronous pulse etching process of upper and lower electrode power, the upper electrode power and the lower electrode power are turned on or off simultaneously. When turned on, etching occurs and by-products and polymers are generated. When turned off, some of the by-products and polymers generated during the power-on stage can be pumped away by the pump of the machine. Since the upper electrode power is turned off, no new by-products and polymers are generated at this time. Therefore, an etching morphology with high aspect ratio and verticality can be obtained. This method can complete silicon oxide etching in only one step, and the process flow is simple.

[0033] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0034] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0035] Figure 1 The etching morphology diagrams corresponding to each step of a silicon oxide etching method of related technology 1 are shown.

[0036] Figure 2 A step diagram of an etching method for silicon oxide according to an embodiment of the present invention is shown.

[0037] Figure 3 A schematic diagram of the substrate film structure in a silicon oxide etching method according to an embodiment of the present invention is shown.

[0038] Figure 4The image shows a TEM characterization of the etching morphology after the main etching step is completed in a silicon oxide etching method according to an embodiment of the present invention.

[0039] Figure 5 A schematic diagram of the etched morphology after the cleaning step is completed in a silicon oxide etching method according to an embodiment of the present invention is shown.

[0040] Figure 6 The TEM image shows the etch morphology after the cleaning step in a silicon oxide etching method according to an embodiment of the present invention.

[0041] Figure 7 The TEM characterization diagram of the process results obtained using the existing Bosch time-division multiplexing etching scheme is shown. Detailed Implementation

[0042] Related technology one proposes a silicon oxide etching method that utilizes the time-division multiplexing method in the Bosch process, employing alternating sidewall deposition protection and chemical etching to achieve silicon oxide etching. The process is as follows: Figure 1 As shown, the deposition step uses octafluorocyclobutane for sidewall protection, with a low lower electrode power (less than 200W) or it can be turned off. Alternatively, other fluorocarbon gases such as CHF3 can be used. The etching step uses a mixture of CF4 and Ar as the chemical etchant. Ne or Kr can be used instead of Ar, and SF6 or NF3 can be added to the CF4 mixture. If silicon is used as the mask or to increase the selectivity of silicon at the bottom, H2 can be added to the etching gas. By using time-division multiplexing in the Bosch process, deposition protection and chemical etching are performed simultaneously, ultimately achieving silicon oxide etching with a high aspect ratio.

[0043] This method involves multiple cycles during the Bosch process, resulting in a long process time.

[0044] Related technology two discloses a silicon oxide etching method, which involves etching into a silicon oxide-containing material in an etching environment with at least 75% helium by volume. The etching environment also includes carbon monoxide, O2, and one or more fluorocarbons. Openings formed in the silicon oxide-containing material can be used to manufacture capacitors.

[0045] The etching morphology obtained by this method is an inverted trapezoid with low perpendicularity.

[0046] To address the aforementioned technical problems in related technologies, this invention provides a silicon oxide etching method that uses synchronous pulsed plasma etching to etch the silicon oxide film, thereby obtaining a silicon oxide etching morphology with a high aspect ratio and high verticality.

[0047] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0048] Example

[0049] like Figure 2 As shown, this embodiment provides a method for etching silicon oxide, specifically including:

[0050] S1: Provides a substrate, the substrate including a silicon oxide layer 104;

[0051] Specifically, such as Figure 3 As shown, the substrate film structure of this embodiment includes, from top to bottom, a photoresist layer 101 (PR), a dielectric antireflective layer 102 (DAC), an organic dielectric layer 103 (ODL), a silicon oxide layer 104, an atomic layer deposited silicon nitride layer 105, and a base layer formed by single-crystal silicon 106 and a silicon nitride layer 107. The photoresist layer 101, the dielectric antireflective layer 102, and the organic dielectric layer 103 together constitute a mask layer.

[0052] The etching process in this embodiment is divided into three parts based on the film layer distribution: etching of the dielectric anti-reflection layer 102, etching of the organic dielectric layer 103, and etching of the silicon oxide layer 104. Among them, the etching of the dielectric anti-reflection layer 102 is used to define the critical dimension (CD) and improve the critical dimension uniformity (CDU), while the etching of the organic dielectric layer 103 is used for pattern transfer.

[0053] Before etching the silicon oxide layer 104, the etching steps for the dielectric antireflective layer 102 and the mechanical dielectric layer 103 are first completed, specifically including:

[0054] Step BT: Etch the dielectric anti-reflection layer 102 using CF4 and CHF3 as etching gases to complete the image transfer from the photoresist mask to the dielectric anti-reflection layer.

[0055] The process parameters for this step include:

[0056] Chamber pressure 10-20 mT; upper electrode power 500-1000 W; lower electrode power 50-200 W; CF4 gas flow rate 20-100 sccm; CHF3 gas flow rate 20-200 sccm; He gas flow rate 100-300 sccm; etching time 20-30 s; chuck temperature 30℃.

[0057] ODL step: Etching organic dielectric layer 103, mainly using O2, COS, and Ar gases, as the key to pattern transfer.

[0058] The process parameters for this step include:

[0059] Chamber pressure 5-10 mT; upper electrode power 700-1200 W; lower electrode power 200-400 W; O2 gas flow rate 20-40 sccm; COS gas flow rate 20-100 sccm; Ar gas flow rate 200-450 sccm; etching time 40-100 s; chuck temperature 30℃.

[0060] S2: A first etching gas is introduced into the process chamber, and upper electrode power signals and lower electrode power signals are applied to the upper and lower electrodes of the process chamber, respectively, to etch the silicon oxide layer 104, forming etching trenches in the silicon oxide layer 104. The upper electrode power signals and lower electrode power signals adopt a synchronous pulse mode, which means that the upper electrode power signals and lower electrode power signals are synchronized. Synchronization means that the upper electrode power signals and lower electrode power signals are turned on and off simultaneously, and their frequencies and duty cycles are the same. The etching process in this embodiment can be performed, for example, in an inductively coupled (ICP) semiconductor process apparatus.

[0061] This step is the main etching step (ME step), which specifically includes:

[0062] The silicon oxide layer 104 is etched using a first etching gas, which includes a first fluorocarbon gas and a byproduct removal gas. During the etching process, when the upper electrode power signal and the lower electrode power signal are in the ON cycle, that is, when the pulse signal is ON, the first fluorocarbon gas etches the silicon oxide layer, and the byproduct removal gas removes the byproducts generated during etching. When the upper electrode power signal and the lower electrode power signal are in the OFF cycle, that is, when the pulse signal is OFF, the byproducts generated during etching are extracted.

[0063] In this first fluorocarbon gas, the ratio of C atoms to F atoms is greater than or equal to 1 / 2. Optionally, the first fluorocarbon gas includes at least one of C4F6 and C4F8, with C4F6 being preferred in this step.

[0064] C4F6, as a gas with a high C / F ratio, exhibits a high etching rate for SiO2 and a high selectivity of the SiO2 film for photoresist or organic dielectric layers. However, due to its high C / F ratio, it readily forms polymers during etching, which can easily lead to etching termination. Therefore, a byproduct removal gas is added in this step to effectively prevent silicon oxide etching termination.

[0065] Preferably, the byproduct removal gas includes O2. Adding O2 during the main etching step effectively reduces byproducts and polymer buildup formed during the etching process of low-C4F6. This allows for simultaneous polymer removal during etching, which is beneficial for the formation of high aspect ratio and highly vertical silicon oxide morphology.

[0066] Optionally, the first etching gas may further include a dilution gas, which includes at least one of Ar and He, with Ar being preferred in this step.

[0067] Adding Ar as a diluent to the first etching gas can adjust the reaction intensity. At the same time, Ar is more easily dissociated to provide electrons to maintain plasma stability. Ar in the etching gas can provide strong physical bombardment capabilities, which is conducive to forming a silicon oxide morphology structure with a high aspect ratio and high verticality.

[0068] The first etching gas in this embodiment includes C4F6, O2 and Ar; preferably, the gas flow rate ratio of Ar, C4F6 and O2 in the first etching gas is in the range of (50-70):(1.5-3):1.

[0069] When choosing C4F6, Ar, and O2 as etching gases, the ratio of the three gases is particularly important. The ratio of Ar:C4F6:O2 should be controlled at (50-70):(1.5-3):1 to make the etching a physicochemical etching process that can form a better morphological structure.

[0070] Preferably, the process temperature used in this step is 60℃-80℃. A relatively high temperature environment is conducive to the volatilization and removal of etching byproducts, and can also accelerate the reaction.

[0071] Preferably, the peak power range of the lower electrode pulse mode loading used in this step is 600-900W. Using a higher lower electrode power can provide stronger bombardment capability and increase the etching rate.

[0072] Preferably, the chamber pressure range used in this step is 4-7 mT. Using a relatively low-pressure environment of 4-7 mT has several advantages. Firstly, the mean free path of molecules increases, reducing the probability of collisions between particles. Ar, as the main inert diluent gas in the etching gas, provides strong physical bombardment capabilities, which is beneficial for forming a silicon oxide morphology with a high aspect ratio and high verticality. Secondly, the low-pressure environment results in relatively good etching uniformity.

[0073] Preferably, the process parameters used in this step further include:

[0074] The peak power range of the upper electrode pulse mode loading is 300-750W;

[0075] In the first etching gas:

[0076] The O2 gas flow rate range is 4-10 sccm;

[0077] Ar gas flow rate range is 250-450 sccm;

[0078] The gas flow rate range of C4F6 is 10-20 sccm;

[0079] The etching process takes 240-300 seconds.

[0080] The chuck temperature is 60℃-80℃, for example, it can be 80℃.

[0081] This step, as the main etching step, uses the upper organic dielectric layer 103 as a mask and employs a synchronous pulse method for the upper and lower electrode power signals. C4F6, Ar, and O2 are used as the main etching gases to improve the selectivity of silicon oxide for the upper organic dielectric layer 103. Simultaneously, high-temperature treatment is performed to make the byproducts and polymers generated during etching more volatile and easily extracted by the dry pump of the machine.

[0082] Preferably, in this step, the frequency range of the pulses for the upper and lower electrodes is 1000-2500Hz, and the pulse duty cycle range is 15-30%.

[0083] In this step, a synchronous pulse mode is used to select the power of the upper and lower electrodes. The power of the upper and lower electrodes is kept synchronized in terms of frequency and duty cycle. When it is turned on, etching occurs and byproducts and polymers are generated. When it is turned off, some of the byproducts and polymers generated earlier can be pumped away by the machine pump. Since the power of the upper electrode is turned off, no new byproducts and polymers can be generated, which is conducive to the cleaning of byproducts and polymers and avoids etching stoppage caused by the accumulation of byproducts and polymers.

[0084] Specifically, the duty cycle of the upper and lower electrode pulse power signals determines the on and off times of the upper and lower electrode power. During the on-time of the upper and lower electrode power, C4F6 reacts with silicon oxide to etch it, while O2 reacts with the byproducts generated during etching, reducing these byproducts. During the off-time of the upper and lower electrode power, the byproducts from the etched silicon oxide surface can be pumped out of the chamber by the machine's pump, thus removing the byproducts. Taking a 30% duty cycle as an example, the on-time of the upper and lower electrode power signals accounts for 30% of one pulse cycle. During this time, silicon oxide is etched, and byproducts are generated on the silicon oxide surface. The off-time of the upper and lower electrode power signals accounts for 70%. During this time, no new byproducts are generated, and the chamber remains under controlled pressure. Therefore, during the off-time, gas flow and molecular pump extraction continue in the process chamber, completing the extraction of byproducts and preventing etching termination due to byproduct accumulation.

[0085] Furthermore, during the later stages of the synchro pulse power shutdown, negatively charged particles transform from electrons to negative ions. The particles in the chamber change from electrons and ions to positive and negative ions, with the positive and negative ion fluxes becoming essentially equal. At this point, the ion sheath collapses, allowing negative ions to reach the bottom of the substrate and balance the accumulated positive charge. This process facilitates the removal of bottom polymers, preventing etching stoppage caused by uneven accumulation of residual polymers during subsequent etching processes. Higher lower electrode power tends to yield morphologies with higher verticality.

[0086] The process result after etching in this step is as follows: Figure 4 As shown, it can be seen that using synchronous pulses has a high selectivity for the upper ODL mask.

[0087] In this embodiment, after etching the silicon oxide layer 104, the method further includes:

[0088] S3: Use the second etching gas to remove residual byproducts on the top and sidewalls of the silicon oxide etching trench;

[0089] The second etching gas includes a second carbon-fluorine gas and a second byproduct removal gas.

[0090] Preferably, the second fluorocarbon gas in this step includes CF4, and the second byproduct removal gas includes O2.

[0091] Preferably, the process chamber pressure in this step is in the range of 10-30 mT; the process temperature is in the range of 60-80℃, preferably 80℃. Higher process temperature and higher chamber pressure can improve the removal effect of by-products and polymers.

[0092] Preferably, the process parameters used in this step further include:

[0093] The upper electrode power range is 800-2000W;

[0094] The lower electrode power range is 0-50W;

[0095] The CF4 gas flow rate range is 10-30 sccm;

[0096] The O2 gas flow rate range is 200-500 sccm;

[0097] The process time ranges from 20 to 50 seconds.

[0098] Specifically, this step is the by-product removal step (Strip step), using CF4 and O2 as etching gases, and cleaning by-products and polymer residues from the top and sidewalls of the etched morphology under high temperature and high chamber pressure. The completed etched morphology is as follows: Figure 5 As shown.

[0099] In this embodiment, the preferred process formulations used in each etching step are shown in Table 1.

[0100] Table 1: Etching Process Formulation Table

[0101]

[0102] The process results obtained using the above process formula are as follows: Figure 6 As shown, the obtained silicon oxide etchable morphology has an aspect ratio of up to 5:1 and a high sidewall verticality.

[0103] At the same time, such as Figure 7 As shown, the process results obtained by etching silicon oxide using the current Bosch time-division multiplexing scheme show that the critical dimensions of the morphology formed by the Bosch process are relatively large (in μm). Furthermore, as the critical dimensions decrease, the Bosch process places higher demands on both the deposition and etching steps. From... Figure 6 As can be seen, the critical dimension of this solution is at the nm level. This solution can achieve a high aspect ratio and high verticality silicon oxide etching solution with a smaller critical dimension by using inductively coupled synchronous pulses, and the process is simpler.

[0104] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. An etching method of silicon oxide, characterized by, include: A substrate is provided, the substrate comprising a silicon oxide layer; A first etching gas is introduced into the process chamber, and an upper electrode power signal and a lower electrode power signal are respectively applied to the upper electrode and the lower electrode of the process chamber to etch the silicon oxide layer and form etching trenches in the silicon oxide layer. The upper electrode power signal and the lower electrode power signal adopt a synchronous pulse mode, and the synchronous pulse mode is that the upper electrode power signal and the lower electrode power signal are synchronized. The first etching gas includes a first fluorocarbon gas, a byproduct removal gas, and a dilution gas. The first fluorocarbon gas includes C4F6, the byproduct removal gas includes O2, and the dilution gas includes Ar. The gas flow rate ratio of Ar, C4F6, and O2 in the first etching gas is in the range of (50-70):(1.5-3):

1.

2. The etching method for silicon oxide according to claim 1, characterized in that, In the step of etching the silicon oxide layer, when the upper electrode power signal and the lower electrode power signal are in the on cycle, the first carbon-fluorine gas etches the silicon oxide layer, and the by-product removal gas removes the by-products generated during etching; when the upper electrode power signal and the lower electrode power signal are in the off cycle, the by-products generated during etching are extracted.

3. The method of claim 1, wherein the silicon oxide is etched by the plasma. In the etching step of the silicon oxide layer, the process temperature used is 60℃-80℃.

4. The etching method for silicon oxide according to claim 3, characterized in that, During the etching step of the silicon oxide layer, the peak power range of the lower electrode power signal is 600-900W; and / or The peak power range of the upper electrode power signal is 300-750W.

5. The etching method for silicon oxide according to claim 4, characterized in that, The frequency range of the upper electrode power signal and the lower electrode power signal is 1000-2500Hz, and the pulse duty cycle range is 15-30%.

6. The etching method for silicon oxide according to claim 5, characterized in that, In the etching step of the silicon oxide layer, the chamber pressure range is 4-7 mT.

7. The etching method for silicon oxide according to claim 1, characterized in that, In the first etching gas: The O2 gas flow rate range is 4-10 sccm; Ar gas flow rate range is 250-450 sccm; The gas flow rate range for C4F6 is 10-20 sccm.

8. The method for etching silicon oxide according to claim 1, characterized in that, After etching the silicon oxide layer, the process further includes: The residual byproducts on the top and sidewalls of the etched trench are removed using a second etching gas, which includes a second fluorocarbon gas and a second byproduct removal gas.

9. The method for etching silicon oxide according to claim 8, characterized in that, The carbon-to-fluorine ratio of the second fluorocarbon gas is less than that of the first fluorocarbon gas; and / or The second byproduct gas removed includes O2.

10. The method for etching silicon oxide according to claim 9, characterized in that, The process parameters used for etching the silicon oxide layer using the second etching gas also include: The pressure range of the process chamber is 10-30 mT; The process temperature range is 60-80℃.

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