A peak time detection circuit in a front end sense circuit

Abstract

This invention discloses a peak time detection circuit in a front-end readout circuit, relating to the fields of nuclear electronics and particle radiation detection front-end readout circuit systems. The circuit includes a peak sampling and holding circuit and a comparator, which measures the output voltage V of the peak sampling and holding circuit. e The input voltage V of the peak time detection circuit i A comparator is used for comparison when the input voltage V i When the comparator reaches its peak and begins to decline, the input voltage V of the comparator... e The input voltage V of the peak time detection circuit is greater than the peak time detection circuit. i The comparator's output voltage flips, outputting a high-level trigger signal OUT. The peak time of the input voltage is obtained by detecting this high-level trigger signal OUT. This circuit has a simple structure, reduces circuit area and power consumption, fundamentally eliminates measurement errors caused by VTH, and eliminates peak time detection errors caused by input voltage amplitude, reducing the impact of time travel.

Description

Technical Field

[0001] This invention relates to the field of nuclear electronics and particle radiation detection front-end readout circuit systems, and particularly to a peak time detection circuit in a front-end readout circuit. Background Technology

[0002] The existing reference "ReadoutASIC for 3DPosition-SensitiveDetectors" discloses a circuit for peak time detection, such as... Figure 1 As shown, the circuit mainly includes: an operational amplifier, a PMOS transistor M1, and a potential-holding capacitor C. H It consists of a reset switch and a comparator. Taking the peak time of detecting an upward input signal as an example, its specific working principle is as follows: when the input signal V... i During the rising phase, the op-amp's output voltage V g The decrease causes the PMOS transistor M1 to turn on, thereby affecting the holding capacitor C. H Charging begins; as the input signal reaches its peak and begins to gradually decrease, the op-amp output voltage rises, causing transistor M1 to turn off and stopping the capacitor from charging. Because this circuit lacks a bleeder circuit, V... e The peak value of the input signal is maintained, so when the input signal reaches its peak and begins to decrease, that is, when V... e The potential is higher than V i Due to the high gain of the operational amplifier, the output voltage V of this circuit is... g It will rapidly increase to VDD, therefore, by setting an appropriate threshold VTH and V g By comparison, its output can effectively reflect the peak time information. Among them, VDD-V THh ≤VTH≤VDD,V THh is the threshold voltage of transistor M1.

[0003] Although the circuit achieves peak time detection, it still has the following drawbacks:

[0004] To eliminate inter-channel inconsistencies caused by process technology and other factors, the threshold voltage VTH requires an on-chip DAC for enhancement, which increases circuit design complexity. Besides occupying a larger area, it also consumes more power and introduces noise, hindering the design of low-noise, low-power front-end readout circuits. Furthermore, the theoretical range of VTH is VDD-V. THhTo prevent false triggering and due to the inherent requirements of the circuit, the lower limit of VTH is typically higher than its theoretical value in practical applications. For example, with a 1.8V power supply, it is generally taken as 1.65V ≤ VTH ≤ 1.8V (VDD), which is basically near VDD. However, for the DAC circuit itself, its linearity is relatively poor when the output is close to VDD, causing the output VTH to deviate from the theoretical value. In addition, considering the effects of comparator kickback noise, its output voltage jumps affect the DAC, causing fluctuations and thus leading to greater errors.

[0005] The accuracy of peak time (tp) measurement depends on the set threshold voltage VTH. Figure 2 The figure shows the relationship between the detected peak time tp and the threshold voltage VTH. It can be seen that the higher the threshold voltage, the longer the detected peak time, resulting in a larger measurement error. Although this error can be reduced by lowering the threshold voltage, noise can cause false triggering, meaning the comparator will still output a high potential even without an input signal. Therefore, the minimum value of the threshold voltage is limited.

[0006] The amplitude of the input signal also has a certain impact on peak time detection. For example... Figure 3 As shown, we can see the op-amp output V corresponding to two input signals with different amplitudes. g1 and V g2 Even with the same set threshold, the trigger signal output by the comparator, i.e., the detected peak time, can vary. This error is usually referred to as time walk. Therefore, for input voltages with the same peak time but different amplitudes, the detected peak time will differ. Summary of the Invention

[0007] This invention provides a peak time detection circuit in a front-end readout circuit, which can solve the problems existing in the background art.

[0008] This invention provides a peak time detection circuit in a front-end readout circuit, comprising: a peak sampling and holding circuit and a comparator;

[0009] The signal input terminal of the peak time detection circuit is connected to the input terminal of the peak sampling and holding circuit and the inverting input terminal of the comparator, respectively. The output terminal of the peak sampling and holding circuit is connected to the non-inverting input terminal of the comparator. The output terminal of the comparator is the signal output terminal of the peak time detection circuit.

[0010] Among them, the output voltage V of the peak sample-and-hold circuit e and the input voltage V of the peak time detection circuiti A comparator is used for comparison when the input voltage V i When the comparator reaches its peak and begins to decline, the input voltage V of the comparator... e The peak time detection circuit has an input voltage V greater than that of the peak time detection circuit. i The comparator's output voltage flips, outputting a high-level trigger signal OUT. The peak time of the input voltage is obtained by detecting the high-level trigger signal OUT.

[0011] Furthermore, the peak sample-and-hold circuit includes: an operational amplifier, a PMOS transistor, a holding capacitor, and a reset switch;

[0012] The inverting input of the operational amplifier serves as the input of the peak sample-and-hold circuit.

[0013] The non-inverting input terminal of the operational amplifier is connected to one end of the reset switch and one end of the holding capacitor, and the other end of the reset switch and the other end of the holding capacitor are both grounded.

[0014] The output terminal of the operational amplifier is connected to the gate of the PMOS transistor, the source of the PMOS transistor is connected to the standard voltage VDD, and the drain of the PMOS transistor is connected to the other end of the holding capacitor.

[0015] Furthermore, when the input voltage V of the peak time detection circuit... i During the upward phase, V e <V i The output voltage V of the operational amplifier g The potential decreases, causing the PMOS transistor to turn on and charge the holding capacitor.

[0016] Furthermore, when the input voltage V of the peak time detection circuit... i When V reaches its peak and begins to decline, then e Maintain the peak voltage.

[0017] Furthermore, the comparator employs a high-speed, high-precision comparator based on a symmetrical transconductance amplifier structure.

[0018] This invention provides a peak time detection circuit in a front-end readout circuit, which has the following advantages compared with the prior art:

[0019] The peak time detection circuit provided in this invention eliminates the need for an on-chip DAC module to generate the threshold voltage VTH, simplifying the circuit and reducing circuit area and power consumption. Furthermore, by avoiding comparison with the absolute value of the threshold voltage VTH to obtain peak time information, the measurement error caused by VTH is fundamentally eliminated; that is, since the comparator no longer requires the threshold voltage VTH, this invention solves the problem of the influence of different threshold voltages on the detected peak time.

[0020] Furthermore, the peak time detection method provided in this embodiment of the invention detects the peak time by generating a trigger signal by comparing the peak voltage with the current input voltage. Because the current input voltage signal is compared with its own peak voltage, the peak time detection error caused by the input voltage amplitude is eliminated, and the influence of time travel is reduced. Attached Figure Description

[0021] Figure 1 The diagram shows the peak time detection circuit structure as disclosed in existing references;

[0022] Figure 2 This is a schematic diagram illustrating the effect of different threshold voltages on peak time in existing references;

[0023] Figure 3 This is a schematic diagram illustrating the effect of different input signal amplitudes on peak time, as shown in existing references.

[0024] Figure 4 This is a schematic diagram of the peak time detection circuit structure in a front-end readout circuit provided by an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram illustrating the peak time detection principle of a peak time detection circuit in a front-end readout circuit provided in an embodiment of the present invention.

[0026] Figure 6 This is a schematic diagram illustrating a specific implementation of peak time detection in a front-end readout circuit according to an embodiment of the present invention.

[0027] Figure 7 A schematic diagram illustrating a specific implementation of a comparator in a front-end readout circuit for detecting peak time, provided in an embodiment of the present invention.

[0028] Figure 8 The simulation results of the peak time detection circuit provided in the embodiments of the present invention and the peak time detection circuit in the existing references are shown below.

[0029] Figure 9 A comparison diagram of the peak time detection results between the peak time detection circuit provided in the embodiment of the present invention and the peak time detection circuit in the existing references. Detailed Implementation

[0030] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0031] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0033] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0035] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0036] See Figure 4 This invention provides a peak time detection circuit in a front-end readout circuit, which includes a peak sample-and-hold (PDH) circuit and a comparator. The PDH module mainly consists of... Figure 1 It consists of an operational amplifier, a PMOS transistor, a holding capacitor, and a reset switch.

[0037] See Figure 6 The peak time detection circuit in the front-end readout circuit provided in this embodiment of the invention includes: an operational amplifier, a PMOS transistor, a holding capacitor, a reset switch, and a high-speed, high-precision comparator. To simplify the circuit and reduce power consumption, and to address the peak time error caused by the threshold voltage VTH in the comparative design in the reference, this invention uses the current input voltage VTH. i and its peak voltage V e Direct comparison. During the rising phase of the input signal, V e <V i V g The decrease in potential causes transistor M1 to conduct and begin charging the holding capacitor. Since there is no discharge path, when the input signal reaches its peak and begins to decline, V... e It will remain at its peak voltage. At this point, the relationship between the two input voltages of the comparator flips, becoming V. e >V i Because a high-speed, high-precision comparator is used, the difference between the two can be quickly identified, and the comparator output level flips. By detecting the time of this level transition, the peak time can be accurately obtained.

[0038] See Figure 5 The main principle of the peak time detection circuit in the front-end readout circuit provided in this embodiment of the invention is: to detect the peak time of the PDH output voltage V. e (Peak protection voltage) and input voltage V i A comparator is used for comparison. When the input signal reaches its peak and begins to decline, the comparator's input terminal V... e It will be greater than V i Its output voltage flips, quickly outputting a high-level trigger signal. By detecting this trigger signal, the peak time of the input voltage can be obtained.

[0039] See Figure 7 The high-speed, high-precision comparator in the front-end readout circuit provided in this embodiment of the invention adopts a high-speed, high-precision comparator based on a symmetrical transconductance amplifier structure. Specifically, the structure consists of source-connected MOS transistors M1 and M... 2, The drain of MOSFET M1 is connected to the drain of MOSFET M3. The source of MOSFET M3 is grounded. The gate and drain of MOSFET M3 are connected. The gate of MOSFET M3 is also connected to the gate of MOSFET M5. The source of MOSFET M5 is grounded. The drain of MOSFET M5 is connected to the drain of MOSFET M7. The gate of MOSFET M7 is connected to the gate of MOSFET M8. The sources of MOSFET M7 and MOSFET M9 are connected together and connected to the power supply VDD. The gate of MOSFET M9 is connected to a standard voltage V. B The drain of MOSFET M9 is connected to the source of MOSFET M1; the drain of MOSFET M2 is connected to the drain of MOSFET M4, the source of MOSFET M4 is grounded, the gate and drain of MOSFET M4 are connected, the gate of MOSFET M4 is also connected to the gate of MOSFET M6, the source of MOSFET M6 is grounded, the drain of MOSFET M6 is connected to the drain of MOSFET M8, the gate and drain of MOSFET M8 are connected, the source of MOSFET M8 and the source of MOSFET M9 are connected, and together they are connected to the power supply VDD; among them, the gate of MOSFET M1 is connected to the positive terminal of the input, the gate of MOSFET M2 is connected to the negative terminal of the input, and the drain of MOSFET M5 is also connected to the output terminal.

[0040] The present invention provides a peak time detection circuit structure: the peak-hold voltage output after the input voltage passes through the peak sampling and holding circuit is compared with the input voltage itself. Once the input voltage reaches its peak value and begins to decrease, its peak-hold voltage will be greater than the input voltage, the comparator will be triggered and output a high level, and the peak time of the input voltage can be obtained by detecting the trigger time of the comparator.

[0041] This invention provides an implementation of a peak-time detection circuit: It employs an operational amplifier, a PMOS transistor, a holding capacitor, and a reset switch to achieve and output a peak-hold voltage. The comparison between the peak-hold voltage and the input voltage is implemented using a comparator with high-speed, low-delay characteristics. When the input voltage reaches its peak value and begins to decrease, the high-speed comparator quickly outputs a trigger signal, thereby achieving the peak-time detection function. In other words, by using a high-speed comparator, the delay between the detected peak-time and the actual peak-time of the circuit can be further reduced, thus minimizing errors.

[0042] Comparative analysis example:

[0043] Figure 8 The figures show the simulation results of peak time detection for the two circuits in this invention and the references under the same input signal. It is clear from the figures that, for the same input, the peak time delay represented by OUT in this invention is smaller than the actual peak time, and therefore the error is smaller.

[0044] Figure 9 This figure illustrates the error between the trigger peak time and the actual peak time of the input signal in this invention and the references under different input signals and different threshold values ​​VTH. First, the figure clearly shows that under different conditions, the error between the peak time detected by this invention and the actual value is much smaller than that in the references. (Using input V...) i Taking the case of VTH = 1.7V and V=150mV as an example, compared with the reference, the output error of the present invention is reduced by 60%, and the optimization effect is quite obvious. Secondly, since the present invention simplifies the circuit and no longer uses a DAC module, it solves the problem of interference of the threshold voltage VTH on the output error. Finally, the time walk phenomenon caused by different input signal amplitudes is analyzed. It can be seen that the comparative technique is greatly affected by the change of input signal amplitude. Taking VTH = 1.7V as an example, its fluctuation range is 1500ns. In contrast, the output error of the present invention is between 450-750ns under different input conditions, with smaller fluctuations, which significantly reduces the impact of time walk on peak time measurement.

[0045] Experimental results show that the peak time error output by the peak time detection circuit provided in this embodiment is significantly smaller than that output by the peak time detection circuit in the reference. Furthermore, this error fluctuates less with the change in the amplitude of the input signal. After correction, an accurate peak time can be obtained, and the optimization effect is obvious.

[0046] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A peak time detection circuit in a front-end readout circuit, characterized in that, include: Peak sample-and-hold circuit and comparator; The signal input terminal of the peak time detection circuit is connected to the input terminal of the peak sampling and holding circuit and the negative input terminal of the comparator, respectively. The output terminal of the peak sampling and holding circuit is connected to the positive input terminal of the comparator. The output terminal of the comparator is the signal output terminal of the peak time detection circuit. Among them, the output voltage V of the peak sample-and-hold circuit e and the input voltage V of the peak time detection circuit i A comparator is used for comparison when the input voltage V i When the comparator reaches its peak and begins to decline, the input voltage V of the comparator... e The peak time detection circuit has an input voltage V greater than that of the peak time detection circuit. i The comparator's output voltage flips, outputting a high-level trigger signal OUT. The peak time of the input voltage is obtained by detecting the high-level trigger signal OUT.

2. The peak time detection circuit in the front-end readout circuit as described in claim 1, characterized in that, The peak sample-and-hold circuit includes: an operational amplifier, a PMOS transistor, a holding capacitor, and a reset switch; The inverting input of the operational amplifier serves as the input of the peak sample-and-hold circuit. The non-inverting input terminal of the operational amplifier is connected to one end of the reset switch and one end of the holding capacitor, and the other end of the reset switch and the other end of the holding capacitor are both grounded. The output terminal of the operational amplifier is connected to the gate of the PMOS transistor, the source of the PMOS transistor is connected to the standard voltage VDD, and the drain of the PMOS transistor is connected to one end of the holding capacitor.

3. The peak time detection circuit in the front-end readout circuit as described in claim 2, characterized in that, Also includes: When the input voltage V of the peak time detection circuit i During the upward phase, V e <V i The output voltage V of the operational amplifier g The potential decreases, causing the PMOS transistor to turn on and charge the holding capacitor.

4. The peak time detection circuit in the front-end readout circuit as described in claim 2, characterized in that, Also includes: When the input voltage V of the peak time detection circuit i When V reaches its peak and begins to decline, then e Maintain the peak voltage.

5. The peak time detection circuit in the front-end readout circuit as described in claim 1, characterized in that, The comparator is a high-speed, high-precision comparator based on a symmetrical transconductance amplifier structure, and its structure specifically includes: MOSFETs M1 and M2 are connected at their sources; The drain of MOSFET M1 is connected to the drain of MOSFET M3. The source of MOSFET M3 is grounded. The gate and drain of MOSFET M3 are connected. The gate of MOSFET M3 is also connected to the gate of MOSFET M5. The source of MOSFET M5 is grounded. The drain of MOSFET M5 is connected to the drain of MOSFET M7. The gate of MOSFET M7 is connected to the gate of MOSFET M8. The source of MOSFET M7 is connected to the source of MOSFET M9. The gate of MOSFET M9 is connected to a standard voltage V. B The drain of MOSFET M9 is connected to the source of MOSFET M1; The drain of MOSFET M2 is connected to the drain of MOSFET M4, the source of MOSFET M4 is grounded, the gate and drain of MOSFET M4 are connected, the gate of MOSFET M4 is also connected to the gate of MOSFET M6, the source of MOSFET M6 is grounded, the drain of MOSFET M6 is connected to the drain of MOSFET M8, the gate and drain of MOSFET M8 are connected, and the source of MOSFET M8 is connected to the source of MOSFET M9. Among them, the gate of MOSFET M1 is connected to the positive terminal of the input, the gate of MOSFET M2 is connected to the negative terminal of the input, and the drain of MOSFET M5 is also connected to the output terminal.

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