Semiconductor device and method of manufacturing the same
By designing a multi-planar side structure for the contact plug in the semiconductor device and forming grooves through wet etching, the problem of contact performance degradation during miniaturization was solved, resulting in reduced contact resistance and improved read/write speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-05-15
- Publication Date
- 2026-06-23
AI Technical Summary
During the miniaturization process, the contact performance of semiconductor devices deteriorates, especially the contact resistance increases, which affects the read and write speed.
By forming multiple contact plugs within the substrate, and setting a first side and a second side located on different planes on the bottom of the contact plugs and the side adjacent to the active region, the contact area is increased. Wet etching is used to form grooves to expose more sides and reduce contact resistance.
It improves the contact performance of semiconductor devices and enhances read and write speeds.
Smart Images
Figure CN116744674B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] As electronic products become increasingly miniaturized, the design of semiconductor memory devices also needs to meet the requirements of high aggregation and high density. For DRAM (Dynamic Random Access Memory) with recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structure.
[0003] Generally, DRAM with a recessed gate structure consists of a large number of memory cells arranged in an array to store data. Each memory cell may contain a transistor and a charge storage device to receive voltage signals from the bit line and word line. Depending on actual needs, the density of memory cells in the array needs to be continuously increased, leading to the continuous miniaturization of semiconductor devices and resulting in deterioration of contact performance.
[0004] Therefore, a new semiconductor device structure is needed to at least solve the above problems. Summary of the Invention
[0005] The main objective of this invention is to provide a semiconductor device and its manufacturing method, which reduces contact resistance and improves the contact performance of the semiconductor device.
[0006] The present invention provides a semiconductor device comprising: a substrate; an isolation region located within the substrate and defining a plurality of active regions; a plurality of bit lines located on the substrate; and a plurality of contact plugs located between the plurality of bit lines, wherein each contact plug includes a bottom located within the active regions of the substrate, and the sides of the bottom adjacent to the active regions include at least a first side and a second side located on different planes.
[0007] Optionally, the first side and / or the second side are generally planar.
[0008] Optionally, the first side and the second side form a preset angle.
[0009] Optionally, the first side and the second side intersect on the surface of the isolation zone.
[0010] Optionally, the first side and the second side intersect within the isolation zone.
[0011] Optionally, the first side and the second side intersect within the active region.
[0012] Optionally, the bottom of the contact plug and the side adjacent to the active region expose the isolation region.
[0013] Optionally, it may also include a third side extending along the boundary of the exposed isolation zone.
[0014] This invention provides a semiconductor device, comprising: a substrate; an isolation region located within the substrate and defining a plurality of active regions; a plurality of bit lines located on the substrate; a plurality of grooves located between the plurality of bit lines, the bottom surface of the plurality of grooves being lower than the top surface of the active regions and exposing a portion of the active regions, wherein the sides of the grooves adjacent to the active regions include at least a first side and a second side located on different planes; and a plurality of contact plugs located between the plurality of bit lines, wherein a portion of the contact plug is located within the groove and in physical contact with the active regions.
[0015] Optionally, the first side and / or the second side are generally planar.
[0016] Optionally, the first side and the second side form a preset angle.
[0017] Optionally, the first side and the second side intersect on the surface of the isolation zone.
[0018] Optionally, the first side and the second side intersect within the isolation zone.
[0019] Optionally, the first side and the second side intersect within the active region.
[0020] Optionally, the side of the groove adjacent to the active region exposes the isolation region.
[0021] Optionally, it may also include a third side extending along the boundary of the exposed isolation zone.
[0022] This invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming an isolation region within the substrate to define a plurality of active regions within the substrate; forming a plurality of bit lines on the substrate; etching the substrate between the plurality of bit lines to form a plurality of grooves, the bottom surface of the grooves being lower than the top surface of the active regions, the sides of the grooves adjacent to the active regions including at least a first side and a second side located on different planes, the first side and the second side forming a predetermined angle; and forming a plurality of contact plugs within the plurality of grooves, the contact plugs being in physical contact with the active regions within the grooves.
[0023] Optionally, etching the substrate between the multiple bit lines to form multiple grooves includes: wet etching the substrate between the multiple bit lines using a mixed solution of ammonium hydroxide and water to form the multiple grooves.
[0024] Optionally, the mixing ratio of the ammonium hydroxide and water solution is 1:10 to 1:30.
[0025] By forming multiple sides located on different planes on the side adjacent to the active region, the contact resistance is reduced, the contact performance of the semiconductor device is improved, and thus the read / write speed of the semiconductor device is increased. Attached Figure Description
[0026] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.
[0027] Figure 1 This is a top view of a semiconductor device according to an exemplary embodiment of this application;
[0028] Figures 2 to 9 For manufacturing according to this application Figure 1 A schematic cross-sectional view of an exemplary manufacturing process for the semiconductor device shown;
[0029] Figure 10 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of this application;
[0030] Figure 11 This is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of this application;
[0031] The accompanying figure is labeled as follows:
[0032] 10 Substrates
[0033] 12 Active regions
[0034] 14. Quarantine Zone
[0035] 16 Insulation layer
[0036] 102 Gate insulating layer
[0037] 104 conductive layer
[0038] 106 Insulating Cover Layer
[0039] 202 Semiconductor Layer
[0040] 204 metal layer
[0041] 206 Hard Mask Layer
[0042] 22 First Insulation Layer
[0043] 24 Second Insulation Layer
[0044] 32 Barrier Layer
[0045] 34 Contact plug
[0046] 34a Semiconductor layer
[0047] 34b metal layer
[0048] 34-B Bottom
[0049] WL lettering
[0050] BL bitline
[0051] AA First section direction
[0052] BB Second Section Direction
[0053] D1 First Direction
[0054] D2 Second Direction
[0055] D3 third direction
[0056] BC Position Line Groove
[0057] SC1, SC2, SC3 grooves
[0058] SC1a, SC2a, SC3a First side
[0059] SC1b, SC2b, SC2b Second side
[0060] SC2c Third Side Detailed Implementation
[0061] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0062] Figure 1 This is a top view of a semiconductor device according to an exemplary embodiment of this application. For the sake of simplicity, Figure 1 The floor plan in the document omits some structural elements; Figures 2 to 9 The middle section is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of this application. The left side is roughly along... Figure 1 A schematic diagram of the cross-section along the first section direction AA; the right side is roughly along... Figure 1 A schematic diagram of the cross-section in the second section direction BB; Figure 10 and Figure 11 For the general outline of semiconductor devices according to other embodiments of this application Figure 1 A cross-sectional diagram of the first section direction AA. The first section direction AA is approximately parallel to the second direction D2, and the second section direction BB is approximately parallel to the first direction D1.
[0063] refer to Figure 1 and Figure 9 , Figure 9 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of this application. The semiconductor device may include a substrate 10, an isolation region 14, an active region 12, bit lines BL, and contact plugs 34. The isolation region 14 is located within the substrate 10 and defines multiple active regions 12 within the substrate 10. There may be multiple bit lines BL located on the substrate 10. There may be multiple contact plugs 34 located between the multiple bit lines BL, and each contact plug 34 includes a bottom 34-B located within the active region 12 of the substrate 10. The sides of the bottom 34-B adjacent to the active region 12 include at least a first side SC1a and a second side SC1b located on different planes.
[0064] Figure 8 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of this application, with reference to... Figure 8 The semiconductor device may further include a plurality of recesses SC1, which are respectively located between a plurality of bit lines BL. The bottom surface of the plurality of recesses SC1 is lower than the top surface of the active region 12 and exposes a portion of the active region 12. The sides of the recesses SC1 adjacent to the active region 12 include at least a first side SC1a and a second side SC1b located on different planes. According to an embodiment of the present application, a plurality of contact plugs 34 located between the plurality of bit lines BL are respectively partially located within the recesses SC1 and in physical contact with the active region 12. In particular, the bottoms 34-B of the plurality of contact plugs 34 are respectively located within the recesses SC1 and in physical contact with the active region 12.
[0065] When the bottom 34-B of the contact plug 34 fills the groove SC1 and is in full contact with the active region 12, the first side SC1a of the bottom 34-B of the contact plug 34 adjacent to the active region 12 is the first side SC1a of the groove SC1 adjacent to the active region 12, and the second side SC1b of the bottom 34-B of the contact plug 34 adjacent to the active region 12 is the second side SC1b of the groove SC1 adjacent to the active region 12. The first side SC1a and the second side SC1b described in the following embodiments can refer to either the first side SC1a and the second side SC1b of the bottom 34-B of the contact plug 34 adjacent to the active region 12, or the first side SC1a and the second side SC1b of the groove SC1 adjacent to the active region 12.
[0066] By setting a first side SC1a and a second side SC1b located on different planes on the side adjacent to the active region 12, the contact area with the active region 12 is increased, the contact resistance is reduced, and the contact performance of the semiconductor device is improved, which is beneficial to improving the read and write speed of the device.
[0067] refer to Figure 1 Multiple active regions 12 can be parallel to each other and can extend along a first direction D1. The multiple active regions 12 can be arranged in an array along a second direction D2 and a third direction D3. The second direction D2 forms a certain angle with the first direction D1, such as 30° to 75° or other angles. The third direction D3 is perpendicular to the second direction D2. According to an embodiment of this application, multiple bit lines BL can extend along the third direction D3 and be arranged parallel to the second direction D2.
[0068] The substrate 10 may be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The material of the isolation region 14 may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorosilica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but is not limited thereto.
[0069] refer to Figure 1 , Figure 8 and Figure 9 According to one embodiment of this application, the semiconductor device may further include multiple word lines (WL). (See reference...) Figure 1 Multiple letter lines WL can extend along the second direction D2 and be arranged parallel to the third direction D3.
[0070] refer to Figure 8 and 9 According to one embodiment of this application, the semiconductor device may further include an insulating layer 16 located above the substrate 10. Multiple word lines WL pass through the insulating layer 16 and extend into the substrate 10, cutting through the isolation region 14 and the active region 12, and are located within word line trenches. The word lines WL may include a conductive layer 104 located at the lower part of the word line trench, an insulating capping layer 106 located at the upper part of the word line trench, and a gate insulating layer 102 located between the conductive layer 104, the insulating capping layer 106, and the substrate 10. The conductive layer 104 may include a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), a work function metal, or a compound, alloy, and / or composite layer of the aforementioned metallic materials, but is not limited thereto. The insulating layer 16, the insulating cap layer 106, and the gate insulating layer 102 may each comprise a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), a high-k dielectric material, or a combination of the above materials, but are not limited thereto. According to one embodiment of this application, the insulating layer 16 and the insulating cap layer 106 may comprise the same material, such as silicon nitride (SiN).
[0071] refer to Figure 8 and 9 According to one embodiment of this application, the bit line BL may include a semiconductor layer 202, a metal layer 204, and a hard mask layer 206 stacked sequentially. The semiconductor layer 202 may be made of polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The metal layer 204 may be made of aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum (TiAl) alloy, or other suitable low-resistance metal materials. The hard mask layer 206 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. In one embodiment, an interface layer (not shown in the figure) may be included between the semiconductor layer 202 and the metal layer 204, for example, it may be a single-layer or multi-layer structure layer composed of titanium (Ti), tungsten silicide (WSi), tungsten nitride (WN), and / or other metal silicides or metal nitrides, but is not limited thereto.
[0072] refer to Figure 8 and 9According to one embodiment of this application, the device may further include a first insulating layer 22 and a second insulating layer 24 located outside the bit line BL. The first insulating layer 22 covers the sidewall of the bit line and the surface of the bit line groove BC, and the second insulating layer 24 covers the surface of the first insulating layer 22. The first insulating layer 22 may completely fill the bit line groove BC, or the first and second insulating layers may jointly fill the bit line groove BC. In one embodiment, the device may include only the first insulating layer 22 or may also include a third and fourth insulating layer, etc. Correspondingly, the bit line groove BC may be filled only by the first insulating layer 22 or by the first to third (and fourth) insulating layers, but is not limited thereto. The first insulating layer 22 and the second insulating layer 24 may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto. According to one embodiment of this application, the first insulating layer 22 may include silicon nitride, and the second insulating layer 24 may include silicon oxide.
[0073] refer to Figure 9 According to one embodiment of this application, the contact plug 34 may include a semiconductor layer 34a, a barrier layer 32, and a metal layer 34b. The semiconductor layer 34a is in physical contact with the active region 12. The barrier layer 32 covers the top surfaces of the semiconductor layer 34a, the bit line BL, and the first and second insulating layers. The metal layer 34b is located above the barrier layer 32 and fills the area between the bit lines BL. The portion of the semiconductor layer 34a located below the insulating layer 16 is the bottom 34-B of the contact plug 34. The bottom 34-B is in physical contact with the active region 12. The sides of the bottom 34-B adjacent to the active region 12 include at least a first side SC1a and a second side SC1b located on different planes. The first side SC1a and the second side SC1b may be located directly below the bit line BL, and the first side SC1a and the second side SC1b are close to each other in the direction of proximity to the isolation region 14. In one embodiment, the bottom 34-B may also include a third side or more sides that are not on the same plane as the first side and the second side. By using the first side SC1a and the second side SC1b, the contact area between the contact plug 34 and the active region 12 is increased, the contact resistance between the contact plug 34 and the active region 12 is reduced, and the contact performance of the semiconductor device is improved, thereby improving the read / write speed of the semiconductor device. The material of the semiconductor layer 34a may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The material of the barrier layer 32 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or compounds, alloys, and / or composite layers of the aforementioned metal materials. The material of the metal layer 34b may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto.
[0074] refer to Figure 8 , Figure 9 , Figure 10 and Figure 11 According to one embodiment of this application, by controlling the process parameters (e.g., etchant concentration and etching time) for forming the first and second side surfaces, the first and / or second side surfaces can be made substantially planar, and / or the first and second side surfaces can form a preset angle, such as 30° to 75°. (Reference) Figure 8 and 9 The first side SC1a and the second side SC1b may intersect on the surface of the isolation zone 14; Reference Figure 10 The first side SC2a and the second side SC2b can intersect within the isolation zone 14; Reference Figure 11 According to one embodiment of this application, the first side SC3a and the second side SC3b may intersect within the active region 12.
[0075] refer to Figure 10 According to one embodiment of this application, when the first side SC2a and the second side SC2b intersect within the isolation region 14, the side of the bottom 34-B of the contact plug 34 adjacent to the active region 12 can expose the isolation region 14. According to one embodiment of this application, when the isolation region 14 is exposed, the side of the bottom 34-B of the contact plug 34 adjacent to the active region 12 may further include a third side SC2c extending along the boundary of the exposed isolation region 14.
[0076] By forming multiple sides located on different planes on the side adjacent to the active region 12, the contact area with the active region 12 can be increased, the contact resistance can be reduced, and the contact performance of the semiconductor device can be improved, thereby increasing the read and write speed of the semiconductor device.
[0077] According to one embodiment of this application, the active region 12 may further include a heavily doped region (not shown in the figure) located in its upper half for forming an ohmic contact with the bit line BL. According to one embodiment of this application, the active region 12 may have doped regions of different concentrations in its upper half that is in physical contact with the bit line BL and in its upper half that is in physical contact with the contact plug 34.
[0078] To enable those skilled in the art to understand and implement the semiconductor device of this application, the manufacturing method of the semiconductor device of this application will be further described below.
[0079] refer to Figures 2 to 9 This is a schematic diagram of a semiconductor device manufacturing method according to an embodiment of this application.
[0080] refer to Figure 2First, a substrate 10 is provided, which may be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. Second, an isolation region 14 is formed within the substrate 10, and a plurality of active regions 12 are defined within the substrate 10 by the isolation region 14. The plurality of active regions 12 extend along a first direction D1 and are arranged in an array along a second direction D2 and a third direction D3. The material of the isolation region 14 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorosilica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or a combination of the above materials, but is not limited thereto.
[0081] After forming the isolation region 14 and the active region 12, an insulating layer 16 can be formed on the substrate 10, and then multiple word lines WL can be formed. The multiple word lines WL extend through the insulating layer 16 toward the substrate 10 and cut through the active region 12 and the isolation region 14. The multiple word lines WL extend along the second direction D2 and are arranged parallel to the third direction D3. After forming the insulating layer 16, word line trenches extending along the second direction D2 can be formed by etching the insulating layer 16, the active region 12 and the isolation region 14. A gate insulating layer 102 is formed covering the sidewalls and bottom surface of the word line trenches. Subsequently, a conductive layer 104 is formed in the word line trenches, and an insulating capping layer 106 is formed above the conductive layer 104. The conductive layer 104 may include a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), work function metals, or compounds, alloys and / or composite layers of the aforementioned metallic materials, but is not limited thereto. The insulating layer 16, the insulating cap layer 106, and the gate insulating layer 102 may each comprise a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), a high-k dielectric material, or a combination of the above materials, but are not limited thereto. According to one embodiment of this application, the insulating layer 16 and the insulating cap layer 106 may comprise the same material, such as silicon nitride (SiN).
[0082] refer to Figure 3After forming the word line WL, a bit line groove BC can be formed on the substrate 10. A patterned hard mask layer can be formed on the substrate 10 first. Using the patterned hard mask layer as a mask, the center positions of each active region 12 are etched to form the bit line groove BC. The bottom surface of the bit line groove BC is lower than the top surface of the active region 12. During the formation of the bit line groove BC, a portion of the isolation region 14 near the center position of the active region 12 may also be etched away, forming the sidewalls of the isolation region 14. The sidewalls of the bit line groove BC can include the sidewalls of the isolation region 14 and the sidewalls of the active region 12 exposed due to etching.
[0083] refer to Figure 4 After forming the bit line groove BC, bit lines BL are formed on the substrate 10. Multiple bit lines BL extend along a third direction D3 and are arranged parallel to each other along a second direction D2. A semiconductor material layer can be formed on the substrate 10 first, which can fill the bit line groove BC. Then, a metal material layer and a hard mask material layer are formed sequentially on the semiconductor material layer. The semiconductor material layer, metal material layer, and hard mask material layer are then patterned, and parts of the semiconductor material layer, metal layer, and hard mask material layer are removed to form multiple bit lines BL on the substrate 10. The bit lines BL are physically contacted with the middle position of the active region 12 through the bit line groove BC to form an electrical connection. The other parts of the bit lines BL are separated from the active region 12 and electrically isolated by the insulating layer 16. The material of the semiconductor layer 202 may include polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The material of the metal layer 204 may include aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum (TiAl) alloy, or other suitable low-resistance metal materials. The hard mask layer 206 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto.
[0084] refer to Figure 5 and 6After forming bit lines BL, a first insulating layer 22 and a second insulating layer 24 are sequentially formed on the sidewalls of each bit line BL, with the first insulating layer 22 filling the bit line groove BC, or the first insulating layer 22 and the second insulating layer 24 jointly filling the bit line groove BC. According to one embodiment of this application, a first insulating material layer can be formed first, a portion of the first insulating material layer can be removed to form the first insulating layer 22, then a second insulating material layer can be formed, and then a portion of the second insulating layer can be removed to form the second insulating layer 24. According to one embodiment of this application, a first insulating material layer and a second insulating material layer can be formed sequentially, and then portions of the first and second insulating material layers can be removed to form the first insulating material layer and the second insulating layer. The first insulating layer 22 and the second insulating layer 24 may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto. According to one embodiment of this application, the first insulating layer 22 may include silicon nitride, and the second insulating layer 24 may include silicon oxide.
[0085] refer to Figure 7 and 8 Next, a groove SC1 is formed on the substrate 10 between the bit lines BL. The insulating layer 16 and a portion of the substrate 10 between the bit lines BL are removed to at least expose the active region 12, forming the groove SC1, such that the sides of the groove SC1 adjacent to the active region 12 include at least a first side SC1a and a second side SC1b located on different planes. The insulating layer 16 and a portion of the substrate 10 between the bit lines BL can be removed using a wet etching process, in which a mixture of ammonium hydroxide and water can be used as the etchant.
[0086] According to one embodiment of this application, the mixing ratio of ammonium hydroxide and water in the etchant can be controlled to be 1:10 to 1:30. According to another embodiment of this application, the mixing ratio of ammonium hydroxide and water in the etchant can be controlled to be 1:12, 1:15, 1:18, 1:20, 1:23, 1:26, 1:29, etc., but is not limited thereto. By controlling the mixing ratio of ammonium hydroxide and water in the etchant and the etching time, the first side and / or the second side can be made approximately planar, and / or the first side and the second side can form a preset angle, allowing the first side SC1a and the second side SC1b to intersect on the surface of the isolation area 14 (e.g., ...). Figure 8 and 9 As shown), or such that the first side SC2a and the second side SC2b intersect within the isolation zone 14 (as shown). Figure 10 The groove SC2 shown, or such that the first side SC3a and the second side SC3b intersect within the active region 12 (e.g., the groove SC2 shown), ... Figure 11 The groove SC3 shown.
[0087] refer to Figure 10 When the first side SC2a and the second side SC2b intersect within the isolation region 14, the isolation region 14 can be exposed on the side of the groove SC2 adjacent to the active region 12 based on the selectivity of the etchant. That is, the portion of the active region 12 between the groove SC2 (bottom 34-B of the contact plug 34) and the isolation region 14 is completely etched away, and the exposed side of the isolation region 14 can serve as the third side SC2c of the groove SC2.
[0088] refer to Figure 9 After forming the groove SC1, a contact plug 34 is formed. First, a semiconductor layer 34a is formed, filling the lower half of the region between the groove SC1 and the bit line BL. Then, a barrier layer 32 is formed, covering the top surface of the semiconductor layer 34a, the top surfaces of the first and second insulating layers, and the top surface of the bit line BL. Next, a metal layer 34b is formed above the barrier layer 32, filling the remaining region between the bit lines BL. Finally, a portion of the metal layer 34b and the barrier layer 32 outside the groove SC1 is removed, forming the contact plug 34 in physical contact with the active region 12. The material of the semiconductor layer 34a may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The material of the barrier layer 32 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or compounds, alloys, and / or composite layers of the aforementioned metal materials. The material of the metal layer 34b may include, but is not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials.
[0089] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application. When the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0090] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate.
[0091] It should be understood that the exemplary embodiments described herein can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. These embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art, and should not be construed as limiting the invention.
[0092] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; An isolation region is located within the substrate and defines a plurality of active regions; Multiple bit lines, the multiple bit lines being located on the substrate; A plurality of contact plugs are located between a plurality of bit lines. Each contact plug includes a semiconductor layer and a metal layer. The semiconductor layer includes a bottom located within the active region of the substrate. The bottom has at least a first side and a second side located on different planes adjacent to the active region. The first side and the second side extend toward the side closer to the isolation region. The width of the semiconductor layer at the intersection of the first side and the second side is greater than the width of the top surface of the semiconductor layer.
2. The semiconductor device according to claim 1, characterized in that, The first side and / or the second side are planar.
3. The semiconductor device according to claim 1, characterized in that, The first side and the second side form a preset angle.
4. The semiconductor device according to claim 3, characterized in that, The first side and the second side intersect on the surface of the isolation zone.
5. The semiconductor device according to claim 3, characterized in that, The first side and the second side intersect within the isolation zone.
6. The semiconductor device according to claim 3, characterized in that, The first side and the second side intersect within the active region.
7. The semiconductor device according to claim 5, characterized in that, The bottom of the contact plug and the side adjacent to the active region expose the isolation area.
8. The semiconductor device according to claim 7, characterized in that, Also includes: The third side extends along the boundary of the exposed isolation zone.
9. A semiconductor device, characterized in that, include: Substrate; An isolation region is located within the substrate and defines a plurality of active regions; Multiple bit lines, the multiple bit lines being located on the substrate; Multiple grooves are located between multiple bit lines. The bottom surface of the multiple grooves is lower than the top surface of the active region and exposes part of the active region. The side of the groove adjacent to the active region includes at least a first side and a second side located on different planes. The first side and the second side extend toward the side closer to the isolation region. The width of the groove at the intersection of the first side and the second side is greater than the width of the top surface of the groove. Multiple contact plugs are located between the multiple bit lines, and the contact plug portions are located within the grooves and in physical contact with the active region.
10. The semiconductor device according to claim 9, characterized in that, The first side and / or the second side are planar.
11. The semiconductor device according to claim 9, characterized in that, The first side and the second side form a preset angle.
12. The semiconductor device according to claim 11, characterized in that, The first side and the second side intersect on the surface of the isolation zone.
13. The semiconductor device according to claim 11, characterized in that, The first side and the second side intersect within the isolation zone.
14. The semiconductor device according to claim 11, characterized in that, The first side and the second side intersect within the active region.
15. The semiconductor device according to claim 13, characterized in that, The side of the groove adjacent to the active region exposes the isolation area.
16. The semiconductor device according to claim 15, characterized in that, Also includes: The third side extends along the boundary of the exposed isolation zone.
17. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; An isolation region is formed within the substrate to define a plurality of active regions within the substrate; Multiple bit lines are formed on the substrate; The substrate between the multiple bit lines is etched to form multiple grooves, the bottom surface of the grooves being lower than the top surface of the active region, and the side of the groove adjacent to the active region including at least a first side and a second side located on different planes, the first side and the second side forming a predetermined angle; the first side and the second side extend toward the side closer to the isolation region, and the width of the groove at the intersection of the first side and the second side is greater than the width of the top surface of the groove; Multiple contact plugs are formed in the multiple grooves, and the contact plugs are in physical contact with the active area in the grooves.
18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, Etching the substrate between the multiple bit lines to form multiple grooves, including: The substrate between the multiple bit lines is wet-etched using a mixed solution of ammonium hydroxide and water to form the multiple grooves.
19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The mixing ratio of the ammonium hydroxide and water solution is 1:10 to 1:
30.
20. A semiconductor device, characterized in that, include: Substrate; An isolation region is located within the substrate and defines a plurality of active regions; Multiple bit lines, the multiple bit lines being located on the substrate; Multiple contact plugs are located between the multiple bit lines, and each contact plug includes a bottom located within the active region of the substrate. The bottom and the side adjacent to the active region include at least a first side and a second side located in different planes. The bottom of the contact plug and the side adjacent to the active region expose the isolation region; the bottom of the contact plug and the side adjacent to the active region further includes a third side extending along the boundary of the exposed isolation region.
21. A semiconductor device, characterized in that, include: Substrate; An isolation region is located within the substrate and defines a plurality of active regions; Multiple bit lines, the multiple bit lines being located on the substrate; A plurality of contact plugs are located between the plurality of bit lines, and each contact plug includes a bottom located within the active region of the substrate. The bottom has at least a first side and a second side located on different planes on its adjacent side to the active region. The first side and the second side extend toward the side closer to the isolation region, and the extension surfaces of the first side and the second side intersect within the isolation region.
22. A semiconductor device, characterized in that, include: Substrate; An isolation region is located within the substrate and defines a plurality of active regions; Multiple bit lines, the multiple bit lines being located on the substrate; A plurality of contact plugs are located between the plurality of bit lines, and each contact plug includes a bottom located within the active region of the substrate. The bottom has at least a first side and a second side located on different planes on its adjacent side to the active region. The first side and the second side are located directly below the bit lines, and the first side and the second side extend toward the side of the isolation region closest to the bottom and are close to each other in the direction closest to the isolation region.