Signal transmission method, timing controller, source driving circuit and display system

Abstract

The embodiment of the application discloses a signal transmission method, a timing controller, a source driving circuit and a display system, and belongs to the technical field of multimedia. In the display system, the timing controller and the source driving circuit communicate through an ISP protocol, and a CTRL_L signal is added in row control data signals sent by the timing controller to the source driving circuit. Therefore, the source driving circuit can subsequently adjust information displayed on corresponding row sub-pixels according to the CTRL_L signal, so as to optimize the information displayed on the row sub-pixels. In other words, the embodiment of the application improves the standard ISP protocol, and the improved ISP protocol adds the CTRL_L signal corresponding to each row sub-pixel, so as to improve the display performance of the display system.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of multimedia, and in particular, to a signal transmission method, a timing controller, a source driving circuit and a display system. BACKGROUND

[0002] At present, a display system usually includes components such as a timing controller, a source driving circuit, a gate driving circuit and a display panel. The timing controller can transmit signals to the source driving circuit through an integrated stream protocol (ISP) to deliver each row of image data of each frame of image to the source driving circuit, and then display the frame of image on the display panel row by row through the source driving circuit. SUMMARY

[0003] Embodiments of the present application provide a signal transmission method, a timing controller, a source driving circuit and a display system, which can improve the performance of the display system. The technical solutions are as follows:

[0004] In one aspect, a signal transmission method is provided, which is applied to a timing controller, and the timing controller communicates with a source driving circuit through an integrated stream protocol (ISP); the method comprises the following steps:

[0005] In a current frame display period, the timing controller sends a first display signal to the source driving circuit.

[0006] The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals includes a first row control data signal and a first row image data signal, and the first row control data signal includes a row data configuration (CTRL_L) signal.

[0007] Optionally, the first row control data signal further includes a polarity inversion (POL) signal.

[0008] The timing controller sends the first display signal to the source driving circuit, comprising the following steps:

[0009] The timing controller sends the CTRL_L signal after sending the POL signal.

[0010] Optionally, before the timing controller sends the first display signal to the source driving circuit, the method further comprises the following steps:

[0011] The timing controller acquires a second display signal sent to the source driving circuit in a previous frame display period, the second display signal comprising a second frame control sub-signal, the second frame control sub-signal comprising a second frame data configuration CTRL_F signal, the second CTRL_F signal carrying a second packet length field;

[0012] The timing controller determines the length of the CTRL_L signal sent in the current frame display period based on the second packet length field.

[0013] Optionally, the first display signal further comprises a first frame control sub-signal, the first frame control sub-signal comprising a first CTRL_F signal, the first CTRL_F signal carrying a first packet length field, the first packet length field being used to indicate the length of the CTRL_L signal sent in a next frame display period.

[0014] Optionally, the second packet length field comprises at least one bit;

[0015] The timing controller determines the length of the CTRL_L signal sent in the current frame display period based on the second packet length field, comprising:

[0016] The timing controller determines the length of the CTRL_L signal sent in the current frame display period based on a bit value of the at least one bit included in the second packet length field from a mapping relationship between bit values and lengths.

[0017] Optionally, the method further comprises:

[0018] If the second packet length field indicates that the length of the CTRL_L signal sent in the current frame display period is 0, the timing controller sends a third display signal to the source driving circuit in the current frame display period;

[0019] The third display signal comprises a plurality of third display sub-signals, each of the third plurality of display sub-signals comprising a third row control data signal and a third row image data signal, the third row control data signal not comprising the CTRL_L signal.

[0020] In a second aspect, a signal transmission method is provided, the method being applied to a source driving circuit, the source driving circuit communicating with a timing controller through an integrated stream (ISP); the method comprising:

[0021] In a current frame display period, the source driving circuit receives a first display signal from the timing controller;

[0022] The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals includes a first row control data signal and a first row image data signal, and the first row control data signal includes a row data configuration CTRL_L signal.

[0023] Optionally, the first row control data signal further includes a polarity flip POL signal.

[0024] The source driving circuit receives a first display signal from the timing controller, including:

[0025] The source driving circuit receives the CTRL_L signal after receiving the POL signal.

[0026] Optionally, the method further includes:

[0027] The source driving circuit acquires a second display signal received in a previous frame display period, the second display signal includes a second frame control sub-signal, the second frame control sub-signal includes a second frame data configuration CTRL_F signal, and the second CTRL_F signal carries a second packet length field.

[0028] The source driving circuit determines the length of the CTRL_L signal received in the current frame display period based on the second packet length field.

[0029] Optionally, the first display signal further includes a first frame control sub-signal, the first frame control sub-signal includes a first frame data configuration CTRL_F signal, the first CTRL_F signal carries a first packet length field, and the first packet length field is used to indicate the length of the CTRL_L signal received in a next frame display period.

[0030] Optionally, the second packet length field includes at least one bit.

[0031] The source driving circuit determines the length of the CTRL_L signal received in the current frame display period based on the second packet length field, including:

[0032] The source driving circuit determines the length of the CTRL_L signal received in the current frame display period based on a bit value of at least one bit included in the second packet length field from a mapping relationship between bit values and lengths.

[0033] Optionally, the method further includes:

[0034] if the second packet length field indicates that the length of the CTRL_L signal received in the current frame display period is 0, the source driving circuit receives a third display signal from the timing controller in the current frame display period;

[0035] wherein the third display signal comprises a plurality of third display sub-signals, each of the third display sub-signals comprises a third row control data signal and a third row image data signal, and the third row control data signal does not comprise the CTRL_L signal.

[0036] In a third aspect, a timing controller is provided, which communicates with a source driving circuit through an integrated stream (ISP); the timing controller is configured to:

[0037] send a first display signal to the source driving circuit in a current frame display period;

[0038] wherein the first display signal comprises a plurality of first display sub-signals, each of the first display sub-signals comprises a first row control data signal and a first row image data signal, and the first row control data signal comprises a row data configuration CTRL_L signal.

[0039] In a fourth aspect, a source driving circuit is provided, which communicates with a timing controller through an integrated stream (ISP); the source driving circuit is configured to:

[0040] receive a first display signal from the timing controller in a current frame display period;

[0041] wherein the first display signal comprises a plurality of first display sub-signals, each of the first display sub-signals comprises a first row control data signal and a first row image data signal, and the first row control data signal comprises a row data configuration CTRL_L signal.

[0042] In a fifth aspect, a display system is provided, which comprises a timing controller and a source driving circuit, the timing controller and the source driving circuit communicate through an integrated stream (ISP);

[0043] the timing controller is configured to send a first display signal to the source driving circuit in a current frame display period;

[0044] the source driving circuit is configured to receive the first display signal from the timing controller in the current frame display period;

[0045] The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals includes a first row control data signal and a first row image data signal, and the first row control data signal includes a row data configuration CTRL_L signal.

[0046] In a sixth aspect, a computer readable storage medium is provided, and the storage medium stores a computer program. The computer program is executed by a processor to implement the steps of the signal transmission method provided in the foregoing aspects.

[0047] In a seventh aspect, a computer program product including instructions which, when executed on a computer, cause the computer to perform the signal transmission method provided in the foregoing aspects.

[0048] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0049] The ISP protocol is used for communication between the timing controller and the source driving circuit, and the CTRL_L signal is added in the row control data signal sent by the timing controller to the source driving circuit. Therefore, the source driving circuit can adjust the information displayed on the corresponding row of sub-pixels according to the CTRL_L signal, so as to optimize the information displayed on the row of sub-pixels. In other words, the standard ISP protocol is improved in the embodiments of the present application, and the CTRL_L signal corresponding to each row of sub-pixels is added in the improved ISP protocol, so as to improve the display performance of the display system. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0051] Figure 1 is a schematic diagram of a display system architecture provided by the embodiments of the present application;

[0052] Figure 2 is a schematic diagram of an ISP system architecture provided by the embodiments of the present application;

[0053] Figure 3 is a flowchart of a signal transmission method provided by the embodiments of the present application;

[0054] Figure 4 is a flowchart of another signal transmission method provided by the embodiments of the present application;

[0055] Figure 5 is a flowchart of a signal transmission method provided by the embodiments of the present application;

[0056] Figure 6 is a format diagram of a display signal provided by an embodiment of the present application;

[0057] Figure 7 is a format diagram of a first display signal provided by an embodiment of the present application;

[0058] Figure 8 is a mapping relationship diagram between a bit value and a length provided by an embodiment of the present application;

[0059] Figure 9 is a flowchart of another signal transmission method provided by an embodiment of the present application;

[0060] Figure 10 is a structure block diagram of a terminal 1000 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0061] To make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0062] Figure 1 is an architecture diagram of a display system provided by an embodiment of the present application. As shown in Figure 1 , the display system includes an AP (application processor) end 01, a driving IC (integrated circuit) 02 and a display panel 03. The driving IC is also called a driving circuit or a DDI (display driver IC).

[0063] The AP end 01 can be connected with the driving IC 02 through a MIPI (mobile industry processor interface). The driving IC 02 is connected with the display panel 03 through cross-set gate lines and data lines.

[0064] For example, as shown in Figure 1As shown, the driving IC 02 can include a timing controller 021, a gate driver IC 022 and a source driver IC 023. The display panel 03 includes a plurality of rows of sub-pixels arranged in an array. The embodiments of the present application take n rows of sub-pixels as an example for illustration, where n is an integer greater than 1. In this scenario, the AP end 01 can be connected to the timing controller 021. The gate driver IC 022 is connected to each row of sub-pixels through a gate line, and the source driver IC 023 is connected to each column of sub-pixels through a data line. Some driving ICs do not include a timing controller, and the AP end is directly connected to the gate driver IC 022 and the source driver IC 023.

[0065] It should be noted that, Figure 1 The embodiments of the present application do not limit the number and layout position of the gate driver IC 022 and the source driver IC 023. The number of gate lines connected to a single gate driver IC 022 is not limited, and the number of data lines connected to a single source driver IC 023 is not limited. For example, the number of source driver ICs is related to the physical resolution of the display panel. For a display panel, dozens or even hundreds of source driver ICs can be required.

[0066] In addition, Figure 1 The display system shown does not constitute a limitation on the embodiments of the present application. In the application of the embodiments of the present application, the display system can include more or fewer components, which will not be illustrated one by one here.

[0067] In addition, the AP end 01 is configured to provide image data to the driving IC 02. The driving IC 02 is configured to charge each row of sub-pixels on the display panel 03 based on the image data, so that the display panel 03 displays an image.

[0068] For example, the AP end 01 inputs the decoded image data to the timing controller 021. The timing controller 021 processes the image data to generate data required by the gate driver IC 022 and the source driver IC 023. For example, the gate-on time corresponding to each row of sub-pixels and the charging voltage corresponding to each column of sub-pixels are generated. The timing controller 021 transmits the generated data to the gate driver IC 022 and the source driver IC 023 according to a certain timing. The gate driver IC 022 can generate a switching signal according to the received data and transmit it to the gate line connected to each row of sub-pixels in the display panel 03. The source driver IC 023 can generate a voltage signal (also referred to as a data signal) according to the received data and transmit it to the data line connected to each column of sub-pixels in the display panel 03.

[0069] Based on Figure 1In the architecture shown, the process of displaying a frame of image by the display system is as follows: the gate driving circuit 022 generates the switching signal corresponding to each row of sub-pixels in turn according to the gate-on time corresponding to each row of sub-pixels in the received data, to open each row of sub-pixels in the n rows of sub-pixels in turn. Taking the i th row of sub-pixels in the n rows of sub-pixels as an example, when the i th row of sub-pixels is opened, the source driving circuit 023 charges each sub-pixel in the i th row of sub-pixels simultaneously according to the charging voltage corresponding to the i th row of sub-pixels in the received data, and the liquid crystal of the i th row of sub-pixels is flipped at the corresponding charging voltage after charging, thereby presenting the corresponding gray scale value.

[0070] That is, in the process of displaying a frame of image by the display system, the timing controller 021 sends image data to the source driving circuit 023 row by row, so that the source driving circuit 023 controls the corresponding row of sub-pixels to display the corresponding gray scale value based on the current row of image data.

[0071] In the embodiment of the present application, the timing controller 021 and the source driving circuit 023 transmit data based on ISP. Wherein, ISP is a kind of P2P (point to point) mode communication protocol, ISP uses embedded clock, without special clock signal, so that the transmission rate can be greatly improved.

[0072] Figure 2 It is an ISP system architecture schematic diagram provided by the embodiment of the present application. As shown in the figure, Figure 2 In the ISP system architecture, a timing controller and a plurality of source driving circuits are included.

[0073] As shown in the figure, Figure 2 The timing controller includes a plurality of output ports (port), and the number of output ports is consistent with the number of source driving circuits, to realize that the first port of each source driving circuit is connected with an output port of the timing controller, to realize the communication in P2P mode. For example, each output port of the timing controller is connected with the first port of a source driving circuit through 1 pair or 2 pairs of differential signal lines, to transmit display signal for displaying image to the source driving circuit through the 1 pair or 2 pairs of differential signal lines.

[0074] In addition, as shown in the figure, Figure 2 The plurality of source driving circuits also share a lock port, Figure 2 The lock port is marked as SDLOCK in the figure, and the lock port can be connected with the timing controller through a single signal line to transmit lock signal. Wherein, the lock signal is used to indicate whether the source driving circuit is in normal working state, such as whether the PLL (phase locked loop) of the source driving circuit is out of lock, etc.

[0075] In the ISP, the format of the display signal transmitted by the timing controller to each source drive circuit is fixed. The method provided by the embodiments of the present application is used for improving the format of the display signal transmitted by the timing controller to each source drive circuit, and the improved ISP adds a CTRL_L signal corresponding to each row of sub-pixels in the display signal, so as to improve the display performance of the display system.

[0076] Next, the signal transmission method provided by the embodiments of the present application will be explained in detail.

[0077] Figure 3 is a flowchart of a signal transmission method provided by the embodiments of the present application. The method is applied to a timing controller, and the timing controller and a source drive circuit communicate through an integrated stream ISP. As shown in Figure 3 , the method comprises the following steps.

[0078] Step 301: In a current frame display period, the timing controller sends a first display signal to the source drive circuit; wherein the first display signal comprises a plurality of first display sub-signals, each of the plurality of first display sub-signals comprises a first row of control data signals and a first row of image data signals, and the first row of control data signals comprises a CTRL_L signal.

[0079] In the embodiments of the present application, the timing controller and the source drive circuit communicate through the ISP protocol, and the CTRL_L signal is added in the row control data signal sent by the timing controller to the source drive circuit, so that the source drive circuit can subsequently adjust the information displayed on the corresponding row of sub-pixels according to the CTRL_L signal, so as to optimize the information displayed by the row of sub-pixels. In other words, the embodiments of the present application improve the standard ISP protocol, and the improved ISP protocol adds a CTRL_L signal corresponding to each row of sub-pixels, so as to improve the display performance of the display system.

[0080] Figure 4 is a flowchart of another signal transmission method provided by the embodiments of the present application. The method is applied to a source drive circuit, and the source drive circuit and a timing controller communicate through an integrated stream ISP. As shown in Figure 4 , the method comprises the following steps.

[0081] Step 401: In a current frame display period, the source drive circuit receives a first display signal from the timing controller; wherein the first display signal comprises a plurality of first display sub-signals, each of the plurality of first display sub-signals comprises a first row of control data signals and a first row of image data signals, and the first row of control data signals comprises a CTRL_L signal.

[0082] In the embodiment of the present application, the timing controller and the source driving circuit communicate through the ISP protocol, and a CTRL L signal is added in the row control data signal sent by the timing controller to the source driving circuit, so that the source driving circuit can subsequently adjust the information displayed on the corresponding row of sub-pixels according to the CTRL L signal, so as to optimize the information displayed by the row of sub-pixels. In other words, the standard ISP protocol is improved in the embodiment of the present application, and the improved ISP protocol adds a CTRL L signal corresponding to each row of sub-pixels, so as to improve the display performance of the display system.

[0083] Figure 5 is a flowchart of a signal transmission method provided by the embodiment of the present application, which is applied to the system shown in Figure 1 and Figure 2 . As shown in Figure 5 , the method comprises the following steps.

[0084] Step 501: In the current frame display period, the timing controller sends a first display signal to the source driving circuit; wherein the first display signal comprises a plurality of first display sub-signals, each of the plurality of first display sub-signals comprises a first row control data signal and a first row image data signal, and the first row control data signal comprises a CTRL L signal.

[0085] Step 502: In the current frame display period, the source driving circuit receives the first display signal from the timing controller.

[0086] Since each display sub-signal in the first display signal further comprises a CTRL L signal, the source driving circuit can adaptively adjust its working parameters according to the fact that each display sub-signal further comprises a CTRL L signal, so as to display the row image data signal in each display sub-signal according to the adjusted working parameters, thereby improving the performance of the source driving circuit.

[0087] Wherein, the first display signal can be understood as the general term of all signals of the current frame sent by the timing controller to the source driving circuit. Each display sub-signal in the plurality of first display sub-signals can be understood as a signal for one row of sub-pixels controlled by the source driving circuit. The first row control data signal can be understood as a control signal for a row of sub-pixels, and the first row image data signal can be understood as an image data signal for a row of sub-pixels.

[0088] The specific format of the CTRL_L (line packet configuration) signal can refer to a related standard protocol. In some embodiments, the CTRL_L signal can carry some working parameters, which can be used to set the rising edge position of the data loading signal of the source driving circuit, set the width of the data loading signal of the source driving circuit, set the charge sharing function, and the like. In this way, in the ISP, the performance of the source driving circuit can be optimized through the CTRL_L signal, so as to improve the display performance of the display system.

[0089] In the current ISP, working parameters such as the rising edge position of the data loading signal of the source driving circuit, the width of the data loading signal of the source driving circuit, the charge sharing function, and the like are carried in the CTRL_F (frame packet configuration) signal, so that all the row sub-pixels controlled by the source driving circuit will use this set of working parameters for display, which is easy to cause the power consumption of the source driving circuit to increase.

[0090] However, in the embodiments of the present application, since the CTRL_L signal is added in each display sub-signal corresponding to each row sub-pixel, the timing controller can adaptively set the CTRL_L signal corresponding to each row sub-pixel according to the differences between different row sub-pixels, such as adjusting the charge sharing mode according to the differences between different row sub-pixels. In this way, the source driving circuit can display each row sub-pixel according to the CTRL_L signal corresponding to the row sub-pixel, instead of displaying all the row sub-pixels according to the same set of working parameters, so that the power consumption of the source driving circuit can be optimized.

[0091] In addition, in some embodiments, the first row control data signal further includes a POL (polarity inversion) signal. In this case, the implementation manner of the timing controller for sending the first display signal to the source driving circuit can be that the timing controller sends the CTRL_L signal after sending the POL signal. Correspondingly, the implementation manner of the source driving circuit for receiving the first display signal from the timing controller can be that the source driving circuit receives the CTRL_L signal after receiving the POL signal.

[0092] That is, in the embodiments of the present application, the CTRL_L signal is added after the POL signal in the display sub-signal corresponding to each row sub-pixel, so that the source driving circuit displays the image data corresponding to the row sub-pixel based on the working parameters indicated by the POL signal and the CTRL_L signal subsequently.

[0093] Figure 6 is a format diagram of a display signal provided by the embodiments of the present application. As shown in FIG. 1, the display signal includes a POL signal and a CTRL_L signal.Figure 6 As shown, if the first display signal adopts Figure 6 The format shown, for the current frame, includes multiple first display sub-signals corresponding to multiple rows of sub-pixels. Each first display sub-signal includes a first row image data signal and a first row control data signal. The first row image data signal is, for example, used to carry RGB (red-green-blue) image data. The first row control data signal typically includes a BAC (bit alignment code) signal, a POL (polarity inversion) signal, and an EOL (end of line code) signal, etc.

[0094] The BAC signal indicates the imminent transmission of valid data, signifying the start of valid data transmission. The EOL signal indicates the completion of current valid data transmission, signifying the end of valid data transmission. The POL signal indicates the polarity reversal of the current row of image data.

[0095] like Figure 6 As shown, if the line control data signal received by the source driver circuit does not include the CTRL_L (line packet configuration) signal, then when the source driver circuit displays the sub-pixel of that line, only the POL working parameter is adaptively adjusted according to the POL signal corresponding to the sub-pixel of the line. Other working parameters, such as the charge sharing mode, are the same as those of other sub-pixels of the line, which limits the performance of the source driver circuit.

[0096] Figure 7 This is a schematic diagram illustrating the format of a first display signal provided in an embodiment of this application. For example... Figure 7 As shown, for the current frame, the first display signal includes multiple first display sub-signals corresponding to the sub-pixels of the multiple rows. Each first display sub-signal includes a first row image data signal and a first row control data signal. The first row image data signal is, for example, used to carry RGB (red-green-blue) image data. The first row control data signal typically includes a BAC (bit alignment code) signal, a POL (polarity inversion) signal, a CTRL_L signal, and an EOL (end of line code) signal, etc.

[0097] That is, Figure 7 The first display signal shown is in Figure 6The POL signal and the EOL signal of each display sub-signal in the first display signal are added with a CTRL_L signal, so as to set more working parameters of the source driving circuit in units of behaviors through the CTRL_L signal, thereby improving the performance of the source driving circuit.

[0098] It should be noted that, Figure 7 The position of the CTRL_L signal in the ISP is illustrated by way of example, Figure 7 The format shown does not limit the position of the CTRL_L signal in the ISP. For example, the CTRL_L signal can also be located before the POL signal, which will not be illustrated one by one here.

[0099] In addition, as shown in Figure 6 and Figure 7 After the transmission of each display sub-signal is completed, the timing controller and the source driving circuit enter a banking interval, which can be referred to as a horizontal banking interval. In the banking interval, the output of the timing controller will change to indicate that the source driving circuit is ready to receive the display sub-signal corresponding to the next row of sub-pixels.

[0100] After the transmission of the display sub-pixels of all rows is completed, the timing controller can also send a setting command signal and a CTRL_F signal required to optimize the performance of the source driving circuit to the source driving circuit.

[0101] In addition, in the embodiments of the present application, the length of the added CTRL_L signal can also be flexibly set, that is, the size of the data carried in the CTRL_L signal can be flexibly set.

[0102] In some embodiments, the length of the added CTRL_L signal can be flexibly set in the CTRL_F signal as shown in Figure 6 and Figure 7 Considering that the CTRL_F signal is usually used to indicate the working parameters used by the source driving circuit when displaying the next frame of image, based on this, in some embodiments, before the timing controller sends the first display signal to the source driving circuit, the timing controller can also obtain a second display signal sent to the source driving circuit in the last frame display period, the second display signal includes a second frame control sub-signal, the second frame control sub-signal includes a second frame data configuration CTRL_F signal, and the second CTRL_F signal carries a second packet length field; the timing controller determines the length of the CTRL_L signal sent in the current frame display period based on the second packet length field.

[0103] The format of the second display signal can refer to the format of the first display signal as shown in Figure 7 , which will not be described here.

[0104] Correspondingly, the source driving circuit acquires a second display signal received in a previous frame display period, the second display signal comprising a second frame control sub-signal, the second frame control sub-signal comprising a second frame data configuration CTRL_F signal, the second CTRL_F signal carrying a second packet length field; and the source driving circuit determines a length of a CTRL_L signal received in a current frame display period based on the second packet length field.

[0105] That is, the source driving circuit determines the length of the CTRL_L signal received in the current frame display period based on the packet length field in the CTRL_F signal received in the previous frame display period, and then parses the received display sub-signal based on the determined length.

[0106] In this scenario, in the current frame display period, the first display signal sent by the timing controller to the source driving circuit can further comprise a first frame control sub-signal, the first frame control sub-signal comprising a first CTRL_F signal, the first CTRL_F signal carrying a first packet length field, the first packet length field being used to indicate a length of a CTRL_L signal sent in a next frame display period.

[0107] That is, the length of the CTRL_L signal in the next frame display period is indicated in the CTRL_F signal in the current frame display period.

[0108] The first packet length field and the second packet length field can be the same. Alternatively, the first packet length field and the second packet length field can also be different, that is, the lengths of the CTRL_L signals included in the display sub-signals sent in different frame display periods can be different.

[0109] In the scenario where the first packet length field and the second packet length field are the same, in the current frame display period, the first CTRL_F signal in the first display signal sent by the timing controller to the source driving circuit can also not comprise the first packet length field. Subsequently, the source driving circuit only needs to determine the length of the CTRL_L signal received in the current frame display period according to the packet length field received most recently.

[0110] In addition, in some embodiments, the second packet length field comprises at least one bit. In this scenario, the implementation manner of the timing controller for determining the length of the CTRL_L signal sent in the current frame display period based on the second packet length field can be: the timing controller determines the length of the CTRL_L signal sent in the current frame display period from a mapping relationship between a bit value on the at least one bit included in the second packet length field and the length based on the bit value.

[0111] Correspondingly, the implementation manner that the source driving circuit determines the length of the CTRL_L signal received in the current frame display period based on the second packet length field can be: the source driving circuit determines the length of the CTRL_L signal received in the current frame display period from a mapping relationship between the bit value and the length based on the bit value on the at least one bit included in the second packet length field.

[0112] In the embodiment of the present application, the mapping relationship between the bit value and the length of the CTRL_L signal can be configured in advance on the timing controller and the source driving circuit, so that the timing controller can quickly determine the length of the currently transmitted CTRL_L signal when transmitting the CTRL_L signal, and the source driving circuit can quickly determine the length of the currently received CTRL_L signal when receiving the CTRL_L signal.

[0113] In addition, in the scenario that the length of the CTRL_L signal in the current frame display period is indicated by the packet length field in the CTRL_F signal in the last frame display period, the current frame display period can also be directly indicated by the packet length field whether the CTRL_L signal is included in the current frame display period.

[0114] For example, if the second packet length field indicates that the length of the CTRL_L signal transmitted in the current frame display period is 0, in the current frame display period, the timing controller transmits a third display signal to the source driving circuit, and the source driving circuit receives the third display signal. Wherein, the third display signal includes a plurality of third display sub-signals, and each third display sub-signal in the third plurality of display sub-signals includes a third row control data signal and a third row image data signal, and the third row control data signal does not include the CTRL_L signal.

[0115] That is, if the packet length field in the CTRL_F signal in the last frame display period indicates that there is no CTRL_L signal in the current frame display period, the timing controller can transmit the display signal according to the ISP data format shown in Figure 6 If the packet length field in the CTRL_F signal in the last frame display period indicates that there is a CTRL_L signal in the current frame display period, the timing controller can transmit the display signal according to the improved ISP data format shown in Figure 7 Further improve the application flexibility of the embodiment of the present application.

[0116] Figure 8 is a mapping relationship between a bit value and a length provided by an embodiment of the present application. As shown in Figure 8As shown, the packet length field in the CTRL_F signal includes two bits, which correspond to four groups of bit values, namely 00, 01, 10 and 11. Among them, 00 corresponds to a length of 0 bytes, 01 corresponds to a length of 4 bytes, 10 corresponds to a length of 8 bytes, and 11 corresponds to a length of 16 bytes.

[0117] Based on Figure 8 According to the mapping relationship shown, the embodiment of the present application further provides Figure 9 As shown in the signal transmission method flow chart. As Figure 9 As shown, in the current frame display period, the packet length field in the CTRL_F signal sent by the timing controller in the previous frame display period is obtained. If the packet length field in the CTRL_F signal sent by the timing controller in the previous frame display period is 00, the timing controller in the current frame display period sends the display signal according to Figure 6 As shown, the ISP data format. Correspondingly, each display sub-signal in the display signal received by the source drive circuit does not include the CTRL_L signal. If the packet length field in the CTRL_F signal sent by the timing controller in the previous frame display period is any one of 01, 10 or 11, the timing controller in the current frame display period sends the display signal according to the length of the CTRL_L signal indicated by the packet length field. As shown Figure 7 As shown, the display signal. Correspondingly, each display sub-signal in the display signal received by the source drive circuit includes the CTRL_L signal.

[0118] Alternatively, in the embodiment of the present application, if the length of the CTRL_L signal sent in each frame display period is the same, the length of the CTRL_L signal in the next frame display period can also not be indicated in the CTRL_F signal in each frame display period. In this case, the timing controller and the source drive circuit can obtain the length of the CTRL_L signal in each frame display period through pre-configuration.

[0119] In summary, in the embodiment of the present application, the timing controller and the source drive circuit communicate through the ISP protocol, and the CTRL_L signal is added to the row control data signal sent by the timing controller to the source drive circuit. Therefore, the source drive circuit can subsequently adjust the information displayed on the corresponding row of sub-pixels according to the CTRL_L signal, so as to optimize the information displayed by the row of sub-pixels. In other words, the embodiment of the present application improves the standard ISP protocol, and adds the CTRL_L signal corresponding to each row of sub-pixels in the improved ISP protocol, so as to improve the display performance of the display system.

[0120] All the optional technical solutions described above can be combined to form optional embodiments of the present application, and the embodiments of the present application will not be described one by one.

[0121] In addition, the embodiment of the present application further provides a timing controller, which is used for the timing controller shown in the timing controller, the timing controller is used for: in the current frame display period, sending a first display signal to a source drive circuit; Figure 1 and Figure 2 The timing controller is used for: in the current frame display period, sending a first display signal to a source drive circuit;

[0122] The first display signal includes a plurality of first display sub-signals, and each of the plurality of first display sub-signals includes a first row control data signal and a first row image data signal, and the first row control data signal includes a row data configuration CTRL_L signal.

[0123] Optionally, the first row control data signal further includes a polarity inversion POL signal; and the timing controller is used for: after sending the POL signal, sending the CTRL_L signal.

[0124] Optionally, before the timing controller sends the first display signal to the source drive circuit, the timing controller is further used for: acquiring a second display signal sent to the source drive circuit in a last frame display period, the second display signal including a second frame control sub-signal, the second frame control sub-signal including a second frame data configuration CTRL_F signal, and the second CTRL_F signal carrying a second packet length field; and determining the length of the CTRL_L signal sent in the current frame display period based on the second packet length field.

[0125] Optionally, the first display signal further includes a first frame control sub-signal, and the first frame control sub-signal includes a first CTRL_F signal carrying a first packet length field, the first packet length field being used for indicating the length of the CTRL_L signal sent in a next frame display period.

[0126] Optionally, the second packet length field includes at least one bit; and the timing controller is used for: determining the length of the CTRL_L signal sent in the current frame display period from a mapping relationship between a bit value and a length based on the bit value on the at least one bit included in the second packet length field.

[0127] Optionally, the timing controller is further used for: if the second packet length field indicates that the length of the CTRL_L signal sent in the current frame display period is 0, sending a third display signal to the source drive circuit in the current frame display period; wherein the third display signal includes a plurality of third display sub-signals, and each of the third plurality of display sub-signals includes a third row control data signal and a third row image data signal, and the third row control data signal does not include the CTRL_L signal.

[0128] In the embodiment of the present application, the timing controller and the source driving circuit communicate through the ISP protocol, and a CTRL_L signal is added in the row control data signal sent by the timing controller to the source driving circuit, so that the source driving circuit can subsequently adjust the information displayed on the corresponding row of sub-pixels according to the CTRL_L signal, so as to optimize the information displayed by the row of sub-pixels. In other words, the embodiment of the present application improves the standard ISP protocol, and the improved ISP protocol adds a CTRL_L signal corresponding to each row of sub-pixels to improve the display performance of the display system.

[0129] It should be noted that: the timing controller provided in the above embodiments only uses the above-mentioned division of functional modules as an example to illustrate the transmission of signals to the source driving circuit. In actual application, the above-mentioned functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the timing controller and the signal transmission method provided in the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0130] In addition, the embodiment of the present application also provides a source driving circuit, which is the source driving circuit shown in Figure 1 and Figure 2 The source driving circuit is configured to: receive a first display signal from a timing controller in a current frame display period;

[0131] The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals includes a first row control data signal and a first row image data signal, and the first row control data signal includes a first row data configuration CTRL_L signal.

[0132] Optionally, the first row control data signal further includes a polarity inversion POL signal; and the source driving circuit is configured to: receive the CTRL_L signal after receiving the POL signal.

[0133] Optionally, the source driving circuit is further configured to: obtain a second display signal received in a previous frame display period, the second display signal includes a second frame control sub-signal, the second frame control sub-signal includes a second frame data configuration CTRL_F signal, and the second CTRL_F signal carries a second packet length field; and determine the length of the CTRL_L signal received in the current frame display period based on the second packet length field.

[0134] Optionally, the first display signal further comprises a first frame control sub-signal, and the first frame control sub-signal comprises a first frame data configuration CTRL_F signal, and the first CTRL_F signal carries a first packet length field, and the first packet length field is used to indicate a length of a CTRL_L signal received in a next frame display period.

[0135] Optionally, the second packet length field comprises at least one bit, and the source drive circuit is configured to determine the length of the CTRL_L signal received in the current frame display period from a mapping relationship between a bit value and a length based on the bit value of the at least one bit included in the second packet length field.

[0136] Optionally, the source drive circuit is further configured to receive a third display signal from the timing controller in the current frame display period if the second packet length field indicates that the length of the CTRL_L signal received in the current frame display period is 0, and the third display signal comprises a plurality of third display sub-signals, and each third display sub-signal of the third plurality of display sub-signals comprises a third row control data signal and a third row image data signal, and the third row control data signal does not comprise the CTRL_L signal.

[0137] In the embodiments of the present application, the timing controller and the source drive circuit communicate through the ISP protocol, and the CTRL_L signal is added to the row control data signal sent by the timing controller to the source drive circuit, so that the source drive circuit can subsequently adjust the information displayed on the corresponding row of sub-pixels according to the CTRL_L signal to optimize the information displayed by the row of sub-pixels. In other words, the standard ISP protocol is improved in the embodiments of the present application, and the CTRL_L signal corresponding to each row of sub-pixels is added to the improved ISP protocol to improve the display performance of the display system.

[0138] It should be noted that the source drive circuit provided in the above embodiments only divides the above functions for example, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the source drive circuit and the signal transmission method provided in the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0139] In addition, the embodiments of the present application also provide a display system, which comprises a timing controller and a source drive circuit, and the timing controller and the source drive circuit communicate through the ISP protocol.

[0140] The timing controller is configured to send a first display signal to the source drive circuit in a current frame display period.

[0141] The source driving circuit is configured to receive a first display signal from the timing controller in a current frame display period.

[0142] The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals includes a first row control data signal and a first row image data signal, and the first row control data signal includes a first row data configuration CTRL_L signal.

[0143] The detailed functions of the timing controller and the source driving circuit can refer to the foregoing method embodiments, and will not be explained in detail here.

[0144] Figure 10 is a structural block diagram of a terminal 1000 provided by an embodiment of the present application, and the foregoing display system can be deployed on the terminal shown in Figure 10 The terminal 1000 can be a smart phone, a tablet computer, an MP3 (Moving Picture Experts Group Audio Layer III) player, an MP4 (Moving Picture Experts Group Audio Layer IV) player, a notebook computer, or a desktop computer. The terminal 1000 can also be referred to as a user equipment, a portable terminal, a laptop terminal, a desktop terminal, or other names.

[0145] Generally, the terminal 1000 includes a processor 1001 and a memory 1002.

[0146] The processor 1001 can include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 1001 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor 1001 can also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a CPU (Central Processing Unit), and the coprocessor being a low-power processor for processing data in a standby state. In some embodiments, the processor 1001 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing of content to be displayed by the display screen. In some embodiments, the processor 1001 can further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

[0147] The memory 1002 can include one or more computer-readable storage media that can be non-transitory. The memory 1002 can also include high-speed random access memory and nonvolatile, computer-readable storage media such as one or more magnetic disk storage devices, flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1002 is used to store at least one instruction for being executed by the processor 1001 to implement the signal transmission method provided by the method embodiment of the present application.

[0148] In some embodiments, the terminal 1000 can also optionally include a peripheral device interface 1003 and at least one peripheral device. The processor 1001, the memory 1002, and the peripheral device interface 1003 can be connected through a bus or a signal line. Each peripheral device can be connected to the peripheral device interface 1003 through a bus, a signal line, or a circuit board. Specifically, the peripheral device includes at least one of a radio frequency circuit 1004, a touch display screen 1005, a camera 1006, an audio circuit 1007, a positioning component 1008, and a power supply 1009.

[0149] The peripheral interface 1003 can be used to connect at least one I / O (Input / Output) related peripheral device to the processor 1001 and the memory 1002. In some embodiments, the processor 1001, the memory 1002 and the peripheral interface 1003 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1001, the memory 1002 and the peripheral interface 1003 can be implemented on a separate chip or circuit board, and the present embodiments are not limited in this regard.

[0150] The radio frequency circuit 1004 is configured to receive and send RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 1004 communicates with communication networks and other communication devices through electromagnetic signals. The radio frequency circuit 1004 converts electrical signals into electromagnetic signals for transmission, or converts electromagnetic signals received into electrical signals. Optionally, the radio frequency circuit 1004 includes an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a subscriber identity module card, and the like. The radio frequency circuit 1004 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes but is not limited to: a metropolitan area network, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 1004 can also include NFC (Near Field Communication) related circuitry, and the present application is not limited in this regard.

[0151] The display screen 1005 is configured to display a UI (User Interface). The UI can include graphics, text, icons, video, and any combination thereof. When the display screen 1005 is a touch display screen, the display screen 1005 is further configured to capture touch signals on or above the surface of the display screen 1005. The touch signals can be input to the processor 1001 as control signals for processing. In this case, the display screen 1005 can also be configured to provide virtual buttons and / or virtual keyboard, also known as soft buttons and / or soft keyboard. In some embodiments, the display screen 1005 can be one, arranged on the front panel of the terminal 1000; in other embodiments, the display screen 1005 can be at least two, arranged on different surfaces of the terminal 1000 or in a folding design; in still other embodiments, the display screen 1005 can be a flexible display screen, arranged on a curved surface or a folding surface of the terminal 1000. Even, the display screen 1005 can also be arranged in an irregular shape, i.e., a special-shaped screen. The display screen 1005 can be made of materials such as LCD (Liquid Crystal Display).

[0152] The camera assembly 1006 is configured to capture images or videos. Optionally, the camera assembly 1006 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is arranged on the front panel of the terminal, and the rear-facing camera is arranged on the back of the terminal. In some embodiments, the rear-facing camera is at least two, which are any one of a main camera, a depth-of-field camera, a wide-angle camera, and a telephoto camera, to realize the background blur function by fusing the main camera and the depth-of-field camera, the panoramic shooting and VR (Virtual Reality) shooting function by fusing the main camera and the wide-angle camera, or other fusion shooting functions. In some embodiments, the camera assembly 1006 can further include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. The dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0153] The audio circuit 1007 can include a microphone and a speaker. The microphone is used to collect sound waves of a user and an environment, and convert the sound waves into an electrical signal input to the processor 1001 for processing, or input to the radio frequency circuit 1004 to realize voice communication. For the purpose of stereo sound collection or noise reduction, the microphone can be multiple, respectively arranged at different parts of the terminal 1000. The microphone can also be an array microphone or an omnidirectional collection type microphone. The speaker is used to convert an electrical signal from the processor 1001 or the radio frequency circuit 1004 into sound waves. The speaker can be a traditional diaphragm speaker, or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, not only can the electrical signal be converted into a sound wave audible to humans, but also can be converted into a sound wave inaudible to humans for ranging purposes. In some embodiments, the audio circuit 1007 can also include a headphone jack.

[0154] The positioning component 1008 is used to position the current geographic position of the terminal 1000 to realize navigation or LBS (Location Based Service). The positioning component 1008 can be a positioning component based on the GPS (Global Positioning System) of the United States, the Beidou system of China, the Glonass system of Russia or the Galileo system of the European Union.

[0155] The power supply 1009 is used to supply power to each component in the terminal 1000. The power supply 1009 can be alternating current, direct current, disposable battery or rechargeable battery. When the power supply 1009 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0156] In some embodiments, the terminal 1000 further includes one or more sensors 1010. The one or more sensors 1010 include but are not limited to: an acceleration sensor 1011, a gyroscope sensor 1012, a pressure sensor 1013, a fingerprint sensor 1014, an optical sensor 1015 and a proximity sensor 1016.

[0157] The acceleration sensor 1011 can detect the acceleration magnitude in three coordinate axes of the coordinate system established by the terminal 1000. For example, the acceleration sensor 1011 can be used to detect the components of the gravitational acceleration in three coordinate axes. The processor 1001 can control the touch display screen 1005 to display the user interface in a landscape view or a portrait view according to the gravitational acceleration signal collected by the acceleration sensor 1011. The acceleration sensor 1011 can also be used for game or user motion data collection.

[0158] The gyroscope sensor 1012 can detect the body direction and rotation angle of the terminal 1000, and can collect 3D motions of a user on the terminal 1000 in cooperation with the acceleration sensor 1011. The processor 1001 can implement the following functions according to the data collected by the gyroscope sensor 1012: motion sensing (e.g., changing a UI according to a tilt operation of the user), image stabilization during shooting, game control, and inertial navigation.

[0159] The pressure sensor 1013 can be disposed on a side frame of the terminal 1000 and / or under the touch display screen 1005. When the pressure sensor 1013 is disposed on the side frame of the terminal 1000, a grip signal of a user on the terminal 1000 can be detected, and left-hand or right-hand recognition or a shortcut operation can be performed by the processor 1001 according to the grip signal collected by the pressure sensor 1013. When the pressure sensor 1013 is disposed under the touch display screen 1005, a pressure operation of a user on the touch display screen 1005 can be detected by the processor 1001, and an operable control on a UI can be controlled according to the pressure operation. The operable control includes at least one of a button control, a scroll bar control, an icon control, and a menu control.

[0160] The fingerprint sensor 1014 is used to collect a fingerprint of a user, and the identity of the user can be recognized by the processor 1001 according to the fingerprint collected by the fingerprint sensor 1014 or by the fingerprint sensor 1014 according to the collected fingerprint. When the identity of the user is recognized as a trusted identity, the processor 1001 authorizes the user to perform a related sensitive operation, which includes unlocking a screen, viewing encrypted information, downloading software, payment, and changing a setting, etc. The fingerprint sensor 1014 can be disposed on the front, back, or side of the terminal 1000. When a physical button or a manufacturer's logo is disposed on the terminal 1000, the fingerprint sensor 1014 can be integrated with the physical button or the manufacturer's logo.

[0161] The optical sensor 1015 is used to collect ambient light intensity. In an embodiment, the processor 1001 can control the display brightness of the touch display screen 1005 according to the ambient light intensity collected by the optical sensor 1015. Specifically, when the ambient light intensity is high, the display brightness of the touch display screen 1005 is increased, and when the ambient light intensity is low, the display brightness of the touch display screen 1005 is decreased. In another embodiment, the processor 1001 can also dynamically adjust the shooting parameters of the camera assembly 1006 according to the ambient light intensity collected by the optical sensor 1015.

[0162] The proximity sensor 1016, also called distance sensor, is usually arranged on the front panel of the terminal 1000. The proximity sensor 1016 is used to collect the distance between the user and the front of the terminal 1000. In one embodiment, when the proximity sensor 1016 detects that the distance between the user and the front of the terminal 1000 gradually becomes smaller, the touch display screen 1005 is switched from the bright screen state to the screen-off state under the control of the processor 1001; when the proximity sensor 1016 detects that the distance between the user and the front of the terminal 1000 gradually becomes larger, the touch display screen 1005 is switched from the screen-off state to the bright screen state under the control of the processor 1001.

[0163] Those skilled in the art can understand that the structure shown in the above embodiments does not constitute a limitation on the terminal 1000, and the terminal 1000 can include more or less components than those shown in the figure, or combine certain components, or adopt a different component arrangement. Figure 10

[0164] The embodiments of the present application further provide a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of a terminal, the terminal can execute the signal transmission method provided in the above embodiments.

[0165] The embodiments of the present application further provide a computer program product containing instructions, when the computer program product is executed on a terminal, the terminal executes the signal transmission method provided in the above embodiments.

[0166] Those skilled in the art can understand that all or part of the steps of the above embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium, and the storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0167] The above only describes the preferred embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.​

Claims

1. A signal transmission method, characterized in that, The method is applied to a timing controller, which communicates with the source driver circuit via an integrated stream communication (ISP); the method includes: During the current frame display period, the timing controller sends a first display signal to the source drive circuit; The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals including a first row control data signal and a first row image data signal, wherein the first row control data signal includes a row data configuration CTRL_L signal; Before the timing controller sends the first display signal to the source drive circuit, the method further includes: The timing controller acquires a second display signal sent to the source driving circuit during the previous frame display cycle. The second display signal includes a second frame control sub-signal, which includes a second frame data configuration CTRL_F signal. The second frame data configuration CTRL_F signal carries a second packet length field. The timing controller determines the length of the CTRL_L signal sent within the current frame display period based on the second packet length field.

2. The method as described in claim 1, characterized in that, The first row of control data signals also includes a polarity reversal POL signal; The timing controller sends a first display signal to the source drive circuit, including: After sending the POL signal, the timing controller sends the CTRL_L signal.

3. The method as described in claim 1, characterized in that, The first display signal further includes a first frame control sub-signal, which includes a first frame data configuration CTRL_F signal. The first frame data configuration CTRL_F signal carries a first packet length field, which is used to indicate the length of the CTRL_L signal sent in the next frame display period.

4. The method as described in claim 1, characterized in that, The second packet length field includes at least one bit; The timing controller determines the length of the CTRL_L signal sent within the current frame display period based on the second packet length field, including: The timing controller determines the length of the CTRL_L signal transmitted within the current frame display period based on the bit values ​​of at least one bit included in the second packet length field, from the mapping relationship between bit values ​​and length.

5. The method as described in claim 1, characterized in that, The method further includes: If the second packet length field indicates that the length of the CTRL_L signal sent within the current frame display period is 0, then within the current frame display period, the timing controller sends a third display signal to the source driver circuit; The third display signal includes multiple third display sub-signals, each of which includes a third row control data signal and a third row image data signal. The third row control data signal does not include the CTRL_L signal.

6. A signal transmission method, characterized in that, The method is applied to a source driver circuit, wherein the source driver circuit communicates with a timing controller via an integrated stream ISP; the method includes: During the current frame display period, the source drive circuit receives a first display signal from the timing controller; The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals including a first row control data signal and a first row image data signal, wherein the first row control data signal includes a row data configuration CTRL_L signal; The method further includes: The source driving circuit acquires a second display signal received in the previous frame display period. The second display signal includes a second frame control sub-signal. The second frame control sub-signal includes a second frame data configuration CTRL_F signal. The second frame data configuration CTRL_F signal carries a second packet length field. The source driving circuit determines the length of the CTRL_L signal received within the current frame display period based on the second packet length field.

7. The method as described in claim 6, characterized in that, The first row of control data signals also includes a polarity reversal POL signal; The source drive circuit receives a first display signal from the timing controller, including: The source drive circuit receives the CTRL_L signal after receiving the POL signal.

8. The method as described in claim 6, characterized in that, The first display signal further includes a first frame control sub-signal, which includes a first frame data configuration CTRL_F signal. The first frame data configuration CTRL_F signal carries a first packet length field, which is used to indicate the length of the CTRL_L signal received in the next frame display period.

9. The method as described in claim 6, characterized in that, The second packet length field includes at least one bit; The source driver circuit determines the length of the CTRL_L signal received within the current frame display period based on the second packet length field, including: The source driving circuit determines the length of the CTRL_L signal received within the current frame display period based on the bit value of at least one bit in the second packet length field, from the mapping relationship between bit value and length.

10. The method as described in claim 6, characterized in that, The method further includes: If the second packet length field indicates that the length of the CTRL_L signal received within the current frame display period is 0, then within the current frame display period, the source drive circuit receives a third display signal from the timing controller; The third display signal includes multiple third display sub-signals, each of which includes a third row control data signal and a third row image data signal. The third row control data signal does not include the CTRL_L signal.

11. A timing controller, characterized in that, The timing controller communicates with the source driver circuit via an integrated streaming ISP; the timing controller is used for: During the current frame display period, a first display signal is sent to the source driving circuit; The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals including a first row control data signal and a first row image data signal, wherein the first row control data signal includes a row data configuration CTRL_L signal; Before the timing controller sends the first display signal to the source drive circuit, it is also used to: Acquire a second display signal sent to the source driving circuit during the previous frame display cycle. The second display signal includes a second frame control sub-signal. The second frame control sub-signal includes a second frame data configuration CTRL_F signal. The second frame data configuration CTRL_F signal carries a second packet length field. Based on the second packet length field, the length of the CTRL_L signal sent within the current frame display period is determined.

12. A source driving circuit, characterized in that, The source driver circuit communicates with the timing controller via an integrated stream ISP; the source driver circuit is used for: During the current frame display period, a first display signal is received from the timing controller; The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals including a first row control data signal and a first row image data signal, wherein the first row control data signal includes a row data configuration CTRL_L signal; The source drive circuit is also used for: Acquire a second display signal received during the previous frame display period. The second display signal includes a second frame control sub-signal. The second frame control sub-signal includes a second frame data configuration CTRL_F signal. The second frame data configuration CTRL_F signal carries a second packet length field. The length of the CTRL_L signal received within the current frame display period is determined based on the second packet length field.

13. A display system, characterized in that, The display system includes a timing controller and a source driver circuit, and the timing controller and the source driver circuit communicate via an integrated stream ISP. The timing controller is configured to: acquire a second display signal sent to the source driver circuit during the previous frame display period, the second display signal including a second frame control sub-signal, the second frame control sub-signal including a second frame data configuration CTRL_F signal, the second frame data configuration CTRL_F signal carrying a second packet length field, determine the length of the CTRL_L signal sent during the current frame display period based on the second packet length field, and send a first display signal to the source driver circuit during the current frame display period; The source driving circuit is configured to: acquire a second display signal received in the previous frame display period, the second display signal including a second frame control sub-signal, the second frame control sub-signal including a second frame data configuration CTRL_F signal, the second frame data configuration CTRL_F signal carrying a second packet length field, the source driving circuit determining the length of the CTRL_L signal received in the current frame display period based on the second packet length field, and receiving the first display signal from the timing controller in the current frame display period; The first display signal includes a plurality of first display sub-signals, each of the plurality of first display sub-signals including a first row control data signal and a first row image data signal, wherein the first row control data signal includes a row data configuration CTRL_L signal.

Images